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authorTom Musta <tommusta@gmail.com>2013-10-22 22:06:17 +1100
committerAlexander Graf <agraf@suse.de>2013-12-20 01:57:47 +0100
commit1f29871cb7518692cf5c1fa8c19b117c789ff7f0 (patch)
tree7c8650829b497d5ebac5bd6a21ed3d09b8c81f19 /target-ppc/excp_helper.c
parent74f239975501cf0ad886a5d40ce40aecbb9dc0b2 (diff)
Add MSR VSX and Associated Exception
This patch adds support for the VSX bit of the PowerPC Machine State Register (MSR) as well as the corresponding VSX Unavailable exception. The VSX bit is added to the defined bits masks of the Power7 and Power8 CPU models. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/excp_helper.c')
-rw-r--r--target-ppc/excp_helper.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index c959460f70..26c57d9a34 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -390,6 +390,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
new_msr |= (target_ulong)MSR_HVB;
}
goto store_current;
+ case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
+ if (lpes1 == 0) {
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+ goto store_current;
case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
LOG_EXCP("PIT exception\n");
goto store_next;