aboutsummaryrefslogtreecommitdiff
path: root/target-ppc/cpu-qom.h
diff options
context:
space:
mode:
authorAlexey Kardashevskiy <aik@ozlabs.ru>2014-05-23 12:26:52 +1000
committerAlexander Graf <agraf@suse.de>2014-06-16 13:24:37 +0200
commit6d9412ea8132d6fa23bb0d57167ea585c728c3f1 (patch)
tree8b003cda7a9e0682cd6a451ff253c097df9ea21e /target-ppc/cpu-qom.h
parent833d46685d2c59078d484ca22708d9b46283fbd4 (diff)
downloadqemu-arm-6d9412ea8132d6fa23bb0d57167ea585c728c3f1.tar.gz
target-ppc: Implement "compat" CPU option
This adds basic support for the "compat" CPU option. By specifying the compat property, the user can manually switch guest CPU mode from "raw" to "architected". This defines feature disable bits which are not used yet as, for example, PowerISA 2.07 says if 2.06 mode is selected, the TM bit does not matter - transactional memory (TM) will be disabled because 2.06 does not define it at all. The same is true for VSX and 2.05 mode. So just setting a mode must be ok. This does not change the existing behavior as the actual compatibility mode support is coming in next patches. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: fix compilation on 32bit hosts] Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu-qom.h')
-rw-r--r--target-ppc/cpu-qom.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index 533de8fbd7..e88e1da2b9 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -84,6 +84,7 @@ typedef struct PowerPCCPUClass {
* @env: #CPUPPCState
* @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
* @max_compat: Maximal supported logical PVR from the command line
+ * @cpu_version: Current logical PVR, zero if in "raw" mode
*
* A PowerPC CPU.
*/
@@ -95,6 +96,7 @@ struct PowerPCCPU {
CPUPPCState env;
int cpu_dt_id;
uint32_t max_compat;
+ uint32_t cpu_version;
};
static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)