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authorRichard Henderson <rth@twiddle.net>2015-09-17 15:58:10 -0700
committerRichard Henderson <rth@twiddle.net>2015-10-07 20:36:28 +1100
commitb933066ae03d924a92b2616b4a24e7d91cd5b841 (patch)
treea5475afc2a27a25b4f91c8376d68daec05183e2e /target-mips/translate.c
parent959082fc4a93a016a6b697e1e0c2b373d8a3a373 (diff)
downloadqemu-arm-b933066ae03d924a92b2616b4a24e7d91cd5b841.tar.gz
target-*: Introduce and use cpu_breakpoint_test
Reduce the boilerplate required for each target. At the same time, move the test for breakpoint after calling tcg_gen_insn_start. Note that arm and aarch64 do not use cpu_breakpoint_test, but still move the inline test down after tcg_gen_insn_start. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-mips/translate.c')
-rw-r--r--target-mips/translate.c25
1 files changed, 10 insertions, 15 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 66147d887f..57e826db21 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19544,7 +19544,6 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
DisasContext ctx;
target_ulong pc_start;
target_ulong next_page_start;
- CPUBreakpoint *bp;
int j, lj = -1;
int num_insns;
int max_insns;
@@ -19591,20 +19590,6 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
gen_tb_start(tb);
while (ctx.bstate == BS_NONE) {
- if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
- QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
- if (bp->pc == ctx.pc) {
- save_cpu_state(&ctx, 1);
- ctx.bstate = BS_BRANCH;
- gen_helper_raise_exception_debug(cpu_env);
- /* Include the breakpoint location or the tb won't
- * be flushed when it must be. */
- ctx.pc += 4;
- goto done_generating;
- }
- }
- }
-
if (search_pc) {
j = tcg_op_buf_count();
if (lj < j) {
@@ -19621,6 +19606,16 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
tcg_gen_insn_start(ctx.pc);
num_insns++;
+ if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
+ save_cpu_state(&ctx, 1);
+ ctx.bstate = BS_BRANCH;
+ gen_helper_raise_exception_debug(cpu_env);
+ /* Include the breakpoint location or the tb won't
+ * be flushed when it must be. */
+ ctx.pc += 4;
+ goto done_generating;
+ }
+
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
}