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authorLeon Alrae <leon.alrae@imgtec.com>2014-07-07 11:23:58 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2014-11-03 11:48:34 +0000
commit2fb58b73746e2f99ac85e82160277b18b18279be (patch)
treecedded3812b8bd8cf5718c655420673c3a6b6ba7 /target-mips/cpu.h
parent9f6bcedba61927438000fb94b0706c22dfb87eaa (diff)
downloadqemu-arm-2fb58b73746e2f99ac85e82160277b18b18279be.tar.gz
target-mips: add RI and XI fields to TLB entry
In Revision 3 of the architecture, the RI and XI bits were added to the TLB to enable more secure access of memory pages. These bits (along with the Dirty bit) allow the implementation of read-only, write-only, no-execute access policies for mapped pages. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target-mips/cpu.h')
-rw-r--r--target-mips/cpu.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 91e781e26a..13f3a48198 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -30,6 +30,10 @@ struct r4k_tlb_t {
uint_fast16_t V1:1;
uint_fast16_t D0:1;
uint_fast16_t D1:1;
+ uint_fast16_t XI0:1;
+ uint_fast16_t XI1:1;
+ uint_fast16_t RI0:1;
+ uint_fast16_t RI1:1;
target_ulong PFN[2];
};
@@ -229,6 +233,13 @@ struct CPUMIPSState {
#define CP0VPEOpt_DWX0 0
target_ulong CP0_EntryLo0;
target_ulong CP0_EntryLo1;
+#if defined(TARGET_MIPS64)
+# define CP0EnLo_RI 63
+# define CP0EnLo_XI 62
+#else
+# define CP0EnLo_RI 31
+# define CP0EnLo_XI 30
+#endif
target_ulong CP0_Context;
target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
int32_t CP0_PageMask;