diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2012-07-12 10:59:04 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-07-12 10:59:53 +0000 |
| commit | ed336850e830711a3b940a1d311b5958f439f342 (patch) | |
| tree | a27ad82502a8d72d4f033587e756e7b5950c8a4b /target-arm | |
| parent | 091fd17ce8ebdc2922d536e13d2bb96f8acc83f0 (diff) | |
target-arm: Fix TCG temp handling in 64 bit cp writes
Fix errors in the TCG temp handling in the 64 bit coprocessor
write path: we were reusing a 32 bit temp after it had been
freed by store_reg(), and failing to free a 64 bit temp.
This bug has no visible effect at this point because there
aren't any non-NOP 64 bit registers yet; it needs to be fixed
as a prerequisite for the 64 bit registers in LPAE support.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/translate.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index f39b9caa28..29008a4b34 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6263,7 +6263,9 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) tcg_gen_trunc_i64_i32(tmp, tmp64); store_reg(s, rt, tmp); tcg_gen_shri_i64(tmp64, tmp64, 32); + tmp = tcg_temp_new_i32(); tcg_gen_trunc_i64_i32(tmp, tmp64); + tcg_temp_free_i64(tmp64); store_reg(s, rt2, tmp); } else { TCGv tmp; |