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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-04-07 22:31:26 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-04-07 22:31:26 +0000
commit2642cdb33b3f7469ec679f1034870b96178ca05a (patch)
treed37f27297f54ae2aadbf70cfcfddb4764b32642a /target-alpha/cpu.h
parent100d9891d61956e503f4ef6f69f73bf2f74b7818 (diff)
target-alpha: document more registers used by 21264
Signed-off-by: Tristan Gingold <gingold@adacore.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7032 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-alpha/cpu.h')
-rw-r--r--target-alpha/cpu.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 582827e55a..8c64def768 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -158,7 +158,7 @@ enum {
IPR_ITB_PTE = 0x01, /* 21264 */
IPR_ITB_IAP = 0x02,
IPR_ITB_IA = 0x03, /* 21264 */
- IPR_ITB_IS = 0x04,
+ IPR_ITB_IS = 0x04, /* 21264 */
IPR_PMPC = 0x05,
IPR_EXC_ADDR = 0x06, /* 21264 */
IPR_IVA_FORM = 0x07, /* 21264 */
@@ -221,7 +221,7 @@ enum {
IPR_M_CTL = 0x28, /* 21264 */
#define IPR_M_CTL_SPE_SHIFT 1
#define IPR_M_CTL_SPE_MASK 7
- IPR_DC_CTL = 0x29,
+ IPR_DC_CTL = 0x29, /* 21264 */
IPR_DC_STAT = 0x2A, /* 21264 */
/* Cbox IPRs */
IPR_C_DATA = 0x2B,