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authorPeter Maydell <peter.maydell@linaro.org>2019-02-01 14:55:43 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-02-01 14:55:43 +0000
commitade67dcd4ac1786637d25bb04a13c836357f44fc (patch)
tree4b32bbd589bb2ff97ca064d928cb8f4d41fcad0b /include
parent5aeb36896600ff92aee1083ed17e80f069befb93 (diff)
hw/arm/armsse: Add CPU_IDENTITY block to SSE-200
Instantiate a copy of the CPU_IDENTITY register block for each CPU in an SSE-200. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-21-peter.maydell@linaro.org
Diffstat (limited to 'include')
-rw-r--r--include/hw/arm/armsse.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index 961dbb3032..3914e8e4bf 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -78,6 +78,7 @@
#include "hw/watchdog/cmsdk-apb-watchdog.h"
#include "hw/misc/iotkit-sysctl.h"
#include "hw/misc/iotkit-sysinfo.h"
+#include "hw/misc/armsse-cpuid.h"
#include "hw/misc/unimp.h"
#include "hw/or-irq.h"
#include "hw/core/split-irq.h"
@@ -153,6 +154,8 @@ typedef struct ARMSSE {
UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
+ ARMSSECPUID cpuid[SSE_MAX_CPUS];
+
/*
* 'container' holds all devices seen by all CPUs.
* 'cpu_container[i]' is the view that CPU i has: this has the