diff options
| author | Bin Meng <bin.meng@windriver.com> | 2020-09-01 09:39:08 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:18 -0700 |
| commit | 47374b0761c1e3b6bff210dbb9d1a965e71c213e (patch) | |
| tree | 82f2cae6bd764051de7d94493d68cbc9673d671f /include/hw | |
| parent | dfc388797cc413072e58a8f9a831633f29212448 (diff) | |
hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
Microchip PolarFire SoC integrates 2 Candence GEMs to provide
IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.
On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
GEM1 connects to a PHY at address 9.
The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we
must specify 2 '-nic' options from the command line in order to get
a working ethernet.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-14-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/riscv/microchip_pfsoc.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 63e786052a..6d20853039 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -24,6 +24,7 @@ #include "hw/char/mchp_pfsoc_mmuart.h" #include "hw/dma/sifive_pdma.h" +#include "hw/net/cadence_gem.h" #include "hw/sd/cadence_sdhci.h" typedef struct MicrochipPFSoCState { @@ -42,6 +43,8 @@ typedef struct MicrochipPFSoCState { MchpPfSoCMMUartState *serial3; MchpPfSoCMMUartState *serial4; SiFivePDMAState dma; + CadenceGEMState gem0; + CadenceGEMState gem1; CadenceSDHCIState sdhci; } MicrochipPFSoCState; @@ -84,6 +87,8 @@ enum { MICROCHIP_PFSOC_MMUART2, MICROCHIP_PFSOC_MMUART3, MICROCHIP_PFSOC_MMUART4, + MICROCHIP_PFSOC_GEM0, + MICROCHIP_PFSOC_GEM1, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, MICROCHIP_PFSOC_IOSCB_CFG, @@ -99,6 +104,8 @@ enum { MICROCHIP_PFSOC_DMA_IRQ5 = 10, MICROCHIP_PFSOC_DMA_IRQ6 = 11, MICROCHIP_PFSOC_DMA_IRQ7 = 12, + MICROCHIP_PFSOC_GEM0_IRQ = 64, + MICROCHIP_PFSOC_GEM1_IRQ = 70, MICROCHIP_PFSOC_EMMC_SD_IRQ = 88, MICROCHIP_PFSOC_MMUART0_IRQ = 90, MICROCHIP_PFSOC_MMUART1_IRQ = 91, |