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authorAurelien Jarno <aurelien@aurel32.net>2013-08-28 14:17:39 +0200
committerStefan Hajnoczi <stefanha@redhat.com>2013-09-20 19:49:14 +0200
commita26405b350c0d31d5ef53f3b459aeb6eaaf50db0 (patch)
treeb630e6c31dbd038c5ceee32dbbe16c40333294e4 /hw/net/pcnet-pci.c
parent6c2679fc19560699679200fb42ab4659bcbe7f79 (diff)
pcnet-pci: mark I/O and MMIO as LITTLE_ENDIAN
Now that the memory subsystem is propagating the endianness correctly, the pcnet-pci device should have its I/O ports and MMIO memory marked as LITTLE_ENDIAN, as PCI devices are little endian. This makes the pcnet-pci NIC to work again on big endian MIPS Malta (default NIC). Cc: qemu-stable@nongnu.org Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'hw/net/pcnet-pci.c')
-rw-r--r--hw/net/pcnet-pci.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c
index a8931652b3..865f2f0c59 100644
--- a/hw/net/pcnet-pci.c
+++ b/hw/net/pcnet-pci.c
@@ -134,7 +134,7 @@ static void pcnet_ioport_write(void *opaque, hwaddr addr,
static const MemoryRegionOps pcnet_io_ops = {
.read = pcnet_ioport_read,
.write = pcnet_ioport_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
@@ -256,7 +256,7 @@ static const MemoryRegionOps pcnet_mmio_ops = {
.read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
.write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,