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authorPeter Maydell <peter.maydell@linaro.org>2012-05-02 16:49:40 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-06-19 13:24:44 +0000
commit306a571a2d75e32cd2eae5486c2714b7b7792a63 (patch)
treea6e1b1e8a6587c808110024b35cc9631162ae4c7 /hw/arm_gic.c
parent2a29ddee82029580fa85276767f73fedc30c8a0a (diff)
hw/arm_gic: Add qdev property for GIC revision
GIC behaviour can be different between revision 1 and 2 of the architectural GIC specification; we also have to handle the legacy 11MPCore GIC, which is different again in some places. Introduce a qdev property so we can behave appropriately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm_gic.c')
-rw-r--r--hw/arm_gic.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 2ec10ce457..ad72ac65a9 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -119,8 +119,13 @@ typedef struct gic_state
struct gic_state *backref[NCPU];
MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */
uint32_t num_irq;
+ uint32_t revision;
} gic_state;
+/* The special cases for the revision property: */
+#define REV_11MPCORE 0
+#define REV_NVIC 0xffffffff
+
static inline int gic_get_current_cpu(gic_state *s)
{
if (s->num_cpu > 1) {
@@ -880,6 +885,11 @@ static int arm_gic_init(SysBusDevice *dev)
static Property arm_gic_properties[] = {
DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1),
DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32),
+ /* Revision can be 1 or 2 for GIC architecture specification
+ * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
+ * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
+ */
+ DEFINE_PROP_UINT32("revision", gic_state, revision, 1),
DEFINE_PROP_END_OF_LIST(),
};