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authorPeter Maydell <peter.maydell@linaro.org>2017-08-04 13:19:52 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-08-04 17:38:27 +0100
commit3fef6cf550b17dd89c3ccc8934231f9f526086cb (patch)
tree4c2faf63137725d2d77afa1d63659026a45ab1a7
parented23d60e59772bc8fa7a59f6e141c36480fc7e4b (diff)
downloadqemu-arm-txfail.tar.gz
target/arm: Implement new do_transaction_failed hooktxfail
Implement the new do_transaction_failed hook for ARM, which should cause the CPU to take a prefetch abort or data abort. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/cpu.c1
-rw-r--r--target/arm/internals.h10
-rw-r--r--target/arm/op_helper.c43
3 files changed, 54 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 05c038bf17..6baede0a99 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1670,6 +1670,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#else
cc->do_interrupt = arm_cpu_do_interrupt;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
+ cc->do_transaction_failed = arm_cpu_do_transaction_failed;
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
cc->vmsd = &vmstate_arm_cpu;
diff --git a/target/arm/internals.h b/target/arm/internals.h
index a3adbd8d09..13bb001bc4 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -471,6 +471,16 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
+/* arm_cpu_do_transaction_failed: handle a memory system error response
+ * (eg "no device/memory present at address") by raising an external abort
+ * exception
+ */
+void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
+
/* Call the EL change hook if one has been registered */
static inline void arm_call_el_change_hook(ARMCPU *cpu)
{
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 7eac2729d3..54b6dd8d61 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -229,6 +229,49 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi);
}
+/* arm_cpu_do_transaction_failed: handle a memory system error response
+ * (eg "no device/memory present at address") by raising an external abort
+ * exception
+ */
+void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ uint32_t fsr, fsc;
+ ARMMMUFaultInfo fi = {};
+ ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
+
+ if (retaddr) {
+ /* now we have a real cpu fault */
+ cpu_restore_state(cs, retaddr);
+ }
+
+ /* The EA bit in syndromes and fault status registers is an
+ * IMPDEF classification of external aborts. ARM implementations
+ * usually use this to indicate AXI bus Decode error (0) or
+ * Slave error (1); in QEMU we follow that.
+ */
+ fi.ea = (response != MEMTX_DECODE_ERROR);
+
+ /* The fault status register format depends on whether we're using
+ * the LPAE long descriptor format, or the short descriptor format.
+ */
+ if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
+ /* long descriptor form, STATUS 0b010000: synchronous ext abort */
+ fsr = (fi.ea << 12) | (1 << 9) | 0x10;
+ } else {
+ /* short descriptor form, FSR 0b01000 : synchronous ext abort */
+ fsr = (fi.ea << 12) | 0x8;
+ }
+ fsc = 0x10;
+
+ deliver_fault(cpu, addr, access_type, fsr, fsc, &fi);
+}
+
#endif /* !defined(CONFIG_USER_ONLY) */
uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)