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authorPeter Maydell <peter.maydell@linaro.org>2018-07-24 12:42:27 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-07-24 12:49:51 +0100
commit56ad3aadb7d2cb7f9993c59f31f36ae25c4a5cb4 (patch)
tree9ca0c4a56967d08eb120d1fff55c03eb2e419583
parent4556438d0cdf8d83eda18551df7821e3fb1714a9 (diff)
downloadqemu-arm-tge.tar.gz
target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is settge
One of the required effects of setting HCR_EL2.TGE is that when SCR_EL3.NS is 1 then SCTLR_EL1.M must behave as if it is zero for all purposes except direct reads. That is, it effectively disables the MMU for the NS EL0/EL1 translation regime. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/helper.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 699189ebd7..efd258fdb5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8402,6 +8402,14 @@ static inline bool regime_translation_disabled(CPUARMState *env,
if (mmu_idx == ARMMMUIdx_S2NS) {
return (env->cp15.hcr_el2 & HCR_VM) == 0;
}
+
+ if (env->cp15.hcr_el2 & HCR_TGE) {
+ /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
+ if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) {
+ return true;
+ }
+ }
+
return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
}