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authorPeter Maydell <peter.maydell@linaro.org>2022-05-03 11:04:09 +0100
committerPeter Maydell <peter.maydell@linaro.org>2022-05-03 11:04:09 +0100
commitd620293bd53bdb2e36826e2b16bf0690956d4386 (patch)
treefcb5c6b679e42dea33c361203bf7e5e3512d74f4
parentf5643914a9e8f79c606a76e6a9d7ea82a3fc3e65 (diff)
debug junkm1-debug
-rw-r--r--target/arm/kvm.c21
-rw-r--r--target/arm/kvm64.c15
2 files changed, 34 insertions, 2 deletions
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 5fc37ac10a..00d58c0954 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -518,7 +518,7 @@ bool write_kvmstate_to_list(ARMCPU *cpu)
CPUState *cs = CPU(cpu);
int i;
bool ok = true;
-
+ printf("write_kvmstate_to_list: CPU %p\n", cpu);
for (i = 0; i < cpu->cpreg_array_len; i++) {
struct kvm_one_reg r;
uint64_t regidx = cpu->cpreg_indexes[i];
@@ -545,6 +545,11 @@ bool write_kvmstate_to_list(ARMCPU *cpu)
if (ret) {
ok = false;
}
+ else if (r.id == 0x603000000013c020) {
+ printf("write_kvmstate_to_list cpu %p KVM id 0x%" PRIx64
+ " read 0x%" PRIx64 "\n", cpu, (uint64_t)r.id,
+ (uint64_t)cpu->cpreg_values[i]);
+ }
}
return ok;
}
@@ -577,6 +582,11 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
default:
abort();
}
+ if (r.id == 0x603000000013c020) {
+ printf("write_list_to_kvmstate cpu %p KVM id 0x%" PRIx64
+ " writing 0x%" PRIx64 "\n", cpu, (uint64_t)r.id,
+ (uint64_t)cpu->cpreg_values[i]);
+ }
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
if (ret) {
/* We might fail for "unknown register" and also for
@@ -584,6 +594,15 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
* a different value from what it actually contains".
*/
ok = false;
+#define F(ID, N) (int)((ID & KVM_REG_ARM64_SYSREG_##N##_MASK) >> KVM_REG_ARM64_SYSREG_##N##_SHIFT)
+ printf("write_list_to_kvmstate cpu %p KVM id 0x%" PRIx64
+ " == (%d, %d, cr%d, cr%d, %d)"
+ " writing 0x%" PRIx64 " failed errno %d (%s)\n",
+ cpu, (uint64_t)r.id,
+ F(r.id, OP0), F(r.id, OP1), F(r.id, CRN), F(r.id, CRM),
+ F(r.id, OP2), (uint64_t)cpu->cpreg_values[i],
+ -ret, strerror(-ret));
+#undef F
}
}
return ok;
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index b8cfaf5782..48a3e10d96 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -1096,7 +1096,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
-
+printf("kvm_arch_put_registers for cpu %p\n", cpu);
/* If we are in AArch32 mode then we need to copy the AArch32 regs to the
* AArch64 registers before pushing them out to 64-bit KVM.
*/
@@ -1109,6 +1109,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
reg.addr = (uintptr_t) &env->xregs[i];
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
if (ret) {
+printf("FAIL cpu %p KVM_SET_ONE_REG for core reg %d\n", cpu, i);
return ret;
}
}
@@ -1122,6 +1123,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
reg.addr = (uintptr_t) &env->sp_el[0];
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
if (ret) {
+printf("FAIL cpu %p KVM_SET_ONE_REG for sp_el0\n", cpu);
return ret;
}
@@ -1129,6 +1131,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
reg.addr = (uintptr_t) &env->sp_el[1];
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
if (ret) {
+printf("FAIL cpu %p KVM_SET_ONE_REG for sp_el1\n", cpu);
return ret;
}
@@ -1142,6 +1145,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
reg.addr = (uintptr_t) &val;
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
if (ret) {
+printf("FAIL cpu %p KVM_SET_ONE_REG for pstate\n", cpu);
return ret;
}
@@ -1149,6 +1153,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
reg.addr = (uintptr_t) &env->pc;
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
if (ret) {
+printf("FAIL cpu %p KVM_SET_ONE_REG for PC\n", cpu);
return ret;
}
@@ -1156,6 +1161,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
reg.addr = (uintptr_t) &env->elr_el[1];
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
if (ret) {
+printf("FAIL cpu %p KVM_SET_ONE_REG for ELR_EL1\n", cpu);
return ret;
}
@@ -1177,6 +1183,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
if (ret) {
+printf("FAIL cpu %p KVM_SET_ONE_REG for SPSR %d\n", cpu, i);
return ret;
}
}
@@ -1187,6 +1194,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
ret = kvm_arch_put_fpsimd(cs);
}
if (ret) {
+printf("FAIL cpu %p KVM_SET_ONE_REG for FP regs\n", cpu);
return ret;
}
@@ -1195,6 +1203,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
if (ret) {
+printf("FAIL cpu %p KVM_SET_ONE_REG for FPSR\n", cpu);
return ret;
}
@@ -1203,12 +1212,14 @@ int kvm_arch_put_registers(CPUState *cs, int level)
reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
if (ret) {
+printf("FAIL cpu %p KVM_SET_ONE_REG for FPCR\n", cpu);
return ret;
}
write_cpustate_to_list(cpu, true);
if (!write_list_to_kvmstate(cpu, level)) {
+printf("FAIL cpu %p write_list_to_kvmstate\n", cpu);
return -EINVAL;
}
@@ -1219,8 +1230,10 @@ int kvm_arch_put_registers(CPUState *cs, int level)
*/
ret = kvm_put_vcpu_events(cpu);
if (ret) {
+printf("FAIL cpu %p kvm_put_vcpu_events\n", cpu);
return ret;
}
+printf("kvm_arch_put_registers calling sync mpstate for cpu %p\n", cpu);
kvm_arm_sync_mpstate_to_kvm(cpu);