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authorAlex Bennée <alex.bennee@linaro.org>2015-03-23 17:05:44 +0000
committerPeter Maydell <peter.maydell@linaro.org>2015-03-26 17:07:36 +0000
commit7ae4f826b095db40a2f8d4c200320e6e8c1df8ce (patch)
parentec3dafeab3745d09f073d7bb13e8f623401fa0cd (diff)
target-arm: cpu.h document why env->spsr existskvm-sync-test
I was getting very confused about the duplication of state so wanted to make it explicit. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1427130344-27986-7-git-send-email-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
1 files changed, 5 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 083211ce39..6dc1799aa4 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -155,6 +155,11 @@ typedef struct CPUARMState {
This contains all the other bits. Use cpsr_{read,write} to access
the whole CPSR. */
uint32_t uncached_cpsr;
+ /* The spsr is a alias for spsr_elN where N is the current
+ * exception level. It is provided for here so the TCG msr/mrs
+ * implementation can access one register. Care needs to be taken
+ * to ensure the banked_spsr[] is also updated.
+ */
uint32_t spsr;
/* Banked registers. */