diff options
authorPeter Maydell <peter.maydell@linaro.org>2018-04-06 17:52:34 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-04-06 17:52:34 +0100
commit5a7d211bbd9fb2766ab91eb56d4e5e078be62365 (patch)
parent31d4f5487313eb5c073eb8e3fa1b03828a73b253 (diff)
target/arm: Don't corrupt insn_start arguments on 32-bit hostsicount-debug
For the Arm target, we have a 3-operand tcg_insn_start, where the 3 arguments are the PC, condexec bits, and a syndrome value. We set it up like this: tcg_gen_insn_start(dc->pc, (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), 0); dc->insn_start = tcg_last_op(); and then we patch in the 3rd operand later in disas_set_insn_syndrome(): tcg_set_insn_param(s->insn_start, 2, syn); Unfortunately, if we're running on a setup where TARGET_LONG_BITS > TCG_TARGET_REG_BITS (ie 64 bit guest on 32 bit host), tcg_gen_insn_start() has under the hood split the 3 operands we gave it into 6, and so we end up patching a syndrome value into the condexec bits. This means we'll end up with corrupted guest condexec state if we have to do a cpu_restore_state(), which happens often when using icount and occasionally for load/store instructions that fault. Fix the bug by using the correct operand offset for the 64-on-32 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
1 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h
index c47febf99d..f04ece9cfd 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -120,7 +120,15 @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
/* We check and clear insn_start_idx to catch multiple updates. */
assert(s->insn_start != NULL);
tcg_set_insn_param(s->insn_start, 2, syn);
+ /* tcg_gen_insn_start has split every target_ulong argument to
+ * op_insn_start into two 32-bit arguments, so we want the low
+ * half of the 3rd argument, which is at index 4.
+ */
+ tcg_set_insn_param(s->insn_start, 4, syn);
s->insn_start = NULL;