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authorPeter Maydell <peter.maydell@linaro.org>2012-04-14 15:26:33 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-04-20 16:49:21 +0000
commit8cff93a1b62a2472d027f679d5877e58cc03a07f (patch)
tree9a927933c4014d1d9e34d0f10c076245737d1e62
parent0389451a61a6b8c2c2641b7019677e7e2ecd4bd8 (diff)
downloadqemu-arm-drop-reset-model-id.tar.gz
target-arm: Move A9 config_base_address reset value to ARMCPUdrop-reset-model-id
Move the A9 config_base_address cp15 register reset value to ARMCPU. This should become a QOM property so that the Highbank board can set it without having to pull in cpu-qom.h, but at least this avoids the implicit dependency on reset ordering that the previous workaround had. Cc: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/highbank.c11
-rw-r--r--target-arm/cpu-qom.h1
-rw-r--r--target-arm/cpu.c4
3 files changed, 6 insertions, 10 deletions
diff --git a/hw/highbank.c b/hw/highbank.c
index 906eed5a47..9ff639bd53 100644
--- a/hw/highbank.c
+++ b/hw/highbank.c
@@ -35,12 +35,6 @@
#define NIRQ_GIC 160
/* Board init. */
-static void highbank_cpu_reset(void *opaque)
-{
- CPUARMState *env = opaque;
-
- env->cp15.c15_config_base_address = GIC_BASE_ADDR;
-}
static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
{
@@ -213,14 +207,17 @@ static void highbank_init(ram_addr_t ram_size,
}
for (n = 0; n < smp_cpus; n++) {
+ ARMCPU *cpu;
env = cpu_init(cpu_model);
if (!env) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
+ cpu = arm_env_get_cpu(env);
+ /* This will become a QOM property eventually */
+ cpu->reset_cbar = GIC_BASE_ADDR;
irqp = arm_pic_init_cpu(env);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
- qemu_register_reset(highbank_cpu_reset, env);
}
sysmem = get_system_memory();
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index b6c044a251..4abfa909a8 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -94,6 +94,7 @@ typedef struct ARMCPU {
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
*/
uint32_t ccsidr[16];
+ uint32_t reset_cbar;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index cc67d4d9f4..3ad1d3a4d4 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -30,7 +30,6 @@ static void arm_cpu_reset(CPUState *s)
ARMCPU *cpu = ARM_CPU(s);
ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
CPUARMState *env = &cpu->env;
- uint32_t tmp = 0;
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@@ -39,9 +38,8 @@ static void arm_cpu_reset(CPUState *s)
acc->parent_reset(s);
- tmp = env->cp15.c15_config_base_address;
memset(env, 0, offsetof(CPUARMState, breakpoints));
- env->cp15.c15_config_base_address = tmp;
+ env->cp15.c15_config_base_address = cpu->reset_cbar;
env->cp15.c0_cpuid = cpu->midr;
env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;