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authorPeter Maydell <peter.maydell@linaro.org>2017-01-10 18:26:55 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-01-10 18:35:32 +0000
commit152d2f91af89d446f4a1e0b7e862263136eacd0e (patch)
treee040bd797955a667a5ab28d97b576b7e2da01ade
parentd89f9aef81edef1de41bed428f9e380f40506c3c (diff)
downloadqemu-arm-aarch32-guest.tar.gz
target/arm: Implement DBGVCR32_EL2 system registeraarch32-guest
The DBGVCR_EL2 system register is needed to run a 32-bit EL1 guest under a Linux EL2 64-bit hypervisor. Its only purpose is to provide AArch64 with access to the state of the DBGVCR AArch32 register. Since we only have a dummy DBGVCR, implement a corresponding dummy DBGVCR32_EL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/helper.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index dc9098658b..bda562d779 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4066,6 +4066,13 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
.cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tda,
.type = ARM_CP_NOP },
+ /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
+ * to save and restore a 32-bit guest's DBGVCR)
+ */
+ { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
+ .access = PL2_RW, .accessfn = access_tda,
+ .type = ARM_CP_NOP },
/* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
* Channel but Linux may try to access this register. The 32-bit
* alias is DBGDCCINT.