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authorPeter Maydell <peter.maydell@linaro.org>2014-03-09 11:57:03 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-03-09 14:42:44 +0000
commit0cfd8b91bb9c65e61ee7a62faf217020f50289fc (patch)
treed10f266e0e67a4be928920fef37634af8a5c8863
parent24fd8eaa2c4c58a59245330ac452f114f196dc7d (diff)
exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decodera64-neon-sixth-set
The ARM A64 decoder's worst case number of TCG ops per instruction is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures store). Raise the MAX_OP_PER_INSTR define accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--include/exec/exec-all.h2
-rw-r--r--target-arm/translate-a64.c12
2 files changed, 11 insertions, 3 deletions
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index a387922df4..6af84f6798 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -44,7 +44,7 @@ struct TranslationBlock;
typedef struct TranslationBlock TranslationBlock;
/* XXX: make safe guess about sizes */
-#define MAX_OP_PER_INSTR 208
+#define MAX_OP_PER_INSTR 266
#if HOST_LONG_BITS == 32
#define MAX_OPC_PARAM_PER_ARG 2
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 6a3597d4a3..2435c95319 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -9007,9 +9007,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x19: /* FRINTM */
case 0x38: /* FRINTP */
case 0x39: /* FRINTZ */
- case 0x58: /* FRINTA */
need_rmode = true;
- rmode = extract32(opcode, 5, 2) | (extract32(opcode, 0, 1) << 1);
+ rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
/* fall through */
case 0x59: /* FRINTX */
case 0x79: /* FRINTI */
@@ -9019,6 +9018,15 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
return;
}
break;
+ case 0x58: /* FRINTA */
+ need_rmode = true;
+ rmode = FPROUNDING_TIEAWAY;
+ need_fpstatus = true;
+ if (size == 3 && !is_q) {
+ unallocated_encoding(s);
+ return;
+ }
+ break;
case 0x3c: /* URECPE */
case 0x3d: /* FRECPE */
case 0x56: /* FCVTXN, FCVTXN2 */