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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-04-29 17:35:58 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-04-29 17:35:58 +0100 |
| commit | 5bcf8ed9401e62c73158ba110864ee1375558bf7 (patch) | |
| tree | e2dd89a4d14dda037265098490ed736c0cbe4fe6 /.gitlab-ci.yml | |
| parent | 79d77bcd366190a81d092177e4f84d34b7a56fc2 (diff) | |
target/arm: Make sure M-profile FPSCR RES0 bits are not settable
Enforce that for M-profile various FPSCR bits which are RES0 there
but have defined meanings on A-profile are never settable. This
ensures that M-profile code can't enable the A-profile behaviour
(notably vector length/stride handling) by accident.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-2-peter.maydell@linaro.org
Diffstat (limited to '.gitlab-ci.yml')
0 files changed, 0 insertions, 0 deletions