blob: 3b52f98478db05c036cd87d7ce8655a8cc872b90 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
* Copyright (C) 2017 Linaro Ltd.
*/
#ifndef __VENUS_HFI_VENUS_IO_H__
#define __VENUS_HFI_VENUS_IO_H__
#define VBIF_BASE 0x80000
#define VBIF_AXI_HALT_CTRL0 (VBIF_BASE + 0x208)
#define VBIF_AXI_HALT_CTRL1 (VBIF_BASE + 0x20c)
#define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
#define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
#define VBIF_AXI_HALT_ACK_TIMEOUT_US 500000
#define CPU_BASE 0xc0000
#define CPU_CS_BASE (CPU_BASE + 0x12000)
#define CPU_IC_BASE (CPU_BASE + 0x1f000)
#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE + 0x1c)
#define VIDC_CTRL_INIT (CPU_CS_BASE + 0x48)
#define VIDC_CTRL_INIT_RESERVED_BITS31_1_MASK 0xfffffffe
#define VIDC_CTRL_INIT_RESERVED_BITS31_1_SHIFT 1
#define VIDC_CTRL_INIT_CTRL_MASK 0x1
#define VIDC_CTRL_INIT_CTRL_SHIFT 0
/* HFI control status */
#define CPU_CS_SCIACMDARG0 (CPU_CS_BASE + 0x4c)
#define CPU_CS_SCIACMDARG0_MASK 0xff
#define CPU_CS_SCIACMDARG0_SHIFT 0x0
#define CPU_CS_SCIACMDARG0_ERROR_STATUS_MASK 0xfe
#define CPU_CS_SCIACMDARG0_ERROR_STATUS_SHIFT 0x1
#define CPU_CS_SCIACMDARG0_INIT_STATUS_MASK 0x1
#define CPU_CS_SCIACMDARG0_INIT_STATUS_SHIFT 0x0
#define CPU_CS_SCIACMDARG0_PC_READY BIT(8)
#define CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK BIT(30)
/* HFI queue table info */
#define CPU_CS_SCIACMDARG1 (CPU_CS_BASE + 0x50)
/* HFI queue table address */
#define CPU_CS_SCIACMDARG2 (CPU_CS_BASE + 0x54)
/* Venus cpu */
#define CPU_CS_SCIACMDARG3 (CPU_CS_BASE + 0x58)
#define SFR_ADDR (CPU_CS_BASE + 0x5c)
#define MMAP_ADDR (CPU_CS_BASE + 0x60)
#define UC_REGION_ADDR (CPU_CS_BASE + 0x64)
#define UC_REGION_SIZE (CPU_CS_BASE + 0x68)
#define CPU_IC_SOFTINT (CPU_IC_BASE + 0x18)
#define CPU_IC_SOFTINT_H2A_MASK 0x8000
#define CPU_IC_SOFTINT_H2A_SHIFT 0xf
/* Venus wrapper */
#define WRAPPER_BASE 0x000e0000
#define WRAPPER_HW_VERSION (WRAPPER_BASE + 0x00)
#define WRAPPER_HW_VERSION_MAJOR_VERSION_MASK 0x78000000
#define WRAPPER_HW_VERSION_MAJOR_VERSION_SHIFT 28
#define WRAPPER_HW_VERSION_MINOR_VERSION_MASK 0xfff0000
#define WRAPPER_HW_VERSION_MINOR_VERSION_SHIFT 16
#define WRAPPER_HW_VERSION_STEP_VERSION_MASK 0xffff
#define WRAPPER_CLOCK_CONFIG (WRAPPER_BASE + 0x04)
#define WRAPPER_INTR_STATUS (WRAPPER_BASE + 0x0c)
#define WRAPPER_INTR_STATUS_A2HWD_MASK 0x10
#define WRAPPER_INTR_STATUS_A2HWD_SHIFT 0x4
#define WRAPPER_INTR_STATUS_A2H_MASK 0x4
#define WRAPPER_INTR_STATUS_A2H_SHIFT 0x2
#define WRAPPER_INTR_MASK (WRAPPER_BASE + 0x10)
#define WRAPPER_INTR_MASK_A2HWD_BASK 0x10
#define WRAPPER_INTR_MASK_A2HWD_SHIFT 0x4
#define WRAPPER_INTR_MASK_A2HVCODEC_MASK 0x8
#define WRAPPER_INTR_MASK_A2HVCODEC_SHIFT 0x3
#define WRAPPER_INTR_MASK_A2HCPU_MASK 0x4
#define WRAPPER_INTR_MASK_A2HCPU_SHIFT 0x2
#define WRAPPER_INTR_CLEAR (WRAPPER_BASE + 0x14)
#define WRAPPER_INTR_CLEAR_A2HWD_MASK 0x10
#define WRAPPER_INTR_CLEAR_A2HWD_SHIFT 0x4
#define WRAPPER_INTR_CLEAR_A2H_MASK 0x4
#define WRAPPER_INTR_CLEAR_A2H_SHIFT 0x2
#define WRAPPER_POWER_STATUS (WRAPPER_BASE + 0x44)
#define WRAPPER_VDEC_VCODEC_POWER_CONTROL (WRAPPER_BASE + 0x48)
#define WRAPPER_VENC_VCODEC_POWER_CONTROL (WRAPPER_BASE + 0x4c)
#define WRAPPER_VDEC_VENC_AHB_BRIDGE_SYNC_RESET (WRAPPER_BASE + 0x64)
#define WRAPPER_CPU_CLOCK_CONFIG (WRAPPER_BASE + 0x2000)
#define WRAPPER_CPU_AXI_HALT (WRAPPER_BASE + 0x2008)
#define WRAPPER_CPU_AXI_HALT_HALT BIT(16)
#define WRAPPER_CPU_AXI_HALT_STATUS (WRAPPER_BASE + 0x200c)
#define WRAPPER_CPU_AXI_HALT_STATUS_IDLE BIT(24)
#define WRAPPER_CPU_CGC_DIS (WRAPPER_BASE + 0x2010)
#define WRAPPER_CPU_STATUS (WRAPPER_BASE + 0x2014)
#define WRAPPER_CPU_STATUS_WFI BIT(0)
#define WRAPPER_SW_RESET (WRAPPER_BASE + 0x3000)
#define WRAPPER_CPA_START_ADDR (WRAPPER_BASE + 0x1020)
#define WRAPPER_CPA_END_ADDR (WRAPPER_BASE + 0x1024)
#define WRAPPER_FW_START_ADDR (WRAPPER_BASE + 0x1028)
#define WRAPPER_FW_END_ADDR (WRAPPER_BASE + 0x102C)
#define WRAPPER_NONPIX_START_ADDR (WRAPPER_BASE + 0x1030)
#define WRAPPER_NONPIX_END_ADDR (WRAPPER_BASE + 0x1034)
#define WRAPPER_A9SS_SW_RESET (WRAPPER_BASE + 0x3000)
#define WRAPPER_A9SS_SW_RESET_BIT BIT(4)
/* Venus 4xx */
#define WRAPPER_VCODEC0_MMCC_POWER_STATUS (WRAPPER_BASE + 0x90)
#define WRAPPER_VCODEC0_MMCC_POWER_CONTROL (WRAPPER_BASE + 0x94)
#define WRAPPER_VCODEC1_MMCC_POWER_STATUS (WRAPPER_BASE + 0x110)
#define WRAPPER_VCODEC1_MMCC_POWER_CONTROL (WRAPPER_BASE + 0x114)
#endif
|
