diff options
Diffstat (limited to 'arch')
286 files changed, 42826 insertions, 1445 deletions
diff --git a/arch/.gitignore b/arch/.gitignore deleted file mode 100644 index a1fbe01d57..0000000000 --- a/arch/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/*/include/asm/arch -/*/include/asm/proc diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 3c5f987167..8a97e15d1e 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -21,38 +21,58 @@ # MA 02111-1307 USA # -CROSS_COMPILE ?= arm-linux- +CROSS_COMPILE ?= arm-eabi- ifndef CONFIG_STANDALONE_LOAD_ADDR ifeq ($(SOC),omap3) CONFIG_STANDALONE_LOAD_ADDR = 0x80300000 else -CONFIG_STANDALONE_LOAD_ADDR = 0xc100000 +CONFIG_STANDALONE_LOAD_ADDR = 0x80008000 endif endif PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ -# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: -PF_CPPFLAGS_ARM := $(call cc-option,-marm,) +# Choose between ARM/Thumb instruction sets +ifeq ($(CONFIG_SYS_THUMB_BUILD),y) +PF_CPPFLAGS_ARM := $(call cc-option, -mthumb -mthumb-interwork,\ + $(call cc-option,-marm,)\ + $(call cc-option,-mno-thumb-interwork,)\ + ) +else +PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \ + $(call cc-option,-mno-thumb-interwork,) +endif +# Only test once +ifneq ($(CONFIG_SPL_BUILD),y) +ALL-$(CONFIG_SYS_THUMB_BUILD) += checkthumb +endif +ifeq ($(CONFIG_SPL_BUILD),y) + ifeq ($(CONFIG_SPL_THUMB_BUILD),y) +PF_CPPFLAGS_ARM := $(call cc-option, -mthumb -mthumb-interwork,\ + $(call cc-option,-marm,)\ + $(call cc-option,-mno-thumb-interwork,)\ + ) + endif +endif # Try if EABI is supported, else fall back to old API, # i. e. for example: # - with ELDK 4.2 (EABI supported), use: -# -mabi=aapcs-linux -mno-thumb-interwork +# -mabi=aapcs-linux # - with ELDK 4.1 (gcc 4.x, no EABI), use: -# -mabi=apcs-gnu -mno-thumb-interwork +# -mabi=apcs-gnu # - with ELDK 3.1 (gcc 3.x), use: -# -mapcs-32 -mno-thumb-interwork +# -mapcs-32 PF_CPPFLAGS_ABI := $(call cc-option,\ - -mabi=aapcs-linux -mno-thumb-interwork,\ - $(call cc-option,\ - -mapcs-32,\ + -mabi=aapcs-linux,\ $(call cc-option,\ - -mabi=apcs-gnu,\ - )\ - ) $(call cc-option,-mno-thumb-interwork,)\ - ) + -mapcs-32,\ + $(call cc-option,\ + -mabi=apcs-gnu,\ + )\ + )\ + ) PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARM) $(PF_CPPFLAGS_ABI) # For EABI, make sure to provide raise() diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index ffb2e6c3ea..6a3a1bb354 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -31,3 +31,9 @@ PLATFORM_CPPFLAGS += -march=armv5te # ========================================================================= PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) + +ifneq ($(CONFIG_IMX_CONFIG),) + +ALL-y += $(obj)u-boot.imx + +endif diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile new file mode 100644 index 0000000000..ae1f0a5c0c --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 +# of the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301, USA. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS = cpu.o clk.o devices.o timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c new file mode 100644 index 0000000000..6f26d626a7 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <common.h> +#include <div64.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/io.h> + +static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; + +unsigned int get_sys_clk_rate(void) +{ + if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397) + return RTC_CLK_FREQUENCY * 397; + else + return OSC_CLK_FREQUENCY; +} + +unsigned int get_hclk_pll_rate(void) +{ + unsigned long long fin, fref, fcco, fout; + u32 val, m_div, n_div, p_div; + + /* + * Valid frequency ranges: + * 1 * 10^6 <= Fin <= 20 * 10^6 + * 1 * 10^6 <= Fref <= 27 * 10^6 + * 156 * 10^6 <= Fcco <= 320 * 10^6 + */ + + fref = fin = get_sys_clk_rate(); + if (fin > 20000000ULL || fin < 1000000ULL) + return 0; + + val = readl(&clk->hclkpll_ctrl); + m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1; + n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1; + if (val & CLK_HCLK_PLL_DIRECT) + p_div = 0; + else + p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1; + p_div = 1 << p_div; + + if (val & CLK_HCLK_PLL_BYPASS) { + do_div(fin, p_div); + return fin; + } + + do_div(fref, n_div); + if (fref > 27000000ULL || fref < 1000000ULL) + return 0; + + fout = fref * m_div; + if (val & CLK_HCLK_PLL_FEEDBACK) { + fcco = fout; + do_div(fout, p_div); + } else + fcco = fout * p_div; + + if (fcco > 320000000ULL || fcco < 156000000ULL) + return 0; + + return fout; +} + +unsigned int get_hclk_clk_div(void) +{ + u32 val; + + val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK; + + return 1 << val; +} + +unsigned int get_hclk_clk_rate(void) +{ + return get_hclk_pll_rate() / get_hclk_clk_div(); +} + +unsigned int get_periph_clk_div(void) +{ + u32 val; + + val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK; + + return (val >> 2) + 1; +} + +unsigned int get_periph_clk_rate(void) +{ + if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN)) + return get_sys_clk_rate(); + + return get_hclk_pll_rate() / get_periph_clk_div(); +} + +int get_serial_clock(void) +{ + return get_periph_clk_rate(); +} diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c new file mode 100644 index 0000000000..e29e130338 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/wdt.h> +#include <asm/io.h> + +static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; +static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE; + +void reset_cpu(ulong addr) +{ + /* Enable watchdog clock */ + setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); + + /* Reset pulse length is 13005 peripheral clock frames */ + writel(13000, &wdt->pulse); + + /* Force WDOG_RESET2 and RESOUT_N signal active */ + writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2, + &wdt->mctrl); + + while (1) + /* NOP */; +} + +#if defined(CONFIG_ARCH_CPU_INIT) +int arch_cpu_init(void) +{ + /* + * It might be necessary to flush data cache, if U-boot is loaded + * from kickstart bootloader, e.g. from S1L loader + */ + flush_dcache_all(); + + return 0; +} +#else +#error "You have to select CONFIG_ARCH_CPU_INIT" +#endif + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + printf("CPU: NXP LPC32XX\n"); + printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000); + printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000); + printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000); + + return 0; +} +#endif diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c new file mode 100644 index 0000000000..9f305b5ba5 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/uart.h> +#include <asm/io.h> + +static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; +static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; + +void lpc32xx_uart_init(unsigned int uart_id) +{ + if (uart_id < 1 || uart_id > 7) + return; + + /* Disable loopback mode, if it is set by S1L bootloader */ + clrbits_le32(&ctrl->loop, + UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART)); + + if (uart_id < 3 || uart_id > 6) + return; + + /* Enable UART system clock */ + setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id)); + + /* Set UART into autoclock mode */ + clrsetbits_le32(&ctrl->clkmode, + UART_CLKMODE_MASK(uart_id), + UART_CLKMODE_AUTO(uart_id)); + + /* Bypass pre-divider of UART clock */ + writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1), + &clk->u3clk + (uart_id - 3)); +} diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c new file mode 100644 index 0000000000..1ce2358afd --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/timer.h> +#include <asm/io.h> + +static struct timer_regs *timer0 = (struct timer_regs *)TIMER0_BASE; +static struct timer_regs *timer1 = (struct timer_regs *)TIMER1_BASE; +static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; + +static void lpc32xx_timer_clock(u32 bit, int enable) +{ + if (enable) + setbits_le32(&clk->timclk_ctrl1, bit); + else + clrbits_le32(&clk->timclk_ctrl1, bit); +} + +static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq) +{ + writel(TIMER_TCR_COUNTER_RESET, &timer->tcr); + writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr); + writel(0, &timer->tc); + writel(0, &timer->pr); + + /* Count mode is every rising PCLK edge */ + writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr); + + /* Set prescale counter value */ + writel((get_periph_clk_rate() / freq) - 1, &timer->pr); +} + +static void lpc32xx_timer_count(struct timer_regs *timer, int enable) +{ + if (enable) + writel(TIMER_TCR_COUNTER_ENABLE, &timer->tcr); + else + writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr); +} + +int timer_init(void) +{ + lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1); + lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ); + lpc32xx_timer_count(timer0, 1); + + return 0; +} + +ulong get_timer(ulong base) +{ + return readl(&timer0->tc) - base; +} + +void __udelay(unsigned long usec) +{ + lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1); + lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000); + lpc32xx_timer_count(timer1, 1); + + while (readl(&timer1->tc) < usec) + /* NOP */; + + lpc32xx_timer_count(timer1, 0); + lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0); +} + +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index 9cadb7c34c..8b07dae2b9 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -28,10 +28,15 @@ #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/imx25-pinmux.h> +#include <asm/arch/clock.h> #ifdef CONFIG_MXC_MMC #include <asm/arch/mxcmmc.h> #endif +#ifdef CONFIG_FSL_ESDHC +DECLARE_GLOBAL_DATA_PTR; +#endif + /* * get the system pll clock in Hz * @@ -105,6 +110,20 @@ ulong imx_get_perclk(int clk) return lldiv(fref, div); } +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + if (clk >= MXC_CLK_NUM) + return -1; + switch (clk) { + case MXC_ARM_CLK: + return imx_get_armclk(); + case MXC_FEC_CLK: + return imx_get_ahbclk(); + default: + return imx_get_perclk(clk); + } +} + u32 get_cpu_rev(void) { u32 srev; @@ -182,6 +201,14 @@ int cpu_eth_init(bd_t *bis) #endif } +int get_clocks(void) +{ +#ifdef CONFIG_FSL_ESDHC + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#endif + return 0; +} + /* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() diff --git a/arch/arm/cpu/arm926ejs/mx28/Makefile b/arch/arm/cpu/arm926ejs/mx28/Makefile index a2e3f771c2..674a3af1be 100644 --- a/arch/arm/cpu/arm926ejs/mx28/Makefile +++ b/arch/arm/cpu/arm926ejs/mx28/Makefile @@ -28,7 +28,7 @@ LIB = $(obj)lib$(SOC).o COBJS = clock.o mx28.o iomux.o timer.o ifdef CONFIG_SPL_BUILD -COBJS += spl_boot.o spl_mem_init.o spl_power_init.o +COBJS += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o endif SRCS := $(START:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c index dc0338dfb5..a82ff2564b 100644 --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c @@ -51,9 +51,16 @@ void reset_cpu(ulong ignored) __attribute__((noreturn)); void reset_cpu(ulong ignored) { - struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE; + struct mx28_lcdif_regs *lcdif_regs = + (struct mx28_lcdif_regs *)MXS_LCDIF_BASE; + + /* + * Shut down the LCD controller as it interferes with BootROM boot mode + * pads sampling. + */ + writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr); /* Wait 1 uS before doing the actual watchdog reset */ writel(1, &rtc_regs->hw_rtc_watchdog); @@ -185,8 +192,12 @@ int arch_cpu_init(void) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { + struct mx28_spl_data *data = (struct mx28_spl_data *) + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); + printf("Freescale i.MX28 family at %d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("BOOT: %s\n", mx28_boot_modes[data->boot_mode_idx].mode); return 0; } #endif @@ -279,22 +290,16 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) int mx28_dram_init(void) { - struct mx28_digctl_regs *digctl_regs = - (struct mx28_digctl_regs *)MXS_DIGCTL_BASE; - uint32_t sz[2]; - - sz[0] = readl(&digctl_regs->hw_digctl_scratch0); - sz[1] = readl(&digctl_regs->hw_digctl_scratch1); + struct mx28_spl_data *data = (struct mx28_spl_data *) + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); - if (sz[0] != sz[1]) { + if (data->mem_dram_size == 0) { printf("MX28:\n" - "Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n" - "HW_DIGCTRL_SCRATCH1 is not the same. Please\n" - "verify these two registers contain valid RAM size!\n"); + "Error, the RAM size passed up from SPL is 0!\n"); hang(); } - gd->ram_size = sz[0]; + gd->ram_size = data->mem_dram_size; return 0; } diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h b/arch/arm/cpu/arm926ejs/mx28/mx28_init.h index 98d363199d..e3a4493fbd 100644 --- a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h +++ b/arch/arm/cpu/arm926ejs/mx28/mx28_init.h @@ -37,5 +37,9 @@ static inline void mx28_power_wait_pswitch(void) { } #endif void mx28_mem_init(void); +uint32_t mx28_mem_get_size(void); + +void mx28_lradc_init(void); +void mx28_lradc_enable_batt_measurement(void); #endif /* __M28_INIT_H__ */ diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c index dfb8309e70..a6dfca3f51 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c @@ -28,6 +28,8 @@ #include <asm/io.h> #include <asm/arch/iomux-mx28.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> #include "mx28_init.h" @@ -46,12 +48,65 @@ void early_delay(int delay) ; } +#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +const iomux_cfg_t iomux_boot[] = { + MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, +}; + +uint8_t mx28_get_bootmode_index(void) +{ + uint8_t bootmode = 0; + int i; + uint8_t masked; + + /* Setup IOMUX of bootmode pads to GPIO */ + mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot)); + + /* Setup bootmode pins as GPIO input */ + gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0); + gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1); + gpio_direction_input(MX28_PAD_LCD_D02__GPIO_1_2); + gpio_direction_input(MX28_PAD_LCD_D03__GPIO_1_3); + gpio_direction_input(MX28_PAD_LCD_D04__GPIO_1_4); + gpio_direction_input(MX28_PAD_LCD_D05__GPIO_1_5); + + /* Read bootmode pads */ + bootmode |= (gpio_get_value(MX28_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; + + for (i = 0; i < ARRAY_SIZE(mx28_boot_modes); i++) { + masked = bootmode & mx28_boot_modes[i].boot_mask; + if (masked == mx28_boot_modes[i].boot_pads) + break; + } + + return i; +} + void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, const unsigned int iomux_size) { + struct mx28_spl_data *data = (struct mx28_spl_data *) + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); + uint8_t bootmode = mx28_get_bootmode_index(); + mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); mx28_power_init(); + mx28_mem_init(); + data->mem_dram_size = mx28_mem_get_size(); + + data->boot_mode_idx = bootmode; + mx28_power_wait_pswitch(); } @@ -68,8 +123,10 @@ inline void board_init_r(gd_t *id, ulong dest_addr) ; } +#ifndef CONFIG_SPL_SERIAL_SUPPORT void serial_putc(const char c) {} void serial_puts(const char *s) {} +#endif void hang(void) __attribute__ ((noreturn)); void hang(void) { diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c new file mode 100644 index 0000000000..88a603c11d --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c @@ -0,0 +1,86 @@ +/* + * Freescale i.MX28 Battery measurement init + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> + +#include "mx28_init.h" + +void mx28_lradc_init(void) +{ + struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE; + + writel(LRADC_CTRL0_SFTRST, ®s->hw_lradc_ctrl0_clr); + writel(LRADC_CTRL0_CLKGATE, ®s->hw_lradc_ctrl0_clr); + writel(LRADC_CTRL0_ONCHIP_GROUNDREF, ®s->hw_lradc_ctrl0_clr); + + clrsetbits_le32(®s->hw_lradc_ctrl3, + LRADC_CTRL3_CYCLE_TIME_MASK, + LRADC_CTRL3_CYCLE_TIME_6MHZ); + + clrsetbits_le32(®s->hw_lradc_ctrl4, + LRADC_CTRL4_LRADC7SELECT_MASK | + LRADC_CTRL4_LRADC6SELECT_MASK, + LRADC_CTRL4_LRADC7SELECT_CHANNEL7 | + LRADC_CTRL4_LRADC6SELECT_CHANNEL10); +} + +void mx28_lradc_enable_batt_measurement(void) +{ + struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE; + + /* Check if the channel is present at all. */ + if (!(readl(®s->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT)) + return; + + writel(LRADC_CTRL1_LRADC7_IRQ_EN, ®s->hw_lradc_ctrl1_clr); + writel(LRADC_CTRL1_LRADC7_IRQ, ®s->hw_lradc_ctrl1_clr); + + clrsetbits_le32(®s->hw_lradc_conversion, + LRADC_CONVERSION_SCALE_FACTOR_MASK, + LRADC_CONVERSION_SCALE_FACTOR_LI_ION); + writel(LRADC_CONVERSION_AUTOMATIC, ®s->hw_lradc_conversion_set); + + /* Configure the channel. */ + writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, + ®s->hw_lradc_ctrl2_clr); + writel(0xffffffff, ®s->hw_lradc_ch7_clr); + clrbits_le32(®s->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK); + writel(LRADC_CH_ACCUMULATE, ®s->hw_lradc_ch7_clr); + + /* Schedule the channel. */ + writel(1 << 7, ®s->hw_lradc_ctrl0_set); + + /* Start the channel sampling. */ + writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) | + ((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) | + 100, ®s->hw_lradc_delay3); + + writel(0xffffffff, ®s->hw_lradc_ch7_clr); + + writel(LRADC_DELAY_KICK, ®s->hw_lradc_delay3_set); +} diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index 911bbefc06..9fa5d29e6c 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c @@ -39,7 +39,7 @@ uint32_t dram_vals[] = { 0x00000000, 0x00000100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010101, 0x01010101, - 0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101, + 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000, 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, @@ -149,6 +149,8 @@ void mx28_mem_setup_cpu_and_hbus(void) /* Disable CPU bypass */ writel(CLKCTRL_CLKSEQ_BYPASS_CPU, &clkctrl_regs->hw_clkctrl_clkseq_clr); + + early_delay(15000); } void mx28_mem_setup_vdda(void) @@ -173,10 +175,8 @@ void mx28_mem_setup_vddd(void) &power_regs->hw_power_vdddctrl); } -void mx28_mem_get_size(void) +uint32_t mx28_mem_get_size(void) { - struct mx28_digctl_regs *digctl_regs = - (struct mx28_digctl_regs *)MXS_DIGCTL_BASE; uint32_t sz, da; uint32_t *vt = (uint32_t *)0x20; /* The following is "subs pc, r14, #4", used as return from DABT. */ @@ -187,11 +187,11 @@ void mx28_mem_get_size(void) vt[4] = data_abort_memdetect_handler; sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - writel(sz, &digctl_regs->hw_digctl_scratch0); - writel(sz, &digctl_regs->hw_digctl_scratch1); /* Restore the old DABT handler. */ vt[4] = da; + + return sz; } void mx28_mem_init(void) @@ -239,6 +239,4 @@ void mx28_mem_init(void) early_delay(10000); mx28_mem_setup_cpu_and_hbus(); - - mx28_mem_get_size(); } diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index aa4117d3a2..4b09b0c3ba 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c @@ -45,11 +45,11 @@ void mx28_power_clock2pll(void) struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - writel(CLKCTRL_PLL0CTRL0_POWER, - &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); + setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0, + CLKCTRL_PLL0CTRL0_POWER); early_delay(100); - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, - &clkctrl_regs->hw_clkctrl_clkseq_clr); + setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq, + CLKCTRL_CLKSEQ_BYPASS_CPU); } void mx28_power_clear_auto_restart(void) @@ -104,6 +104,62 @@ void mx28_power_set_linreg(void) POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW); } +int mx28_get_batt_volt(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t volt = readl(&power_regs->hw_power_battmonitor); + volt &= POWER_BATTMONITOR_BATT_VAL_MASK; + volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; + volt *= 8; + return volt; +} + +int mx28_is_batt_ready(void) +{ + return (mx28_get_batt_volt() >= 3600); +} + +int mx28_is_batt_good(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t volt = mx28_get_batt_volt(); + + if ((volt >= 2400) && (volt <= 4300)) + return 1; + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, + 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_clr); + + clrsetbits_le32(&power_regs->hw_power_charge, + POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, + POWER_CHARGE_STOP_ILIMIT_10MA | 0x3); + + writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_clr); + + early_delay(500000); + + volt = mx28_get_batt_volt(); + + if (volt >= 3500) + return 0; + + if (volt >= 2400) + return 1; + + writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, + &power_regs->hw_power_charge_clr); + writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set); + + return 0; +} + void mx28_power_setup_5v_detect(void) { struct mx28_power_regs *power_regs = @@ -399,9 +455,14 @@ void mx28_power_enable_4p2(void) mx28_power_init_4p2_regulator(); /* Shutdown battery (none present) */ - clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); - writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); - writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr); + if (!mx28_is_batt_ready()) { + clrbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_BO_MASK); + writel(POWER_CTRL_DCDC4P2_BO_IRQ, + &power_regs->hw_power_ctrl_clr); + writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, + &power_regs->hw_power_ctrl_clr); + } mx28_power_init_dcdc_4p2_source(); @@ -459,6 +520,50 @@ void mx28_powerdown(void) &power_regs->hw_power_reset); } +void mx28_batt_boot(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC); + + clrbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2); + writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr); + + /* 5V to battery handoff. */ + setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); + early_delay(30); + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); + + writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr); + + clrsetbits_le32(&power_regs->hw_power_minpwr, + POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); + + mx28_power_set_linreg(); + + clrbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG); + + clrbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG); + + clrbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_DISABLE_FET); + + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_PWD_CHARGE_4P2_MASK); + + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_ENABLE_DCDC); + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, + 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); +} + void mx28_handle_5v_conflict(void) { struct mx28_power_regs *power_regs = @@ -483,23 +588,12 @@ void mx28_handle_5v_conflict(void) mx28_powerdown(); break; } - } -} -int mx28_get_batt_volt(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t volt = readl(&power_regs->hw_power_battmonitor); - volt &= POWER_BATTMONITOR_BATT_VAL_MASK; - volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; - volt *= 8; - return volt; -} - -int mx28_is_batt_ready(void) -{ - return (mx28_get_batt_volt() >= 3600); + if (tmp & POWER_STS_PSWITCH_MASK) { + mx28_batt_boot(); + break; + } + } } void mx28_5v_boot(void) @@ -553,62 +647,44 @@ void mx28_switch_vddd_to_dcdc_source(void) POWER_VDDDCTRL_DISABLE_STEPPING); } -int mx28_is_batt_good(void) +void mx28_power_configure_power_source(void) { + int batt_ready, batt_good; struct mx28_power_regs *power_regs = (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t volt; - - volt = readl(&power_regs->hw_power_battmonitor); - volt &= POWER_BATTMONITOR_BATT_VAL_MASK; - volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; - volt *= 8; + struct mx28_lradc_regs *lradc_regs = + (struct mx28_lradc_regs *)MXS_LRADC_BASE; - if ((volt >= 2400) && (volt <= 4300)) - return 1; - - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, - 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, - &power_regs->hw_power_5vctrl_clr); - - clrsetbits_le32(&power_regs->hw_power_charge, - POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, - POWER_CHARGE_STOP_ILIMIT_10MA | 0x3); - - writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr); - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, - &power_regs->hw_power_5vctrl_clr); - - early_delay(500000); - - volt = readl(&power_regs->hw_power_battmonitor); - volt &= POWER_BATTMONITOR_BATT_VAL_MASK; - volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; - volt *= 8; - - if (volt >= 3500) - return 0; - - if (volt >= 2400) - return 1; - - writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, - &power_regs->hw_power_charge_clr); - writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set); + mx28_src_power_init(); - return 0; -} + batt_ready = mx28_is_batt_ready(); -void mx28_power_configure_power_source(void) -{ - mx28_src_power_init(); + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + batt_good = mx28_is_batt_good(); + if (batt_ready) { + /* 5V source detected, good battery detected. */ + mx28_batt_boot(); + } else { + if (batt_good) { + /* 5V source detected, low battery detceted. */ + } else { + /* 5V source detected, bad battery detected. */ + writel(LRADC_CONVERSION_AUTOMATIC, + &lradc_regs->hw_lradc_conversion_clr); + clrbits_le32(&power_regs->hw_power_battmonitor, + POWER_BATTMONITOR_BATT_VAL_MASK); + } + mx28_5v_boot(); + } + } else { + /* 5V not detected, booting from battery. */ + mx28_batt_boot(); + } - mx28_5v_boot(); mx28_power_clock2pll(); mx28_init_batt_bo(); + mx28_switch_vddd_to_dcdc_source(); } @@ -883,6 +959,13 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); } +void mx28_setup_batt_detect(void) +{ + mx28_lradc_init(); + mx28_lradc_enable_batt_measurement(); + early_delay(10); +} + void mx28_power_init(void) { struct mx28_power_regs *power_regs = @@ -892,6 +975,9 @@ void mx28_power_init(void) mx28_power_clear_auto_restart(); mx28_power_set_linreg(); mx28_power_setup_5v_detect(); + + mx28_setup_batt_detect(); + mx28_power_configure_power_source(); mx28_enable_output_rail_protection(); diff --git a/arch/arm/cpu/arm926ejs/rda/Makefile b/arch/arm/cpu/arm926ejs/rda/Makefile new file mode 100644 index 0000000000..a8ebda3a72 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/rda/Makefile @@ -0,0 +1,58 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS-y += timer.o serial.o ifc.o cpu.o + +ifdef CONFIG_SPL_BUILD +COBJS-y += spl.o +endif + +SOBJS = reset.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +SOBJS += lowlevel_init.o +endif + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm926ejs/rda/config.mk b/arch/arm/cpu/arm926ejs/rda/config.mk new file mode 100644 index 0000000000..565adda11d --- /dev/null +++ b/arch/arm/cpu/arm926ejs/rda/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj@denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float + +PLATFORM_CPPFLAGS += -march=armv5te +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/arch/arm/cpu/arm926ejs/rda/cpu.c b/arch/arm/cpu/arm926ejs/rda/cpu.c new file mode 100644 index 0000000000..ae7a18ed7c --- /dev/null +++ b/arch/arm/cpu/arm926ejs/rda/cpu.c @@ -0,0 +1,12 @@ +#include <common.h> +#include <asm/arch/hardware.h> + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} diff --git a/arch/arm/cpu/arm926ejs/rda/ifc.c b/arch/arm/cpu/arm926ejs/rda/ifc.c new file mode 100644 index 0000000000..cdda6935ea --- /dev/null +++ b/arch/arm/cpu/arm926ejs/rda/ifc.c @@ -0,0 +1,171 @@ +#include "common.h" +#include <errno.h> + +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/reg_ifc.h> +#include <asm/arch/ifc.h> + +#ifdef DEBUG +#include <assert.h> +#else +#define assert(...) +#endif + +#define HAL_TRACE(...) + +HAL_IFC_REQUEST_ID_T g_halModuleIfcChannelOwner[SYS_IFC_STD_CHAN_NB]; + +void hal_IfcOpen(void) +{ + u8 channel; + + // Initialize the channel table with unknown requests. + for (channel = 0; channel < SYS_IFC_STD_CHAN_NB; channel++) + { + g_halModuleIfcChannelOwner[channel] = HAL_IFC_NO_REQWEST; + } +} + +HAL_IFC_REQUEST_ID_T hal_IfcGetOwner(u8 channel) +{ + // Here, we consider the transfer as previously finished. + if (channel == HAL_UNKNOWN_CHANNEL) return HAL_IFC_NO_REQWEST; + + // Channel number too big. + assert(channel < SYS_IFC_STD_CHAN_NB, channel); + + return g_halModuleIfcChannelOwner[channel]; +} + +void hal_IfcChannelRelease(HAL_IFC_REQUEST_ID_T requestId, u8 channel) +{ + //u32 status; + + // Here, we consider the transfer as previously finished. + if (channel == HAL_UNKNOWN_CHANNEL) return; + + // Channel number too big. + assert(channel < SYS_IFC_STD_CHAN_NB, channel); + + //status = hal_SysEnterCriticalSection(); + if (g_halModuleIfcChannelOwner[channel] == requestId) + { + // disable this channel + hwp_sysIfc->std_ch[channel].control = (SYS_IFC_REQ_SRC(requestId) + | SYS_IFC_CH_RD_HW_EXCH + | SYS_IFC_DISABLE); + // read the status of this channel + if (hwp_sysIfc->std_ch[channel].status & SYS_IFC_ENABLE) + { + HAL_TRACE(_HAL | TSTDOUT,0," Strange, the released channel not disabled yet"); + } + // Write the TC to 0 for next time the channel is re-enabled + hwp_sysIfc->std_ch[channel].tc = 0; + } + //hal_SysExitCriticalSection(status); +} + +void hal_IfcChannelFlush(HAL_IFC_REQUEST_ID_T requestId, u8 channel) +{ + //u32 status; + + // Here, we consider the transfer as previously finished. + if (channel == HAL_UNKNOWN_CHANNEL) return; + + // Channel number too big. + assert(channel < SYS_IFC_STD_CHAN_NB, channel); + + // Check that the channel is really owned by the peripheral + // which is doing the request, it could have been release + // automatically or by an IRQ handler. + //status = hal_SysEnterCriticalSection(); + if (g_halModuleIfcChannelOwner[channel] == requestId) + { + // If fifo not empty, flush it. + if ( !(hwp_sysIfc->std_ch[channel].status & SYS_IFC_FIFO_EMPTY) ) + { + hwp_sysIfc->std_ch[channel].control = + hwp_sysIfc->std_ch[channel].control | SYS_IFC_FLUSH; + } + } + //hal_SysExitCriticalSection(status); +} + +BOOL hal_IfcChannelIsFifoEmpty(HAL_IFC_REQUEST_ID_T requestId, u8 channel) +{ + //u32 status; + BOOL fifoIsEmpty = TRUE; + + // Here, we consider the transfer as previously finished. + if (channel == HAL_UNKNOWN_CHANNEL) return fifoIsEmpty; + + // Channel number too big. + assert(channel < SYS_IFC_STD_CHAN_NB, channel); + + // Check that the channel is really owned by the peripheral + // which is doing the request, it could have been release + // automatically or by an IRQ handler. + //status = hal_SysEnterCriticalSection(); + if (g_halModuleIfcChannelOwner[channel] == requestId) + { + fifoIsEmpty = + (FALSE != (hwp_sysIfc->std_ch[channel].status & SYS_IFC_FIFO_EMPTY)); + } + //hal_SysExitCriticalSection(status); + + return fifoIsEmpty; +} + +u8 hal_IfcTransferStart(HAL_IFC_REQUEST_ID_T requestId, u8* memStartAddr, u32 xferSize, HAL_IFC_MODE_T ifcMode) +{ + //u32 status = hal_SysEnterCriticalSection(); + u8 channel; + u8 i; + + // Check buffer alignment depending on the mode + if (ifcMode != HAL_IFC_SIZE_8_MODE_MANUAL && ifcMode != HAL_IFC_SIZE_8_MODE_AUTO) + { + // Then ifcMode == HAL_IFC_SIZE_32, check word alignment + assert(((u32)memStartAddr%4) == 0, + "HAL IFC: 32 bits transfer misaligned 0x@%08X", memStartAddr); + } + else + { + // ifcMode == HAL_IFC_SIZE_8, nothing to check + } + + // Check the requested id is not currently already used. + for (i = 0; i < SYS_IFC_STD_CHAN_NB ; i++) + { + if (GET_BITFIELD(hwp_sysIfc->std_ch[i].control, SYS_IFC_REQ_SRC) == requestId) + { + // This channel is or was used for the requestId request. + // Check it is still in use. + assert((hwp_sysIfc->std_ch[i].status & SYS_IFC_ENABLE) == 0, + "HAL: Attempt to use the IFC to deal with a %d" + " request still active on channel %d", requestId, i); + } + } + + channel = SYS_IFC_CH_TO_USE(hwp_sysIfc->get_ch) ; + + if (channel >= SYS_IFC_STD_CHAN_NB) + { + serial_puts("HAL_UNKNOWN_CHANNEL\n"); + //hal_SysExitCriticalSection(status); + return HAL_UNKNOWN_CHANNEL; + } + + g_halModuleIfcChannelOwner[channel] = requestId; + hwp_sysIfc->std_ch[channel].start_addr = (u32) memStartAddr; + hwp_sysIfc->std_ch[channel].tc = xferSize; + hwp_sysIfc->std_ch[channel].control = (SYS_IFC_REQ_SRC(requestId) + | ifcMode + | SYS_IFC_CH_RD_HW_EXCH + | SYS_IFC_ENABLE); + + //hal_SysExitCriticalSection(status); + return channel; +} + diff --git a/arch/arm/cpu/arm926ejs/rda/reset.S b/arch/arm/cpu/arm926ejs/rda/reset.S new file mode 100644 index 0000000000..51748160ae --- /dev/null +++ b/arch/arm/cpu/arm926ejs/rda/reset.S @@ -0,0 +1,32 @@ +/* + * Processor reset using WDT for TI TMS320DM644x SoC. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * ----------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.globl reset_cpu +reset_cpu: + nop + nop + nop + nop +reset_cpu_loop: + b reset_cpu_loop + diff --git a/arch/arm/cpu/arm926ejs/rda/serial.c b/arch/arm/cpu/arm926ejs/rda/serial.c new file mode 100644 index 0000000000..f7c1d2d244 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/rda/serial.c @@ -0,0 +1,132 @@ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> +#include <asm/arch/reg_sysctrl.h> +#include <asm/arch/reg_uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +void _serial_set_baudrate(int rate) +{ + hwp_sysCtrlAp->Cfg_Clk_Uart[2] = 0x36; // 115200 @ 26MHz + //hwp_sysCtrlAp->Cfg_Clk_Uart[2] = 0x05; // 921600 @ 26MHz +} + +void _serial_enable_rtscts(void) +{ + hwp_uart->ctrl |= UART_AUTO_FLOW_CONTROL; +} + +void _serial_disable_rtscts(void) +{ + hwp_uart->ctrl &= ~UART_AUTO_FLOW_CONTROL; +} + +void _serial_init(void) +{ + _serial_set_baudrate(CONFIG_BAUDRATE); + hwp_uart->triggers = UART_AFC_LEVEL(1); //7 ? + + hwp_uart->ctrl = UART_ENABLE | UART_DATA_BITS_8_BITS | + UART_TX_STOP_BITS_1_BIT | UART_PARITY_ENABLE_NO; + + /* Allow reception */ + hwp_uart->CMD_Set = UART_RTS; +} + +void _serial_deinit(void) +{ + hwp_uart->ctrl = 0; + hwp_uart->CMD_Clr = UART_RTS; +} + +/* + * Test whether a character is in the RX buffer + */ +int _serial_tstc(const int port) +{ + return (GET_BITFIELD(hwp_uart->status, UART_RX_FIFO_LEVEL)); +} + +int _serial_getc(const int port) +{ + /* wait for character to arrive */ ; + while (!(GET_BITFIELD(hwp_uart->status, UART_RX_FIFO_LEVEL))) + ; + + return (hwp_uart->rxtx_buffer & 0xff); +} + +void _serial_putc_hw(const char c, const int port) +{ + // Place in the TX Fifo ? + while (!(GET_BITFIELD(hwp_uart->status, UART_TX_FIFO_SPACE))) + ; + hwp_uart->rxtx_buffer = (u32)c; +} + +void _serial_putc(const char c, const int port) +{ + if (c == '\n') { + _serial_putc_hw('\r', 0); + } + _serial_putc_hw(c, 0); +} + +void _serial_puts(const char *s, const int port) +{ + while (*s) { + _serial_putc(*s++, 0); + } +} + +static int hwflow = 0; /* turned off by default */ +int hwflow_onoff(int on) +{ + switch(on) { + case 0: + default: + break; /* return current */ + case 1: + hwflow = 1; + _serial_enable_rtscts(); /* turn on */ + break; + case -1: + hwflow = 0; + _serial_disable_rtscts(); /* turn off */ + break; + } + return hwflow; +} + +int serial_init(void) +{ + //_serial_init(); // already init in boot_test + return 0; +} + +int serial_getc(void) +{ + return _serial_getc(0); +} + +int serial_tstc(void) +{ + return _serial_tstc(0); +} + +void serial_putc(const char c) +{ + _serial_putc(c, 0); +} + +void serial_puts(const char *s) +{ + _serial_puts(s, 0); +} + +void serial_setbrg (void) +{ +} + diff --git a/arch/arm/cpu/arm926ejs/rda/spl.c b/arch/arm/cpu/arm926ejs/rda/spl.c new file mode 100644 index 0000000000..5111638288 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/rda/spl.c @@ -0,0 +1,74 @@ +#include <common.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <nand.h> +#include <malloc.h> + +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + +DECLARE_GLOBAL_DATA_PTR; +/* Define global data structure pointer to it*/ +static gd_t gdata __attribute__ ((section(".data"))); +static bd_t bdata __attribute__ ((section(".data"))); + +#else + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} + +void putc(char c) +{ +} + +#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */ + +inline void hang(void) +{ + puts("### ERROR ### Please RESET the board ###\n"); + for (;;) + ; +} + +void board_init_f(ulong dummy) +{ + relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE); +} + +void board_init_r(gd_t *id, ulong dummy) +{ +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + gd = &gdata; + gd->bd = &bdata; + gd->flags |= GD_FLG_RELOC; + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); /* serial communications setup */ + gd->have_console = 1; +#endif + puts("board_init_r\n"); + while(1) + ; +#if 0 +#ifdef CONFIG_SPL_NAND_LOAD + nand_init(); + puts("Nand boot...\n"); + nand_boot(); +#endif +#ifdef CONFIG_SPL_SPI_LOAD + mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN, + CONFIG_SYS_MALLOC_LEN); + + gd = &gdata; + gd->bd = &bdata; + gd->flags |= GD_FLG_RELOC; + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); /* serial communications setup */ + gd->have_console = 1; + + puts("SPI boot...\n"); + spi_boot(); +#endif +#endif +} diff --git a/arch/arm/cpu/arm926ejs/rda/timer.c b/arch/arm/cpu/arm926ejs/rda/timer.c new file mode 100644 index 0000000000..a54081b7b2 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/rda/timer.c @@ -0,0 +1,93 @@ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +DECLARE_GLOBAL_DATA_PTR; + +typedef volatile struct +{ + REG32 OSTimer_Ctrl; //0x00000000 + REG32 OSTimer_CurVal; //0x00000004 + REG32 WDTimer_Ctrl; //0x00000008 + REG32 WDTimer_LoadVal; //0x0000000C + REG32 HWTimer_Ctrl; //0x00000010 + REG32 HWTimer_CurVal; //0x00000014 + REG32 Timer_Irq_Mask_Set; //0x00000018 + REG32 Timer_Irq_Mask_Clr; //0x0000001C + REG32 Timer_Irq_Clr; //0x00000020 + REG32 Timer_Irq_Cause; //0x00000024 +} HWP_TIMER_T; + +#define hwp_timer ((HWP_TIMER_T*)(RDA_TIMER_BASE)) + +int timer_init(void) +{ + gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK; + gd->timer_reset_value = 0; + + /* We are using timer34 in unchained 32-bit mode, full speed */ + return(0); +} + +void reset_timer(void) +{ + gd->timer_reset_value = get_ticks(); +} + +/* + * Get the current 64 bit timer tick count + */ +unsigned long long get_ticks(void) +{ + unsigned long now = hwp_timer->HWTimer_CurVal; + + /* increment tbu if tbl has rolled over */ + if (now < gd->tbl) + gd->tbu++; + gd->tbl = now; + + return (((unsigned long long)gd->tbu) << 32) | gd->tbl; +} + +ulong get_timer(ulong base) +{ + unsigned long long timer_diff; + + timer_diff = get_ticks() - gd->timer_reset_value; + + return (timer_diff / (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base; +} + +#pragma GCC push_options +#pragma GCC optimize ("O0") + +void __udelay(unsigned long usec) +{ +#if 0 /* our timer is 16kHz, can NOT support udelay */ + unsigned long long endtime; + + endtime = ((unsigned long long)usec * gd->timer_rate_hz) / 1000000UL; + endtime += get_ticks(); + + while (get_ticks() < endtime) + ; +#else /* use loop instead */ +#define USEC_LOOP (1) + int i, j; + for (i=0;i<(usec);i++) + for (j=0;j<USEC_LOOP;j++) + ; +#endif +} + +#pragma GCC pop_options + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index d64ae6936c..6b7a494d7c 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -105,7 +105,7 @@ void init_timer(void) #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0); + return omap_mmc_init(0, 0, 0); } #endif diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index f532d62e57..5407cb68a8 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -22,8 +22,11 @@ # PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -# Make ARMv5 to allow more compilers to work, even though its v7a. -PLATFORM_CPPFLAGS += -march=armv5 +# If armv7-a is not supported by GCC fall-back to armv5, which is +# supported by more tool-chains +PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5) +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7) + # ========================================================================= # # Supply options according to compiler version diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile index 124c38018c..90ec2bd404 100644 --- a/arch/arm/cpu/armv7/exynos/Makefile +++ b/arch/arm/cpu/armv7/exynos/Makefile @@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS += clock.o soc.o +COBJS += clock.o power.o soc.o system.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 2f7048b6a3..330bd75da9 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -414,6 +414,170 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); } +/* get_lcd_clk: return lcd clock frequency */ +static unsigned long exynos4_get_lcd_clk(void) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + unsigned long pclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_LCD0 + * FIMD0_SEL [3:0] + */ + sel = readl(&clk->src_lcd0); + sel = sel & 0xf; + + /* + * 0x6: SCLK_MPLL + * 0x7: SCLK_EPLL + * 0x8: SCLK_VPLL + */ + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + /* + * CLK_DIV_LCD0 + * FIMD0_RATIO [3:0] + */ + ratio = readl(&clk->div_lcd0); + ratio = ratio & 0xf; + + pclk = sclk / (ratio + 1); + + return pclk; +} + +void exynos4_set_lcd_clk(void) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + unsigned int cfg = 0; + + /* + * CLK_GATE_BLOCK + * CLK_CAM [0] + * CLK_TV [1] + * CLK_MFC [2] + * CLK_G3D [3] + * CLK_LCD0 [4] + * CLK_LCD1 [5] + * CLK_GPS [7] + */ + cfg = readl(&clk->gate_block); + cfg |= 1 << 4; + writel(cfg, &clk->gate_block); + + /* + * CLK_SRC_LCD0 + * FIMD0_SEL [3:0] + * MDNIE0_SEL [7:4] + * MDNIE_PWM0_SEL [8:11] + * MIPI0_SEL [12:15] + * set lcd0 src clock 0x6: SCLK_MPLL + */ + cfg = readl(&clk->src_lcd0); + cfg &= ~(0xf); + cfg |= 0x6; + writel(cfg, &clk->src_lcd0); + + /* + * CLK_GATE_IP_LCD0 + * CLK_FIMD0 [0] + * CLK_MIE0 [1] + * CLK_MDNIE0 [2] + * CLK_DSIM0 [3] + * CLK_SMMUFIMD0 [4] + * CLK_PPMULCD0 [5] + * Gating all clocks for FIMD0 + */ + cfg = readl(&clk->gate_ip_lcd0); + cfg |= 1 << 0; + writel(cfg, &clk->gate_ip_lcd0); + + /* + * CLK_DIV_LCD0 + * FIMD0_RATIO [3:0] + * MDNIE0_RATIO [7:4] + * MDNIE_PWM0_RATIO [11:8] + * MDNIE_PWM_PRE_RATIO [15:12] + * MIPI0_RATIO [19:16] + * MIPI0_PRE_RATIO [23:20] + * set fimd ratio + */ + cfg &= ~(0xf); + cfg |= 0x1; + writel(cfg, &clk->div_lcd0); +} + +void exynos4_set_mipi_clk(void) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + unsigned int cfg = 0; + + /* + * CLK_SRC_LCD0 + * FIMD0_SEL [3:0] + * MDNIE0_SEL [7:4] + * MDNIE_PWM0_SEL [8:11] + * MIPI0_SEL [12:15] + * set mipi0 src clock 0x6: SCLK_MPLL + */ + cfg = readl(&clk->src_lcd0); + cfg &= ~(0xf << 12); + cfg |= (0x6 << 12); + writel(cfg, &clk->src_lcd0); + + /* + * CLK_SRC_MASK_LCD0 + * FIMD0_MASK [0] + * MDNIE0_MASK [4] + * MDNIE_PWM0_MASK [8] + * MIPI0_MASK [12] + * set src mask mipi0 0x1: Unmask + */ + cfg = readl(&clk->src_mask_lcd0); + cfg |= (0x1 << 12); + writel(cfg, &clk->src_mask_lcd0); + + /* + * CLK_GATE_IP_LCD0 + * CLK_FIMD0 [0] + * CLK_MIE0 [1] + * CLK_MDNIE0 [2] + * CLK_DSIM0 [3] + * CLK_SMMUFIMD0 [4] + * CLK_PPMULCD0 [5] + * Gating all clocks for MIPI0 + */ + cfg = readl(&clk->gate_ip_lcd0); + cfg |= 1 << 3; + writel(cfg, &clk->gate_ip_lcd0); + + /* + * CLK_DIV_LCD0 + * FIMD0_RATIO [3:0] + * MDNIE0_RATIO [7:4] + * MDNIE_PWM0_RATIO [11:8] + * MDNIE_PWM_PRE_RATIO [15:12] + * MIPI0_RATIO [19:16] + * MIPI0_PRE_RATIO [23:20] + * set mipi ratio + */ + cfg &= ~(0xf << 16); + cfg |= (0x1 << 16); + writel(cfg, &clk->div_lcd0); +} + unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) @@ -453,3 +617,23 @@ void set_mmc_clk(int dev_index, unsigned int div) else exynos4_set_mmc_clk(dev_index, div); } + +unsigned long get_lcd_clk(void) +{ + if (cpu_is_exynos4()) + return exynos4_get_lcd_clk(); + else + return 0; +} + +void set_lcd_clk(void) +{ + if (cpu_is_exynos4()) + exynos4_set_lcd_clk(); +} + +void set_mipi_clk(void) +{ + if (cpu_is_exynos4()) + exynos4_set_mipi_clk(); +} diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c new file mode 100644 index 0000000000..c765304fd5 --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Donghwa Lee <dh09.lee@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/power.h> + +static void exynos4_mipi_phy_control(unsigned int dev_index, + unsigned int enable) +{ + struct exynos4_power *pmu = + (struct exynos4_power *)samsung_get_base_power(); + unsigned int addr, cfg = 0; + + if (dev_index == 0) + addr = (unsigned int)&pmu->mipi_phy0_control; + else + addr = (unsigned int)&pmu->mipi_phy1_control; + + + cfg = readl(addr); + if (enable) + cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE); + else + cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE); + + writel(cfg, addr); +} + +void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable) +{ + if (cpu_is_exynos4()) + exynos4_mipi_phy_control(dev_index, enable); +} diff --git a/arch/arm/cpu/armv7/exynos/system.c b/arch/arm/cpu/armv7/exynos/system.c new file mode 100644 index 0000000000..6c34730b97 --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/system.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Donghwa Lee <dh09.lee@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/system.h> + +static void exynos4_set_system_display(void) +{ + struct exynos4_sysreg *sysreg = + (struct exynos4_sysreg *)samsung_get_base_sysreg(); + unsigned int cfg = 0; + + /* + * system register path set + * 0: MIE/MDNIE + * 1: FIMD Bypass + */ + cfg = readl(&sysreg->display_ctrl); + cfg |= (1 << 1); + writel(cfg, &sysreg->display_ctrl); +} + +void set_system_display_ctrl(void) +{ + if (cpu_is_exynos4()) + exynos4_set_system_display(); +} diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c index 3d58d8ae91..b3195dd6fb 100644 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ b/arch/arm/cpu/armv7/imx-common/cpu.c @@ -29,12 +29,13 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif -static char *get_reset_cause(void) +char *get_reset_cause(void) { u32 cause; struct src *src_regs = (struct src *)SRC_BASE_ADDR; @@ -127,3 +128,15 @@ void reset_cpu(ulong addr) { __raw_writew(4, WDOG1_BASE_ADDR); } + +u32 get_ahb_clk(void) +{ + struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg, ahb_podf; + + reg = __raw_readl(&imx_ccm->cbcdr); + reg &= MXC_CCM_CBCDR_AHB_PODF_MASK; + ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; + + return get_periph_clk() / (ahb_podf + 1); +} diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index e92f10623a..fc2406bcad 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -30,6 +30,7 @@ #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> #include <div64.h> +#include <asm/arch/sys_proto.h> enum pll_clocks { PLL1_CLOCK = 0, @@ -48,6 +49,42 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { #endif }; +#define AHB_CLK_ROOT 133333333 +#define SZ_DEC_1M 1000000 +#define PLL_PD_MAX 16 /* Actual pd+1 */ +#define PLL_MFI_MAX 15 +#define PLL_MFI_MIN 5 +#define ARM_DIV_MAX 8 +#define IPG_DIV_MAX 4 +#define AHB_DIV_MAX 8 +#define EMI_DIV_MAX 8 +#define NFC_DIV_MAX 8 + +#define MX5_CBCMR 0x00015154 +#define MX5_CBCDR 0x02888945 + +struct fixed_pll_mfd { + u32 ref_clk_hz; + u32 mfd; +}; + +const struct fixed_pll_mfd fixed_mfd[] = { + {CONFIG_SYS_MX5_HCLK, 24 * 16}, +}; + +struct pll_param { + u32 pd; + u32 mfi; + u32 mfn; + u32 mfd; +}; + +#define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX) +#define PLL_FREQ_MIN(ref_clk) \ + ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX) +#define MAX_DDR_CLK 420000000 +#define NFC_CLK_MAX 34000000 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; void set_usboh3_clk(void) @@ -192,7 +229,7 @@ u32 get_mcu_main_clk(void) /* * Get the rate of peripheral's root clock. */ -static u32 get_periph_clk(void) +u32 get_periph_clk(void) { u32 reg; @@ -213,22 +250,6 @@ static u32 get_periph_clk(void) } /* - * Get the rate of ahb clock. - */ -static u32 get_ahb_clk(void) -{ - uint32_t freq, div, reg; - - freq = get_periph_clk(); - - reg = __raw_readl(&mxc_ccm->cbcdr); - div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> - MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; - - return freq / div; -} - -/* * Get the rate of ipg clock. */ static u32 get_ipg_clk(void) @@ -306,7 +327,7 @@ static u32 get_uart_clk(void) /* * This function returns the low power audio clock. */ -u32 get_lp_apm(void) +static u32 get_lp_apm(void) { u32 ret_val = 0; u32 ccsr = __raw_readl(&mxc_ccm->ccsr); @@ -322,7 +343,7 @@ u32 get_lp_apm(void) /* * get cspi clock rate. */ -u32 imx_get_cspiclk(void) +static u32 imx_get_cspiclk(void) { u32 ret_val = 0, pdf, pre_pdf, clk_sel; u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1); @@ -359,8 +380,77 @@ u32 imx_get_cspiclk(void) return ret_val; } +static u32 get_axi_a_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \ + >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET; + + return get_periph_clk() / (pdf + 1); +} + +static u32 get_axi_b_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \ + >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET; + + return get_periph_clk() / (pdf + 1); +} + +static u32 get_emi_slow_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL; + u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \ + >> MXC_CCM_CBCDR_EMI_PODF_OFFSET; + + if (emi_clk_sel) + return get_ahb_clk() / (pdf + 1); + + return get_periph_clk() / (pdf + 1); +} + +static u32 get_ddr_clk(void) +{ + u32 ret_val = 0; + u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr); + u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \ + >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET; +#ifdef CONFIG_MX51 + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) { + u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \ + MXC_CCM_CBCDR_DDR_PODF_OFFSET; + + ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); + ret_val /= ddr_clk_podf + 1; + + return ret_val; + } +#endif + switch (ddr_clk_sel) { + case 0: + ret_val = get_axi_a_clk(); + break; + case 1: + ret_val = get_axi_b_clk(); + break; + case 2: + ret_val = get_emi_slow_clk(); + break; + case 3: + ret_val = get_ahb_clk(); + break; + default: + break; + } + + return ret_val; +} + /* - * The API of get mxc clockes. + * The API of get mxc clocks. */ unsigned int mxc_get_clock(enum mxc_clock clk) { @@ -380,10 +470,14 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_FEC_CLK: return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); + case MXC_SATA_CLK: + return get_ahb_clk(); + case MXC_DDR_CLK: + return get_ddr_clk(); default: break; } - return -1; + return -EINVAL; } u32 imx_get_uartclk(void) @@ -397,6 +491,362 @@ u32 imx_get_fecclk(void) return mxc_get_clock(MXC_IPG_CLK); } +static int gcd(int m, int n) +{ + int t; + while (m > 0) { + if (n > m) { + t = m; + m = n; + n = t; + } /* swap */ + m -= n; + } + return n; +} + +/* + * This is to calculate various parameters based on reference clock and + * targeted clock based on the equation: + * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1) + * This calculation is based on a fixed MFD value for simplicity. + */ +static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) +{ + u64 pd, mfi = 1, mfn, mfd, t1; + u32 n_target = target; + u32 n_ref = ref, i; + + /* + * Make sure targeted freq is in the valid range. + * Otherwise the following calculation might be wrong!!! + */ + if (n_target < PLL_FREQ_MIN(ref) || + n_target > PLL_FREQ_MAX(ref)) { + printf("Targeted peripheral clock should be" + "within [%d - %d]\n", + PLL_FREQ_MIN(ref) / SZ_DEC_1M, + PLL_FREQ_MAX(ref) / SZ_DEC_1M); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) { + if (fixed_mfd[i].ref_clk_hz == ref) { + mfd = fixed_mfd[i].mfd; + break; + } + } + + if (i == ARRAY_SIZE(fixed_mfd)) + return -EINVAL; + + /* Use n_target and n_ref to avoid overflow */ + for (pd = 1; pd <= PLL_PD_MAX; pd++) { + t1 = n_target * pd; + do_div(t1, (4 * n_ref)); + mfi = t1; + if (mfi > PLL_MFI_MAX) + return -EINVAL; + else if (mfi < 5) + continue; + break; + } + /* + * Now got pd and mfi already + * + * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref; + */ + t1 = n_target * pd; + do_div(t1, 4); + t1 -= n_ref * mfi; + t1 *= mfd; + do_div(t1, n_ref); + mfn = t1; + debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n", + ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd); + i = 1; + if (mfn != 0) + i = gcd(mfd, mfn); + pll->pd = (u32)pd; + pll->mfi = (u32)mfi; + do_div(mfn, i); + pll->mfn = (u32)mfn; + do_div(mfd, i); + pll->mfd = (u32)mfd; + + return 0; +} + +#define calc_div(tgt_clk, src_clk, limit) ({ \ + u32 v = 0; \ + if (((src_clk) % (tgt_clk)) <= 100) \ + v = (src_clk) / (tgt_clk); \ + else \ + v = ((src_clk) / (tgt_clk)) + 1;\ + if (v > limit) \ + v = limit; \ + (v - 1); \ + }) + +#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \ + { \ + __raw_writel(0x1232, &pll->ctrl); \ + __raw_writel(0x2, &pll->config); \ + __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \ + &pll->op); \ + __raw_writel(fn, &(pll->mfn)); \ + __raw_writel((fd) - 1, &pll->mfd); \ + __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \ + &pll->hfs_op); \ + __raw_writel(fn, &pll->hfs_mfn); \ + __raw_writel((fd) - 1, &pll->hfs_mfd); \ + __raw_writel(0x1232, &pll->ctrl); \ + while (!__raw_readl(&pll->ctrl) & 0x1) \ + ;\ + } + +static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param) +{ + u32 ccsr = __raw_readl(&mxc_ccm->ccsr); + struct mxc_pll_reg *pll = mxc_plls[index]; + + switch (index) { + case PLL1_CLOCK: + /* Switch ARM to PLL2 clock */ + __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr); + break; + case PLL2_CLOCK: + /* Switch to pll2 bypass clock */ + __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr); + break; + case PLL3_CLOCK: + /* Switch to pll3 bypass clock */ + __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr); + break; + case PLL4_CLOCK: + /* Switch to pll4 bypass clock */ + __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr); + break; + default: + return -EINVAL; + } + + return 0; +} + +/* Config CPU clock */ +static int config_core_clk(u32 ref, u32 freq) +{ + int ret = 0; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + /* The case that periph uses PLL1 is not considered here */ + ret = calc_pll_params(ref, freq, &pll_param); + if (ret != 0) { + printf("Error:Can't find pll parameters: %d\n", ret); + return ret; + } + + return config_pll_clk(PLL1_CLOCK, &pll_param); +} + +static int config_nfc_clk(u32 nfc_clk) +{ + u32 reg; + u32 parent_rate = get_emi_slow_clk(); + u32 div = parent_rate / nfc_clk; + + if (nfc_clk <= 0) + return -EINVAL; + if (div == 0) + div++; + if (parent_rate / div > NFC_CLK_MAX) + div++; + reg = __raw_readl(&mxc_ccm->cbcdr); + reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET; + __raw_writel(reg, &mxc_ccm->cbcdr); + while (__raw_readl(&mxc_ccm->cdhipr) != 0) + ; + return 0; +} + +/* Config main_bus_clock for periphs */ +static int config_periph_clk(u32 ref, u32 freq) +{ + int ret = 0; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { + ret = calc_pll_params(ref, freq, &pll_param); + if (ret != 0) { + printf("Error:Can't find pll parameters: %d\n", + ret); + return ret; + } + switch ((__raw_readl(&mxc_ccm->cbcmr) & \ + MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \ + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { + case 0: + return config_pll_clk(PLL1_CLOCK, &pll_param); + break; + case 1: + return config_pll_clk(PLL3_CLOCK, &pll_param); + break; + default: + return -EINVAL; + } + } + + return 0; +} + +static int config_ddr_clk(u32 emi_clk) +{ + u32 clk_src; + s32 shift = 0, clk_sel, div = 1; + u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr); + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + + if (emi_clk > MAX_DDR_CLK) { + printf("Warning:DDR clock should not exceed %d MHz\n", + MAX_DDR_CLK / SZ_DEC_1M); + emi_clk = MAX_DDR_CLK; + } + + clk_src = get_periph_clk(); + /* Find DDR clock input */ + clk_sel = (cbcmr >> 10) & 0x3; + switch (clk_sel) { + case 0: + shift = 16; + break; + case 1: + shift = 19; + break; + case 2: + shift = 22; + break; + case 3: + shift = 10; + break; + default: + return -EINVAL; + } + + if ((clk_src % emi_clk) < 10000000) + div = clk_src / emi_clk; + else + div = (clk_src / emi_clk) + 1; + if (div > 8) + div = 8; + + cbcdr = cbcdr & ~(0x7 << shift); + cbcdr |= ((div - 1) << shift); + __raw_writel(cbcdr, &mxc_ccm->cbcdr); + while (__raw_readl(&mxc_ccm->cdhipr) != 0) + ; + __raw_writel(0x0, &mxc_ccm->ccdr); + + return 0; +} + +/* + * This function assumes the expected core clock has to be changed by + * modifying the PLL. This is NOT true always but for most of the times, + * it is. So it assumes the PLL output freq is the same as the expected + * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN. + * In the latter case, it will try to increase the presc value until + * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to + * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based + * on the targeted PLL and reference input clock to the PLL. Lastly, + * it sets the register based on these values along with the dividers. + * Note 1) There is no value checking for the passed-in divider values + * so the caller has to make sure those values are sensible. + * 2) Also adjust the NFC divider such that the NFC clock doesn't + * exceed NFC_CLK_MAX. + * 3) IPU HSP clock is independent of AHB clock. Even it can go up to + * 177MHz for higher voltage, this function fixes the max to 133MHz. + * 4) This function should not have allowed diag_printf() calls since + * the serial driver has been stoped. But leave then here to allow + * easy debugging by NOT calling the cyg_hal_plf_serial_stop(). + */ +int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) +{ + freq *= SZ_DEC_1M; + + switch (clk) { + case MXC_ARM_CLK: + if (config_core_clk(ref, freq)) + return -EINVAL; + break; + case MXC_PERIPH_CLK: + if (config_periph_clk(ref, freq)) + return -EINVAL; + break; + case MXC_DDR_CLK: + if (config_ddr_clk(freq)) + return -EINVAL; + break; + case MXC_NFC_CLK: + if (config_nfc_clk(freq)) + return -EINVAL; + break; + default: + printf("Warning:Unsupported or invalid clock type\n"); + } + + return 0; +} + +#ifdef CONFIG_MX53 +/* + * The clock for the external interface can be set to use internal clock + * if fuse bank 4, row 3, bit 2 is set. + * This is an undocumented feature and it was confirmed by Freescale's support: + * Fuses (but not pins) may be used to configure SATA clocks. + * Particularly the i.MX53 Fuse_Map contains the next information + * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C) + * '00' - 100MHz (External) + * '01' - 50MHz (External) + * '10' - 120MHz, internal (USB PHY) + * '11' - Reserved +*/ +void mxc_set_sata_internal_clock(void) +{ + u32 *tmp_base = + (u32 *)(IIM_BASE_ADDR + 0x180c); + + set_usb_phy1_clk(); + + writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base); +} +#endif + /* * Dump some core clockes. */ @@ -419,6 +869,7 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); + printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); return 0; } diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 74ab753a4a..683a7b53af 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -22,6 +22,7 @@ #include <config.h> #include <asm/arch/imx-regs.h> #include <generated/asm-offsets.h> +#include <linux/linkage.h> /* * L2CC Cache setup/invalidation/disable @@ -326,8 +327,7 @@ .section ".text.init", "x" -.globl lowlevel_init -lowlevel_init: +ENTRY(lowlevel_init) #if defined(CONFIG_MX51) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] @@ -348,6 +348,7 @@ lowlevel_init: /* r12 saved upper lr*/ mov pc,lr +ENDPROC(lowlevel_init) /* Board level setting value */ W_DP_OP_864: .word DP_OP_864 diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index ef98563ff7..52d5dc4d90 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -24,8 +24,9 @@ #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/ccm_regs.h> +#include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> enum pll_clocks { PLL_SYS, /* System PLL */ @@ -34,7 +35,7 @@ enum pll_clocks { PLL_ENET, /* ENET PLL */ }; -struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR; +struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; void enable_usboh3_clk(unsigned char enable) { @@ -92,7 +93,7 @@ static u32 get_mcu_main_clk(void) return freq / (reg + 1); } -static u32 get_periph_clk(void) +u32 get_periph_clk(void) { u32 reg, freq = 0; @@ -139,18 +140,6 @@ static u32 get_periph_clk(void) return freq; } - -static u32 get_ahb_clk(void) -{ - u32 reg, ahb_podf; - - reg = __raw_readl(&imx_ccm->cbcdr); - reg &= MXC_CCM_CBCDR_AHB_PODF_MASK; - ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; - - return get_periph_clk() / (ahb_podf + 1); -} - static u32 get_ipg_clk(void) { u32 reg, ipg_podf; @@ -303,6 +292,37 @@ u32 imx_get_fecclk(void) return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK); } +int enable_sata_clock(void) +{ + u32 reg = 0; + s32 timeout = 100000; + struct mxc_ccm_reg *const imx_ccm + = (struct mxc_ccm_reg *) CCM_BASE_ADDR; + + /* Enable sata clock */ + reg = readl(&imx_ccm->CCGR5); /* CCGR5 */ + reg |= MXC_CCM_CCGR5_CG2_MASK; + writel(reg, &imx_ccm->CCGR5); + + /* Enable PLLs */ + reg = readl(&imx_ccm->analog_pll_enet); + reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; + writel(reg, &imx_ccm->analog_pll_enet); + reg |= BM_ANADIG_PLL_SYS_ENABLE; + while (timeout--) { + if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK) + break; + } + if (timeout <= 0) + return -EIO; + reg &= ~BM_ANADIG_PLL_SYS_BYPASS; + writel(reg, &imx_ccm->analog_pll_enet); + reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA; + writel(reg, &imx_ccm->analog_pll_enet); + + return 0 ; +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { diff --git a/arch/arm/cpu/armv7/mx6/lowlevel_init.S b/arch/arm/cpu/armv7/mx6/lowlevel_init.S index 1864356d0b..acadef221c 100644 --- a/arch/arm/cpu/armv7/mx6/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx6/lowlevel_init.S @@ -18,7 +18,8 @@ */ .section ".text.init", "x" -.globl lowlevel_init -lowlevel_init: +#include <linux/linkage.h> +ENTRY(lowlevel_init) mov pc, lr +ENDPROC(lowlevel_init) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 543b2cc6d8..90f208809b 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -77,10 +77,40 @@ void init_aips(void) writel(0x00000000, &aips2->opacr4); } +/* + * Set the VDDSOC + * + * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set + * them to the specified millivolt level. + * Possible values are from 0.725V to 1.450V in steps of + * 0.025V (25mV). + */ +void set_vddsoc(u32 mv) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + u32 val, reg = readl(&anatop->reg_core); + + if (mv < 725) + val = 0x00; /* Power gated off */ + else if (mv > 1450) + val = 0x1F; /* Power FET switched full on. No regulation */ + else + val = (mv - 700) / 25; + + /* + * Mask out the REG_CORE[22:18] bits (REG2_TRIG) + * and set them to the calculated value (0.7V + val * 0.25V) + */ + reg = (reg & ~(0x1F << 18)) | (val << 18); + writel(reg, &anatop->reg_core); +} + int arch_cpu_init(void) { init_aips(); + set_vddsoc(1200); /* Set VDDSOC to 1.2V */ + return 0; } #endif diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 447fcd5eff..2a6625f1c4 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -37,6 +37,7 @@ ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) COBJS += hwinit-common.o COBJS += clocks-common.o COBJS += emif-common.o +COBJS += vc.o endif ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 4e7456992f..10d286a6d4 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -245,6 +245,11 @@ void configure_mpu_dpll(void) CM_CLKSEL_DCC_EN_MASK); } + setbits_le32(&prcm->cm_mpu_mpu_clkctrl, + MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); + setbits_le32(&prcm->cm_mpu_mpu_clkctrl, + MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); + params = get_mpu_dpll_params(); do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); @@ -360,56 +365,51 @@ static void setup_non_essential_dplls(void) } #endif -void do_scale_tps62361(u32 reg, u32 volt_mv) +void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv) { - u32 temp, step; + u32 step; + int ret = 0; + + /* See if we can first get the GPIO if needed */ + if (gpio >= 0) + ret = gpio_request(gpio, "TPS62361_VSEL0_GPIO"); + if (ret < 0) { + printf("%s: gpio %d request failed %d\n", __func__, gpio, ret); + gpio = -1; + } + + /* Pull the GPIO low to select SET0 register, while we program SET1 */ + if (gpio >= 0) + gpio_direction_output(gpio, 0); step = volt_mv - TPS62361_BASE_VOLT_MV; step /= 10; - temp = TPS62361_I2C_SLAVE_ADDR | - (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | - (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) | - PRM_VC_VAL_BYPASS_VALID_BIT; debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step); - - writel(temp, &prcm->prm_vc_val_bypass); - if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0, - &prcm->prm_vc_val_bypass, LDELAY)) { + if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step)) puts("Scaling voltage failed for vdd_mpu from TPS\n"); - } + + /* Pull the GPIO high to select SET1 register */ + if (gpio >= 0) + gpio_direction_output(gpio, 1); } void do_scale_vcore(u32 vcore_reg, u32 volt_mv) { - u32 temp, offset_code; - u32 step = 12660; /* 12.66 mV represented in uV */ + u32 offset_code; u32 offset = volt_mv; /* convert to uV for better accuracy in the calculations */ offset *= 1000; - if (omap_revision() == OMAP4430_ES1_0) - offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; - else - offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; - - offset_code = (offset + step - 1) / step; - /* The code starts at 1 not 0 */ - offset_code++; + offset_code = get_offset_code(offset); debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, offset_code); - temp = SMPS_I2C_SLAVE_ADDR | - (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | - (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) | - PRM_VC_VAL_BYPASS_VALID_BIT; - writel(temp, &prcm->prm_vc_val_bypass); - if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0, - &prcm->prm_vc_val_bypass, LDELAY)) { + if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR, + vcore_reg, offset_code)) printf("Scaling voltage failed for 0x%x\n", vcore_reg); - } } static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) @@ -452,6 +452,7 @@ void freq_update_core(void) { u32 freq_config1 = 0; const struct dpll_params *core_dpll_params; + u32 omap_rev = omap_revision(); core_dpll_params = get_core_dpll_params(); /* Put EMIF clock domain in sw wakeup mode */ @@ -477,11 +478,18 @@ void freq_update_core(void) hang(); } - /* Put EMIF clock domain back in hw auto mode */ - enable_clock_domain(&prcm->cm_memif_clkstctrl, - CD_CLKCTRL_CLKTRCTRL_HW_AUTO); - wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); - wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); + /* + * Putting EMIF in HW_AUTO is seen to be causing issues with + * EMIF clocks and the master DLL. Put EMIF in SW_WKUP + * in OMAP5430 ES1.0 silicon + */ + if (omap_rev != OMAP5430_ES1_0) { + /* Put EMIF clock domain back in hw auto mode */ + enable_clock_domain(&prcm->cm_memif_clkstctrl, + CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); + wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); + } } void bypass_dpll(u32 *const base) @@ -529,29 +537,6 @@ void setup_clocks_for_console(void) CD_CLKCTRL_CLKTRCTRL_SHIFT); } -void setup_sri2c(void) -{ - u32 sys_clk_khz, cycles_hi, cycles_low, temp; - - sys_clk_khz = get_sys_clk_freq() / 1000; - - /* - * Setup the dedicated I2C controller for Voltage Control - * I2C clk - high period 40% low period 60% - */ - cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; - cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; - /* values to be set in register - less by 5 & 7 respectively */ - cycles_hi -= 5; - cycles_low -= 7; - temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | - (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); - writel(temp, &prcm->prm_vc_cfg_i2c_clk); - - /* Disable high speed mode and all advanced features */ - writel(0x0, &prcm->prm_vc_cfg_i2c_mode); -} - void do_enable_clocks(u32 *const *clk_domains, u32 *const *clk_modules_hw_auto, u32 *const *clk_modules_explicit_en, diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 62678ff5d3..db509c9295 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -90,20 +90,33 @@ static void do_lpddr2_init(u32 base, u32 cs) * tZQINIT = 1 us * Enough loops assuming a maximum of 2GHz */ + sdelay(2000); - set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3); + + if (omap_revision() >= OMAP5430_ES1_0) + set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8); + else + set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3); + set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY); + /* * Enable refresh along with writing MR2 * Encoding of RL in MR2 is (RL - 2) */ mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; set_mr(base, cs, mr_addr, RL_FINAL - 2); + + if (omap_revision() >= OMAP5430_ES1_0) + set_mr(base, cs, LPDDR2_MR3, 0x1); } static void lpddr2_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + u32 i = 0; /* Not NVM */ clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK); @@ -119,7 +132,31 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs) * un-locked frequency & default RL */ writel(regs->sdram_config_init, &emif->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + + ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); + + if (omap_revision() >= OMAP5430_ES1_0) { + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + + /* + * external phy 6-24 registers do not change with + * ddr frequency + */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { + writel(ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + } + } do_lpddr2_init(base, CS0); if (regs->sdram_config & EMIF_REG_EBANK_MASK) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index ab46bff5af..cf71ab4443 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -203,21 +203,15 @@ int checkboard(void) } /* -* This function is called by start_armboot. You can reliably use static -* data. Any boot-time function that require static data should be -* called from here -*/ -int arch_cpu_init(void) -{ - return 0; -} - -/* * get_device_type(): tell if GP/HS/EMU/TST */ u32 get_device_type(void) { - return 0; + struct omap_sys_ctrl_regs *ctrl = + (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + + return (readl(&ctrl->control_status) & + (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; } /* diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 35f38acf5d..ccc6bb6b85 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -27,9 +27,9 @@ */ #include <asm/arch/omap.h> +#include <linux/linkage.h> -.global save_boot_params -save_boot_params: +ENTRY(save_boot_params) /* * See if the rom code passed pointer is valid: * It is not valid if it is not in non-secure SRAM @@ -76,10 +76,9 @@ save_boot_params: strb r2, [r3, #CH_FLAGS_OFFSET] 1: bx lr +ENDPROC(save_boot_params) - -.globl lowlevel_init -lowlevel_init: +ENTRY(lowlevel_init) /* * Setup a temporary stack */ @@ -95,12 +94,13 @@ lowlevel_init: */ bl s_init pop {ip, pc} +ENDPROC(lowlevel_init) -.globl set_pl310_ctrl_reg -set_pl310_ctrl_reg: +ENTRY(set_pl310_ctrl_reg) PUSH {r4-r11, lr} @ save registers - ROM code may pollute @ our registers LDR r12, =0x102 @ Set PL310 control register - value in R0 .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 @ call ROM Code API to set control register POP {r4-r11, pc} +ENDPROC(set_pl310_ctrl_reg) diff --git a/arch/arm/cpu/armv7/omap-common/reset.S b/arch/arm/cpu/armv7/omap-common/reset.c index 838b1221ee..234e90a868 100644 --- a/arch/arm/cpu/armv7/omap-common/reset.S +++ b/arch/arm/cpu/armv7/omap-common/reset.c @@ -1,6 +1,11 @@ /* - * Copyright (c) 2009 Samsung Electronics. - * Minkyu Kang <mk7.kang@samsung.com> + * + * Common layer for reset related functionality of OMAP based socs. + * + * (C) Copyright 2012 + * Texas Instruments, <www.ti.com> + * + * Sricharan R <r.sricharan@ti.com> * * See file CREDITS for list of people who contributed to this * project. @@ -20,19 +25,12 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - #include <config.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <linux/compiler.h> -.global reset_cpu -reset_cpu: - ldr r1, rstctl @ get addr for global reset - @ reg - ldr r3, rstbit @ sw reset bit - str r3, [r1] @ force reset - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl: - .word PRM_RSTCTRL -rstbit: - .word PRM_RSTCTRL_RESET +void __weak reset_cpu(unsigned long ignored) +{ + writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); +} diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index 0f2e0a2d27..4d1ac85d00 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -162,6 +162,7 @@ void board_init_r(gd_t *id, ulong dummy) #ifdef CONFIG_SPL_MMC_SUPPORT case BOOT_DEVICE_MMC1: case BOOT_DEVICE_MMC2: + case BOOT_DEVICE_MMC2_2: spl_mmc_load_image(); break; #endif diff --git a/arch/arm/cpu/armv7/omap-common/spl_mmc.c b/arch/arm/cpu/armv7/omap-common/spl_mmc.c index 6f5b43e559..2f921bb07d 100644 --- a/arch/arm/cpu/armv7/omap-common/spl_mmc.c +++ b/arch/arm/cpu/armv7/omap-common/spl_mmc.c @@ -39,10 +39,11 @@ int board_mmc_init(bd_t *bis) { switch (omap_boot_device()) { case BOOT_DEVICE_MMC1: - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); break; case BOOT_DEVICE_MMC2: - omap_mmc_init(1); + case BOOT_DEVICE_MMC2_2: + omap_mmc_init(1, 0, 0); break; } return 0; diff --git a/arch/arm/cpu/armv7/omap-common/spl_nand.c b/arch/arm/cpu/armv7/omap-common/spl_nand.c index 1295e88752..8cf55c9a1c 100644 --- a/arch/arm/cpu/armv7/omap-common/spl_nand.c +++ b/arch/arm/cpu/armv7/omap-common/spl_nand.c @@ -54,7 +54,7 @@ void spl_nand_load_image(void) * load parameter image * load to temp position since nand_spl_load_image reads * a whole block which is typically larger than - * CONFIG_CMD_SAVEBP_WRITE_SIZE therefore may overwrite + * CONFIG_CMD_SPL_WRITE_SIZE therefore may overwrite * following sections like BSS */ nand_spl_load_image(CONFIG_CMD_SPL_NAND_OFS, diff --git a/arch/arm/cpu/armv7/omap-common/vc.c b/arch/arm/cpu/armv7/omap-common/vc.c new file mode 100644 index 0000000000..a045b77180 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/vc.c @@ -0,0 +1,138 @@ +/* + * Voltage Controller implementation for OMAP + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Nishanth Menon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/omap_common.h> +#include <asm/arch/sys_proto.h> + +/* + * Define Master code if there are multiple masters on the I2C_SR bus. + * Normally not required + */ +#ifndef CONFIG_OMAP_VC_I2C_HS_MCODE +#define CONFIG_OMAP_VC_I2C_HS_MCODE 0x0 +#endif + +/* Register defines and masks for VC IP Block */ +/* PRM_VC_CFG_I2C_MODE */ +#define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT (0x1 << 6) +#define PRM_VC_CFG_I2C_MODE_SRMODEEN_BIT (0x1 << 4) +#define PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT (0x1 << 3) +#define PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT 0x0 +#define PRM_VC_CFG_I2C_MODE_HSMCODE_MASK 0x3 + +/* PRM_VC_CFG_I2C_CLK */ +#define PRM_VC_CFG_I2C_CLK_HSCLL_SHIFT 24 +#define PRM_VC_CFG_I2C_CLK_HSCLL_MASK 0xFF +#define PRM_VC_CFG_I2C_CLK_HSCLH_SHIFT 16 +#define PRM_VC_CFG_I2C_CLK_HSCLH_MASK 0xFF +#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 +#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF +#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 +#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) + +/* PRM_VC_VAL_BYPASS */ +#define PRM_VC_VAL_BYPASS_VALID_BIT (0x1 << 24) +#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 +#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F +#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 +#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF +#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 +#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF + +/** + * omap_vc_init() - Initialization for Voltage controller + * @speed_khz: I2C buspeed in KHz + */ +void omap_vc_init(u16 speed_khz) +{ + u32 val; + u32 sys_clk_khz, cycles_hi, cycles_low; + + sys_clk_khz = get_sys_clk_freq() / 1000; + + if (speed_khz > 400) { + puts("higher speed requested - throttle to 400Khz\n"); + speed_khz = 400; + } + + /* + * Setup the dedicated I2C controller for Voltage Control + * I2C clk - high period 40% low period 60% + */ + speed_khz /= 10; + cycles_hi = sys_clk_khz * 4 / speed_khz; + cycles_low = sys_clk_khz * 6 / speed_khz; + /* values to be set in register - less by 5 & 7 respectively */ + cycles_hi -= 5; + cycles_low -= 7; + val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | + (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); + writel(val, &prcm->prm_vc_cfg_i2c_clk); + + val = CONFIG_OMAP_VC_I2C_HS_MCODE << + PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT; + /* No HS mode for now */ + val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT; + writel(val, &prcm->prm_vc_cfg_i2c_mode); +} + +/** + * omap_vc_bypass_send_value() - Send a data using VC Bypass command + * @sa: 7 bit I2C slave address of the PMIC + * @reg_addr: I2C register address(8 bit) address in PMIC + * @reg_data: what 8 bit data to write + */ +int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) +{ + /* + * Unfortunately we need to loop here instead of a defined time + * use arbitary large value + */ + u32 timeout = 0xFFFF; + u32 reg_val; + + sa &= PRM_VC_VAL_BYPASS_SLAVEADDR_MASK; + reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK; + reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK; + + /* program VC to send data */ + reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT | + reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT | + reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT; + writel(reg_val, &prcm->prm_vc_val_bypass); + + /* Signal VC to send data */ + writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, &prcm->prm_vc_val_bypass); + + /* Wait on VC to complete transmission */ + do { + reg_val = readl(&prcm->prm_vc_val_bypass) & + PRM_VC_VAL_BYPASS_VALID_BIT; + if (!reg_val) + break; + + sdelay(100); + } while (--timeout); + + /* Optional: cleanup PRM_IRQSTATUS_Ax */ + /* In case we can do something about it in future.. */ + if (!timeout) + return -1; + + /* All good.. */ + return 0; +} diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 1fee574364..f2e52e9ce1 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -41,6 +41,7 @@ #include <asm/arch/gpio.h> #include <asm/omap_common.h> #include <i2c.h> +#include <linux/compiler.h> /* Declarations */ extern omap3_sysinfo sysinfo; @@ -244,6 +245,17 @@ void s_init(void) mem_init(); } +/* + * Routine: misc_init_r + * Description: A basic misc_init_r that just displays the die ID + */ +int __weak misc_init_r(void) +{ + dieid_num_r(); + + return 0; +} + /****************************************************************************** * Routine: wait_for_command_complete * Description: Wait for posting to finish on watchdog diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 567817e0ec..09c51f62aa 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -572,6 +572,22 @@ void prcm_init(void) } if (get_cpu_family() == CPU_OMAP36XX) { + /* + * In warm reset conditions on OMAP36xx/AM/DM37xx + * the rom code incorrectly sets the DPLL4 clock + * input divider to /6.5. Section 3.5.3.3.3.2.1 of + * the AM/DM37x TRM explains that the /6.5 divider + * is used only when the input clock is 13MHz. + * + * If the part is in this cpu family *and* the input + * clock *is not* 13 MHz, then reset the DPLL4 clock + * input divider to /1 as it should never set to /6.5 + * in this case. + */ + if (sys_clkin_sel != 1) /* 13 MHz */ + /* Bit 8: DPLL4_CLKINP_DIV */ + sr32(&prm_base->clksrc_ctrl, 8, 1, 0); + /* Unlock MPU DPLL (slows things down, and needed later) */ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index c42c5ddcc9..ebf69fa17d 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -31,22 +31,22 @@ #include <version.h> #include <asm/arch/mem.h> #include <asm/arch/clocks_omap3.h> +#include <linux/linkage.h> _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ #ifdef CONFIG_SPL_BUILD -.global save_boot_params -save_boot_params: +ENTRY(save_boot_params) ldr r4, =omap3_boot_device ldr r5, [r0, #0x4] and r5, r5, #0xff str r5, [r4] bx lr +ENDPROC(save_boot_params) #endif -.global omap3_gp_romcode_call -omap3_gp_romcode_call: +ENTRY(omap3_gp_romcode_call) PUSH {r4-r12, lr} @ Save all registers from ROM code! MOV r12, r0 @ Copy the Service ID in R12 MOV r0, r1 @ Copy parameter to R0 @@ -55,6 +55,7 @@ omap3_gp_romcode_call: .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled @ because we use -march=armv5 POP {r4-r12, pc} +ENDPROC(omap3_gp_romcode_call) /* * Funtion for making PPA HAL API calls in secure devices @@ -62,8 +63,7 @@ omap3_gp_romcode_call: * R0 - Service ID * R1 - paramer list */ -.global do_omap3_emu_romcode_call -do_omap3_emu_romcode_call: +ENTRY(do_omap3_emu_romcode_call) PUSH {r4-r12, lr} @ Save all registers from ROM code! MOV r12, r0 @ Copy the Secure Service ID in R12 MOV r3, r1 @ Copy the pointer to va_list in R3 @@ -76,14 +76,14 @@ do_omap3_emu_romcode_call: .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled @ because we use -march=armv5 POP {r4-r12, pc} +ENDPROC(do_omap3_emu_romcode_call) #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) /************************************************************************** * cpy_clk_code: relocates clock code into SRAM where its safer to execute * R1 = SRAM destination address. *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: +ENTRY(cpy_clk_code) /* Copy DPLL code into SRAM */ adr r0, go_to_speed /* get addr of clock setting code */ mov r2, #384 /* r2 size to copy (div by 32 bytes) */ @@ -95,6 +95,7 @@ next2: cmp r0, r2 /* until source end address [r2] */ bne next2 mov pc, lr /* back to caller */ +ENDPROC(cpy_clk_code) /* *************************************************************************** * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed @@ -109,8 +110,7 @@ next2: * L3 when its not in self refresh seems bad for it. Normally, this * code runs from flash before SDR is init so that should be ok. ****************************************************************************/ -.global go_to_speed - go_to_speed: +ENTRY(go_to_speed) stmfd sp!, {r4 - r6} /* move into fast relock bypass */ @@ -171,6 +171,7 @@ wait2: nop ldmfd sp!, {r4 - r6} mov pc, lr /* back to caller, locked */ +ENDPROC(go_to_speed) _go_to_speed: .word go_to_speed @@ -211,8 +212,7 @@ pll_div_val5: #endif -.globl lowlevel_init -lowlevel_init: +ENTRY(lowlevel_init) ldr sp, SRAM_STACK str ip, [sp] /* stash old link register */ mov ip, lr /* save link reg across call */ @@ -230,6 +230,7 @@ lowlevel_init: /* back to arch calling code */ mov pc, lr +ENDPROC(lowlevel_init) /* the literal pools origin */ .ltorg @@ -480,22 +481,22 @@ per_36x_dpll_param: .word 26000, 432, 12, 9, 16, 9, 4, 3, 1 .word 38400, 360, 15, 9, 16, 5, 4, 3, 1 -.globl get_36x_mpu_dpll_param -get_36x_mpu_dpll_param: +ENTRY(get_36x_mpu_dpll_param) adr r0, mpu_36x_dpll_param mov pc, lr +ENDPROC(get_36x_mpu_dpll_param) -.globl get_36x_iva_dpll_param -get_36x_iva_dpll_param: +ENTRY(get_36x_iva_dpll_param) adr r0, iva_36x_dpll_param mov pc, lr +ENDPROC(get_36x_iva_dpll_param) -.globl get_36x_core_dpll_param -get_36x_core_dpll_param: +ENTRY(get_36x_core_dpll_param) adr r0, core_36x_dpll_param mov pc, lr +ENDPROC(get_36x_core_dpll_param) -.globl get_36x_per_dpll_param -get_36x_per_dpll_param: +ENTRY(get_36x_per_dpll_param) adr r0, per_36x_dpll_param mov pc, lr +ENDPROC(get_36x_per_dpll_param) diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index e2189f729f..c568951a91 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -46,8 +46,6 @@ #define puts(s) #endif -#define abs(x) (((x) < 0) ? ((x)*-1) : (x)) - struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100; const u32 sys_clk_array[8] = { @@ -275,47 +273,70 @@ void scale_vcores(void) { u32 volt, omap_rev; - setup_sri2c(); + omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); omap_rev = omap_revision(); - /* TPS - supplies vdd_mpu on 4460 */ - if (omap_rev >= OMAP4460_ES1_0) { - volt = 1203; - do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt); - } /* - * VCORE 1 - * - * 4430 : supplies vdd_mpu - * Setting a high voltage for Nitro mode as smart reflex is not enabled. - * We use the maximum possible value in the AVS range because the next - * higher voltage in the discrete range (code >= 0b111010) is way too - * high - * - * 4460 : supplies vdd_core + * Scale Voltage rails: + * 1. VDD_CORE + * 3. VDD_MPU + * 3. VDD_IVA */ if (omap_rev < OMAP4460_ES1_0) { + /* + * OMAP4430: + * VDD_CORE = TWL6030 VCORE3 + * VDD_MPU = TWL6030 VCORE1 + * VDD_IVA = TWL6030 VCORE2 + */ + volt = 1200; + do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); + + /* + * note on VDD_MPU: + * Setting a high voltage for Nitro mode as smart reflex is not + * enabled. We use the maximum possible value in the AVS range + * because the next higher voltage in the discrete range + * (code >= 0b111010) is way too high. + */ volt = 1325; do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); + volt = 1200; + do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); + } else { + /* + * OMAP4460: + * VDD_CORE = TWL6030 VCORE1 + * VDD_MPU = TPS62361 + * VDD_IVA = TWL6030 VCORE2 + */ volt = 1200; do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); + /* TPS62361 */ + volt = 1203; + do_scale_tps62361(TPS62361_VSEL0_GPIO, + TPS62361_REG_ADDR_SET1, volt); + /* VCORE 2 - supplies vdd_iva */ + volt = 1200; + do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); } +} - /* VCORE 2 - supplies vdd_iva */ - volt = 1200; - do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); +u32 get_offset_code(u32 offset) +{ + u32 offset_code, step = 12660; /* 12.66 mV represented in uV */ - /* - * VCORE 3 - * 4430 : supplies vdd_core - * 4460 : not connected - */ - if (omap_rev < OMAP4460_ES1_0) { - volt = 1200; - do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); - } + if (omap_revision() == OMAP4430_ES1_0) + offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; + else + offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; + + offset_code = (offset + step - 1) / step; + + /* The code starts at 1 not 0 */ + return ++offset_code; } /* @@ -355,7 +376,6 @@ void enable_basic_clocks(void) &prcm->cm_l4per_gptimer2_clkctrl, &prcm->cm_wkup_wdtimer2_clkctrl, &prcm->cm_l4per_uart3_clkctrl, - &prcm->cm_l3init_fsusb_clkctrl, &prcm->cm_l3init_hsusbhost_clkctrl, 0 }; @@ -432,10 +452,6 @@ void enable_non_essential_clocks(void) }; u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_mpu_m3_mpu_m3_clkctrl, - &prcm->cm_ivahd_ivahd_clkctrl, - &prcm->cm_ivahd_sl2_clkctrl, - &prcm->cm_dsp_dsp_clkctrl, &prcm->cm_l3_2_gpmc_clkctrl, &prcm->cm_l3instr_l3_3_clkctrl, &prcm->cm_l3instr_l3_instr_clkctrl, @@ -482,7 +498,6 @@ void enable_non_essential_clocks(void) &prcm->cm_dss_dss_clkctrl, &prcm->cm_sgx_sgx_clkctrl, &prcm->cm_l3init_hsusbhost_clkctrl, - &prcm->cm_l3init_fsusb_clkctrl, 0 }; diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 91f83205ed..187e93887b 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; -u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV; +u32 *const omap_si_rev = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV; static const struct gpio_bank gpio_bank_44xx[6] = { { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX }, @@ -59,8 +59,8 @@ void do_io_settings(void) u32 lpddr2io; struct control_lpddr2io_regs *lpddr2io_regs = (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE; - struct omap4_sys_ctrl_regs *const ctrl = - (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; + struct omap_sys_ctrl_regs *const ctrl = + (struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; u32 omap4_rev = omap_revision(); @@ -129,40 +129,40 @@ void init_omap_revision(void) switch (arm_rev) { case MIDR_CORTEX_A9_R0P1: - *omap4_revision = OMAP4430_ES1_0; + *omap_si_rev = OMAP4430_ES1_0; break; case MIDR_CORTEX_A9_R1P2: switch (readl(CONTROL_ID_CODE)) { case OMAP4_CONTROL_ID_CODE_ES2_0: - *omap4_revision = OMAP4430_ES2_0; + *omap_si_rev = OMAP4430_ES2_0; break; case OMAP4_CONTROL_ID_CODE_ES2_1: - *omap4_revision = OMAP4430_ES2_1; + *omap_si_rev = OMAP4430_ES2_1; break; case OMAP4_CONTROL_ID_CODE_ES2_2: - *omap4_revision = OMAP4430_ES2_2; + *omap_si_rev = OMAP4430_ES2_2; break; default: - *omap4_revision = OMAP4430_ES2_0; + *omap_si_rev = OMAP4430_ES2_0; break; } break; case MIDR_CORTEX_A9_R1P3: - *omap4_revision = OMAP4430_ES2_3; + *omap_si_rev = OMAP4430_ES2_3; break; case MIDR_CORTEX_A9_R2P10: switch (readl(CONTROL_ID_CODE)) { case OMAP4460_CONTROL_ID_CODE_ES1_1: - *omap4_revision = OMAP4460_ES1_1; + *omap_si_rev = OMAP4460_ES1_1; break; case OMAP4460_CONTROL_ID_CODE_ES1_0: default: - *omap4_revision = OMAP4460_ES1_0; + *omap_si_rev = OMAP4460_ES1_0; break; } break; default: - *omap4_revision = OMAP4430_SILICON_ID_INVALID; + *omap_si_rev = OMAP4430_SILICON_ID_INVALID; break; } } diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index a5ec7d3dcc..b5389606b6 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -89,6 +89,10 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = { .emif_ddr_phy_ctlr_1_init = 0x049ffff5, .emif_ddr_phy_ctlr_1 = 0x049ff418 }; + +/* Dummy registers for OMAP44xx */ +const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; + const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, .dmm_lisa_map_1 = 0, diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index f8ca9ac367..9b261c4df2 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -28,7 +28,7 @@ LIB = $(obj)lib$(SOC).o COBJS += hwinit.o COBJS += clocks.o COBJS += emif.o -COBJS += sdram_elpida.o +COBJS += sdram.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index dd882a202e..1a59f265f7 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -88,6 +88,26 @@ static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = { {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; +static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { + {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = { + {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = { {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ @@ -100,24 +120,24 @@ static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = { static const struct dpll_params core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { - {266, 2, 1, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */ + {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {570, 8, 1, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */ - {665, 11, 1, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */ - {532, 12, 1, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */ + {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */ + {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */ + {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {665, 23, 1, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */ + {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */ }; static const struct dpll_params core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { - {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */ + {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */ - {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */ - {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */ + {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */ + {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */ + {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */ + {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */ }; static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { @@ -131,40 +151,40 @@ static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { }; static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { - {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */ - {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */ - {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */ - {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ - {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ - {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ - {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ + {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */ + {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */ + {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */ }; /* ABE M & N values with sys_clk as source */ static const struct dpll_params abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { - {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */ - {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */ - {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */ - {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */ - {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */ - {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */ - {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */ + {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; /* ABE M & N values with 32K clock as source */ static const struct dpll_params abe_dpll_params_32k_196608khz = { - 750, 0, 1, 1, -1, -1, -1, -1 + 750, 0, 1, 1, -1, -1, -1, -1, -1, -1 }; static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { - {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */ - {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */ - {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */ - {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */ - {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; void setup_post_dividers(u32 *const base, const struct dpll_params *params) @@ -193,7 +213,7 @@ void setup_post_dividers(u32 *const base, const struct dpll_params *params) const struct dpll_params *get_mpu_dpll_params(void) { u32 sysclk_ind = get_sys_clk_index(); - return &mpu_dpll_params_1100mhz[sysclk_ind]; + return &mpu_dpll_params_800mhz[sysclk_ind]; } const struct dpll_params *get_core_dpll_params(void) @@ -201,8 +221,7 @@ const struct dpll_params *get_core_dpll_params(void) u32 sysclk_ind = get_sys_clk_index(); /* Configuring the DDR to be at 532mhz */ - return &core_dpll_params_2128mhz_ddr266[sysclk_ind]; - + return &core_dpll_params_2128mhz_ddr532[sysclk_ind]; } const struct dpll_params *get_per_dpll_params(void) @@ -243,19 +262,33 @@ void scale_vcores(void) { u32 volt; - setup_sri2c(); + omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); + + /* Palmas settings */ + volt = VDD_CORE; + do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt); - /* Enable 1.22V from TPS for vdd_mpu */ - volt = 1220; - do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt); + volt = VDD_MPU; + do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt); - /* VCORE 1 - for vdd_core */ - volt = 1000; - do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); + volt = VDD_MM; + do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt); - /* VCORE 2 - for vdd_MM */ - volt = 1125; - do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); +} + +u32 get_offset_code(u32 volt_offset) +{ + u32 offset_code, step = 10000; /* 10 mV represented in uV */ + + volt_offset -= PALMAS_SMPS_BASE_VOLT_UV; + + offset_code = (volt_offset + step - 1) / step; + + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + return offset_code + 6; } /* @@ -306,6 +339,12 @@ void enable_basic_clocks(void) setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); + /* Set the correct clock dividers for mmc */ + setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + /* Select 32KHz clock as the source of GPTIMER1 */ setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl, GPTIMER1_CLKCTRL_CLKSEL_MASK); @@ -314,6 +353,18 @@ void enable_basic_clocks(void) clk_modules_hw_auto_essential, clk_modules_explicit_en_essential, 1); + + /* Select 384Mhz for GPU as its the POR for ES1.0 */ + setbits_le32(&prcm->cm_sgx_sgx_clkctrl, + CLKSEL_GPU_HYD_GCLK_MASK); + setbits_le32(&prcm->cm_sgx_sgx_clkctrl, + CLKSEL_GPU_CORE_GCLK_MASK); + + /* Enable SCRM OPT clocks for PER and CORE dpll */ + setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl, + OPTFCLKEN_SCRM_PER_MASK); + setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl, + OPTFCLKEN_SCRM_CORE_MASK); } void enable_basic_uboot_clocks(void) @@ -371,6 +422,7 @@ void enable_non_essential_clocks(void) &prcm->cm_l3instr_intrconn_wp1_clkctrl, &prcm->cm_l3init_hsi_clkctrl, &prcm->cm_l3init_hsusbtll_clkctrl, + &prcm->cm_l4per_hdq1w_clkctrl, 0 }; @@ -393,7 +445,6 @@ void enable_non_essential_clocks(void) &prcm->cm_l4per_gptimer11_clkctrl, &prcm->cm_l4per_gptimer3_clkctrl, &prcm->cm_l4per_gptimer4_clkctrl, - &prcm->cm_l4per_hdq1w_clkctrl, &prcm->cm_l4per_mcspi2_clkctrl, &prcm->cm_l4per_mcspi3_clkctrl, &prcm->cm_l4per_mcspi4_clkctrl, diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index fa8e390c17..d01cc81333 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; -u32 *const omap5_revision = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV; +u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV; static struct gpio_bank gpio_bank_54xx[6] = { { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX }, @@ -57,6 +57,89 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx; */ void do_io_settings(void) { + u32 io_settings = 0, mask = 0; + struct omap_sys_ctrl_regs *ioregs_base = + (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + + /* Impedance settings EMMC, C2C 1,2, hsi2 */ + mask = (ds_mask << 2) | (ds_mask << 8) | + (ds_mask << 16) | (ds_mask << 18); + io_settings = readl(&(ioregs_base->control_smart1io_padconf_0)) & + (~mask); + io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) | + (ds_45_ohm << 18) | (ds_60_ohm << 2); + writel(io_settings, &(ioregs_base->control_smart1io_padconf_0)); + + /* Impedance settings Mcspi2 */ + mask = (ds_mask << 30); + io_settings = readl(&(ioregs_base->control_smart1io_padconf_1)) & + (~mask); + io_settings |= (ds_60_ohm << 30); + writel(io_settings, &(ioregs_base->control_smart1io_padconf_1)); + + /* Impedance settings C2C 3,4 */ + mask = (ds_mask << 14) | (ds_mask << 16); + io_settings = readl(&(ioregs_base->control_smart1io_padconf_2)) & + (~mask); + io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16); + writel(io_settings, &(ioregs_base->control_smart1io_padconf_2)); + + /* Slew rate settings EMMC, C2C 1,2 */ + mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18); + io_settings = readl(&(ioregs_base->control_smart2io_padconf_0)) & + (~mask); + io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18); + writel(io_settings, &(ioregs_base->control_smart2io_padconf_0)); + + /* Slew rate settings hsi2, Mcspi2 */ + mask = (sc_mask << 24) | (sc_mask << 28); + io_settings = readl(&(ioregs_base->control_smart2io_padconf_1)) & + (~mask); + io_settings |= (sc_fast << 28) | (sc_fast << 24); + writel(io_settings, &(ioregs_base->control_smart2io_padconf_1)); + + /* Slew rate settings C2C 3,4 */ + mask = (sc_mask << 16) | (sc_mask << 18); + io_settings = readl(&(ioregs_base->control_smart2io_padconf_2)) & + (~mask); + io_settings |= (sc_na << 16) | (sc_na << 18); + writel(io_settings, &(ioregs_base->control_smart2io_padconf_2)); + + /* impedance and slew rate settings for usb */ + mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) | + (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14); + io_settings = readl(&(ioregs_base->control_smart3io_padconf_1)) & + (~mask); + io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) | + (ds_60_ohm << 23) | (sc_fast << 20) | + (sc_fast << 17) | (sc_fast << 14); + writel(io_settings, &(ioregs_base->control_smart3io_padconf_1)); + + /* LPDDR2 io settings */ + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch1_0)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch1_1)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch2_0)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch2_1)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, + &(ioregs_base->control_lpddr2ch1_0)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, + &(ioregs_base->control_lpddr2ch1_1)); + writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, + &(ioregs_base->control_ddrio_0)); + writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, + &(ioregs_base->control_ddrio_1)); + writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, + &(ioregs_base->control_ddrio_2)); + + /* Efuse settings */ + writel(EFUSE_1, &(ioregs_base->control_efuse_1)); + writel(EFUSE_2, &(ioregs_base->control_efuse_2)); + writel(EFUSE_3, &(ioregs_base->control_efuse_3)); + writel(EFUSE_4, &(ioregs_base->control_efuse_4)); } #endif @@ -71,8 +154,23 @@ void init_omap_revision(void) switch (rev) { case MIDR_CORTEX_A15_R0P0: - *omap5_revision = OMAP5430_ES1_0; + *omap_si_rev = OMAP5430_ES1_0; + break; default: - *omap5_revision = OMAP5430_SILICON_ID_INVALID; + *omap_si_rev = OMAP5430_SILICON_ID_INVALID; } } + +void reset_cpu(ulong ignored) +{ + u32 omap_rev = omap_revision(); + + /* + * WARM reset is not functional in case of OMAP5430 ES1.0 soc. + * So use cold reset in case instead. + */ + if (omap_rev == OMAP5430_ES1_0) + writel(PRM_RSTCTRL_RESET << 0x1, PRM_RSTCTRL); + else + writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); +} diff --git a/arch/arm/cpu/armv7/omap5/sdram_elpida.c b/arch/arm/cpu/armv7/omap5/sdram.c index ad198e6d1b..b2b5753e89 100644 --- a/arch/arm/cpu/armv7/omap5/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -1,5 +1,5 @@ /* - * Timing and Organization details of the Elpida parts used in OMAP5 + * Timing and Organization details of the ddr device parts used in OMAP5 * EVM * * (C) Copyright 2010 @@ -48,31 +48,76 @@ */ #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - -const struct emif_regs emif_regs_elpida_532_mhz_1cs = { - .sdram_config_init = 0x80801aB2, - .sdram_config = 0x808022B2, +const struct emif_regs emif_regs_532_mhz_2cs = { + .sdram_config_init = 0x80800EBA, + .sdram_config = 0x808022BA, .ref_ctrl = 0x0000081A, .sdram_tim1 = 0x772F6873, - .sdram_tim2 = 0x304A129A, - .sdram_tim3 = 0x02F7E45F, + .sdram_tim2 = 0x304a129a, + .sdram_tim3 = 0x02f7e45f, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x000b3215, + .temp_alert_config = 0x08000a05, + .emif_ddr_phy_ctlr_1_init = 0x0E28420d, + .emif_ddr_phy_ctlr_1 = 0x0E28420d, + .emif_ddr_ext_phy_ctrl_1 = 0x04020080, + .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3, + .emif_ddr_ext_phy_ctrl_3 = 0x518A3146, + .emif_ddr_ext_phy_ctrl_4 = 0x0014628C, + .emif_ddr_ext_phy_ctrl_5 = 0x04010040 +}; + +const struct emif_regs emif_regs_266_mhz_2cs = { + .sdram_config_init = 0x80800EBA, + .sdram_config = 0x808022BA, + .ref_ctrl = 0x0000040D, + .sdram_tim1 = 0x2A86B419, + .sdram_tim2 = 0x1025094A, + .sdram_tim3 = 0x026BA22F, .read_idle_ctrl = 0x00050000, - .zq_config = 0x000B3215, - .temp_alert_config = 0x08000A05, - .emif_ddr_phy_ctlr_1_init = 0x0E38200D, - .emif_ddr_phy_ctlr_1 = 0x0E38200D + .zq_config = 0x000b3215, + .temp_alert_config = 0x08000a05, + .emif_ddr_phy_ctlr_1_init = 0x0E28420d, + .emif_ddr_phy_ctlr_1 = 0x0E28420d, + .emif_ddr_ext_phy_ctrl_1 = 0x04020080, + .emif_ddr_ext_phy_ctrl_2 = 0x0A414829, + .emif_ddr_ext_phy_ctrl_3 = 0x14829052, + .emif_ddr_ext_phy_ctrl_4 = 0x000520A4, + .emif_ddr_ext_phy_ctrl_5 = 0x04010040 }; -const struct dmm_lisa_map_regs lisa_map_4G_x_1_x_2 = { - .dmm_lisa_map_0 = 0xFF020100, +const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { + .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0, .dmm_lisa_map_2 = 0, - .dmm_lisa_map_3 = 0x80640300 + .dmm_lisa_map_3 = 0x80740300 +}; + +const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x01004010, + 0x00001004, + 0x04010040, + 0x01004010, + 0x00001004, + 0x00000000, + 0x00000000, + 0x00000000, + 0x80080080, + 0x00800800, + 0x08102040, + 0x00000001, + 0x540A8150, + 0xA81502a0, + 0x002A0540, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000077 }; static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) { - *regs = &emif_regs_elpida_532_mhz_1cs; + *regs = &emif_regs_532_mhz_2cs; } void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) __attribute__((weak, alias("emif_get_reg_dump_sdp"))); @@ -80,7 +125,7 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs) { - *dmm_lisa_regs = &lisa_map_4G_x_1_x_2; + *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; } void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) @@ -88,11 +133,11 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) #else -static const struct lpddr2_device_details elpida_4G_S4_details = { +static const struct lpddr2_device_details dev_4G_S4_details = { .type = LPDDR2_TYPE_S4, .density = LPDDR2_DENSITY_4Gb, .io_width = LPDDR2_IO_WIDTH_32, - .manufacturer = LPDDR2_MANUFACTURER_ELPIDA + .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG }; static void emif_get_device_details_sdp(u32 emif_nr, @@ -100,10 +145,8 @@ static void emif_get_device_details_sdp(u32 emif_nr, struct lpddr2_device_details *cs1_device_details) { /* EMIF1 & EMIF2 have identical configuration */ - *cs0_device_details = elpida_4G_S4_details; - - /* Nothing is conected on cs1 */ - cs1_device_details = NULL; + *cs0_device_details = dev_4G_S4_details; + *cs1_device_details = dev_4G_S4_details; } void emif_get_device_details(u32 emif_nr, @@ -137,7 +180,7 @@ static const struct lpddr2_ac_timings timings_jedec_532_mhz = { .tFAW = 50 }; -static const struct lpddr2_min_tck min_tck_elpida = { +static const struct lpddr2_min_tck min_tck = { .tRL = 3, .tRP_AB = 3, .tRCD = 3, @@ -152,13 +195,13 @@ static const struct lpddr2_min_tck min_tck_elpida = { .tFAW = 8 }; -static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = { +static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = { &timings_jedec_532_mhz }; -static const struct lpddr2_device_timings elpida_4G_S4_timings = { - .ac_timings = elpida_ac_timings, - .min_tck = &min_tck_elpida, +static const struct lpddr2_device_timings dev_4G_S4_timings = { + .ac_timings = ac_timings, + .min_tck = &min_tck, }; void emif_get_device_timings_sdp(u32 emif_nr, @@ -166,8 +209,8 @@ void emif_get_device_timings_sdp(u32 emif_nr, const struct lpddr2_device_timings **cs1_device_timings) { /* Identical devices on EMIF1 & EMIF2 */ - *cs0_device_timings = &elpida_4G_S4_timings; - *cs1_device_timings = NULL; + *cs0_device_timings = &dev_4G_S4_timings; + *cs1_device_timings = &dev_4G_S4_timings; } void emif_get_device_timings(u32 emif_nr, diff --git a/arch/arm/cpu/armv7/rda/Makefile b/arch/arm/cpu/armv7/rda/Makefile new file mode 100644 index 0000000000..b09e7b48ca --- /dev/null +++ b/arch/arm/cpu/armv7/rda/Makefile @@ -0,0 +1,62 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS-y += timer.o serial.o ifc.o cpu.o rda_sys.o ispi.o +COBJS-$(CONFIG_SPL_SIGNATURE_CHECK_IMAGE) += rda_crypto.o rda_romapi.o + +ifdef CONFIG_SPL_BUILD +COBJS-y += spl.o +COBJS-$(CONFIG_SPL_XMODEM_LOAD) += xmodem_boot.o +else +ifdef CONFIG_MDCOM +COBJS-y += mdcom.o +endif +endif + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +SOBJS += lowlevel_init.o +endif + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/rda/config.mk b/arch/arm/cpu/armv7/rda/config.mk new file mode 100644 index 0000000000..79fde41c14 --- /dev/null +++ b/arch/arm/cpu/armv7/rda/config.mk @@ -0,0 +1,95 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj@denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +include $(TOPDIR)/slt.mk +include $(TOPDIR)/customer.mk +include $(TOPDIR)/board/$(SOC)/$(BOARD)/config.mk + +image_flags := + +ifneq ($(TARGET_SYSTEMIMAGE_USE_UBIFS),) +image_flags += -DUBIFS_SYSTEM_IMAGE +endif + +ifneq ($(TARGET_USERIMAGES_USE_UBIFS),) +image_flags += -DUBIFS_USER_IMAGES +endif + +ifneq ($(TARGET_SYSTEMIMAGE_USE_EXT4),) +image_flags += -DEXTFS_SYSTEM_IMAGE +endif + +ifneq ($(TARGET_USERIMAGES_USE_EXT4),) +image_flags += -DEXTFS_USER_IMAGES +endif + +image_flags += -DSPL_APPENDING_TO=$(SPL_APPENDING_TO) + +pdl_flags := +ifeq ($(pdl), 1) +pdl_flags += -DCONFIG_RDA_PDL +endif + +nand_flags := +ifneq ($(BOARD_NAND_PAGE_SIZE),) +nand_flags += -DNAND_PAGE_SIZE=$(BOARD_NAND_PAGE_SIZE) +else +nand_flags += -DNAND_PAGE_SIZE=4096 +endif +ifneq ($(BOARD_FLASH_BLOCK_SIZE),) +nand_flags += -DNAND_BLOCK_SIZE=$(BOARD_FLASH_BLOCK_SIZE) +else +nand_flags += -DNAND_BLOCK_SIZE=262144 +endif +ifneq ($(BOARD_NAND_SPARE_SIZE),) +nand_flags += -DNAND_SPARE_SIZE=$(BOARD_NAND_SPARE_SIZE) +else +nand_flags += -DNAND_SPARE_SIZE=218 +endif +ifneq ($(BOARD_NAND_ECCMSGLEN),) +nand_flags += -DNAND_ECCMSGLEN=$(BOARD_NAND_ECCMSGLEN) +else +nand_flags += -DNAND_ECCMSGLEN=1024 +endif +ifneq ($(BOARD_NAND_ECCBITS),) +nand_flags += -DNAND_ECCBITS=$(BOARD_NAND_ECCBITS) +else +nand_flags += -DNAND_ECCBITS=24 +endif +ifneq ($(BOARD_NAND_OOB_SIZE),) +nand_flags += -DNAND_OOBSIZE=$(BOARD_NAND_OOB_SIZE) +else +nand_flags += -DNAND_OOBSIZE=32 +endif + +build_variant_flags := + +ifneq ($(UBOOT_VARIANT), user) +build_variant_flags += -DCONFIG_UBOOT_VARIANT_DEBUG +endif + +ifneq ($(BUILD_DISPLAY_ID),) +build_variant_flags += -DBUILD_DISPLAY_ID="\"$(BUILD_DISPLAY_ID)\"" +endif + +PLATFORM_CPPFLAGS += $(image_flags) $(pdl_flags) $(build_variant_flags) $(nand_flags) + diff --git a/arch/arm/cpu/armv7/rda/cpu.c b/arch/arm/cpu/armv7/rda/cpu.c new file mode 100644 index 0000000000..e040455aa6 --- /dev/null +++ b/arch/arm/cpu/armv7/rda/cpu.c @@ -0,0 +1,87 @@ +#include <common.h> +#include <asm/arch/hardware.h> + +void enable_neon(void) +{ + /* enable cp10 and cp11 */ + uint32_t val; + + __asm__ volatile("mrc p15, 0, %0, c1, c1, 2" : "=r" (val)); + printf("CPU: p15-c1-c1 (NSACR): 0x%08x", val); + val |= (3<<10); + val &= ~(3<<14); + __asm__ volatile("mcr p15, 0, %0, c1, c1, 2" :: "r" (val)); + printf(" -> 0x%08x\n", val); + + __asm__ volatile("mrc p15, 0, %0, c1, c0, 2" : "=r" (val)); + printf("CPU: p15-c1-c0 (CPACR): 0x%08x", val); + val |= (3<<22)|(3<<20); + __asm__ volatile("mcr p15, 0, %0, c1, c0, 2" :: "r" (val)); + printf(" -> 0x%08x\n", val); + + /* set enable bit in fpexc */ + val = (1<<30); + __asm__ volatile("mcr p10, 7, %0, c8, c0, 0" :: "r" (val)); +} + +#if (defined(CONFIG_MACH_RDA8810E) \ +||defined(CONFIG_MACH_RDA8820) \ +||defined(CONFIG_MACH_RDA8810H) \ +||defined(CONFIG_MACH_RDA8850E)) +/* SMP MACHs */ +void smp_setup(void) +{ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #0x40\n" + "mcr p15, 0, r0, c1, c0, 1\n"); +} +#endif + +void enable_caches(void) +{ +#if (defined(CONFIG_MACH_RDA8810E) \ +||defined(CONFIG_MACH_RDA8820) \ +||defined(CONFIG_MACH_RDA8810H) \ +||defined(CONFIG_MACH_RDA8850E)) + printf("CPU: enable smp\n"); + smp_setup(); +#endif +#ifndef CONFIG_SYS_ICACHE_OFF + printf("CPU: enable instruction caches\n"); + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + printf("CPU: enable data caches\n"); + dcache_enable(); +#endif +#ifndef CONFIG_SYS_NEON_OFF + printf("CPU: enable neon\n"); + enable_neon(); +#endif +} + +#ifdef CONFIG_DISPLAY_CPUINFO +/* Print CPU information */ +int print_cpuinfo(void) +{ +#if defined(CONFIG_MACH_RDAARM926EJS) + printf("RDAARM926EJS FPGA\n"); +#elif defined(CONFIG_MACH_RDA8810) + printf("RDA8810 SoC\n"); +#elif defined(CONFIG_MACH_RDA8810E) + printf("RDA8810E SoC\n"); +#elif defined(CONFIG_MACH_RDA8820) + printf("RDA8820 SoC\n"); +#elif defined(CONFIG_MACH_RDA8850) + printf("RDA8850 SoC\n"); +#elif defined(CONFIG_MACH_RDA8850E) + printf("RDA8850E SoC\n"); +#elif defined(CONFIG_MACH_RDA8810H) + printf("RDA8810H SoC\n"); +#else +#error "Unknown RDA CPU" +#endif + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/cpu/armv7/rda/ifc.c b/arch/arm/cpu/armv7/rda/ifc.c new file mode 100644 index 0000000000..f280cac0af --- /dev/null +++ b/arch/arm/cpu/armv7/rda/ifc.c @@ -0,0 +1,172 @@ +#include "common.h" +#include <errno.h> + +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/reg_ifc.h> +#include <asm/arch/ifc.h> + +#undef assert +#ifdef DEBUG +#include <assert.h> +#else +#define assert(...) +#endif + +#define HAL_TRACE(...) + +HAL_IFC_REQUEST_ID_T g_halModuleIfcChannelOwner[SYS_IFC_STD_CHAN_NB]; + +void hal_IfcOpen(void) +{ + u8 channel; + + // Initialize the channel table with unknown requests. + for (channel = 0; channel < SYS_IFC_STD_CHAN_NB; channel++) + { + g_halModuleIfcChannelOwner[channel] = HAL_IFC_NO_REQWEST; + } +} + +HAL_IFC_REQUEST_ID_T hal_IfcGetOwner(u8 channel) +{ + // Here, we consider the transfer as previously finished. + if (channel == HAL_UNKNOWN_CHANNEL) return HAL_IFC_NO_REQWEST; + + // Channel number too big. + assert(channel < SYS_IFC_STD_CHAN_NB, channel); + + return g_halModuleIfcChannelOwner[channel]; +} + +void hal_IfcChannelRelease(HAL_IFC_REQUEST_ID_T requestId, u8 channel) +{ + //u32 status; + + // Here, we consider the transfer as previously finished. + if (channel == HAL_UNKNOWN_CHANNEL) return; + + // Channel number too big. + assert(channel < SYS_IFC_STD_CHAN_NB, channel); + + //status = hal_SysEnterCriticalSection(); + if (g_halModuleIfcChannelOwner[channel] == requestId) + { + // disable this channel + hwp_sysIfc->std_ch[channel].control = (SYS_IFC_REQ_SRC(requestId) + | SYS_IFC_CH_RD_HW_EXCH + | SYS_IFC_DISABLE); + // read the status of this channel + if (hwp_sysIfc->std_ch[channel].status & SYS_IFC_ENABLE) + { + HAL_TRACE(_HAL | TSTDOUT,0," Strange, the released channel not disabled yet"); + } + // Write the TC to 0 for next time the channel is re-enabled + hwp_sysIfc->std_ch[channel].tc = 0; + } + //hal_SysExitCriticalSection(status); +} + +void hal_IfcChannelFlush(HAL_IFC_REQUEST_ID_T requestId, u8 channel) +{ + //u32 status; + + // Here, we consider the transfer as previously finished. + if (channel == HAL_UNKNOWN_CHANNEL) return; + + // Channel number too big. + assert(channel < SYS_IFC_STD_CHAN_NB, channel); + + // Check that the channel is really owned by the peripheral + // which is doing the request, it could have been release + // automatically or by an IRQ handler. + //status = hal_SysEnterCriticalSection(); + if (g_halModuleIfcChannelOwner[channel] == requestId) + { + // If fifo not empty, flush it. + if ( !(hwp_sysIfc->std_ch[channel].status & SYS_IFC_FIFO_EMPTY) ) + { + hwp_sysIfc->std_ch[channel].control = + hwp_sysIfc->std_ch[channel].control | SYS_IFC_FLUSH; + } + } + //hal_SysExitCriticalSection(status); +} + +BOOL hal_IfcChannelIsFifoEmpty(HAL_IFC_REQUEST_ID_T requestId, u8 channel) +{ + //u32 status; + BOOL fifoIsEmpty = TRUE; + + // Here, we consider the transfer as previously finished. + if (channel == HAL_UNKNOWN_CHANNEL) return fifoIsEmpty; + + // Channel number too big. + assert(channel < SYS_IFC_STD_CHAN_NB, channel); + + // Check that the channel is really owned by the peripheral + // which is doing the request, it could have been release + // automatically or by an IRQ handler. + //status = hal_SysEnterCriticalSection(); + if (g_halModuleIfcChannelOwner[channel] == requestId) + { + fifoIsEmpty = + (FALSE != (hwp_sysIfc->std_ch[channel].status & SYS_IFC_FIFO_EMPTY)); + } + //hal_SysExitCriticalSection(status); + + return fifoIsEmpty; +} + +u8 hal_IfcTransferStart(HAL_IFC_REQUEST_ID_T requestId, u8* memStartAddr, u32 xferSize, HAL_IFC_MODE_T ifcMode) +{ + //u32 status = hal_SysEnterCriticalSection(); + u8 channel; + u8 i; + + // Check buffer alignment depending on the mode + if (ifcMode != HAL_IFC_SIZE_8_MODE_MANUAL && ifcMode != HAL_IFC_SIZE_8_MODE_AUTO) + { + // Then ifcMode == HAL_IFC_SIZE_32, check word alignment + assert(((u32)memStartAddr%4) == 0, + "HAL IFC: 32 bits transfer misaligned 0x@%08X", memStartAddr); + } + else + { + // ifcMode == HAL_IFC_SIZE_8, nothing to check + } + + // Check the requested id is not currently already used. + for (i = 0; i < SYS_IFC_STD_CHAN_NB ; i++) + { + if (GET_BITFIELD(hwp_sysIfc->std_ch[i].control, SYS_IFC_REQ_SRC) == requestId) + { + // This channel is or was used for the requestId request. + // Check it is still in use. + assert((hwp_sysIfc->std_ch[i].status & SYS_IFC_ENABLE) == 0, + "HAL: Attempt to use the IFC to deal with a %d" + " request still active on channel %d", requestId, i); + } + } + + channel = SYS_IFC_CH_TO_USE(hwp_sysIfc->get_ch) ; + + if (channel >= SYS_IFC_STD_CHAN_NB) + { + serial_puts("HAL_UNKNOWN_CHANNEL\n"); + //hal_SysExitCriticalSection(status); + return HAL_UNKNOWN_CHANNEL; + } + + g_halModuleIfcChannelOwner[channel] = requestId; + hwp_sysIfc->std_ch[channel].start_addr = (u32) memStartAddr; + hwp_sysIfc->std_ch[channel].tc = xferSize; + hwp_sysIfc->std_ch[channel].control = (SYS_IFC_REQ_SRC(requestId) + | ifcMode + | SYS_IFC_CH_RD_HW_EXCH + | SYS_IFC_ENABLE); + + //hal_SysExitCriticalSection(status); + return channel; +} + diff --git a/arch/arm/cpu/armv7/rda/ispi.c b/arch/arm/cpu/armv7/rda/ispi.c new file mode 100644 index 0000000000..d466ef0ced --- /dev/null +++ b/arch/arm/cpu/armv7/rda/ispi.c @@ -0,0 +1,314 @@ +/* + * (C) Copyright 2013 + * RDA Microelectronics Inc. + * + * Derived from drivers/spi/rda_ispi.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ +#include <common.h> +#include <linux/types.h> +#include <asm/arch/reg_spi.h> +#include <asm/arch/ispi.h> + +#ifdef CONFIG_MACH_RDA8850E +#include <asm/arch/reg_rf_spi.h> + +#define RDA6220_ADDR_MASK 0xFF +#define RDA6220_ADDR_OFFSET 23 +#define RDA6220_DATA_MASK 0xFFFF +#define RDA6220_DATA_OFFSET 7 + +#define RDA6220_WRITE_FMT(addr, data) (((addr & RDA6220_ADDR_MASK) << RDA6220_ADDR_OFFSET) |\ + ((data & RDA6220_DATA_MASK) << RDA6220_DATA_OFFSET)) + +#define RDA6220_READ_FMT(addr, data) ( ((addr & RDA6220_ADDR_MASK) << RDA6220_ADDR_OFFSET)|\ + ((data & RDA6220_DATA_MASK) << RDA6220_DATA_OFFSET)|\ + 1<<31); + +void modem_RfspiOpen(void) +{ + // Setter + hwp_rfSpi->Ctrl = 0x8fd82e45; + + // To remove the "FORCE ZERO" in case of low-active CS + hwp_rfSpi->Command = 0; + hwp_rfSpi->Divider = RF_SPI_DIVIDER(23); +} + +void modem_rf_spiWrite(const u8 *Cmd, u32 CmdSize) +{ + u32 loop=0; + + // Flush the Tx fifo + hwp_rfSpi->Command = RF_SPI_FLUSH_CMD_FIFO | RF_SPI_FLUSH_RX_FIFO; + for (loop=0; loop<CmdSize; loop++) + { + hwp_rfSpi->Cmd_Data = Cmd[loop]; + } + // Set the cmd size + hwp_rfSpi->Cmd_Size = RF_SPI_CMD_SIZE(CmdSize); + + // And send the command + hwp_rfSpi->Command = RF_SPI_SEND_CMD; + + // Wait for the SPI to start - at least one byte has been sent + while(GET_BITFIELD(hwp_rfSpi->Status, RF_SPI_CMD_DATA_LEVEL) >= CmdSize); + // Wait for the SPI to finish + while((hwp_rfSpi->Status & RF_SPI_ACTIVE_STATUS) != 0); +} + + +void modem_RfspiWrite(const u8 addr, u32 data) +{ + u8 cmd[4] = {0}; + u32 cmd_word = RDA6220_WRITE_FMT(addr, data); + + cmd[0] = (cmd_word >> 24) & 0xff; + cmd[1] = (cmd_word >>16) & 0xff; + cmd[2] = (cmd_word >> 8) & 0xff; + cmd[3] = (cmd_word >> 0) & 0xff; + + modem_rf_spiWrite(cmd, 4); +} + +void modem_RfspiInit_624M(void) +{ + modem_RfspiOpen(); + + modem_RfspiWrite(0x30, 0x5182); + + mdelay(10); // delay 10 ms + modem_RfspiWrite(0x30, 0x5187); + mdelay(10); // delay 10 ms + // xtal setting + modem_RfspiWrite(0xb0, 0xe404); + modem_RfspiWrite(0xb8, 0x1800); + modem_RfspiWrite(0xba, 0x0401); + modem_RfspiWrite(0xc0, 0x0008); + modem_RfspiWrite(0xfe, 0x4000); + modem_RfspiWrite(0x10, 0x0880); + modem_RfspiWrite(0x20, 0x03e4); + modem_RfspiWrite(0x22, 0x0488); + modem_RfspiWrite(0xe8, 0x1000); + modem_RfspiWrite(0xe6, 0x0000); + modem_RfspiWrite(0xe4, 0x0c00); + modem_RfspiWrite(0xe4, 0x8c00); + modem_RfspiWrite(0xfe, 0x0000); + modem_RfspiWrite(0x4e, 0xe538); + modem_RfspiWrite(0x4c, 0x04b9); + modem_RfspiWrite(0x4c, 0x84b9); + +} + +void modem_8850eeco2_RfspiInit_624M(void) +{ + modem_RfspiOpen(); + + modem_RfspiWrite(0x30, 0x5182); + + mdelay(10); // delay 10 ms + modem_RfspiWrite(0x30, 0x5187); + mdelay(10); // delay 10 ms + // xtal setting + + modem_RfspiWrite(0xfe, 0x4000); + modem_RfspiWrite(0x10, 0x0880); + modem_RfspiWrite(0xfe, 0x0000); +} +#endif + +static HWP_SPI_T *hwp_ispi = hwp_spi3; + +void ispi_open(int modemSpi) +{ + u32 cfgReg = 0; + u32 ctrlReg = 0; + + // spi_clk_freq = APB2 / ((div+1)*2) + // the maximum clock frequency is 7MHz~8MHz + // the spi clock frequency is 5MHz when div is 0x13 + cfgReg = 0x130003; + ctrlReg = 0x2019d821; + + if (modemSpi) + hwp_ispi = hwp_mspi2; + else + hwp_ispi = hwp_spi3; + + // Activate the ISPI. + hwp_ispi->cfg = cfgReg; + hwp_ispi->ctrl = ctrlReg; + + // No IRQ. + hwp_ispi->irq = 0; +} + +static u8 ispi_tx_fifo_avail(void) +{ + u8 freeRoom; + + // Get avail level. + freeRoom = GET_BITFIELD(hwp_ispi->status, SPI_TX_SPACE); + + return freeRoom; +} + +static int ispi_tx_finished(void) +{ + u32 spiStatus; + spiStatus = hwp_ispi->status; + + // If ISPI FSM is active and the TX Fifo is empty + // (ie available space == Fifo size), the tf is not done + if ((!(hwp_ispi->status & SPI_ACTIVE_STATUS)) + && (SPI_TX_FIFO_SIZE == GET_BITFIELD(spiStatus, SPI_TX_SPACE))) { + return TRUE; + } else { + return FALSE; + } +} + +static u32 ispi_send_data(u32 csId, u32 data, int read) +{ + u32 freeRoom; + + // Clear data upper bit to only keep the data frame. + u32 reg = data & ~(SPI_CS_MASK | SPI_READ_ENA_MASK); + + // Add CS and read mode bit + reg |= SPI_CS(csId) | (read ? SPI_READ_ENA : 0); + + // Enter critical section. + //u32 status = hwp_sysIrq->SC; + + // Check FIFO availability. + freeRoom = GET_BITFIELD(hwp_ispi->status, SPI_TX_SPACE); + + if (freeRoom > 0) { + // Write data. + hwp_ispi->rxtx_buffer = reg; + + // Exit critical section. + //hwp_sysIrq->SC = status; + return 1; + } else { + // Exit critical section. + //hwp_sysIrq->SC = status; + return 0; + } +} + +static u32 ispi_get_data(u32 * recData) +{ + u32 nbAvailable; + + // Enter critical section. + //u32 status = hwp_sysIrq->SC; + + nbAvailable = GET_BITFIELD(hwp_ispi->status, SPI_RX_LEVEL); + + if (nbAvailable > 0) { + *recData = hwp_ispi->rxtx_buffer; + + // Exit critical section. + //hwp_sysIrq->SC = status; + return 1; + } else { + // Exit critical section. + //hwp_sysIrq->SC = status; + return 0; + } +} + +void ispi_reg_write(u32 regIdx, u32 value) +{ + u32 wrData; + + wrData = (0 << 25) | ((regIdx & 0x1ff) << 16) | (value & 0xffff); + + while (ispi_tx_fifo_avail() < 1 || + ispi_send_data(0, wrData, FALSE) == 0) ; + + //wait until any previous transfers have ended + while (!ispi_tx_finished()) ; +} + +u32 ispi_reg_read(u32 regIdx) +{ + u32 wrData, rdData = 0; + u32 count; + + wrData = (1 << 25) | ((regIdx & 0x1ff) << 16) | 0; + + while (ispi_tx_fifo_avail() < 1 || + ispi_send_data(0, wrData, TRUE) == 0) ; + + //wait until any previous transfers have ended + while (!ispi_tx_finished()) ; + + count = ispi_get_data(&rdData); + if (1 != count) + serial_puts("ABB ISPI count err!"); + + rdData &= 0xffff; + + return rdData; +} + +u16 rda_read_efuse(int page_index) +{ + u16 rvalue, wvalue; + + ispi_open(1); + + wvalue = 0x2e0 | page_index; + pmu_reg_write(0x51, wvalue); + udelay(2000); + wvalue = 0x2f0 | page_index; + pmu_reg_write(0x51, wvalue); + rvalue = pmu_reg_read(0x52); + pmu_reg_write(0x51, 0x0200); + + ispi_open(0); + return rvalue; +} + +#ifdef EFUSE_DUMP +void dump_efuse(void) +{ + u16 rvalue,wvalue; + int i; + + ispi_open(1); + + for(i = 0;i<16;i++){ + wvalue = 0x2e0 | i; + pmu_reg_write(0x51, wvalue); + udelay(2000); + wvalue = 0x2f0 | i; + pmu_reg_write(0x51, wvalue); + rvalue = pmu_reg_read(0x52); + pmu_reg_write(0x51, 0x0200); + + printf("page%d = %d \n", i, rvalue); + } + ispi_open(0); +} +#endif diff --git a/arch/arm/cpu/armv7/rda/mdcom.c b/arch/arm/cpu/armv7/rda/mdcom.c new file mode 100644 index 0000000000..8bb9e082c4 --- /dev/null +++ b/arch/arm/cpu/armv7/rda/mdcom.c @@ -0,0 +1,877 @@ +#include "common.h" +#include <errno.h> + +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/reg_sysctrl.h> +#include <asm/arch/reg_mdcom.h> +#include <asm/arch/reg_xcpu.h> +#include <asm/arch/defs_mdcom.h> +#include <asm/arch/mdcom.h> +#include <asm/arch/factory.h> +#include <asm/arch/rda_iomap.h> +#include <asm/arch/reg_cfg_regs.h> + + +static u32 modem_logic_base_addr = 0x02000000; +void rda_mdcom_set_logic_base_addr(u32 base) +{ + modem_logic_base_addr = base & 0xffff0000; + printf("## Set modem logic base address %#x\n", modem_logic_base_addr); +} + +#define RDA_MODEM_IN_DDR(addr, modem_logic_base_addr) \ + (((u32)(addr) & 0x0F000000) == (modem_logic_base_addr & 0x0F000000)) + +/* + * Convert a modem address to an AP address + */ +u32 rda_mdcom_address_modem2ap(u32 addr) +{ +#if defined(_TGT_MODEM_MEM_SIZE) && (_TGT_MODEM_MEM_SIZE > 0) + if (RDA_MODEM_IN_DDR(addr, modem_logic_base_addr)) + return (RDA_MODEM_RAM_BASE - modem_logic_base_addr + addr); + else + return RDA_ADD_M2A(addr); +#else + return RDA_ADD_M2A(addr); +#endif +} + +/* + * Setup modem running env + */ +int rda_mdcom_setup_run_env(u32 pc, u32 param) +{ + RDA_BOOT_HST_MONITOR_X_CTX_T *ctx = + (RDA_BOOT_HST_MONITOR_X_CTX_T *)RDA_BOOT_CTX_ADD; + ctx->cmdType = 0xFF; + ctx->pc = pc; + ctx->sp = 0; + ctx->param = (void *)param; + ctx->returnedValue = (void *)0; + +#if defined(_TGT_MODEM_MEM_SIZE) && (_TGT_MODEM_MEM_SIZE > 0) + // Set DDR access offset + if (RDA_MODEM_IN_DDR(pc, modem_logic_base_addr)) { +#ifdef CONFIG_MACH_RDA8850E + u32 offs = RDA_MODEM_RAM_BASE - modem_logic_base_addr; + + /* 0x1000000 alignment */ + if(offs & 0xffffff) { + printf("\nERROR: modem memory map offset %#x is not aligned to 0x1000000.\n", offs); + printf("ERROR: modem cannot work, abort.\n"); + return -1; + } + + hwp_configRegs->Mem_mode_Sel = 0; + hwp_configRegs->H2X_DDR_Offset = offs; + hwp_configRegs->H2X_WD_DDR_Offset = offs; +#else + u32 offs = CFG_REGS_H2X_DDR_OFFSET((RDA_MODEM_RAM_BASE - modem_logic_base_addr) >> 24); + hwp_configRegs->H2X_DDR_Offset = offs; +#endif + }; +#endif + + return 0; +} + +/* + * Modem calibration data section address + */ +void rda_mdcom_get_calib_section(u32 *addr, u32 *len) +{ + if (addr) + *addr = RDA_MODEM_CAL_ADDR; + if (len) + *len = RDA_MODEM_CAL_LEN; +} + +/* + * Modem extended calibration data section address + */ +void rda_mdcom_get_ext_calib_section(u32 *addr, u32 *len) +{ + if (addr) + *addr = RDA_MODEM_EXT_CAL_ADDR; + if (len) + *len = RDA_MODEM_EXT_CAL_LEN; +} + +/* + * Modem factory section address + */ +void rda_mdcom_get_factory_section(u32 *addr, u32 *len) +{ + if (addr) + *addr = RDA_MODEM_FACT_ADDR; + if (len) + *len = RDA_MODEM_FACT_LEN; +} + +/* + * AP factory section address + */ +void rda_mdcom_get_ap_factory_section(u32 *addr, u32 *len) +{ + if (addr) + *addr = RDA_AP_FACT_ADDR; + if (len) + *len = RDA_AP_FACT_LEN; +} + +/* + * Reset cause + */ +u32 rda_mdcom_get_reset_cause(void) +{ + return ((RDA_AP_MBX_HEARTBEAT_T *)RDA_AP_MBX_HEARTBEAT_ADD)->resetCause; +} + +/* + * Interface version + */ +u32 rda_mdcom_get_interface_version(void) +{ + return ((RDA_AP_MBX_HEARTBEAT_T *)RDA_AP_MBX_HEARTBEAT_ADD)->version; +} + +/* + * Magic number + */ +int rda_mdcom_system_started_before(void) +{ + RDA_AP_MBX_MAGIC_NUMBER_T *magic = + (RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD; + return magic->sysStarted == RDA_MAGIC_SYSTEM_STARTED_FLAG; +} + +void rda_mdcom_set_system_started_flag(void) +{ + RDA_AP_MBX_MAGIC_NUMBER_T *magic = + (RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD; + magic->sysStarted = RDA_MAGIC_SYSTEM_STARTED_FLAG; +} + +int rda_mdcom_modem_crashed_before(void) +{ + RDA_AP_MBX_MAGIC_NUMBER_T *magic = + (RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD; + return magic->modemCrashed == RDA_MAGIC_MODEM_CRASH_FLAG; +} + +int rda_mdcom_calib_update_cmd_valid(void) +{ + RDA_AP_MBX_MAGIC_NUMBER_T *magic = + (RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD; + if (magic->factUpdateCmd == RDA_MAGIC_FACT_UPD_CMD_FLAG && + (magic->factUpdateType & + RDA_MAGIC_FACT_UPD_TYPE_FLAG_MASK) == + RDA_MAGIC_FACT_UPD_TYPE_FLAG && + (magic->factUpdateType & RDA_MAGIC_FACT_UPD_TYPE_CALIB)) + return 1; + else + return 0; +} + +int rda_mdcom_factory_update_cmd_valid(void) +{ + RDA_AP_MBX_MAGIC_NUMBER_T *magic = + (RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD; + if (magic->factUpdateCmd == RDA_MAGIC_FACT_UPD_CMD_FLAG && + (magic->factUpdateType & + RDA_MAGIC_FACT_UPD_TYPE_FLAG_MASK) == + RDA_MAGIC_FACT_UPD_TYPE_FLAG && + (magic->factUpdateType & RDA_MAGIC_FACT_UPD_TYPE_FACT)) + return 1; + else + return 0; +} + +int rda_mdcom_ap_factory_update_cmd_valid(void) +{ + RDA_AP_MBX_MAGIC_NUMBER_T *magic = + (RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD; + if (magic->factUpdateCmd == RDA_MAGIC_FACT_UPD_CMD_FLAG && + (magic->factUpdateType & + RDA_MAGIC_FACT_UPD_TYPE_FLAG_MASK) == + RDA_MAGIC_FACT_UPD_TYPE_FLAG && + (magic->factUpdateType & RDA_MAGIC_FACT_UPD_TYPE_AP_FACT)) + return 1; + else + return 0; +} + +/* + * Modem log info + */ +static int rda_mdcom_modem_address_valid(u32 addr) +{ + if ((addr >= RDA_MODEM_INTSRAM_BASE && + addr < RDA_MODEM_INTSRAM_END) || + (addr >= RDA_MODEM_RAM_BASE && + addr < RDA_MODEM_RAM_END)) { + return 1; + } + return 0; +} + +void rda_mdcom_init_all_log_info(void) +{ + /* Init log info */ + RDA_AP_MBX_LOG_BUF_INFO_T *log = + (RDA_AP_MBX_LOG_BUF_INFO_T *)RDA_AP_MBX_LOG_BUF_INFO_ADD; + memset(log, 0, sizeof(*log)); + /* Init modem crash flag */ + RDA_AP_MBX_MAGIC_NUMBER_T *magic = + (RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD; + magic->modemCrashed = 0; + magic->factUpdateCmd = 0; + magic->factUpdateType = 0; + /* Init heartbeat structure members */ + memset((RDA_AP_MBX_HEARTBEAT_T *)RDA_AP_MBX_HEARTBEAT_ADD, 0, + sizeof(RDA_AP_MBX_HEARTBEAT_T)); +} + +void rda_mdcom_get_modem_log_info(u32 *addr, u32 *len) +{ + RDA_AP_MBX_LOG_BUF_INFO_T *log = + (RDA_AP_MBX_LOG_BUF_INFO_T *)RDA_AP_MBX_LOG_BUF_INFO_ADD; + u32 log_addr = rda_mdcom_address_modem2ap(log->modemAddr); + u32 log_len = log->modemLen; + + /* Check whether the address is valid */ + if (!rda_mdcom_modem_address_valid(log_addr) || + log_len > RDA_AP_MBX_MAX_MODEM_LOG_LEN) { + log_addr = 0; + log_len = 0; + } + + if (addr) + *addr = log_addr; + if (len) + *len = log_len; +} + +void rda_mdcom_get_modem_exception_info(u32 *addr, u32 *len) +{ + RDA_AP_MBX_LOG_BUF_INFO_T *log = + (RDA_AP_MBX_LOG_BUF_INFO_T *)RDA_AP_MBX_LOG_BUF_INFO_ADD; + u32 exc_addr = RDA_ADD_M2A(log->modemExcAddr); + u32 exc_len = log->modemExcLen; + + /* Check whether the address is valid */ + if (!rda_mdcom_modem_address_valid(exc_addr) || + exc_len > RDA_AP_MBX_MAX_MODEM_EXC_LEN) { + exc_addr = 0; + exc_len = 0; + } + + if (addr) + *addr = exc_addr; + if (len) + *len = exc_len; +} + +/* + * Modem XCPU info + */ +void rda_mdcom_show_xcpu_info(void) +{ + printf("\n"); + printf("Modem XCPU info:\n"); + printf("----------------\n"); + printf("Cause = 0x%08x\n", hwp_xcpu->cp0_Cause); + printf("Status = 0x%08x\n", hwp_xcpu->cp0_Status); + printf("BadAddr = 0x%08x\n", hwp_xcpu->cp0_BadVAddr); + printf("EPC = 0x%08x\n", hwp_xcpu->cp0_EPC); + printf("RA = 0x%08x\n", hwp_xcpu->Regfile_RA); + printf("PC = 0x%08x\n", hwp_xcpu->rf0_addr); + printf("----------------\n"); +} + +/* + * Modem software version info + */ +void rda_mdcom_show_software_version(void) +{ + int i = 0; + char buf[256]; + char *str; + RDA_MODEM_MAP_VERSION_T *version; + RDA_MODEM_MAP_MODULE_T *map; + RDA_MODEM_MAP_MODULE_T **ptr = + (RDA_MODEM_MAP_MODULE_T **)RDA_MODEM_MAP_PTR; + + printf("\n"); + map = (RDA_MODEM_MAP_MODULE_T *)rda_mdcom_address_modem2ap( + (u32)*ptr); + if (!ptr || !rda_mdcom_modem_address_valid((u32)map)) { + printf("No modem software versions\n"); + return; + } + + printf("Modem software versions:\n"); + printf("------------------------\n"); + for (i = 0; i < RDA_MODEM_MAP_QTY; i++, map++) { + if (!map->version) + continue; + version = (RDA_MODEM_MAP_VERSION_T *) + rda_mdcom_address_modem2ap((u32)map->version); + if (!rda_mdcom_modem_address_valid((u32)version)) + continue; + printf("[%02d]\n", i); + printf("revision = %d / 0x %07x\n", + version->revision, + version->revision); + printf("number = %d\n", version->number); + printf("date = %d\n", version->date); + str = (char *)rda_mdcom_address_modem2ap((u32)version->string); + if (version->string && + rda_mdcom_modem_address_valid((u32)str)) { + snprintf(buf, sizeof(buf), "%s", str); + buf[sizeof(buf) - 1] = '\0'; + printf("string = %s\n", buf); + } else { + printf("string = <n/a>\n"); + } + } + printf("------------------------\n"); +} + +/* + * Communication channels + */ +static struct rda_mdcom_channel rda_rda_mdcom_chn[] = { + /* AT command channel */ + { + RDA_MDCOM_LINE_AT_CMD, + RDA_MDCOM_LINE_AT_CMD_FC, + (struct rda_mdcom_channel_head*)RDA_MDCOM_CHN_AT_HEAD_ADD_READ, + (void *)RDA_MDCOM_CHN_AT_BUF_ADD_READ, + RDA_MDCOM_CHN_AT_BUF_LEN_READ-1, + (struct rda_mdcom_channel_head*)RDA_MDCOM_CHN_AT_HEAD_ADD_WRITE, + (void *)RDA_MDCOM_CHN_AT_BUF_ADD_WRITE, + RDA_MDCOM_CHN_AT_BUF_LEN_WRITE-1 + }, + + /* SYSTEM command channel */ + { + RDA_MDCOM_LINE_SYSTEM, + RDA_MDCOM_LINE_SYSTEM_FC, + (struct rda_mdcom_channel_head*)RDA_MDCOM_CHN_SYS_HEAD_ADD_READ, + (void *)RDA_MDCOM_CHN_SYS_BUF_ADD_READ, + RDA_MDCOM_CHN_SYS_BUF_LEN_READ-1, + (struct rda_mdcom_channel_head*)RDA_MDCOM_CHN_SYS_HEAD_ADD_WRITE, + (void *)RDA_MDCOM_CHN_SYS_BUF_ADD_WRITE, + RDA_MDCOM_CHN_SYS_BUF_LEN_WRITE-1 + }, + + /* TRACE communciation channel */ + { + RDA_MDCOM_LINE_TRACE, + RDA_MDCOM_LINE_TRACE_FC, + (struct rda_mdcom_channel_head*)RDA_MDCOM_CHN_TRACE_HEAD_ADD_READ, + (void *)RDA_MDCOM_CHN_TRACE_BUF_ADD_READ, + RDA_MDCOM_CHN_TRACE_BUF_LEN_READ-1, + (struct rda_mdcom_channel_head*)RDA_MDCOM_CHN_TRACE_HEAD_ADD_WRITE, + (void *)RDA_MDCOM_CHN_TRACE_BUF_ADD_WRITE, + RDA_MDCOM_CHN_TRACE_BUF_LEN_WRITE-1 + } +}; + +int rda_mdcom_init_port(int port_id) +{ + switch (port_id) { + case RDA_MDCOM_PORT0: + hwp_mdComregs->Mask_Set = COMREGS_IRQ0_MASK_SET(0); + hwp_mdComregs->Mask_Clr = COMREGS_IRQ0_MASK_CLR(0xFF); + hwp_mdComregs->ItReg_Set = COMREGS_IRQ0_SET(0); + hwp_mdComregs->ItReg_Clr = COMREGS_IRQ0_CLR(0xFF); + return 0; + + case RDA_MDCOM_PORT1: + hwp_mdComregs->Mask_Set = COMREGS_IRQ1_MASK_SET(0); + hwp_mdComregs->Mask_Clr = COMREGS_IRQ1_MASK_CLR(0xFF); + hwp_mdComregs->ItReg_Set = COMREGS_IRQ1_SET(0); + hwp_mdComregs->ItReg_Clr = COMREGS_IRQ1_CLR(0xFF); + return 0; + + default: + return -EINVAL; + } +} + +int rda_mdcom_line_set(int port_id, int line_id) +{ + if (line_id & ~0x7) { + return -EINVAL; + } + + switch (port_id) { + case RDA_MDCOM_PORT0: + hwp_mdComregs->ItReg_Set = COMREGS_IRQ0_SET(1 << line_id); + return 0; + + case RDA_MDCOM_PORT1: + hwp_mdComregs->ItReg_Set = COMREGS_IRQ1_SET(1 << line_id); + return 0; + + default: + return -EINVAL; + } +} + +int rda_mdcom_line_clear(int port_id, int line_id) +{ + if (line_id & ~0x7) { + return -EINVAL; + } + + switch (port_id) { + case RDA_MDCOM_PORT0: + hwp_mdComregs->ItReg_Clr = COMREGS_IRQ0_CLR(1 << line_id); + return 0; + + case RDA_MDCOM_PORT1: + hwp_mdComregs->ItReg_Clr = COMREGS_IRQ0_CLR(1 << line_id); + return 0; + + default: + return -EINVAL; + } +} + +int rda_mdcom_line_set_check(int port_id, int line_id) +{ + if (line_id & ~0x7) { + return 0; + } + + switch (port_id) { + case RDA_MDCOM_PORT0: + return !!(hwp_mdComregs->ItReg_Clr & COMREGS_IRQ0_CLR(1 << line_id)); + + case RDA_MDCOM_PORT1: + return !!(hwp_mdComregs->ItReg_Clr & COMREGS_IRQ1_CLR(1 << line_id)); + + default: + return 0; + } +} + +int rda_mdcom_line_clear_check(int port_id, int line_id) +{ + if (line_id & ~0x7) { + return 0; + } + + switch (port_id) { + case RDA_MDCOM_PORT0: + return !(hwp_mdComregs->ItReg_Set & COMREGS_IRQ0_SET(1 << line_id)); + + case RDA_MDCOM_PORT1: + return !(hwp_mdComregs->ItReg_Set & COMREGS_IRQ0_SET(1 << line_id)); + + default: + return 0; + } +} + +int rda_mdcom_line_set_wait(int port_id, int line_id, int waittime) +{ + unsigned long end_time = get_ticks() + waittime; + + if (line_id & ~0x7) { + return 0; + } + + switch (port_id) { + case RDA_MDCOM_PORT0: + while (!(hwp_mdComregs->ItReg_Clr & COMREGS_IRQ0_CLR(1 << line_id))) { + if ((waittime >= 0) && (end_time <= get_ticks())) + return 0; + } + return 1; + + case RDA_MDCOM_PORT1: + while (!(hwp_mdComregs->ItReg_Clr & COMREGS_IRQ1_CLR(1 << line_id))) { + if ((waittime >= 0) && (end_time <= get_ticks())) + return 0; + } + return 1; + + default: + return 0; + } +} + +int rda_mdcom_line_clear_wait(int port_id, int line_id, int waittime) +{ + unsigned long end_time = get_ticks() + waittime; + + if (line_id & ~0x7) { + return 0; + } + + switch (port_id) { + case RDA_MDCOM_PORT0: + while (hwp_mdComregs->ItReg_Set & COMREGS_IRQ0_SET(1 << line_id)) { + if ((waittime >= 0) && (end_time <= get_ticks())) + return 0; + } + return 1; + + case RDA_MDCOM_PORT1: + while (hwp_mdComregs->ItReg_Set & COMREGS_IRQ0_SET(1 << line_id)) { + if ((waittime >= 0) && (end_time <= get_ticks())) + return 0; + } + return 1; + + default: + return 0; + } +} + +void rda_mdcom_port_show(void) +{ + printf("RDA MDCOM ports stauts:\n"); + printf("REGISTER Cause = 0x%.16x\n", hwp_mdComregs->Cause); + printf("REGISTER Mask_Set = 0x%.16x\n", hwp_mdComregs->Mask_Set); + printf("REGISTER Mask_Clr = 0x%.16x\n", hwp_mdComregs->Mask_Clr); + printf("REGISTER ItReg_Set = 0x%.16x\n", hwp_mdComregs->ItReg_Set); + printf("REGISTER ItReg_Clr = 0x%.16x\n", hwp_mdComregs->ItReg_Clr); + printf("RDA MDCOM ports stauts end.\n"); +} + +int rda_mdcom_channel_init(const unsigned int channel) +{ + if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) { + return -EINVAL; + } + + memset(rda_rda_mdcom_chn[channel].read_buf_head, 0, + sizeof(struct rda_mdcom_channel_head)); + memset(rda_rda_mdcom_chn[channel].write_buf_head, 0, + sizeof(struct rda_mdcom_channel_head)); + return 0; +} + +int rda_mdcom_channel_all_init(void) +{ + return rda_mdcom_channel_init(RDA_MDCOM_CHANNEL_AT) || + rda_mdcom_channel_init(RDA_MDCOM_CHANNEL_SYSTEM) || + rda_mdcom_channel_init(RDA_MDCOM_CHANNEL_TRACE); +} + +int rda_mdcom_channel_buf_send_stream(const unsigned int channel, void *buf, + int size, int waittime) +{ + unsigned long end_time = get_ticks() + waittime; + struct rda_mdcom_channel* channel_ptr; + struct rda_mdcom_channel_head* channel_head_ptr; + int buffer_size_mask; + int count = 0; + + if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) { + return -EINVAL; + } + + if (size < 0) { + return -EINVAL; + } + + channel_ptr = &rda_rda_mdcom_chn[channel]; + channel_head_ptr = channel_ptr->write_buf_head; + buffer_size_mask = channel_ptr->write_buf_size_mask; + + while (1) { + int write_offset = channel_head_ptr->write_offset; + int remain_len = (buffer_size_mask + 1) - + ((write_offset - channel_head_ptr->read_offset) & buffer_size_mask); + + if (remain_len > buffer_size_mask + 1 - write_offset) { + remain_len = buffer_size_mask + 1 - write_offset; + } + + if (remain_len) { + if (remain_len > size) { + remain_len = size; + } + + memcpy(((char*)channel_ptr->write_buf) + write_offset, buf, remain_len); + channel_head_ptr->write_offset = (write_offset + remain_len) & buffer_size_mask; + size -= remain_len; + buf = (char*)buf + remain_len; + count += remain_len; + + if (!size) { + return count; + } + } else if ((waittime >= 0) && (end_time <= get_ticks())) { + return count; + } + } +} + +int rda_mdcom_channel_buf_send_dgram(const unsigned int channel, void *buf, + int size, int waittime) +{ + unsigned long end_time = get_ticks() + waittime; + struct rda_mdcom_channel* channel_ptr; + struct rda_mdcom_channel_head* channel_head_ptr; + int buffer_size_mask, write_offset; + + if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) { + return -EINVAL; + } + + if (size < 0) { + return -EINVAL; + } + + channel_ptr = &rda_rda_mdcom_chn[channel]; + channel_head_ptr = channel_ptr->write_buf_head; + buffer_size_mask = channel_ptr->write_buf_size_mask; + write_offset = ALIGN(channel_head_ptr->write_offset, 4) & buffer_size_mask; + + while (1) { + int remain_len = (buffer_size_mask + 1) - + ((write_offset - channel_head_ptr->read_offset) & buffer_size_mask); + + if (remain_len >= size) { + remain_len = buffer_size_mask + 1 - write_offset; + + if (remain_len > size) { + remain_len = size; + } + + memcpy(((char*)channel_ptr->write_buf) + write_offset, buf, + remain_len); + + if (remain_len != size) { + memcpy(channel_ptr->write_buf, (char*)buf + remain_len, + size - remain_len); + } + channel_head_ptr->write_offset = (write_offset + size) & + buffer_size_mask; + return 0; + } + + if ((waittime >= 0) && (end_time <= get_ticks())) { + return -EAGAIN; + } + } +} + +int rda_mdcom_channel_buf_send_available(const unsigned int channel) +{ + struct rda_mdcom_channel* channel_ptr; + struct rda_mdcom_channel_head* channel_head_ptr; + int buffer_size_mask; + int read_offset; + int write_offset; + + if (channel >= sizeof(rda_rda_mdcom_chn)/sizeof(struct rda_mdcom_channel)) { + return 0; + } + + channel_ptr = &rda_rda_mdcom_chn[channel]; + channel_head_ptr = channel_ptr->write_buf_head; + buffer_size_mask = channel_ptr->write_buf_size_mask; + read_offset = channel_head_ptr->read_offset; + write_offset = channel_head_ptr->write_offset; + + return ((buffer_size_mask + 1) - ((write_offset - read_offset) & buffer_size_mask)); +} + +int rda_mdcom_channel_buf_recv_stream(const unsigned int channel, void *buf, + int size, int waittime) +{ + unsigned long end_time = get_ticks() + waittime; + struct rda_mdcom_channel* channel_ptr; + struct rda_mdcom_channel_head* channel_head_ptr; + int buffer_size_mask; + int count = 0; + int buf_offset = 0; + + if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) { + return -EINVAL; + } + + if (size < 0) { + return -EINVAL; + } + + channel_ptr = &rda_rda_mdcom_chn[channel]; + channel_head_ptr = channel_ptr->read_buf_head; + buffer_size_mask = channel_ptr->read_buf_size_mask; + + while (1) { + int read_offset = channel_head_ptr->read_offset; + int remain_len = channel_head_ptr->write_offset - read_offset; + + if (remain_len < 0) { + remain_len = buffer_size_mask + 1 - read_offset; + } + + if (remain_len) { + if (remain_len > size) { + remain_len = size; + } + + memcpy((char *)buf + buf_offset, ((char*)channel_ptr->read_buf) + read_offset, remain_len); + channel_head_ptr->read_offset = (read_offset + remain_len) & + buffer_size_mask; + size -= remain_len; + count += remain_len; + buf_offset += remain_len; + + if (!size) { + return count; + } + } else if ((waittime >= 0) && (end_time <= get_ticks())) { + return count; + } + } +} + +int rda_mdcom_channel_buf_recv_dgram(const unsigned int channel, void *buf, + int size, int waittime) +{ + unsigned long end_time = get_ticks() + waittime; + struct rda_mdcom_channel* channel_ptr; + struct rda_mdcom_channel_head* channel_head_ptr; + int buffer_size_mask, read_offset; + + if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) { + return -EINVAL; + } + + if (size < 0) { + return -EINVAL; + } + + channel_ptr = &rda_rda_mdcom_chn[channel]; + channel_head_ptr = channel_ptr->read_buf_head; + buffer_size_mask = channel_ptr->read_buf_size_mask; + read_offset = ALIGN(channel_head_ptr->read_offset, 4) & buffer_size_mask; + + while (1) { + int remain_len = (channel_head_ptr->write_offset - read_offset + + buffer_size_mask + 1) & buffer_size_mask; + + if (remain_len >= size) { + remain_len = buffer_size_mask + 1 - read_offset; + + if (remain_len > size) { + remain_len = size; + } + + memcpy(buf, ((char*)channel_ptr->read_buf) + read_offset, remain_len); + + if (remain_len != size) { + memcpy(((char *)buf + remain_len), channel_ptr->read_buf, size - remain_len); + } + channel_head_ptr->read_offset = (read_offset + size) & buffer_size_mask; + + return 0; + } + + if ((waittime >= 0) && (end_time <= get_ticks())) { + return -EAGAIN; + } + } +} + +int rda_mdcom_channel_buf_recv_available(const unsigned int channel) +{ + struct rda_mdcom_channel* channel_ptr; + struct rda_mdcom_channel_head* channel_head_ptr; + int buffer_size_mask; + int read_offset; + int write_offset; + + if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) { + return 0; + } + + channel_ptr = &rda_rda_mdcom_chn[channel]; + channel_head_ptr = channel_ptr->write_buf_head; + buffer_size_mask = channel_ptr->write_buf_size_mask; + read_offset = channel_head_ptr->read_offset; + write_offset = channel_head_ptr->write_offset; + + return ((write_offset - read_offset) & buffer_size_mask); +} + +void rda_mdcom_channel_show(const unsigned int channel) +{ + printf("RDA MDCOM channel %d stauts:\n", channel); + + if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) { + printf("Channel number is out of range, ERROR!\n"); + } else { + struct rda_mdcom_channel* channel_ptr = &rda_rda_mdcom_chn[channel]; + struct rda_mdcom_channel_head* channel_head_ptr; + printf("Read buffer head address = 0x%p\n", + channel_ptr->read_buf_head); + printf("Read buffer address = 0x%p\n", + channel_ptr->read_buf); + printf("Read buffer length = %d\n", + channel_ptr->read_buf_size_mask + 1); + channel_head_ptr = channel_ptr->read_buf_head; + printf("Read buffer offset read = 0x%x\n", + channel_head_ptr->read_offset); + printf("Read buffer offset write = 0x%x\n", + channel_head_ptr->write_offset); + + printf("Write buffer head address = 0x%p\n", + channel_ptr->write_buf_head); + printf("Write buffer address = 0x%p\n", + channel_ptr->write_buf); + printf("Write buffer length = %d\n", + channel_ptr->write_buf_size_mask + 1); + channel_head_ptr = channel_ptr->write_buf_head; + printf("Write buffer offset read = 0x%x\n", + channel_head_ptr->read_offset); + printf("Write buffer offset write = 0x%x\n", + channel_head_ptr->write_offset); + } + + printf("RDA MDCOM channel %d stauts end.\n", channel); +} + +int rda_mdcom_tstc(const unsigned int channel) +{ + struct rda_mdcom_channel_head* channel_head_ptr; + + if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) { + return 0; + } + + channel_head_ptr = rda_rda_mdcom_chn[channel].read_buf_head; + + return (channel_head_ptr->write_offset != channel_head_ptr->read_offset); +} + +int rda_mdcom_getc(const unsigned int channel) +{ + char c = 0; + + rda_mdcom_channel_buf_recv_stream(channel, &c, 1, -1); + return c; +} + +void rda_mdcom_putc(const char c, const unsigned int channel) +{ + rda_mdcom_channel_buf_send_stream(channel, (void*)&c, 1, -1); +} + +void rda_mdcom_puts(const char *s, const unsigned int channel) +{ + rda_mdcom_channel_buf_send_stream(channel, (void*)s, strlen(s), -1); +} + diff --git a/arch/arm/cpu/armv7/rda/rda_crypto.c b/arch/arm/cpu/armv7/rda/rda_crypto.c new file mode 100644 index 0000000000..63eca2e271 --- /dev/null +++ b/arch/arm/cpu/armv7/rda/rda_crypto.c @@ -0,0 +1,260 @@ +#include <common.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <nand.h> +#include <malloc.h> +#include <image.h> +#include <usb/usbserial.h> +#include <asm/arch/rda_sys.h> +#include <asm/arch/rda_crypto.h> +#include <pdl.h> + +//#define RDA_CRYPTO_DEBUG + +#ifdef CONFIG_SIGNATURE_CHECK_IMAGE + +struct pubkey_cert_t { + struct { + uint16_t se_cfg; // vendor_id and key_index + uint8_t dummy[94]; // 96 + struct pubkey pubkey; // +64 + } c; + struct sig signature; // +96 +}; + +struct rda_cert_t { + // R&D Certificate: + // Create a signature with name[16] = + // " R&D-CERT"(10) + // "F:0000"(6) + // zeros[16] = 0... + // Then Hash: + // sig.name, zeros, UNIQUE-ID + struct sig rnd_cert; // 96 + + // free space without sign checking: + uint8_t dummy[160]; // 160 +}; + + +struct rda_se_image { + uint8_t spl_code[48128+160]; + struct sig image_signature; // 96 + struct rda_cert_t cert; // 256 + struct pubkey_cert_t vendor_pubkey_cert; // 256 +}; + +#ifdef RDA_CRYPTO_DEBUG +# define puts_deb(a) puts(a) +#else +# define puts_deb(a) +# define debug_dump_key_and_signature(h,pk,sig,d,l) +#endif + +#ifdef RDA_CRYPTO_DEBUG +static void debug_dump_key_and_signature( + const char *header, const struct pubkey *pk, const struct sig *sig, + const void *data, unsigned data_len) +{ + if (sig) { + printf("%s signature:\n", header); + rda_dump_buf((char *)sig, 96); + } + if (pk) { + printf("%s public key:\n", header); + rda_dump_buf((char *)pk, 64); + } + if (data) { + printf("%s data:\n", header); + rda_dump_buf((char *)data, data_len); + } +} +#endif + + +static int check_rnd_certificate( + const struct rda_cert_t *certs, + const struct pubkey *pubkey, + struct spl_security_info *info) +{ + int ret; + const struct sig *rnd_signature = &certs->rnd_cert; + struct { + uint8_t message[32]; + struct chip_unique_id id; + } hashme; + + puts_deb("Checking R&D Certificate\n"); + + // create message + memset(&hashme, 0, sizeof(hashme)); + memcpy(hashme.message, rnd_signature->name, 16); + hashme.id = info->chip_unique_id; + + // Dump the R&D hashme + debug_dump_key_and_signature("R&D hashme", pubkey, rnd_signature, + (char *)&hashme, sizeof(hashme)); + + ret = signature_check( + (const uint8_t*)&hashme, sizeof(hashme), + rnd_signature, + pubkey); + + return ret; +} + + +static void get_device_security_context( + const struct rda_se_image *image, + struct spl_security_info *info) +{ + // Get ROM public key and context + info->secure_mode = get_chip_security_context( + &info->chip_security_context, + &info->pubkey); + + int flags = info->chip_security_context.flags; + + // Fix the return code if security hasn't been enabled + if ((flags & RDA_SE_CFG_SECURITY_ENABLE_BIT) == 0) { + puts_deb("(Security disabled by efuse flags)\n"); + info->secure_mode = ROM_API_SECURITY_DISABLED; + return; + } + + // Check if we a using the customer public-key certificate + if (flags & RDA_SE_CFG_INDIRECT_SIGN_BIT) { + const struct pubkey_cert_t *vendor_cert = &image->vendor_pubkey_cert; + puts_deb("(Using vendor pkcert as per efuse flags)\n"); + + // The vendor pkey cert has already been verified + // by the bootrom. For debugging check again here: +#ifdef RDA_CRYPTO_DEBUG + // Dump the PKCERT data + debug_dump_key_and_signature("PKCERT", + &info->pubkey, &vendor_cert->signature, + &vendor_cert->c, sizeof(vendor_cert->c)); + + int ret; + ret = signature_check( + (uint8_t*)&vendor_cert->c, sizeof(vendor_cert->c), + &vendor_cert->signature, + &info->pubkey); + printf("PKCERT check return %d\n", ret); +#endif + // copy public key certificate + info->pubkey = vendor_cert->c.pubkey; + } + + // Sanity check for PKEY + if (memcmp(&info->pubkey, "RDASEd", 6) != 0) { + puts_deb("(Public key for signature check invalid)\n"); + info->secure_mode = -1; // better: ROM_API_SECURITY_INVALID_PKEY + return; + } + + // Dump the keys and signature when debugging + debug_dump_key_and_signature("PDL1 -", + &info->pubkey, &image->image_signature, NULL, 0); + + // Check if device is in R&D mode + int rnd_status = check_rnd_certificate(&image->cert, &info->pubkey, info); + if (rnd_status == 0) { + puts("(R&D mode override) "); + // ... and disable security... + info->secure_mode = ROM_API_SECURITY_DISABLED; + } +} + + +int set_security_context(struct spl_security_info *info, const void *_image) +{ + const struct rda_se_image *image = _image; + + memset(info, 0, sizeof(*info)); + + if (memcmp(romapi->magic, "RDA API", 8) != 0) { + puts("Board security: Not present\n"); + info->secure_mode = ROM_API_SECURITY_UNAVAILABLE; + } + else { + puts("Board security: present "); + + info->version = romapi->version; + get_chip_id(&info->chip_id); + get_chip_true_random(info->random, 32); + get_chip_unique(&info->chip_unique_id); + + get_device_security_context(image, info); + + switch (info->secure_mode) { + case ROM_API_SECURITY_ENABLED: + puts("and enabled.\n"); + break; + case ROM_API_SECURITY_DISABLED: + puts("but disabled.\n"); + break; + case ROM_API_INVALID_KEYINDEX: + case ROM_API_INVALID_VENDOR_ID: + puts("but has invalid key-index or vendor-id!\n"); + break; + default: + puts("but has invalid configuration!\n"); + break; + } + } + return info->secure_mode; +} + +int image_sign_verify(const uint8_t *buffer, uint32_t len) +{ + spl_bd_t *spl_board_info = (spl_bd_t *)CONFIG_SPL_BOARD_INFO_ADDR; + struct spl_security_info *info = &spl_board_info->spl_security_info; + + len -= sizeof(struct sig); + const struct sig *signature = (const struct sig *)(buffer + len); + + puts("Verify image:\n"); + + // Check security mode + int secure_mode = info->secure_mode; + switch (secure_mode) { + case ROM_API_SECURITY_ENABLED: + // Check the signature of the image + debug_dump_key_and_signature("bootloader -", + &info->pubkey, signature, NULL, 0); + return signature_check(buffer, len, signature, &info->pubkey); + case ROM_API_SECURITY_DISABLED: + case ROM_API_SECURITY_UNAVAILABLE: + return 0; + default: + return secure_mode; // This is != 0 -> verify error + } +} + +int image_sign_verify_uimage(image_header_t *hdr) +{ + return image_sign_verify((const uint8_t *)hdr, + image_get_image_size(hdr) + sizeof(struct sig)); +} + +#else +int set_security_context(struct spl_security_info *info, const void *_image) +{ + memset(info, 0, sizeof(*info)); + + if (memcmp(romapi->magic, "RDA API", 8) == 0) { + puts("Board security: present "); + + info->version = romapi->version; + get_chip_unique(&info->chip_unique_id); + } + return ROM_API_SECURITY_DISABLED; +} + +int image_sign_verify(const uint8_t *buffer, uint32_t len) +{ + return 0; +} +#endif + diff --git a/arch/arm/cpu/armv7/rda/rda_romapi.c b/arch/arm/cpu/armv7/rda/rda_romapi.c new file mode 100644 index 0000000000..3eca055ed5 --- /dev/null +++ b/arch/arm/cpu/armv7/rda/rda_romapi.c @@ -0,0 +1,133 @@ +/* + * Warning: + * + * This file is a mess of debugging and ROM bug workarounds. + */ + +/* Enable a workaround for a bug in the bootrom romapi. */ +#define RDA8810_VENDOR_EFUSE_WORKAROUND + +/* Enable debugging certificates in pdl1: */ +//#define RDA_CRYPTO_DEBUG_FAKE_ROMCERT + + + +#ifdef RDA_CRYPTO_DEBUG_FAKE_ROMCERT +/* + * Debugging version og get_chip_security_context(). + * This version is enabled with RDA_CRYPTO_DEBUG_FAKE_ROMCERT + * +TEST DATA + Use this secret key (file: rdatest.sec, pw: pa$$w0rd): + +"Comment: RDA PDL-Test-01 secret key +UkRBU0VkQksAAAAq0Ai4xjiIrmda3G8qI6q3B4gPbVQMPISmUkRBIFBETC1UZXN0LTAxACU+PXqYnPYI +gGYdDrpN5PljQAAht3pYTN4bNgtA6oRp/sEVIrSXZiEkZPRGsnqlGPGFRHn3MMsDZBz/FhZGdE1m2FnD +YYgQMg==" + */ +int get_chip_security_context( + struct chip_security_context *context, + struct pubkey *pubkey) +{ + const struct chip_security_context c = { + 3, 0x42, + RDA_SE_CFG_SECURITY_ENABLE_BIT | + RDA_SE_CFG_INDIRECT_SIGN_BIT | + RDA_SE_CFG_UNLOCK_ALLOWED + }; + const struct pubkey pk = { + /* Public key: rdatest.pub */ + {'R','D','A','S'}, {'E','d'},{}, "RDA PDL-Test-01 ", + { 0x25,0x3e,0x3d,0x7a,0x98,0x9c,0xf6,0x08 }, + { 0x7b,0x4a,0x5a,0xa8,0xa1,0xda,0x92,0xea,0x9e,0x90,0xa8,0x7e, + 0xfa,0x76,0x37,0x52,0xe0,0xe0,0x40,0x63,0x09,0x02,0xd3,0x86, + 0x8b,0x9d,0xe0,0xae,0xf3,0x57,0xd7,0x44 } + }; + + // Set the hardcoded debug public key and context + *context = c; + *pubkey = pk; + + return ROM_API_SECURITY_ENABLED; +} +#endif + + + +#ifdef RDA8810_VENDOR_EFUSE_WORKAROUND + +#include <common.h> +#include <asm/arch/rda_crypto.h> +#include <asm/arch/ispi.h> + +#define RDA_EFUSE_INDEX_SECURITY (11) + +/* + Fuse layout: + VVVVVVVV.T.H.I.S.KKKK + VVVVVVVV: Vendor ID - 6bit + 2bit armour + T: Trace disable + H: Host serial disable + I: Indirectly signed image + S: Security enable + KKKK: RDA Public Key Index - 3bit + 1 bit armour +*/ +/* define bit for rda se config */ +#define RDA_SE_CFG_KEY_INDEX(n) (((n)&0xF)<<0) +#define RDA_SE_CFG_GET_KEY_INDEX(r) (((r)>>0)&0xF) +#define RDA_SE_CFG_SECURITY_ENABLE_BIT (1<<4) +#define RDA_SE_CFG_INDIRECT_SIGN_BIT (1<<5) +#define RDA_SE_CFG_HOST_DISABLE_BIT (1<<6) +#define RDA_SE_CFG_TRACE_DISABLE_BIT (1<<7) +#define RDA_SE_CFG_VENDOR_ID(n) (((n)&0xFF)<<8) +#define RDA_SE_CFG_GET_VENDOR_ID(r) (((r)>>8)&0xFF) + +// RDA Public Key index map +// (armour 6 indexes in 4 bits) +static const uint8_t keyindex_map[16] = { + 15, 15, 15, 0, 15, 1, 2, 15, + 15, 3, 4, 15, 5, 15, 15, 15 +}; + +// Vendor ID +// (armour 50 vendor ID'd in 8 bits) +static int valid_vendor_id( unsigned vendor ) +{ + unsigned c; + unsigned i = vendor >> 2; + c = ((i & 0xaa)>>1) + (i & 0x55); + c = ((c & 0xcc)>>2) + (c & 0x33); + c = ((c & 0xf0)>>4) + (c & 0x0f); + return ((vendor & 3) + c) == 5; +} +#endif + + + + +#ifndef RDA_CRYPTO_DEBUG_FAKE_ROMCERT +int get_chip_security_context( + struct chip_security_context *context, + struct pubkey *pubkey) +{ + int ret = romapi->get_chip_security_context(context, pubkey); + +#ifdef RDA8810_VENDOR_EFUSE_WORKAROUND + if (ret == ROM_API_INVALID_VENDOR_ID && romapi->version == 100) { + uint16_t sec = rda_read_efuse(RDA_EFUSE_INDEX_SECURITY); + + // check validity of key index + int key = keyindex_map[RDA_SE_CFG_GET_KEY_INDEX(sec)]; + + // check validity of vendor id + int vendor = RDA_SE_CFG_GET_VENDOR_ID(sec); + if (valid_vendor_id(vendor)) { + context->rda_key_index = key; + context->vendor_id = vendor; + ret = 0; + } + } +#endif + return ret; +} +#endif diff --git a/arch/arm/cpu/armv7/rda/rda_sys.c b/arch/arm/cpu/armv7/rda/rda_sys.c new file mode 100644 index 0000000000..2e612a358a --- /dev/null +++ b/arch/arm/cpu/armv7/rda/rda_sys.c @@ -0,0 +1,507 @@ +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/io.h> +#include <asm/arch/reg_sysctrl.h> +#include <asm/arch/reg_md_sysctrl.h> +#include <asm/arch/reg_cfg_regs.h> +#include <asm/arch/reg_keypad.h> +#include <asm/arch/reg_gpio.h> +#include <asm/arch/hwcfg.h> +#include <asm/arch/ispi.h> +#include <asm/arch/reg_md_sysctrl.h> +#include <asm/arch/hwcfg.h> +#include <asm/arch/rda_sys.h> +#include <asm/arch/spl_board_info.h> +#ifdef CONFIG_CMD_MISC +#include <usb/usbserial.h> +#include <asm/arch/mdcom.h> +#endif + +#define RDA_AP_MBX_HWCFG_SWCFG_ADD (RDA_MD_MAILBOX_BASE + 0x1AE0) +#define RDA_HWCFG_SWCFG (*(u32 *)RDA_AP_MBX_HWCFG_SWCFG_ADD) + +/* + * Hardware and software configuration + */ +void hwcfg_swcfg_init(void) +{ + u16 hwcfg, swcfg; + + RDA_HWCFG_SWCFG = hwp_sysCtrlMd->Reset_Cause; + + hwcfg = rda_hwcfg_reg_get(); + swcfg = rda_swcfg_reg_get(); + + /* clear the sw boot modes handled by bootloader */ + rda_swcfg_reg_set(swcfg & ~(RDA_SW_CFG_BIT_2 | + RDA_SW_CFG_BIT_3 | + RDA_SW_CFG_BIT_4 | + RDA_SW_CFG_BIT_5 | + RDA_SW_CFG_BIT_6)); + + /* clear the hw boot modes for download/factory modes */ + rda_hwcfg_reg_set(hwcfg & ~(RDA_HW_CFG_BIT_10 | + RDA_HW_CFG_BIT_11 | + RDA_HW_CFG_BIT_12 | + RDA_HW_CFG_BIT_13 | + RDA_HW_CFG_BIT_14 | + RDA_HW_CFG_BIT_15)); + +} + +void rda_hwcfg_reg_set(u16 hwcfg) +{ + hwp_sysCtrlMd->Reset_Cause = SET_BITFIELD(hwp_sysCtrlMd->Reset_Cause, + SYS_CTRL_BOOT_MODE, hwcfg); + hwp_sysCtrlAp->Reset_Cause = hwp_sysCtrlMd->Reset_Cause; +} + +u16 rda_hwcfg_reg_get(void) +{ + u16 hwcfg = GET_BITFIELD(hwp_sysCtrlMd->Reset_Cause, SYS_CTRL_BOOT_MODE); + return hwcfg; +} + +u16 rda_hwcfg_get(void) +{ + u16 hwcfg = GET_BITFIELD(RDA_HWCFG_SWCFG, SYS_CTRL_BOOT_MODE); + return hwcfg; +} + +void rda_swcfg_reg_set(u16 swcfg) +{ + hwp_sysCtrlMd->Reset_Cause = SET_BITFIELD(hwp_sysCtrlMd->Reset_Cause, + SYS_CTRL_SW_BOOT_MODE, swcfg); + hwp_sysCtrlAp->Reset_Cause = hwp_sysCtrlMd->Reset_Cause; +} + +u16 rda_swcfg_reg_get(void) +{ + u16 swcfg = GET_BITFIELD(hwp_sysCtrlMd->Reset_Cause, SYS_CTRL_SW_BOOT_MODE); + return swcfg; +} + +u16 rda_swcfg_get(void) +{ + u16 swcfg = GET_BITFIELD(RDA_HWCFG_SWCFG, SYS_CTRL_SW_BOOT_MODE); + return swcfg; +} + +u16 rda_prod_id_get(void) +{ + u16 prod_id = GET_BITFIELD(hwp_configRegs->CHIP_ID, CFG_REGS_PROD_ID); + return prod_id; +} + +u16 rda_metal_id_get(void) +{ + u16 metal_id = GET_BITFIELD(hwp_configRegs->CHIP_ID, CFG_REGS_METAL_ID); + return metal_id; +} + +u16 rda_bond_id_get(void) +{ + u16 bond_id = GET_BITFIELD(hwp_configRegs->CHIP_ID, CFG_REGS_BOND_ID); + return bond_id; +} + +void rda_nand_iodrive_set(void) +{ + u32 value = hwp_configRegs->IO_Drive1_Select & (~ CFG_REGS_NFLSH_DRIVE_MASK); + + hwp_configRegs->IO_Drive1_Select = value | CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK; +} + +/* + * System-level control + */ +enum media_type rda_media_get(void) +{ +#ifdef CONFIG_SDMMC_BOOT + return MEDIA_MMC; +#else + u16 hwcfg = rda_hwcfg_get(); +#ifdef CONFIG_MACH_RDA8810H +/* + * HW BOOT MODE + * + * BIT_2 BIT1 BIT0 MODE + * 0 0 0 emmc + * 0 0 1 spi nand + * 0 1 0 spi nor + * 0 1 1 t-card0(run) + * 1 0 0 t-card1(update) + * 1 0 1 nand 8bit + * 1 1 0 nand 16bit + * 1 1 1 reserved + */ + u32 bm_media = RDA_HW_CFG_GET_BM_IDX(hwcfg); + + if (bm_media == RDA_MODE_EMMC) + return MEDIA_MMC; + else if (bm_media == RDA_MODE_SPINAND) + return MEDIA_SPINAND; + else if ((bm_media == RDA_MODE_NAND_8BIT) + || (bm_media == RDA_MODE_NAND_16BIT)) + return MEDIA_NAND; +#else + u16 metal_id = rda_metal_id_get(); + u16 prod_id = rda_prod_id_get(); + u16 metal_new_bm; + + if (prod_id == 0x8810) + metal_new_bm = 0xB; + else if (prod_id == 0x810E || prod_id == 0x8850 || prod_id == 0x850E) + metal_new_bm = 0x2; + else + metal_new_bm = 0; + + if (metal_id < metal_new_bm) { + /* SDMMC or SPI NAND */ + if (hwcfg & RDA_HW_CFG_BIT_3) { + if (hwcfg & RDA_HW_CFG_BIT_7) + return MEDIA_MMC; + else + return MEDIA_NAND; + } else if (hwcfg & RDA_HW_CFG_BIT_4) { + return MEDIA_MMC; + } + /* EMMC */ + if (hwcfg & RDA_HW_CFG_BIT_2) + return MEDIA_MMC; + /* PARALLEL NAND */ + if (!(hwcfg & RDA_HW_CFG_BIT_4)) + return MEDIA_NAND; + + } else { + /* SPI NAND */ + if (hwcfg & RDA_HW_CFG_BIT_3) + return MEDIA_NAND; + /* EMMC */ + if (hwcfg & RDA_HW_CFG_BIT_2) + return MEDIA_MMC; + /* PARALLEL NAND */ + if (!(hwcfg & RDA_HW_CFG_BIT_4)) + return MEDIA_NAND; + } +#endif +#endif + return MEDIA_UNKNOWN; +} + +void reset_cpu(ulong addr) +{ +#ifdef CONFIG_RDA_PDL + enable_charger(1); +#endif + + while (1) { + /* to unlock first */ + hwp_sysCtrlMd->REG_DBG = 0xa50001; + /* reset */ + hwp_sysCtrlMd->Sys_Rst_Set |= SYS_CTRL_SOFT_RST; + } +} + +void shutdown_system(void) +{ +#ifdef CONFIG_RDA_PDL + enable_charger(1); +#endif + + while (1) { + /* to unlock first */ + hwp_sysCtrlMd->REG_DBG = 0xa50001; + /* shutdown */ + hwp_sysCtrlMd->WakeUp = 0; + } +} + +int rda_bm_is_calib(void) +{ + u16 swcfg = rda_swcfg_get(); + return !!(swcfg & RDA_SW_CFG_BIT_4); +} + +int rda_bm_is_autocall(void) +{ + u16 swcfg = rda_swcfg_get(); + return !!(swcfg & RDA_SW_CFG_BIT_5); +} + +int rda_bm_is_download(void) +{ +#ifdef CONFIG_RDA_PDL /* for PDL mode, always enable download mode */ + return 1; +#else + u16 hwcfg = rda_hwcfg_get(); + return !!(hwcfg & RDA_HW_CFG_BIT_11); +#endif +} + +/* Check if download keys are pressed. */ +int rda_bm_download_key_pressed(void) +{ + int key_power = !!(hwp_apKeypad->KP_STATUS & KEYPAD_KP_ON); + int key_vol_up = !!(hwp_apGpioD->gpio_val & 0x40); /* GPIO D6 */ +#ifdef CONFIG_SDMMC_BOOT + int key_vol_down = !!(hwp_apGpioD->gpio_val & 0x20); /* GPIO D5 */ + return (key_power && key_vol_up && !key_vol_down); +#else + return (key_power && key_vol_up); +#endif +} + +void rda_reboot(enum reboot_type type) +{ + u16 hwcfg = rda_hwcfg_reg_get(); + u16 swcfg = rda_swcfg_reg_get(); + int key_vol_down; + + hwcfg &= ~(RDA_HW_CFG_BIT_10 | RDA_HW_CFG_BIT_11 | + RDA_HW_CFG_BIT_12 | RDA_HW_CFG_BIT_13 | + RDA_HW_CFG_BIT_14 | RDA_HW_CFG_BIT_15); + + switch (type) { + case REBOOT_TO_DOWNLOAD_MODE: + hwcfg |= RDA_HW_CFG_BIT_11 | RDA_HW_CFG_BIT_12 | + RDA_HW_CFG_BIT_14; + key_vol_down = !!(hwp_apGpioD->gpio_val & 0x20); /* GPIO D5 */ + if (key_vol_down) + hwcfg |= RDA_HW_CFG_BIT_10 | RDA_HW_CFG_BIT_13; + break; + case REBOOT_TO_FASTBOOT_MODE: + swcfg |= RDA_SW_CFG_BIT_2; + break; + case REBOOT_TO_RECOVERY_MODE: + swcfg |= RDA_SW_CFG_BIT_3; + break; + case REBOOT_TO_CALIB_MODE: + swcfg |= RDA_SW_CFG_BIT_4; + break; + case REBOOT_TO_PDL2_MODE: + swcfg |= RDA_SW_CFG_BIT_6; + break; + default: + break; + } + + rda_hwcfg_reg_set(hwcfg); + rda_swcfg_reg_set(swcfg); + reset_cpu(0); +} + +void enable_vibrator(int enable) +{ + u32 value; + + ispi_open(1); + + value = ispi_reg_read(0x03); + + if (enable) + value |= 0x20; + else + value &= ~0x20; + if (rda_metal_id_get() >= 9) + value ^= 0x20; + + ispi_reg_write(0x03, value); + + ispi_open(0); +} + +void enable_charger(int enable) +{ + u32 val; + + ispi_open(1); + val = ispi_reg_read(0x15); + if (enable) { + val &= ~((1 << 15) | (1 << 14)); + } else { + val |= (1 << 15); + val &= ~(1 << 14); + } + ispi_reg_write(0x15, val); + ispi_open(0); +} + +void rda_dump_buf(char *data, size_t len) +{ + char temp_buf[64]; + size_t i, off = 0; + + memset(temp_buf, 0, 64); + for (i=0;i<len;i++) { + if(i%8 == 0) { + sprintf(&temp_buf[off], " "); + off += 2; + } + sprintf(&temp_buf[off], "%02x ", data[i]); + off += 3; + if((i+1)%16 == 0 || (i+1) == len) { + printf("%8d %s\n", (unsigned int)i/16,temp_buf); + memset(temp_buf, 0, 64); + off = 0; + } + } + printf("\n"); +} + +void print_cur_time(void) +{ + unsigned long long time = ticks2usec(get_ticks()); + printf("\n****** [CURRENT TIME: %3d.%06d] ******\n\n", + (int)(time / 1000000), + (int)(time % 1000000)); +} + +#ifdef CONFIG_CMD_MISC + +int usb_cable_connected(void) +{ + u32 val; + + ispi_open(1); + val = ispi_reg_read(0x14); + ispi_open(0); + if (val & (1 << 8)) + return 1; + else + return 0; +} + +int system_rebooted(void) +{ + static int system_rebooted_flag = -1; + + if (system_rebooted_flag == -1) { + if (rda_mdcom_system_started_before()) + system_rebooted_flag = 1; + else + system_rebooted_flag = 0; + rda_mdcom_set_system_started_flag(); + } + return system_rebooted_flag; +} + +static int boot_key_long_pressed = 0; + +void save_current_boot_key_state(void) +{ + int boot_key_on = ((hwp_apKeypad->KP_STATUS & KEYPAD_KP_ON) != 0); + int start_by_boot_key = ((rda_hwcfg_get() & RDA_HW_CFG_BIT_12) != 0); + boot_key_long_pressed = (boot_key_on && start_by_boot_key); +} + +int get_saved_boot_key_state(void) +{ + return boot_key_long_pressed; +} + +void get_board_serial(struct tag_serialnr *serialnr) +{ + struct spl_security_info *info = get_bd_spl_security_info(); + const uint32_t *id256 = (uint32_t *)info->chip_unique_id.id; + + serialnr->low = id256[0]; + serialnr->high = id256[1]; + + if ((serialnr->low | serialnr->high) == 0) { + serialnr->low = 0x90abcdef; + serialnr->high = 0x12345678; + } + + /* Set serialno enviroment variable */ + char tmp[32]; + sprintf(tmp, "%08x%08x", serialnr->high, serialnr->low); + setenv("serialno", tmp); +} + +static int boot_mode = RDA_BM_NORMAL; + +void rda_bm_init(void) +{ + u16 hwcfg = rda_hwcfg_get(); + u16 swcfg = rda_swcfg_get(); +#ifndef CONFIG_RDA_PDL + int rebooted = system_rebooted(); + u32 fastboot_key_mask, all_key_mask; +#endif + char str[2]; + struct tag_serialnr serialnr; + get_board_serial(&serialnr); + + printf("RDA: HW_CFG 0x%04x\n", hwcfg); + printf("RDA: SW_CFG 0x%04x\n", swcfg); + printf("RDA: ID PROD %04x M %03x B %01x\n", + rda_prod_id_get(), rda_metal_id_get(), + rda_bond_id_get()); + +#ifdef CONFIG_RDA_PDL + /* PDL: always enable download mode */ + boot_mode = RDA_BM_FORCEDOWNLOAD; +#else + /* SPL */ + boot_mode = RDA_BM_NORMAL; + + if (swcfg & RDA_SW_CFG_BIT_2) { + boot_mode = RDA_BM_FASTBOOT; + } else if (swcfg & RDA_SW_CFG_BIT_3) { + boot_mode = RDA_BM_RECOVERY; + } else if (swcfg & RDA_SW_CFG_BIT_4) { + boot_mode = RDA_BM_CALIB; + } else if (swcfg & RDA_SW_CFG_BIT_5) { + boot_mode = RDA_BM_AUTOCALL; + } else if (swcfg & RDA_SW_CFG_BIT_6) { + /* force to 'pdl2', called by kernel */ + boot_mode = RDA_BM_FORCEDOWNLOAD; + } else if ((hwcfg & RDA_HW_CFG_BIT_10) && (hwcfg & RDA_HW_CFG_BIT_11)) { + /* + * If power key, vol-up, and vol-down are all pressed, consider + * it as normal boot (for T-Card) + */ + boot_mode = RDA_BM_NORMAL; + } else if ((hwcfg & RDA_HW_CFG_BIT_10) && !rebooted) { + /* Distinguish between factory mode and h/w force reset */ + boot_mode = RDA_BM_FACTORY; + } else if (hwcfg & RDA_HW_CFG_BIT_11) { + /* Force download mode for pdl2 */ + boot_mode = RDA_BM_FORCEDOWNLOAD; + } else if (usb_cable_connected()) { + all_key_mask = RDA_HW_CFG_BIT_15 | RDA_HW_CFG_BIT_14 | + RDA_HW_CFG_BIT_13 | RDA_HW_CFG_BIT_12 | + RDA_HW_CFG_BIT_11 | RDA_HW_CFG_BIT_10; + /* Fastboot keys are volume-up + volume-down keys */ + fastboot_key_mask = RDA_HW_CFG_BIT_13 | RDA_HW_CFG_BIT_14; + + if ((hwcfg & fastboot_key_mask) == fastboot_key_mask && + (hwcfg & all_key_mask & ~fastboot_key_mask) == 0) { + /* + * All the keys are up, except for the fastboot keys; + * and the usb cable is plugged in + */ + boot_mode = RDA_BM_FASTBOOT; + } + } +#endif /* !CONFIG_RDA_PDL */ + + printf("RDA: Boot_Mode %d\n", boot_mode); + + sprintf(str, "%1d", boot_mode); + setenv ("bootmode", str); +} + +enum rda_bm_type rda_bm_get(void) +{ + return boot_mode; +} + +void rda_bm_set(enum rda_bm_type bm) +{ + boot_mode = bm; +} + +#endif /* CONFIG_CMD_MISC */ + diff --git a/arch/arm/cpu/armv7/rda/serial.c b/arch/arm/cpu/armv7/rda/serial.c new file mode 100644 index 0000000000..f7c1d2d244 --- /dev/null +++ b/arch/arm/cpu/armv7/rda/serial.c @@ -0,0 +1,132 @@ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> +#include <asm/arch/reg_sysctrl.h> +#include <asm/arch/reg_uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +void _serial_set_baudrate(int rate) +{ + hwp_sysCtrlAp->Cfg_Clk_Uart[2] = 0x36; // 115200 @ 26MHz + //hwp_sysCtrlAp->Cfg_Clk_Uart[2] = 0x05; // 921600 @ 26MHz +} + +void _serial_enable_rtscts(void) +{ + hwp_uart->ctrl |= UART_AUTO_FLOW_CONTROL; +} + +void _serial_disable_rtscts(void) +{ + hwp_uart->ctrl &= ~UART_AUTO_FLOW_CONTROL; +} + +void _serial_init(void) +{ + _serial_set_baudrate(CONFIG_BAUDRATE); + hwp_uart->triggers = UART_AFC_LEVEL(1); //7 ? + + hwp_uart->ctrl = UART_ENABLE | UART_DATA_BITS_8_BITS | + UART_TX_STOP_BITS_1_BIT | UART_PARITY_ENABLE_NO; + + /* Allow reception */ + hwp_uart->CMD_Set = UART_RTS; +} + +void _serial_deinit(void) +{ + hwp_uart->ctrl = 0; + hwp_uart->CMD_Clr = UART_RTS; +} + +/* + * Test whether a character is in the RX buffer + */ +int _serial_tstc(const int port) +{ + return (GET_BITFIELD(hwp_uart->status, UART_RX_FIFO_LEVEL)); +} + +int _serial_getc(const int port) +{ + /* wait for character to arrive */ ; + while (!(GET_BITFIELD(hwp_uart->status, UART_RX_FIFO_LEVEL))) + ; + + return (hwp_uart->rxtx_buffer & 0xff); +} + +void _serial_putc_hw(const char c, const int port) +{ + // Place in the TX Fifo ? + while (!(GET_BITFIELD(hwp_uart->status, UART_TX_FIFO_SPACE))) + ; + hwp_uart->rxtx_buffer = (u32)c; +} + +void _serial_putc(const char c, const int port) +{ + if (c == '\n') { + _serial_putc_hw('\r', 0); + } + _serial_putc_hw(c, 0); +} + +void _serial_puts(const char *s, const int port) +{ + while (*s) { + _serial_putc(*s++, 0); + } +} + +static int hwflow = 0; /* turned off by default */ +int hwflow_onoff(int on) +{ + switch(on) { + case 0: + default: + break; /* return current */ + case 1: + hwflow = 1; + _serial_enable_rtscts(); /* turn on */ + break; + case -1: + hwflow = 0; + _serial_disable_rtscts(); /* turn off */ + break; + } + return hwflow; +} + +int serial_init(void) +{ + //_serial_init(); // already init in boot_test + return 0; +} + +int serial_getc(void) +{ + return _serial_getc(0); +} + +int serial_tstc(void) +{ + return _serial_tstc(0); +} + +void serial_putc(const char c) +{ + _serial_putc(c, 0); +} + +void serial_puts(const char *s) +{ + _serial_puts(s, 0); +} + +void serial_setbrg (void) +{ +} + diff --git a/arch/arm/cpu/armv7/rda/spl.c b/arch/arm/cpu/armv7/rda/spl.c new file mode 100644 index 0000000000..93bbb85c42 --- /dev/null +++ b/arch/arm/cpu/armv7/rda/spl.c @@ -0,0 +1,189 @@ +#include <common.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <nand.h> +#include <malloc.h> +#include <image.h> +#include <usb/usbserial.h> +#include <asm/arch/rda_sys.h> +#include <asm/arch/spl_board_info.h> +#include <asm/arch/rda_crypto.h> +#include <pdl.h> + +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + +DECLARE_GLOBAL_DATA_PTR; +/* Define global data structure pointer to it*/ +static gd_t gdata __attribute__ ((section(".data"))); +static bd_t bdata __attribute__ ((section(".data"))); + +#else + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} + +void putc(char c) +{ +} + +#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */ + +void board_init_f(ulong dummy) +{ + relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE); +} + +#ifdef CONFIG_SPL_CHECK_IMAGE +int check_uimage(unsigned int *buf) +{ + image_header_t *hdr = (image_header_t *)buf; + puts("Check Image "); + if (!image_check_magic(hdr)) { + printf("Magic Error %x\n", image_get_magic(hdr)); + rda_dump_buf((char *)buf, 256); + return -1; + } + puts("."); + if (!image_check_hcrc(hdr)) { + printf("HCRC Error %x\n", image_get_hcrc(hdr)); + rda_dump_buf((char *)buf, 256); + return -2; + } + puts("."); + if (!image_check_dcrc(hdr)) { + printf("DCRC Error %x\n", image_get_dcrc(hdr)); + rda_dump_buf((char *)buf, 256); + //rda_dump_buf(buf, + // image_get_header_size() + image_get_size(hdr)); + return -3; + } + puts("."); +#ifdef CONFIG_SIGNATURE_CHECK_IMAGE + if (image_sign_verify_uimage(hdr) != 0) { + printf("Image Signature check failed!\n"); + return -4; + } +#endif + puts(" Done\n"); + return 0; +} +#endif + +#ifdef CONFIG_SPL_EMMC_LOAD +extern void emmc_init(void); +extern void emmc_boot(void); +#endif + +#ifdef CONFIG_SPL_XMODEM_LOAD +extern void xmodem_boot(void); +#endif + +extern void hwcfg_swcfg_init(void); +extern int clock_init(void); + + +#ifdef CONFIG_SIGNATURE_CHECK_IMAGE +static const uint8_t *get_spl_load_addr(void) +{ + const uint8_t *spl_image = (uint8_t*)CONFIG_SPL_LOAD_ADDRESS + CONFIG_UIMAGEHDR_SIZE; + return spl_image; +} +#endif + +void board_init_r(gd_t *id, ulong dummy) +{ +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + gd = &gdata; + gd->bd = &bdata; + gd->flags |= GD_FLG_RELOC; + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); /* serial communications setup */ + gd->have_console = 1; +#endif + hwcfg_swcfg_init(); + clock_init(); + +#ifdef CONFIG_SIGNATURE_CHECK_IMAGE + // Set the security contex (or get the unique ID of the device) + struct spl_security_info *info = get_bd_spl_security_info(); + const uint8_t *spl_image = get_spl_load_addr(); + + puts("SETTING SECURITY CONTEXT\n"); + set_security_context(info, spl_image); +#endif + +#ifndef CONFIG_RDA_PDL + /* Note BIT3 for SPINAND got higher priority */ +#ifdef CONFIG_SPL_EMMC_SUPPORT + if (rda_media_get() == MEDIA_MMC) { + puts("Init emmc ...\n"); + emmc_init(); + } +#endif + +#ifdef CONFIG_SPL_NAND_SUPPORT + if (rda_media_get() == MEDIA_NAND || rda_media_get() == MEDIA_SPINAND) { + puts("Init nand ...\n"); + nand_init(); + } +#endif +#endif + +#ifdef CONFIG_RDA_PDL + drv_usbser_init(); + pdl_main(); +#else + /* A workaround to handle the timing issue when detecting + * download mode in h/w */ + if( !rda_bm_is_autocall() && + !rda_bm_is_calib() && + !rda_bm_is_download() && + rda_bm_download_key_pressed()) { + puts("Download key pressed. Enter download mode ...\n"); + rda_reboot(REBOOT_TO_DOWNLOAD_MODE); + } +#endif + +#ifdef CONFIG_SPL_EMMC_LOAD + if (rda_media_get() == MEDIA_MMC) { + puts("EMMC boot ...\n"); + emmc_boot(); + } +#endif + +#ifdef CONFIG_SPL_NAND_LOAD + if (rda_media_get() == MEDIA_NAND || rda_media_get() == MEDIA_SPINAND) { + puts("NAND boot ...\n"); + nand_boot(); + } +#endif + +#ifdef CONFIG_SPL_SPI_LOAD + mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN, + CONFIG_SYS_MALLOC_LEN); + + gd = &gdata; + gd->bd = &bdata; + gd->flags |= GD_FLG_RELOC; + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); /* serial communications setup */ + gd->have_console = 1; + + puts("SPI boot...\n"); + spi_boot(); +#endif + +#ifdef CONFIG_SPL_XMODEM_LOAD + puts("Xmodem boot ...\n"); + xmodem_boot(); +#endif + + /* + should never go here + */ + while(1) + ; +} diff --git a/arch/arm/cpu/armv7/rda/timer.c b/arch/arm/cpu/armv7/rda/timer.c new file mode 100644 index 0000000000..9da8958dc2 --- /dev/null +++ b/arch/arm/cpu/armv7/rda/timer.c @@ -0,0 +1,132 @@ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> +#include <asm/arch/reg_timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +typedef union +{ + unsigned long long timer; + struct + { + unsigned long timer_l :32; + unsigned long timer_h :32; + } fields; +} RDA_TIMER; + +#if (CONFIG_SYS_HZ_CLOCK == 2000000) +/* optimize for 2M Hz */ +static unsigned long tick_to_ms(unsigned long long tick) __attribute__((unused)); +static unsigned long tick_to_ms(unsigned long long tick) +{ + return (u32)(tick >> 11); // divide 2048 +} + +static unsigned long long ms_to_tick(unsigned long ms) +{ + return (((unsigned long long)ms) << 11); // x 2048 +} + +static unsigned long tick_to_us(unsigned long long tick) +{ + return (unsigned long)(tick >> 1); // divide 2 +} + +static unsigned long long us_to_tick(unsigned long ms) +{ + return (((unsigned long long)ms) << 1); // x2 +} +#else +/* need to calc */ +#error "Timer is not 2M Hz" +#endif + +static void rda_timer_get(RDA_TIMER *timer) +{ + /* always read low 32bit first */ + timer->fields.timer_l = + (unsigned long)(hwp_apTimer->HWTimer_LockVal_L); + timer->fields.timer_h = + (unsigned long)(hwp_apTimer->HWTimer_LockVal_H); +} + +static void rda_timeout_setup_ms(RDA_TIMER *timer, unsigned long ms) + __attribute__((unused)); +static void rda_timeout_setup_ms(RDA_TIMER *timer, unsigned long ms) +{ + timer->timer = get_ticks() + ms_to_tick(ms); +} + +static void rda_timeout_setup_us(RDA_TIMER *timer, unsigned long us) +{ + timer->timer = get_ticks() + us_to_tick(us); +} + +static int rda_timeout_check(RDA_TIMER *timer) +{ + return (get_ticks() > timer->timer); +} + +int timer_init(void) +{ + gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK; + gd->timer_reset_value = 0; + + /* We are using timer34 in unchained 32-bit mode, full speed */ + return(0); +} + +void reset_timer(void) +{ + gd->timer_reset_value = get_ticks(); +} + +/* + * Get the current 64 bit timer tick count + */ +unsigned long long get_ticks(void) +{ + RDA_TIMER timer; + + rda_timer_get(&timer); + return timer.timer; +} + +ulong usec2ticks (unsigned long usec) +{ + return (ulong)us_to_tick(usec); +} + +ulong ticks2usec (unsigned long ticks) +{ + return tick_to_us(ticks); +} + +ulong get_timer(ulong base) +{ + unsigned long long timer_diff; + + timer_diff = get_ticks() - gd->timer_reset_value; + + return (timer_diff / (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base; +} + +void __udelay(unsigned long usec) +{ + RDA_TIMER timer; + + rda_timeout_setup_us(&timer, usec); + while(!rda_timeout_check(&timer)) + ; +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ_CLOCK; +} diff --git a/arch/arm/cpu/armv7/rda/xmodem_boot.c b/arch/arm/cpu/armv7/rda/xmodem_boot.c new file mode 100644 index 0000000000..48b3047f03 --- /dev/null +++ b/arch/arm/cpu/armv7/rda/xmodem_boot.c @@ -0,0 +1,75 @@ +#include <common.h> +#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <xyzModem.h> + +void _serial_enable_rtscts(void); +#ifdef CONFIG_SPL_CHECK_IMAGE +int check_uimage(unsigned int *buf); +#endif + +static int getcxmodem(void) { + if (tstc()) + return (getc()); + return -1; +} + +static ulong load_serial_xmodem (ulong offset) +{ + int size; + int err; + int res; + connection_info_t info; + char ymodemBuf[1024]; + ulong store_addr = ~0; + ulong addr = 0; + + size = 0; + info.mode = xyzModem_xmodem; + _serial_enable_rtscts(); + mdelay(10); + res = xyzModem_stream_open (&info, &err); + if (!res) { + while ((res = + xyzModem_stream_read (ymodemBuf, 1024, &err)) > 0) { + store_addr = addr + offset; + size += res; + addr += res; + memcpy ((char *) (store_addr), ymodemBuf,res); + } + } else { + printf ("%s\n", xyzModem_error (err)); + } + + xyzModem_stream_close (&err); + xyzModem_stream_terminate (false, &getcxmodem); + + + flush_cache (offset, size); + printf("\nXmodem Download Success.\n"); + printf("Total Size = 0x%08x = %d Bytes\n", size, size); + + return offset; +} + +void xmodem_boot(void) +{ + __attribute__((noreturn)) void (*uboot)(void); + + load_serial_xmodem(CONFIG_SYS_XMODEM_U_BOOT_DST); + +#ifdef CONFIG_SPL_CHECK_IMAGE + if (check_uimage((unsigned int*)CONFIG_SYS_XMODEM_U_BOOT_DST)) { + printf("Xmodem boot failed.\n"); + return; + } +#endif + + /* + * Jump to U-Boot image + */ + printf("Running U-Boot ...\n"); + uboot = (void *)CONFIG_SYS_XMODEM_U_BOOT_START; + (*uboot)(); +} diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S index c7d62212bd..000192c254 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/cache.S +++ b/arch/arm/cpu/armv7/s5pc1xx/cache.S @@ -25,20 +25,22 @@ .align 5 +#include <linux/linkage.h> + #ifndef CONFIG_SYS_L2CACHE_OFF -.global v7_outer_cache_enable -v7_outer_cache_enable: +ENTRY(v7_outer_cache_enable) push {r0, r1, r2, lr} mrc 15, 0, r3, cr1, cr0, 1 orr r3, r3, #2 mcr 15, 0, r3, cr1, cr0, 1 pop {r1, r2, r3, pc} +ENDPROC(v7_outer_cache_enable) -.global v7_outer_cache_disable -v7_outer_cache_disable: +ENTRY(v7_outer_cache_disable) push {r0, r1, r2, lr} mrc 15, 0, r3, cr1, cr0, 1 bic r3, r3, #2 mcr 15, 0, r3, cr1, cr0, 1 pop {r1, r2, r3, pc} +ENDPROC(v7_outer_cache_disable) #endif diff --git a/arch/arm/cpu/armv7/s5pc1xx/reset.S b/arch/arm/cpu/armv7/s5pc1xx/reset.S index 70fa146cf3..c7a41d03d2 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/reset.S +++ b/arch/arm/cpu/armv7/s5pc1xx/reset.S @@ -22,12 +22,12 @@ */ #include <asm/arch/cpu.h> +#include <linux/linkage.h> #define S5PC100_SWRESET 0xE0200000 #define S5PC110_SWRESET 0xE0102000 -.globl reset_cpu -reset_cpu: +ENTRY(reset_cpu) ldr r1, =S5PC100_PRO_ID ldr r2, [r1] ldr r4, =0x00010000 @@ -45,3 +45,4 @@ reset_cpu: str r2, [r1] _loop_forever: b _loop_forever +ENDPROC(reset_cpu) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index ef08a55abc..3fd8ded9c6 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -31,8 +31,8 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <asm/system.h> +#include <linux/linkage.h> .globl _start _start: b reset @@ -158,7 +158,11 @@ reset: /* Set stackpointer in internal RAM to call board_init_f */ call_board_init_f: +#ifdef CONFIG_SPL_BUILD + ldr sp, =(CONFIG_SPL_STACK) +#else ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) +#endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ ldr r0,=0x00000000 bl board_init_f @@ -172,8 +176,7 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code -relocate_code: +ENTRY(relocate_code) mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ @@ -257,12 +260,17 @@ clear_bss: add r0, r0, r4 add r1, r1, r4 #endif + + cmp r0, r1 + beq clbss_d + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l +clbss_d: /* * We are done. Do not return, instead branch to second part of board @@ -289,6 +297,7 @@ jump_2_ram: _board_init_r_ofs: .word board_init_r - _start +ENDPROC(relocate_code) /************************************************************************* * @@ -298,8 +307,7 @@ _board_init_r_ofs: * CONFIG_SYS_ICACHE_OFF is defined. * *************************************************************************/ -.globl cpu_init_cp15 -cpu_init_cp15: +ENTRY(cpu_init_cp15) /* * Invalidate L1 I/D */ @@ -325,7 +333,7 @@ cpu_init_cp15: #endif mcr p15, 0, r0, c1, c0, 0 mov pc, lr @ back to my caller - +ENDPROC(cpu_init_cp15) #ifndef CONFIG_SKIP_LOWLEVEL_INIT /************************************************************************* @@ -336,7 +344,7 @@ cpu_init_cp15: * setup memory timing * *************************************************************************/ -cpu_init_crit: +ENTRY(cpu_init_crit) /* * Jump to board specific initialization... * The Mask ROM will have already initialized @@ -347,6 +355,7 @@ cpu_init_crit: bl lowlevel_init @ go setup pll,mux,memory mov lr, ip @ restore link mov pc, lr @ back to my caller +ENDPROC(cpu_init_crit) #endif #ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index e9ac6c9a71..08c4137a34 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -27,6 +27,7 @@ # flags for any startup files it might use. CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t +CFLAGS_arch/arm/cpu/armv7/tegra2/warmboot_avp.o += -march=armv4t include $(TOPDIR)/config.mk @@ -34,7 +35,10 @@ LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o COBJS-y := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o +COBJS-$(CONFIG_TEGRA_PMU) += pmu.o COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o +COBJS-$(CONFIG_TEGRA2_LP0) += crypto.o warmboot.o warmboot_avp.o COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index b749821e5a..698bfd0e17 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -21,16 +21,53 @@ * MA 02111-1307 USA */ -#include "ap20.h" #include <asm/io.h> #include <asm/arch/tegra2.h> +#include <asm/arch/ap20.h> #include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> +#include <asm/arch/fuse.h> +#include <asm/arch/gp_padctrl.h> #include <asm/arch/pmc.h> #include <asm/arch/pinmux.h> #include <asm/arch/scu.h> +#include <asm/arch/warmboot.h> #include <common.h> +int tegra_get_chip_type(void) +{ + struct apb_misc_gp_ctlr *gp; + struct fuse_regs *fuse = (struct fuse_regs *)TEGRA2_FUSE_BASE; + uint tegra_sku_id, rev; + + /* + * This is undocumented, Chip ID is bits 15:8 of the register + * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for + * Tegra30 + */ + gp = (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE; + rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; + + tegra_sku_id = readl(&fuse->sku_info) & 0xff; + + switch (rev) { + case CHIPID_TEGRA2: + switch (tegra_sku_id) { + case SKU_ID_T20: + return TEGRA_SOC_T20; + case SKU_ID_T25SE: + case SKU_ID_AP25: + case SKU_ID_T25: + case SKU_ID_AP25E: + case SKU_ID_T25E: + return TEGRA_SOC_T25; + } + break; + } + /* unknown sku id */ + return TEGRA_SOC_UNKNOWN; +} + /* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */ static int ap20_cpu_is_cortexa9(void) { @@ -286,6 +323,11 @@ void init_pmc_scratch(void) /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20); + +#ifdef CONFIG_TEGRA2_LP0 + /* save Sdram params to PMC 2, 4, and 24 for WB0 */ + warmboot_save_sdram_params(); +#endif } void tegra2_start(void) diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index a797e6fc30..a50b1b988a 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -23,12 +23,12 @@ #include <common.h> #include <asm/io.h> -#include "ap20.h" +#include <asm/arch/ap20.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> +#include <asm/arch/pmc.h> #include <asm/arch/sys_proto.h> #include <asm/arch/tegra2.h> -#include <asm/arch/pmc.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index 39376ab86e..ccad351639 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -410,6 +410,16 @@ enum clock_osc_freq clock_get_osc_freq(void) return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; } +int clock_get_osc_bypass(void) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + reg = readl(&clkrst->crc_osc_ctrl); + return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT; +} + /* Returns a pointer to the registers of the given pll */ static struct clk_pll *get_pll(enum clock_id clkid) { @@ -420,6 +430,28 @@ static struct clk_pll *get_pll(enum clock_id clkid) return &clkrst->crc_pll[clkid]; } +int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, + u32 *divp, u32 *cpcon, u32 *lfcon) +{ + struct clk_pll *pll = get_pll(clkid); + u32 data; + + assert(clkid != CLOCK_ID_USB); + + /* Safety check, adds to code size but is small */ + if (!clock_id_isvalid(clkid) || clkid == CLOCK_ID_USB) + return -1; + data = readl(&pll->pll_base); + *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT; + *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT; + *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT; + data = readl(&pll->pll_misc); + *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT; + *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT; + + return 0; +} + unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, u32 divp, u32 cpcon, u32 lfcon) { @@ -1027,7 +1059,10 @@ void clock_early_init(void) clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); break; - case CLOCK_OSC_FREQ_13_0: + case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ + clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8); + clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); + break; case CLOCK_OSC_FREQ_19_2: default: /* diff --git a/arch/arm/cpu/armv7/tegra2/crypto.c b/arch/arm/cpu/armv7/tegra2/crypto.c new file mode 100644 index 0000000000..5f0b240e27 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/crypto.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/errno.h> +#include "crypto.h" +#include "aes.h" + +static u8 zero_key[16]; + +#define AES_CMAC_CONST_RB 0x87 /* from RFC 4493, Figure 2.2 */ + +enum security_op { + SECURITY_SIGN = 1 << 0, /* Sign the data */ + SECURITY_ENCRYPT = 1 << 1, /* Encrypt the data */ +}; + +static void debug_print_vector(char *name, u32 num_bytes, u8 *data) +{ + u32 i; + + debug("%s [%d] @0x%08x", name, num_bytes, (u32)data); + for (i = 0; i < num_bytes; i++) { + if (i % 16 == 0) + debug(" = "); + debug("%02x", data[i]); + if ((i+1) % 16 != 0) + debug(" "); + } + debug("\n"); +} + +/** + * Apply chain data to the destination using EOR + * + * Each array is of length AES_AES_KEY_LENGTH. + * + * \param cbc_chain_data Chain data + * \param src Source data + * \param dst Destination data, which is modified here + */ +static void apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst) +{ + int i; + + for (i = 0; i < 16; i++) + *dst++ = *src++ ^ *cbc_chain_data++; +} + +/** + * Encrypt some data with AES. + * + * \param key_schedule Expanded key to use + * \param src Source data to encrypt + * \param dst Destination buffer + * \param num_aes_blocks Number of AES blocks to encrypt + */ +static void encrypt_object(u8 *key_schedule, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + u8 tmp_data[AES_KEY_LENGTH]; + u8 *cbc_chain_data; + u32 i; + + cbc_chain_data = zero_key; /* Convenient array of 0's for IV */ + + for (i = 0; i < num_aes_blocks; i++) { + debug("encrypt_object: block %d of %d\n", i, num_aes_blocks); + debug_print_vector("AES Src", AES_KEY_LENGTH, src); + + /* Apply the chain data */ + apply_cbc_chain_data(cbc_chain_data, src, tmp_data); + debug_print_vector("AES Xor", AES_KEY_LENGTH, tmp_data); + + /* encrypt the AES block */ + aes_encrypt(tmp_data, key_schedule, dst); + debug_print_vector("AES Dst", AES_KEY_LENGTH, dst); + + /* Update pointers for next loop. */ + cbc_chain_data = dst; + src += AES_KEY_LENGTH; + dst += AES_KEY_LENGTH; + } +} + +/** + * Shift a vector left by one bit + * + * \param in Input vector + * \param out Output vector + * \param size Length of vector in bytes + */ +static void left_shift_vector(u8 *in, u8 *out, int size) +{ + int carry = 0; + int i; + + for (i = size - 1; i >= 0; i--) { + out[i] = (in[i] << 1) | carry; + carry = in[i] >> 7; /* get most significant bit */ + } +} + +/** + * Sign a block of data, putting the result into dst. + * + * \param key Input AES key, length AES_KEY_LENGTH + * \param key_schedule Expanded key to use + * \param src Source data of length 'num_aes_blocks' blocks + * \param dst Destination buffer, length AES_KEY_LENGTH + * \param num_aes_blocks Number of AES blocks to encrypt + */ +static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + u8 tmp_data[AES_KEY_LENGTH]; + u8 left[AES_KEY_LENGTH]; + u8 k1[AES_KEY_LENGTH]; + u8 *cbc_chain_data; + unsigned i; + + cbc_chain_data = zero_key; /* Convenient array of 0's for IV */ + + /* compute K1 constant needed by AES-CMAC calculation */ + for (i = 0; i < AES_KEY_LENGTH; i++) + tmp_data[i] = 0; + + encrypt_object(key_schedule, tmp_data, left, 1); + debug_print_vector("AES(key, nonce)", AES_KEY_LENGTH, left); + + left_shift_vector(left, k1, sizeof(left)); + debug_print_vector("L", AES_KEY_LENGTH, left); + + if ((left[0] >> 7) != 0) /* get MSB of L */ + k1[AES_KEY_LENGTH-1] ^= AES_CMAC_CONST_RB; + debug_print_vector("K1", AES_KEY_LENGTH, k1); + + /* compute the AES-CMAC value */ + for (i = 0; i < num_aes_blocks; i++) { + /* Apply the chain data */ + apply_cbc_chain_data(cbc_chain_data, src, tmp_data); + + /* for the final block, XOR K1 into the IV */ + if (i == num_aes_blocks - 1) + apply_cbc_chain_data(tmp_data, k1, tmp_data); + + /* encrypt the AES block */ + aes_encrypt(tmp_data, key_schedule, dst); + + debug("sign_obj: block %d of %d\n", i, num_aes_blocks); + debug_print_vector("AES-CMAC Src", AES_KEY_LENGTH, src); + debug_print_vector("AES-CMAC Xor", AES_KEY_LENGTH, tmp_data); + debug_print_vector("AES-CMAC Dst", AES_KEY_LENGTH, dst); + + /* Update pointers for next loop. */ + cbc_chain_data = dst; + src += AES_KEY_LENGTH; + } + + debug_print_vector("AES-CMAC Hash", AES_KEY_LENGTH, dst); +} + +/** + * Encrypt and sign a block of data (depending on security mode). + * + * \param key Input AES key, length AES_KEY_LENGTH + * \param oper Security operations mask to perform (enum security_op) + * \param src Source data + * \param length Size of source data + * \param sig_dst Destination address for signature, AES_KEY_LENGTH bytes + */ +static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src, + u32 length, u8 *sig_dst) +{ + u32 num_aes_blocks; + u8 key_schedule[AES_EXPAND_KEY_LENGTH]; + + debug("encrypt_and_sign: length = %d\n", length); + debug_print_vector("AES key", AES_KEY_LENGTH, key); + + /* + * The only need for a key is for signing/checksum purposes, so + * if not encrypting, expand a key of 0s. + */ + aes_expand_key(oper & SECURITY_ENCRYPT ? key : zero_key, key_schedule); + + num_aes_blocks = (length + AES_KEY_LENGTH - 1) / AES_KEY_LENGTH; + + if (oper & SECURITY_ENCRYPT) { + /* Perform this in place, resulting in src being encrypted. */ + debug("encrypt_and_sign: begin encryption\n"); + encrypt_object(key_schedule, src, src, num_aes_blocks); + debug("encrypt_and_sign: end encryption\n"); + } + + if (oper & SECURITY_SIGN) { + /* encrypt the data, overwriting the result in signature. */ + debug("encrypt_and_sign: begin signing\n"); + sign_object(key, key_schedule, src, sig_dst, num_aes_blocks); + debug("encrypt_and_sign: end signing\n"); + } + + return 0; +} + +int sign_data_block(u8 *source, unsigned length, u8 *signature) +{ + return encrypt_and_sign(zero_key, SECURITY_SIGN, source, + length, signature); +} diff --git a/arch/arm/cpu/armv7/tegra2/crypto.h b/arch/arm/cpu/armv7/tegra2/crypto.h new file mode 100644 index 0000000000..aff67e77b0 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/crypto.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _CRYPTO_H_ +#define _CRYPTO_H_ + +/** + * Sign a block of data + * + * \param source Source data + * \param length Size of source data + * \param signature Destination address for signature, AES_KEY_LENGTH bytes + */ +int sign_data_block(u8 *source, unsigned length, u8 *signature); + +#endif /* #ifndef _CRYPTO_H_ */ diff --git a/arch/arm/cpu/armv7/tegra2/emc.c b/arch/arm/cpu/armv7/tegra2/emc.c new file mode 100644 index 0000000000..c0e5c565f1 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/emc.c @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <fdtdec.h> +#include <asm/io.h> +#include <asm/arch/ap20.h> +#include <asm/arch/apb_misc.h> +#include <asm/arch/clock.h> +#include <asm/arch/emc.h> +#include <asm/arch/tegra2.h> + +/* + * The EMC registers have shadow registers. When the EMC clock is updated + * in the clock controller, the shadow registers are copied to the active + * registers, allowing glitchless memory bus frequency changes. + * This function updates the shadow registers for a new clock frequency, + * and relies on the clock lock on the emc clock to avoid races between + * multiple frequency changes + */ + +/* + * This table defines the ordering of the registers provided to + * tegra_set_mmc() + * TODO: Convert to fdt version once available + */ +static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = { + 0x2c, /* RC */ + 0x30, /* RFC */ + 0x34, /* RAS */ + 0x38, /* RP */ + 0x3c, /* R2W */ + 0x40, /* W2R */ + 0x44, /* R2P */ + 0x48, /* W2P */ + 0x4c, /* RD_RCD */ + 0x50, /* WR_RCD */ + 0x54, /* RRD */ + 0x58, /* REXT */ + 0x5c, /* WDV */ + 0x60, /* QUSE */ + 0x64, /* QRST */ + 0x68, /* QSAFE */ + 0x6c, /* RDV */ + 0x70, /* REFRESH */ + 0x74, /* BURST_REFRESH_NUM */ + 0x78, /* PDEX2WR */ + 0x7c, /* PDEX2RD */ + 0x80, /* PCHG2PDEN */ + 0x84, /* ACT2PDEN */ + 0x88, /* AR2PDEN */ + 0x8c, /* RW2PDEN */ + 0x90, /* TXSR */ + 0x94, /* TCKE */ + 0x98, /* TFAW */ + 0x9c, /* TRPAB */ + 0xa0, /* TCLKSTABLE */ + 0xa4, /* TCLKSTOP */ + 0xa8, /* TREFBW */ + 0xac, /* QUSE_EXTRA */ + 0x114, /* FBIO_CFG6 */ + 0xb0, /* ODT_WRITE */ + 0xb4, /* ODT_READ */ + 0x104, /* FBIO_CFG5 */ + 0x2bc, /* CFG_DIG_DLL */ + 0x2c0, /* DLL_XFORM_DQS */ + 0x2c4, /* DLL_XFORM_QUSE */ + 0x2e0, /* ZCAL_REF_CNT */ + 0x2e4, /* ZCAL_WAIT_CNT */ + 0x2a8, /* AUTO_CAL_INTERVAL */ + 0x2d0, /* CFG_CLKTRIM_0 */ + 0x2d4, /* CFG_CLKTRIM_1 */ + 0x2d8, /* CFG_CLKTRIM_2 */ +}; + +struct emc_ctlr *emc_get_controller(const void *blob) +{ + fdt_addr_t addr; + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC); + if (node > 0) { + addr = fdtdec_get_addr(blob, node, "reg"); + if (addr != FDT_ADDR_T_NONE) + return (struct emc_ctlr *)addr; + } + return NULL; +} + +/* Error codes we use */ +enum { + ERR_NO_EMC_NODE = -10, + ERR_NO_EMC_REG, + ERR_NO_FREQ, + ERR_FREQ_NOT_FOUND, + ERR_BAD_REGS, + ERR_NO_RAM_CODE, + ERR_RAM_CODE_NOT_FOUND, +}; + +/** + * Find EMC tables for the given ram code. + * + * The tegra EMC binding has two options, one using the ram code and one not. + * We detect which is in use by looking for the nvidia,use-ram-code property. + * If this is not present, then the EMC tables are directly below 'node', + * otherwise we select the correct emc-tables subnode based on the 'ram_code' + * value. + * + * @param blob Device tree blob + * @param node EMC node (nvidia,tegra20-emc compatible string) + * @param ram_code RAM code to select (0-3, or -1 if unknown) + * @return 0 if ok, otherwise a -ve ERR_ code (see enum above) + */ +static int find_emc_tables(const void *blob, int node, int ram_code) +{ + int need_ram_code; + int depth; + int offset; + + /* If we are using RAM codes, scan through the tables for our code */ + need_ram_code = fdtdec_get_bool(blob, node, "nvidia,use-ram-code"); + if (!need_ram_code) + return node; + if (ram_code == -1) { + debug("%s: RAM code required but not supplied\n", __func__); + return ERR_NO_RAM_CODE; + } + + offset = node; + depth = 0; + do { + /* + * Sadly there is no compatible string so we cannot use + * fdtdec_next_compatible_subnode(). + */ + offset = fdt_next_node(blob, offset, &depth); + if (depth <= 0) + break; + + /* Make sure this is a direct subnode */ + if (depth != 1) + continue; + if (strcmp("emc-tables", fdt_get_name(blob, offset, NULL))) + continue; + + if (fdtdec_get_int(blob, offset, "nvidia,ram-code", -1) + == ram_code) + return offset; + } while (1); + + debug("%s: Could not find tables for RAM code %d\n", __func__, + ram_code); + return ERR_RAM_CODE_NOT_FOUND; +} + +/** + * Decode the EMC node of the device tree, returning a pointer to the emc + * controller and the table to be used for the given rate. + * + * @param blob Device tree blob + * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) + * @param emcp Returns address of EMC controller registers + * @param tablep Returns pointer to table to program into EMC. There are + * TEGRA_EMC_NUM_REGS entries, destined for offsets as per the + * emc_reg_addr array. + * @return 0 if ok, otherwise a -ve error code which will allow someone to + * figure out roughly what went wrong by looking at this code. + */ +static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp, + const u32 **tablep) +{ + struct apb_misc_pp_ctlr *pp = + (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE; + int ram_code; + int depth; + int node; + + ram_code = (readl(&pp->strapping_opt_a) & RAM_CODE_MASK) + >> RAM_CODE_SHIFT; + /* + * The EMC clock rate is twice the bus rate, and the bus rate is + * measured in kHz + */ + rate = rate / 2 / 1000; + + node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC); + if (node < 0) { + debug("%s: No EMC node found in FDT\n", __func__); + return ERR_NO_EMC_NODE; + } + *emcp = (struct emc_ctlr *)fdtdec_get_addr(blob, node, "reg"); + if (*emcp == (struct emc_ctlr *)FDT_ADDR_T_NONE) { + debug("%s: No EMC node reg property\n", __func__); + return ERR_NO_EMC_REG; + } + + /* Work out the parent node which contains our EMC tables */ + node = find_emc_tables(blob, node, ram_code & 3); + if (node < 0) + return node; + + depth = 0; + for (;;) { + int node_rate; + + node = fdtdec_next_compatible_subnode(blob, node, + COMPAT_NVIDIA_TEGRA20_EMC_TABLE, &depth); + if (node < 0) + break; + node_rate = fdtdec_get_int(blob, node, "clock-frequency", -1); + if (node_rate == -1) { + debug("%s: Missing clock-frequency\n", __func__); + return ERR_NO_FREQ; /* we expect this property */ + } + + if (node_rate == rate) + break; + } + if (node < 0) { + debug("%s: No node found for clock frequency %d\n", __func__, + rate); + return ERR_FREQ_NOT_FOUND; + } + + *tablep = fdtdec_locate_array(blob, node, "nvidia,emc-registers", + TEGRA_EMC_NUM_REGS); + if (!*tablep) { + debug("%s: node '%s' array missing / wrong size\n", __func__, + fdt_get_name(blob, node, NULL)); + return ERR_BAD_REGS; + } + + /* All seems well */ + return 0; +} + +int tegra_set_emc(const void *blob, unsigned rate) +{ + struct emc_ctlr *emc; + const u32 *table; + int err, i; + + err = decode_emc(blob, rate, &emc, &table); + if (err) { + debug("Warning: no valid EMC (%d), memory timings unset\n", + err); + return err; + } + + debug("%s: Table found, setting EMC values as follows:\n", __func__); + for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) { + u32 value = fdt32_to_cpu(table[i]); + u32 addr = (uintptr_t)emc + emc_reg_addr[i]; + + debug(" %#x: %#x\n", addr, value); + writel(value, addr); + } + + /* trigger emc with new settings */ + clock_adjust_periph_pll_div(PERIPH_ID_EMC, CLOCK_ID_MEMORY, + clock_get_rate(CLOCK_ID_MEMORY), NULL); + debug("EMC clock set to %lu\n", + clock_get_periph_rate(PERIPH_ID_EMC, CLOCK_ID_MEMORY)); + + return 0; +} diff --git a/arch/arm/cpu/armv7/tegra2/funcmux.c b/arch/arm/cpu/armv7/tegra2/funcmux.c index c1d2dfec5f..0ef7753021 100644 --- a/arch/arm/cpu/armv7/tegra2/funcmux.c +++ b/arch/arm/cpu/armv7/tegra2/funcmux.c @@ -169,6 +169,22 @@ int funcmux_select(enum periph_id id, int config) } break; + case PERIPH_ID_KBC: + if (config == FUNCMUX_DEFAULT) { + enum pmux_pingrp grp[] = {PINGRP_KBCA, PINGRP_KBCB, + PINGRP_KBCC, PINGRP_KBCD, PINGRP_KBCE, + PINGRP_KBCF}; + int i; + + for (i = 0; i < ARRAY_SIZE(grp); i++) { + pinmux_tristate_disable(grp[i]); + pinmux_set_func(grp[i], PMUX_FUNC_KBC); + pinmux_set_pullupdown(grp[i], PMUX_PULL_UP); + } + + break; + } + default: debug("%s: invalid periph_id %d", __func__, id); return -1; diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S index 6b866476ce..d117f23a62 100644 --- a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S +++ b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S @@ -25,10 +25,10 @@ #include <config.h> #include <version.h> +#include <linux/linkage.h> .align 5 -.global reset_cpu -reset_cpu: +ENTRY(reset_cpu) ldr r1, rstctl @ get addr for global reset @ reg ldr r3, [r1] @@ -39,3 +39,4 @@ _loop_forever: b _loop_forever rstctl: .word PRM_RSTCTRL +ENDPROC(reset_cpu) diff --git a/arch/arm/cpu/armv7/tegra2/pmu.c b/arch/arm/cpu/armv7/tegra2/pmu.c new file mode 100644 index 0000000000..46738023ff --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/pmu.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <tps6586x.h> +#include <asm/io.h> +#include <asm/arch/ap20.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/tegra_i2c.h> +#include <asm/arch/sys_proto.h> + +#define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */ +#define VDD_CPU_NOMINAL_T25 0x10 /* 1.125v */ + +#define VDD_CORE_NOMINAL_T20 0x16 /* 1.275v */ +#define VDD_CPU_NOMINAL_T20 0x0f /* 1.1v */ + +#define VDD_RELATION 0x02 /* 50mv */ +#define VDD_TRANSITION_STEP 0x06 /* 150mv */ +#define VDD_TRANSITION_RATE 0x06 /* 3.52mv/us */ + +int pmu_set_nominal(void) +{ + int core, cpu, bus; + + /* by default, the table has been filled with T25 settings */ + switch (tegra_get_chip_type()) { + case TEGRA_SOC_T20: + core = VDD_CORE_NOMINAL_T20; + cpu = VDD_CPU_NOMINAL_T20; + break; + case TEGRA_SOC_T25: + core = VDD_CORE_NOMINAL_T25; + cpu = VDD_CPU_NOMINAL_T25; + break; + default: + debug("%s: Unknown chip type\n", __func__); + return -1; + } + + bus = tegra_i2c_get_dvc_bus_num(); + if (bus == -1) { + debug("%s: Cannot find DVC I2C bus\n", __func__); + return -1; + } + tps6586x_init(bus); + tps6586x_set_pwm_mode(TPS6586X_PWM_SM1); + return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP, + VDD_TRANSITION_RATE, VDD_RELATION); +} diff --git a/arch/arm/cpu/armv7/tegra2/warmboot.c b/arch/arm/cpu/armv7/tegra2/warmboot.c new file mode 100644 index 0000000000..25d896888a --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/warmboot.c @@ -0,0 +1,386 @@ +/* + * (C) Copyright 2010 - 2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/ap20.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/pmc.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/fuse.h> +#include <asm/arch/emc.h> +#include <asm/arch/gp_padctrl.h> +#include <asm/arch/warmboot.h> +#include <asm/arch/sdram_param.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_TEGRA_CLOCK_SCALING +#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA2_LP0" +#endif + +/* + * This is the place in SRAM where the SDRAM parameters are stored. There + * are 4 blocks, one for each RAM code + */ +#define SDRAM_PARAMS_BASE (AP20_BASE_PA_SRAM + 0x188) + +/* TODO: If we later add support for the Misc GP controller, refactor this */ +union xm2cfga_reg { + struct { + u32 reserved0:2; + u32 hsm_en:1; + u32 reserved1:2; + u32 preemp_en:1; + u32 vref_en:1; + u32 reserved2:5; + u32 cal_drvdn:5; + u32 reserved3:3; + u32 cal_drvup:5; + u32 reserved4:3; + u32 cal_drvdn_slwr:2; + u32 cal_drvup_slwf:2; + }; + u32 word; +}; + +union xm2cfgd_reg { + struct { + u32 reserved0:2; + u32 hsm_en:1; + u32 schmt_en:1; + u32 lpmd:2; + u32 vref_en:1; + u32 reserved1:5; + u32 cal_drvdn:5; + u32 reserved2:3; + u32 cal_drvup:5; + u32 reserved3:3; + u32 cal_drvdn_slwr:2; + u32 cal_drvup_slwf:2; + }; + u32 word; +}; + +/* + * TODO: This register is not documented in the TRM yet. We could move this + * into the EMC and give it a proper interface, but not while it is + * undocumented. + */ +union fbio_spare_reg { + struct { + u32 reserved:24; + u32 cfg_wb0:8; + }; + u32 word; +}; + +/* We pack the resume information into these unions for later */ +union scratch2_reg { + struct { + u32 pllm_base_divm:5; + u32 pllm_base_divn:10; + u32 pllm_base_divp:3; + u32 pllm_misc_lfcon:4; + u32 pllm_misc_cpcon:4; + u32 gp_xm2cfga_padctrl_preemp:1; + u32 gp_xm2cfgd_padctrl_schmt:1; + u32 osc_ctrl_xobp:1; + u32 memory_type:3; + }; + u32 word; +}; + +union scratch4_reg { + struct { + u32 emc_clock_divider:8; + u32 pllm_stable_time:8; + u32 pllx_stable_time:8; + u32 emc_fbio_spare_cfg_wb0:8; + }; + u32 word; +}; + +union scratch24_reg { + struct { + u32 emc_auto_cal_wait:8; + u32 emc_pin_program_wait:8; + u32 warmboot_wait:8; + u32 reserved:8; + }; + u32 word; +}; + +int warmboot_save_sdram_params(void) +{ + u32 ram_code; + struct sdram_params sdram; + struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + struct apb_misc_gp_ctlr *gp = + (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE; + struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob); + union scratch2_reg scratch2; + union scratch4_reg scratch4; + union scratch24_reg scratch24; + union xm2cfga_reg xm2cfga; + union xm2cfgd_reg xm2cfgd; + union fbio_spare_reg fbio_spare; + + /* get ram code that is used as index to array sdram_params in BCT */ + ram_code = (readl(&pmt->pmt_strap_opt_a) >> + STRAP_OPT_A_RAM_CODE_SHIFT) & 3; + memcpy(&sdram, + (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code), + sizeof(sdram)); + + xm2cfga.word = readl(&gp->xm2cfga); + xm2cfgd.word = readl(&gp->xm2cfgd); + + scratch2.word = 0; + scratch2.osc_ctrl_xobp = clock_get_osc_bypass(); + + /* Get the memory PLL settings */ + { + u32 divm, divn, divp, cpcon, lfcon; + + if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp, + &cpcon, &lfcon)) + return -1; + scratch2.pllm_base_divm = divm; + scratch2.pllm_base_divn = divn; + scratch2.pllm_base_divp = divp; + scratch2.pllm_misc_cpcon = cpcon; + scratch2.pllm_misc_lfcon = lfcon; + } + + scratch2.gp_xm2cfga_padctrl_preemp = xm2cfga.preemp_en; + scratch2.gp_xm2cfgd_padctrl_schmt = xm2cfgd.schmt_en; + scratch2.memory_type = sdram.memory_type; + writel(scratch2.word, &pmc->pmc_scratch2); + + /* collect data from various sources for pmc_scratch4 */ + fbio_spare.word = readl(&emc->fbio_spare); + scratch4.word = 0; + scratch4.emc_fbio_spare_cfg_wb0 = fbio_spare.cfg_wb0; + scratch4.emc_clock_divider = sdram.emc_clock_divider; + scratch4.pllm_stable_time = -1; + scratch4.pllx_stable_time = -1; + writel(scratch4.word, &pmc->pmc_scratch4); + + /* collect various data from sdram for pmc_scratch24 */ + scratch24.word = 0; + scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait; + scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait; + scratch24.warmboot_wait = sdram.warm_boot_wait; + writel(scratch24.word, &pmc->pmc_scratch24); + + return 0; +} + +static u32 get_major_version(void) +{ + u32 major_id; + struct apb_misc_gp_ctlr *gp = + (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE; + + major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >> + HIDREV_MAJORPREV_SHIFT; + return major_id; +} + +static int is_production_mode_fuse_set(struct fuse_regs *fuse) +{ + return readl(&fuse->production_mode); +} + +static int is_odm_production_mode_fuse_set(struct fuse_regs *fuse) +{ + return readl(&fuse->security_mode); +} + +static int is_failure_analysis_mode(struct fuse_regs *fuse) +{ + return readl(&fuse->fa); +} + +static int ap20_is_odm_production_mode(void) +{ + struct fuse_regs *fuse = (struct fuse_regs *)TEGRA2_FUSE_BASE; + + if (!is_failure_analysis_mode(fuse) && + is_odm_production_mode_fuse_set(fuse)) + return 1; + else + return 0; +} + +static int ap20_is_production_mode(void) +{ + struct fuse_regs *fuse = (struct fuse_regs *)TEGRA2_FUSE_BASE; + + if (get_major_version() == 0) + return 1; + + if (!is_failure_analysis_mode(fuse) && + is_production_mode_fuse_set(fuse) && + !is_odm_production_mode_fuse_set(fuse)) + return 1; + else + return 0; +} + +static enum fuse_operating_mode fuse_get_operation_mode(void) +{ + u32 chip_id; + struct apb_misc_gp_ctlr *gp = + (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE; + + chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> + HIDREV_CHIPID_SHIFT; + if (chip_id == CHIPID_TEGRA2) { + if (ap20_is_odm_production_mode()) { + printf("!! odm_production_mode is not supported !!\n"); + return MODE_UNDEFINED; + } else + if (ap20_is_production_mode()) + return MODE_PRODUCTION; + else + return MODE_UNDEFINED; + } + return MODE_UNDEFINED; +} + +static void determine_crypto_options(int *is_encrypted, int *is_signed, + int *use_zero_key) +{ + switch (fuse_get_operation_mode()) { + case MODE_PRODUCTION: + *is_encrypted = 0; + *is_signed = 1; + *use_zero_key = 1; + break; + case MODE_UNDEFINED: + default: + *is_encrypted = 0; + *is_signed = 0; + *use_zero_key = 0; + break; + } +} + +static int sign_wb_code(u32 start, u32 length, int use_zero_key) +{ + int err; + u8 *source; /* Pointer to source */ + u8 *hash; + + /* Calculate AES block parameters. */ + source = (u8 *)(start + offsetof(struct wb_header, random_aes_block)); + length -= offsetof(struct wb_header, random_aes_block); + hash = (u8 *)(start + offsetof(struct wb_header, hash)); + err = sign_data_block(source, length, hash); + + return err; +} + +int warmboot_prepare_code(u32 seg_address, u32 seg_length) +{ + int err = 0; + u32 length; /* length of the signed/encrypt code */ + struct wb_header *dst_header; /* Pointer to dest WB header */ + int is_encrypted; /* Segment is encrypted */ + int is_signed; /* Segment is signed */ + int use_zero_key; /* Use key of all zeros */ + + /* Determine crypto options. */ + determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key); + + /* Get the actual code limits. */ + length = roundup(((u32)wb_end - (u32)wb_start), 16); + + /* + * The region specified by seg_address must be in SDRAM and must be + * nonzero in length. + */ + if (seg_length == 0 || seg_address < NV_PA_SDRAM_BASE || + seg_address + seg_length >= NV_PA_SDRAM_BASE + gd->ram_size) { + err = -EFAULT; + goto fail; + } + + /* Things must be 16-byte aligned. */ + if ((seg_length & 0xF) || (seg_address & 0xF)) { + err = -EINVAL; + goto fail; + } + + /* Will the code fit? (destination includes wb_header + wb code) */ + if (seg_length < (length + sizeof(struct wb_header))) { + err = -EINVAL; + goto fail; + } + + dst_header = (struct wb_header *)seg_address; + memset((char *)dst_header, 0, sizeof(struct wb_header)); + + /* Populate the random_aes_block as requested. */ + { + u32 *aes_block = (u32 *)&(dst_header->random_aes_block); + u32 *end = (u32 *)(((u32)aes_block) + + sizeof(dst_header->random_aes_block)); + + do { + *aes_block++ = 0; + } while (aes_block < end); + } + + /* Populate the header. */ + dst_header->length_insecure = length + sizeof(struct wb_header); + dst_header->length_secure = length + sizeof(struct wb_header); + dst_header->destination = AP20_WB_RUN_ADDRESS; + dst_header->entry_point = AP20_WB_RUN_ADDRESS; + dst_header->code_length = length; + + if (is_encrypted) { + printf("!!!! Encryption is not supported !!!!\n"); + dst_header->length_insecure = 0; + err = -EACCES; + goto fail; + } else + /* copy the wb code directly following dst_header. */ + memcpy((char *)(dst_header+1), (char *)wb_start, length); + + if (is_signed) + err = sign_wb_code(seg_address, dst_header->length_insecure, + use_zero_key); + +fail: + if (err) + printf("Warning: warmboot code copy failed (error=%d)\n", err); + + return err; +} diff --git a/arch/arm/cpu/armv7/tegra2/warmboot_avp.c b/arch/arm/cpu/armv7/tegra2/warmboot_avp.c new file mode 100644 index 0000000000..70bcd8e5f3 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/warmboot_avp.c @@ -0,0 +1,250 @@ +/* + * (C) Copyright 2010 - 2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ap20.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/flow.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/pmc.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/warmboot.h> +#include "warmboot_avp.h" + +#define DEBUG_RESET_CORESIGHT + +void wb_start(void) +{ + struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + union osc_ctrl_reg osc_ctrl; + union pllx_base_reg pllx_base; + union pllx_misc_reg pllx_misc; + union scratch3_reg scratch3; + u32 reg; + + /* enable JTAG & TBE */ + writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl); + + /* Are we running where we're supposed to be? */ + asm volatile ( + "adr %0, wb_start;" /* reg: wb_start address */ + : "=r"(reg) /* output */ + /* no input, no clobber list */ + ); + + if (reg != AP20_WB_RUN_ADDRESS) + goto do_reset; + + /* Are we running with AVP? */ + if (readl(NV_PA_PG_UP_BASE + PG_UP_TAG_0) != PG_UP_TAG_AVP) + goto do_reset; + +#ifdef DEBUG_RESET_CORESIGHT + /* Assert CoreSight reset */ + reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); + reg |= SWR_CSITE_RST; + writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]); +#endif + + /* TODO: Set the drive strength - maybe make this a board parameter? */ + osc_ctrl.word = readl(&clkrst->crc_osc_ctrl); + osc_ctrl.xofs = 4; + osc_ctrl.xoe = 1; + writel(osc_ctrl.word, &clkrst->crc_osc_ctrl); + + /* Power up the CPU complex if necessary */ + if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) { + reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START; + writel(reg, &pmc->pmc_pwrgate_toggle); + while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) + ; + } + + /* Remove the I/O clamps from the CPU power partition. */ + reg = readl(&pmc->pmc_remove_clamping); + reg |= CPU_CLMP; + writel(reg, &pmc->pmc_remove_clamping); + + reg = EVENT_ZERO_VAL_20 | EVENT_MSEC | EVENT_MODE_STOP; + writel(reg, &flow->halt_cop_events); + + /* Assert CPU complex reset */ + reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]); + reg |= CPU_RST; + writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]); + + /* Hold both CPUs in reset */ + reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_CPURESET1 | CPU_CMPLX_DERESET0 | + CPU_CMPLX_DERESET1 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DBGRESET1; + writel(reg, &clkrst->crc_cpu_cmplx_set); + + /* Halt CPU1 at the flow controller for uni-processor configurations */ + writel(EVENT_MODE_STOP, &flow->halt_cpu1_events); + + /* + * Set the CPU reset vector. SCRATCH41 contains the physical + * address of the CPU-side restoration code. + */ + reg = readl(&pmc->pmc_scratch41); + writel(reg, EXCEP_VECTOR_CPU_RESET_VECTOR); + + /* Select CPU complex clock source */ + writel(CCLK_PLLP_BURST_POLICY, &clkrst->crc_cclk_brst_pol); + + /* Start the CPU0 clock and stop the CPU1 clock */ + reg = CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 | CPU_CMPLX_CPU0_CLK_STP_RUN | + CPU_CMPLX_CPU1_CLK_STP_STOP; + writel(reg, &clkrst->crc_clk_cpu_cmplx); + + /* Enable the CPU complex clock */ + reg = readl(&clkrst->crc_clk_out_enb[TEGRA_DEV_L]); + reg |= CLK_ENB_CPU; + writel(reg, &clkrst->crc_clk_out_enb[TEGRA_DEV_L]); + + /* Make sure the resets were held for at least 2 microseconds */ + reg = readl(TIMER_USEC_CNTR); + while (readl(TIMER_USEC_CNTR) <= (reg + 2)) + ; + +#ifdef DEBUG_RESET_CORESIGHT + /* + * De-assert CoreSight reset. + * NOTE: We're leaving the CoreSight clock on the oscillator for + * now. It will be restored to its original clock source + * when the CPU-side restoration code runs. + */ + reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); + reg &= ~SWR_CSITE_RST; + writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]); +#endif + + /* Unlock the CPU CoreSight interfaces */ + reg = 0xC5ACCE55; + writel(reg, CSITE_CPU_DBG0_LAR); + writel(reg, CSITE_CPU_DBG1_LAR); + + /* + * Sample the microsecond timestamp again. This is the time we must + * use when returning from LP0 for PLL stabilization delays. + */ + reg = readl(TIMER_USEC_CNTR); + writel(reg, &pmc->pmc_scratch1); + + pllx_base.word = 0; + pllx_misc.word = 0; + scratch3.word = readl(&pmc->pmc_scratch3); + + /* Get the OSC. For 19.2 MHz, use 19 to make the calculations easier */ + reg = (readl(TIMER_USEC_CFG) & USEC_CFG_DIVISOR_MASK) + 1; + + /* + * According to the TRM, for 19.2MHz OSC, the USEC_DIVISOR is 0x5f, and + * USEC_DIVIDEND is 0x04. So, if USEC_DIVISOR > 26, OSC is 19.2 MHz. + * + * reg is used to calculate the pllx freq, which is used to determine if + * to set dccon or not. + */ + if (reg > 26) + reg = 19; + + /* PLLX_BASE.PLLX_DIVM */ + if (scratch3.pllx_base_divm == reg) + reg = 0; + else + reg = 1; + + /* PLLX_BASE.PLLX_DIVN */ + pllx_base.divn = scratch3.pllx_base_divn; + reg = scratch3.pllx_base_divn << reg; + + /* PLLX_BASE.PLLX_DIVP */ + pllx_base.divp = scratch3.pllx_base_divp; + reg = reg >> scratch3.pllx_base_divp; + + pllx_base.bypass = 1; + + /* PLLX_MISC_DCCON must be set for pllx frequency > 600 MHz. */ + if (reg > 600) + pllx_misc.dccon = 1; + + /* PLLX_MISC_LFCON */ + pllx_misc.lfcon = scratch3.pllx_misc_lfcon; + + /* PLLX_MISC_CPCON */ + pllx_misc.cpcon = scratch3.pllx_misc_cpcon; + + writel(pllx_misc.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_misc); + writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); + + pllx_base.enable = 1; + writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); + pllx_base.bypass = 0; + writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); + + writel(0, flow->halt_cpu_events); + + reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DERESET0; + writel(reg, &clkrst->crc_cpu_cmplx_clr); + + reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE | + PLLM_OUT1_RATIO_VAL_8; + writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out); + + reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 | + SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 | + SCLK_SYS_STATE_IDLE; + writel(reg, &clkrst->crc_sclk_brst_pol); + + /* avp_resume: no return after the write */ + reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]); + reg &= ~CPU_RST; + writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]); + + /* avp_halt: */ +avp_halt: + reg = EVENT_MODE_STOP | EVENT_JTAG; + writel(reg, flow->halt_cop_events); + goto avp_halt; + +do_reset: + /* + * Execution comes here if something goes wrong. The chip is reset and + * a cold boot is performed. + */ + writel(SWR_TRIG_SYS_RST, &clkrst->crc_rst_dev[TEGRA_DEV_L]); + goto do_reset; +} + +/* + * wb_end() is a dummy function, and must be directly following wb_start(), + * and is used to calculate the size of wb_start(). + */ +void wb_end(void) +{ +} diff --git a/arch/arm/cpu/armv7/tegra2/warmboot_avp.h b/arch/arm/cpu/armv7/tegra2/warmboot_avp.h new file mode 100644 index 0000000000..4b71c07843 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/warmboot_avp.h @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2010, 2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _WARMBOOT_AVP_H_ +#define _WARMBOOT_AVP_H_ + +#define TEGRA_DEV_L 0 +#define TEGRA_DEV_H 1 +#define TEGRA_DEV_U 2 + +#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) +#define SIMPLE_PLLE (CLOCK_ID_EPCI - CLOCK_ID_FIRST_SIMPLE) + +#define TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) +#define TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) + +#define USEC_CFG_DIVISOR_MASK 0xffff + +#define CONFIG_CTL_TBE (1 << 7) +#define CONFIG_CTL_JTAG (1 << 6) + +#define CPU_RST (1 << 0) +#define CLK_ENB_CPU (1 << 0) +#define SWR_TRIG_SYS_RST (1 << 2) +#define SWR_CSITE_RST (1 << 9) + +#define PWRGATE_STATUS_CPU (1 << 0) +#define PWRGATE_TOGGLE_PARTID_CPU (0 << 0) +#define PWRGATE_TOGGLE_START (1 << 8) + +#define CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 (3 << 0) +#define CPU_CMPLX_CPU0_CLK_STP_STOP (1 << 8) +#define CPU_CMPLX_CPU0_CLK_STP_RUN (0 << 8) +#define CPU_CMPLX_CPU1_CLK_STP_STOP (1 << 9) +#define CPU_CMPLX_CPU1_CLK_STP_RUN (0 << 9) + +#define CPU_CMPLX_CPURESET0 (1 << 0) +#define CPU_CMPLX_CPURESET1 (1 << 1) +#define CPU_CMPLX_DERESET0 (1 << 4) +#define CPU_CMPLX_DERESET1 (1 << 5) +#define CPU_CMPLX_DBGRESET0 (1 << 12) +#define CPU_CMPLX_DBGRESET1 (1 << 13) + +#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) +#define PLLM_OUT1_CLKEN_ENABLE (1 << 1) +#define PLLM_OUT1_RATIO_VAL_8 (8 << 8) + +#define SCLK_SYS_STATE_IDLE (1 << 28) +#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12) +#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8) +#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4) +#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0) + +#define EVENT_ZERO_VAL_20 (20 << 0) +#define EVENT_MSEC (1 << 24) +#define EVENT_JTAG (1 << 28) +#define EVENT_MODE_STOP (2 << 29) + +#define CCLK_PLLP_BURST_POLICY 0x20004444 + +#endif diff --git a/arch/arm/cpu/armv7/u8500/lowlevel.S b/arch/arm/cpu/armv7/u8500/lowlevel.S index cffdfd1381..289cfb0779 100644 --- a/arch/arm/cpu/armv7/u8500/lowlevel.S +++ b/arch/arm/cpu/armv7/u8500/lowlevel.S @@ -20,16 +20,17 @@ */ #include <config.h> +#include <linux/linkage.h> -.globl lowlevel_init -lowlevel_init: +ENTRY(lowlevel_init) mov pc, lr +ENDPROC(lowlevel_init) .align 5 -.globl reset_cpu -reset_cpu: +ENTRY(reset_cpu) ldr r0, =CFG_PRCMU_BASE ldr r1, =0x1 str r1, [r0, #0x228] _loop_forever: b _loop_forever +ENDPROC(reset_cpu) diff --git a/arch/arm/cpu/ixp/npe/npe.c b/arch/arm/cpu/ixp/npe/npe.c index f0e02bf7d9..1fe3a95eaf 100644 --- a/arch/arm/cpu/ixp/npe/npe.c +++ b/arch/arm/cpu/ixp/npe/npe.c @@ -518,7 +518,7 @@ static void npe_halt(struct eth_device *dev) } -static int npe_send(struct eth_device *dev, volatile void *packet, int len) +static int npe_send(struct eth_device *dev, void *packet, int len) { struct npe *p_npe = (struct npe *)dev->priv; u8 *dest; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index d5ca02c5f5..f95be58135 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -193,4 +193,15 @@ clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ }; + emc@7000f400 { + #address-cells = < 1 >; + #size-cells = < 0 >; + compatible = "nvidia,tegra20-emc"; + reg = <0x7000f400 0x200>; + }; + + kbc@7000e200 { + compatible = "nvidia,tegra20-kbc"; + reg = <0x7000e200 0x0078>; + }; }; diff --git a/arch/arm/include/asm/arch b/arch/arm/include/asm/arch new file mode 120000 index 0000000000..802cf12ac7 --- /dev/null +++ b/arch/arm/include/asm/arch @@ -0,0 +1 @@ +arch-rda
\ No newline at end of file diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 943526b94a..26cc300e70 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -159,6 +159,6 @@ typedef struct hsmmc { #define mmc_reg_out(addr, mask, val)\ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) -int omap_mmc_init(int dev_index); +int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index ff0f6415d8..637fb4bd14 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -33,5 +33,8 @@ unsigned long get_arm_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div); +unsigned long get_lcd_clk(void); +void set_lcd_clk(void); +void set_mipi_clk(void); #endif diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 89f2c2e3e9..ac4ddc7354 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -29,6 +29,7 @@ /* EXYNOS4 */ #define EXYNOS4_GPIO_PART3_BASE 0x03860000 #define EXYNOS4_PRO_ID 0x10000000 +#define EXYNOS4_SYSREG_BASE 0x10010000 #define EXYNOS4_POWER_BASE 0x10020000 #define EXYNOS4_SWRESET 0x10020400 #define EXYNOS4_CLOCK_BASE 0x10030000 @@ -40,6 +41,7 @@ #define EXYNOS4_GPIO_PART2_BASE 0x11000000 #define EXYNOS4_GPIO_PART1_BASE 0x11400000 #define EXYNOS4_FIMD_BASE 0x11C00000 +#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 #define EXYNOS4_USBOTG_BASE 0x12480000 #define EXYNOS4_MMC_BASE 0x12510000 #define EXYNOS4_SROMC_BASE 0x12570000 @@ -65,6 +67,7 @@ #define EXYNOS5_GPIO_PART3_BASE 0x10D10000 #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 #define EXYNOS5_GPIO_PART1_BASE 0x11400000 +#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 #define EXYNOS5_MMC_BASE 0x12200000 #define EXYNOS5_SROMC_BASE 0x12250000 #define EXYNOS5_USBOTG_BASE 0x12480000 @@ -127,7 +130,9 @@ static inline unsigned int samsung_get_base_##device(void) \ SAMSUNG_BASE(adc, ADC_BASE) SAMSUNG_BASE(clock, CLOCK_BASE) +SAMSUNG_BASE(sysreg, SYSREG_BASE) SAMSUNG_BASE(fimd, FIMD_BASE) +SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE) SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE) diff --git a/arch/arm/include/asm/arch-exynos/dsim.h b/arch/arm/include/asm/arch-exynos/dsim.h new file mode 100644 index 0000000000..e148aca2e8 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/dsim.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: InKi Dae <inki.dae@samsung.com> + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_DSIM_H_ +#define __ASM_ARM_ARCH_DSIM_H_ + +#ifndef __ASSEMBLY__ + +struct exynos_mipi_dsim { + unsigned int status; + unsigned int swrst; + unsigned int clkctrl; + unsigned int timeout; + unsigned int config; + unsigned int escmode; + unsigned int mdresol; + unsigned int mvporch; + unsigned int mhporch; + unsigned int msync; + unsigned int sdresol; + unsigned int intsrc; + unsigned int intmsk; + unsigned int pkthdr; + unsigned int payload; + unsigned int rxfifo; + unsigned int fifothld; + unsigned int fifoctrl; + unsigned int memacchr; + unsigned int pllctrl; + unsigned int plltmr; + unsigned int phyacchr; + unsigned int phyacchr1; +}; + +#endif /* __ASSEMBLY__ */ + +/* + * Bit Definitions + */ +/* DSIM_STATUS */ +#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) +#define DSIM_STOP_STATE_CLK (1 << 8) +#define DSIM_TX_READY_HS_CLK (1 << 10) +#define DSIM_PLL_STABLE (1 << 31) + +/* DSIM_SWRST */ +#define DSIM_FUNCRST (1 << 16) +#define DSIM_SWRST (1 << 0) + +/* EXYNOS_DSIM_TIMEOUT */ +#define DSIM_LPDR_TOUT_SHIFT (0) +#define DSIM_BTA_TOUT_SHIFT (16) + +/* EXYNOS_DSIM_CLKCTRL */ +#define DSIM_LANE_ESC_CLKEN_SHIFT (19) +#define DSIM_BYTE_CLKEN_SHIFT (24) +#define DSIM_BYTE_CLK_SRC_SHIFT (25) +#define DSIM_PLL_BYPASS_SHIFT (27) +#define DSIM_ESC_CLKEN_SHIFT (28) +#define DSIM_TX_REQUEST_HSCLK_SHIFT (31) +#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << \ + DSIM_LANE_ESC_CLKEN_SHIFT) +#define DSIM_BYTE_CLK_ENABLE (1 << DSIM_BYTE_CLKEN_SHIFT) +#define DSIM_BYTE_CLK_DISABLE (0 << DSIM_BYTE_CLKEN_SHIFT) +#define DSIM_PLL_BYPASS_EXTERNAL (1 << DSIM_PLL_BYPASS_SHIFT) +#define DSIM_ESC_CLKEN_ENABLE (1 << DSIM_ESC_CLKEN_SHIFT) +#define DSIM_ESC_CLKEN_DISABLE (0 << DSIM_ESC_CLKEN_SHIFT) + +/* EXYNOS_DSIM_CONFIG */ +#define DSIM_NUM_OF_DATALANE_SHIFT (5) +#define DSIM_SUBPIX_SHIFT (8) +#define DSIM_MAINPIX_SHIFT (12) +#define DSIM_SUBVC_SHIFT (16) +#define DSIM_MAINVC_SHIFT (18) +#define DSIM_HSA_MODE_SHIFT (20) +#define DSIM_HBP_MODE_SHIFT (21) +#define DSIM_HFP_MODE_SHIFT (22) +#define DSIM_HSE_MODE_SHIFT (23) +#define DSIM_AUTO_MODE_SHIFT (24) +#define DSIM_VIDEO_MODE_SHIFT (25) +#define DSIM_BURST_MODE_SHIFT (26) +#define DSIM_EOT_PACKET_SHIFT (28) +#define DSIM_AUTO_FLUSH_SHIFT (29) +#define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0) + +#define DSIM_NUM_OF_DATA_LANE(x) ((x) << DSIM_NUM_OF_DATALANE_SHIFT) + +/* EXYNOS_DSIM_ESCMODE */ +#define DSIM_TX_LPDT_SHIFT (6) +#define DSIM_CMD_LPDT_SHIFT (7) +#define DSIM_TX_LPDT_LP (1 << DSIM_TX_LPDT_SHIFT) +#define DSIM_CMD_LPDT_LP (1 << DSIM_CMD_LPDT_SHIFT) +#define DSIM_STOP_STATE_CNT_SHIFT (21) +#define DSIM_FORCE_STOP_STATE_SHIFT (20) + +/* EXYNOS_DSIM_MDRESOL */ +#define DSIM_MAIN_STAND_BY (1 << 31) +#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) +#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0) + +/* EXYNOS_DSIM_MVPORCH */ +#define DSIM_CMD_ALLOW_SHIFT (28) +#define DSIM_STABLE_VFP_SHIFT (16) +#define DSIM_MAIN_VBP_SHIFT (0) +#define DSIM_CMD_ALLOW_MASK (0xf << DSIM_CMD_ALLOW_SHIFT) +#define DSIM_STABLE_VFP_MASK (0x7ff << DSIM_STABLE_VFP_SHIFT) +#define DSIM_MAIN_VBP_MASK (0x7ff << DSIM_MAIN_VBP_SHIFT) + +/* EXYNOS_DSIM_MHPORCH */ +#define DSIM_MAIN_HFP_SHIFT (16) +#define DSIM_MAIN_HBP_SHIFT (0) +#define DSIM_MAIN_HFP_MASK ((0xffff) << DSIM_MAIN_HFP_SHIFT) +#define DSIM_MAIN_HBP_MASK ((0xffff) << DSIM_MAIN_HBP_SHIFT) + +/* EXYNOS_DSIM_MSYNC */ +#define DSIM_MAIN_VSA_SHIFT (22) +#define DSIM_MAIN_HSA_SHIFT (0) +#define DSIM_MAIN_VSA_MASK ((0x3ff) << DSIM_MAIN_VSA_SHIFT) +#define DSIM_MAIN_HSA_MASK ((0xffff) << DSIM_MAIN_HSA_SHIFT) + +/* EXYNOS_DSIM_SDRESOL */ +#define DSIM_SUB_STANDY_SHIFT (31) +#define DSIM_SUB_VRESOL_SHIFT (16) +#define DSIM_SUB_HRESOL_SHIFT (0) +#define DSIM_SUB_STANDY_MASK ((0x1) << DSIM_SUB_STANDY_SHIFT) +#define DSIM_SUB_VRESOL_MASK ((0x7ff) << DSIM_SUB_VRESOL_SHIFT) +#define DSIM_SUB_HRESOL_MASK ((0x7ff) << DSIM_SUB_HRESOL_SHIFT) + +/* EXYNOS_DSIM_INTSRC */ +#define INTSRC_FRAME_DONE (1 << 24) +#define INTSRC_PLL_STABLE (1 << 31) +#define INTSRC_SWRST_RELEASE (1 << 30) + +/* EXYNOS_DSIM_INTMSK */ +#define INTMSK_FRAME_DONE (1 << 24) + +/* EXYNOS_DSIM_FIFOCTRL */ +#define SFR_HEADER_EMPTY (1 << 22) + +/* EXYNOS_DSIM_PKTHDR */ +#define DSIM_PKTHDR_DI(x) (((x) & 0x3f) << 0) +#define DSIM_PKTHDR_DAT0(x) ((x) << 8) +#define DSIM_PKTHDR_DAT1(x) ((x) << 16) + +/* EXYNOS_DSIM_PHYACCHR */ +#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) +#define DSIM_AFC_CTL_SHIFT (5) +#define DSIM_AFC_EN (1 << 14) + +/* EXYNOS_DSIM_PHYACCHR1 */ +#define DSIM_DPDN_SWAP_DATA_SHIFT (0) + +/* EXYNOS_DSIM_PLLCTRL */ +#define DSIM_SCALER_SHIFT (1) +#define DSIM_MAIN_SHIFT (4) +#define DSIM_PREDIV_SHIFT (13) +#define DSIM_PRECTRL_SHIFT (20) +#define DSIM_PLL_EN_SHIFT (23) +#define DSIM_FREQ_BAND_SHIFT (24) +#define DSIM_ZEROCTRL_SHIFT (28) + +#endif diff --git a/arch/arm/include/asm/arch-exynos/ehci-s5p.h b/arch/arm/include/asm/arch-exynos/ehci-s5p.h new file mode 100644 index 0000000000..68feb85ede --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/ehci-s5p.h @@ -0,0 +1,66 @@ +/* + * SAMSUNG S5P USB HOST EHCI Controller + * + * Copyright (C) 2012 Samsung Electronics Co.Ltd + * Vivek Gautam <gautam.vivek@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ +#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ + +#define CLK_24MHZ 5 + +#define HOST_CTRL0_PHYSWRSTALL (1 << 31) +#define HOST_CTRL0_COMMONON_N (1 << 9) +#define HOST_CTRL0_SIDDQ (1 << 6) +#define HOST_CTRL0_FORCESLEEP (1 << 5) +#define HOST_CTRL0_FORCESUSPEND (1 << 4) +#define HOST_CTRL0_WORDINTERFACE (1 << 3) +#define HOST_CTRL0_UTMISWRST (1 << 2) +#define HOST_CTRL0_LINKSWRST (1 << 1) +#define HOST_CTRL0_PHYSWRST (1 << 0) + +#define HOST_CTRL0_FSEL_MASK (7 << 16) + +#define EHCICTRL_ENAINCRXALIGN (1 << 29) +#define EHCICTRL_ENAINCR4 (1 << 28) +#define EHCICTRL_ENAINCR8 (1 << 27) +#define EHCICTRL_ENAINCR16 (1 << 26) + +/* Register map for PHY control */ +struct s5p_usb_phy { + unsigned int usbphyctrl0; + unsigned int usbphytune0; + unsigned int reserved1[2]; + unsigned int hsicphyctrl1; + unsigned int hsicphytune1; + unsigned int reserved2[2]; + unsigned int hsicphyctrl2; + unsigned int hsicphytune2; + unsigned int reserved3[2]; + unsigned int ehcictrl; + unsigned int ohcictrl; + unsigned int usbotgsys; + unsigned int reserved4; + unsigned int usbotgtune; +}; + +/* Switch on the VBUS power. */ +int board_usb_vbus_init(void); + +#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */ diff --git a/arch/arm/include/asm/arch-exynos/fb.h b/arch/arm/include/asm/arch-exynos/fb.h new file mode 100644 index 0000000000..b10b0da07e --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/fb.h @@ -0,0 +1,446 @@ +/* + * (C) Copyright 2012 Samsung Electronics + * Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * aint with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_FB_H_ +#define __ASM_ARM_ARCH_FB_H_ + +#ifndef __ASSEMBLY__ +struct exynos4_fb { + unsigned int vidcon0; + unsigned int vidcon1; + unsigned int vidcon2; + unsigned int vidcon3; + unsigned int vidtcon0; + unsigned int vidtcon1; + unsigned int vidtcon2; + unsigned int vidtcon3; + unsigned int wincon0; + unsigned int wincon1; + unsigned int wincon2; + unsigned int wincon3; + unsigned int wincon4; + + unsigned int winshmap; + unsigned int res1; + + unsigned int winchmap2; + unsigned int vidosd0a; + unsigned int vidosd0b; + unsigned int vidosd0c; + unsigned int res2; + + unsigned int vidosd1a; + unsigned int vidosd1b; + unsigned int vidosd1c; + unsigned int vidosd1d; + + unsigned int vidosd2a; + unsigned int vidosd2b; + unsigned int vidosd2c; + unsigned int vidosd2d; + + unsigned int vidosd3a; + unsigned int vidosd3b; + unsigned int vidosd3c; + unsigned int res3; + + unsigned int vidosd4a; + unsigned int vidosd4b; + unsigned int vidosd4c; + unsigned int res4[5]; + + unsigned int vidw00add0b0; + unsigned int vidw00add0b1; + unsigned int vidw01add0b0; + unsigned int vidw01add0b1; + + unsigned int vidw02add0b0; + unsigned int vidw02add0b1; + unsigned int vidw03add0b0; + unsigned int vidw03add0b1; + unsigned int vidw04add0b0; + unsigned int vidw04add0b1; + unsigned int res5[2]; + + unsigned int vidw00add1b0; + unsigned int vidw00add1b1; + unsigned int vidw01add1b0; + unsigned int vidw01add1b1; + + unsigned int vidw02add1b0; + unsigned int vidw02add1b1; + unsigned int vidw03add1b0; + unsigned int vidw03add1b1; + + unsigned int vidw04add1b0; + unsigned int vidw04add1b1; + unsigned int res7[2]; + + unsigned int vidw00add2; + unsigned int vidw01add2; + unsigned int vidw02add2; + unsigned int vidw03add2; + unsigned int vidw04add2; + unsigned int res8[7]; + + unsigned int vidintcon0; + unsigned int vidintcon1; + unsigned int res9[1]; + + unsigned int w1keycon0; + unsigned int w1keycon1; + unsigned int w2keycon0; + unsigned int w2keycon1; + unsigned int w3keycon0; + unsigned int w3keycon1; + unsigned int w4keycon0; + unsigned int w4keycon1; + + unsigned int w1keyalpha; + unsigned int w2keyalpha; + unsigned int w3keyalpha; + unsigned int w4keyalpha; + + unsigned int dithmode; + unsigned int res10[2]; + + unsigned int win0map; + unsigned int win1map; + unsigned int win2map; + unsigned int win3map; + unsigned int win4map; + unsigned int res11[1]; + + unsigned int wpalcon_h; + unsigned int wpalcon_l; + + unsigned int trigcon; + unsigned int res12[2]; + + unsigned int i80ifcona0; + unsigned int i80ifcona1; + unsigned int i80ifconb0; + unsigned int i80ifconb1; + + unsigned int colorgaincon; + unsigned int res13[2]; + + unsigned int ldi_cmdcon0; + unsigned int ldi_cmdcon1; + unsigned int res14[1]; + + /* To be updated */ + + unsigned char res15[156]; + unsigned int dualrgb; +}; +#endif + +/* + * Register offsets +*/ +#define EXYNOS_WINCON(x) (x * 0x04) +#define EXYNOS_VIDOSD(x) (x * 0x10) +#define EXYNOS_BUFFER_OFFSET(x) (x * 0x08) +#define EXYNOS_BUFFER_SIZE(x) (x * 0x04) + +/* + * Bit Definitions +*/ + +/* VIDCON0 */ +#define EXYNOS_VIDCON0_DSI_DISABLE (0 << 30) +#define EXYNOS_VIDCON0_DSI_ENABLE (1 << 30) +#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE (0 << 29) +#define EXYNOS_VIDCON0_SCAN_INTERLACE (1 << 29) +#define EXYNOS_VIDCON0_SCAN_MASK (1 << 29) +#define EXYNOS_VIDCON0_VIDOUT_RGB (0 << 26) +#define EXYNOS_VIDCON0_VIDOUT_ITU (1 << 26) +#define EXYNOS_VIDCON0_VIDOUT_I80LDI0 (2 << 26) +#define EXYNOS_VIDCON0_VIDOUT_I80LDI1 (3 << 26) +#define EXYNOS_VIDCON0_VIDOUT_WB_RGB (4 << 26) +#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0 (6 << 26) +#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1 (7 << 26) +#define EXYNOS_VIDCON0_VIDOUT_MASK (7 << 26) +#define EXYNOS_VIDCON0_PNRMODE_RGB_P (0 << 17) +#define EXYNOS_VIDCON0_PNRMODE_BGR_P (1 << 17) +#define EXYNOS_VIDCON0_PNRMODE_RGB_S (2 << 17) +#define EXYNOS_VIDCON0_PNRMODE_BGR_S (3 << 17) +#define EXYNOS_VIDCON0_PNRMODE_MASK (3 << 17) +#define EXYNOS_VIDCON0_PNRMODE_SHIFT (17) +#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS (0 << 16) +#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME (1 << 16) +#define EXYNOS_VIDCON0_CLKVALUP_MASK (1 << 16) +#define EXYNOS_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6) +#define EXYNOS_VIDCON0_VCLKEN_NORMAL (0 << 5) +#define EXYNOS_VIDCON0_VCLKEN_FREERUN (1 << 5) +#define EXYNOS_VIDCON0_VCLKEN_MASK (1 << 5) +#define EXYNOS_VIDCON0_CLKDIR_DIRECTED (0 << 4) +#define EXYNOS_VIDCON0_CLKDIR_DIVIDED (1 << 4) +#define EXYNOS_VIDCON0_CLKDIR_MASK (1 << 4) +#define EXYNOS_VIDCON0_CLKSEL_HCLK (0 << 2) +#define EXYNOS_VIDCON0_CLKSEL_SCLK (1 << 2) +#define EXYNOS_VIDCON0_CLKSEL_MASK (1 << 2) +#define EXYNOS_VIDCON0_ENVID_ENABLE (1 << 1) +#define EXYNOS_VIDCON0_ENVID_DISABLE (0 << 1) +#define EXYNOS_VIDCON0_ENVID_F_ENABLE (1 << 0) +#define EXYNOS_VIDCON0_ENVID_F_DISABLE (0 << 0) + +/* VIDCON1 */ +#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE (0 << 7) +#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE (1 << 7) +#define EXYNOS_VIDCON1_IHSYNC_NORMAL (0 << 6) +#define EXYNOS_VIDCON1_IHSYNC_INVERT (1 << 6) +#define EXYNOS_VIDCON1_IVSYNC_NORMAL (0 << 5) +#define EXYNOS_VIDCON1_IVSYNC_INVERT (1 << 5) +#define EXYNOS_VIDCON1_IVDEN_NORMAL (0 << 4) +#define EXYNOS_VIDCON1_IVDEN_INVERT (1 << 4) + +/* VIDCON2 */ +#define EXYNOS_VIDCON2_EN601_DISABLE (0 << 23) +#define EXYNOS_VIDCON2_EN601_ENABLE (1 << 23) +#define EXYNOS_VIDCON2_EN601_MASK (1 << 23) +#define EXYNOS_VIDCON2_WB_DISABLE (0 << 15) +#define EXYNOS_VIDCON2_WB_ENABLE (1 << 15) +#define EXYNOS_VIDCON2_WB_MASK (1 << 15) +#define EXYNOS_VIDCON2_TVFORMATSEL_HW (0 << 14) +#define EXYNOS_VIDCON2_TVFORMATSEL_SW (1 << 14) +#define EXYNOS_VIDCON2_TVFORMATSEL_MASK (1 << 14) +#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422 (1 << 12) +#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444 (2 << 12) +#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK (3 << 12) +#define EXYNOS_VIDCON2_ORGYUV_YCBCR (0 << 8) +#define EXYNOS_VIDCON2_ORGYUV_CBCRY (1 << 8) +#define EXYNOS_VIDCON2_ORGYUV_MASK (1 << 8) +#define EXYNOS_VIDCON2_YUVORD_CBCR (0 << 7) +#define EXYNOS_VIDCON2_YUVORD_CRCB (1 << 7) +#define EXYNOS_VIDCON2_YUVORD_MASK (1 << 7) + +/* PRTCON */ +#define EXYNOS_PRTCON_UPDATABLE (0 << 11) +#define EXYNOS_PRTCON_PROTECT (1 << 11) + +/* VIDTCON0 */ +#define EXYNOS_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24) +#define EXYNOS_VIDTCON0_VBPD(x) (((x) & 0xff) << 16) +#define EXYNOS_VIDTCON0_VFPD(x) (((x) & 0xff) << 8) +#define EXYNOS_VIDTCON0_VSPW(x) (((x) & 0xff) << 0) + +/* VIDTCON1 */ +#define EXYNOS_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24) +#define EXYNOS_VIDTCON1_HBPD(x) (((x) & 0xff) << 16) +#define EXYNOS_VIDTCON1_HFPD(x) (((x) & 0xff) << 8) +#define EXYNOS_VIDTCON1_HSPW(x) (((x) & 0xff) << 0) + +/* VIDTCON2 */ +#define EXYNOS_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11) +#define EXYNOS_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0) + +/* Window 0~4 Control - WINCONx */ +#define EXYNOS_WINCON_DATAPATH_DMA (0 << 22) +#define EXYNOS_WINCON_DATAPATH_LOCAL (1 << 22) +#define EXYNOS_WINCON_DATAPATH_MASK (1 << 22) +#define EXYNOS_WINCON_BUFSEL_0 (0 << 20) +#define EXYNOS_WINCON_BUFSEL_1 (1 << 20) +#define EXYNOS_WINCON_BUFSEL_MASK (1 << 20) +#define EXYNOS_WINCON_BUFSEL_SHIFT (20) +#define EXYNOS_WINCON_BUFAUTO_DISABLE (0 << 19) +#define EXYNOS_WINCON_BUFAUTO_ENABLE (1 << 19) +#define EXYNOS_WINCON_BUFAUTO_MASK (1 << 19) +#define EXYNOS_WINCON_BITSWP_DISABLE (0 << 18) +#define EXYNOS_WINCON_BITSWP_ENABLE (1 << 18) +#define EXYNOS_WINCON_BITSWP_SHIFT (18) +#define EXYNOS_WINCON_BYTESWP_DISABLE (0 << 17) +#define EXYNOS_WINCON_BYTESWP_ENABLE (1 << 17) +#define EXYNOS_WINCON_BYTESWP_SHIFT (17) +#define EXYNOS_WINCON_HAWSWP_DISABLE (0 << 16) +#define EXYNOS_WINCON_HAWSWP_ENABLE (1 << 16) +#define EXYNOS_WINCON_HAWSWP_SHIFT (16) +#define EXYNOS_WINCON_WSWP_DISABLE (0 << 15) +#define EXYNOS_WINCON_WSWP_ENABLE (1 << 15) +#define EXYNOS_WINCON_WSWP_SHIFT (15) +#define EXYNOS_WINCON_INRGB_RGB (0 << 13) +#define EXYNOS_WINCON_INRGB_YUV (1 << 13) +#define EXYNOS_WINCON_INRGB_MASK (1 << 13) +#define EXYNOS_WINCON_BURSTLEN_16WORD (0 << 9) +#define EXYNOS_WINCON_BURSTLEN_8WORD (1 << 9) +#define EXYNOS_WINCON_BURSTLEN_4WORD (2 << 9) +#define EXYNOS_WINCON_BURSTLEN_MASK (3 << 9) +#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE (0 << 7) +#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE (1 << 7) +#define EXYNOS_WINCON_BLD_PLANE (0 << 6) +#define EXYNOS_WINCON_BLD_PIXEL (1 << 6) +#define EXYNOS_WINCON_BLD_MASK (1 << 6) +#define EXYNOS_WINCON_BPPMODE_1BPP (0 << 2) +#define EXYNOS_WINCON_BPPMODE_2BPP (1 << 2) +#define EXYNOS_WINCON_BPPMODE_4BPP (2 << 2) +#define EXYNOS_WINCON_BPPMODE_8BPP_PAL (3 << 2) +#define EXYNOS_WINCON_BPPMODE_8BPP (4 << 2) +#define EXYNOS_WINCON_BPPMODE_16BPP_565 (5 << 2) +#define EXYNOS_WINCON_BPPMODE_16BPP_A555 (6 << 2) +#define EXYNOS_WINCON_BPPMODE_18BPP_666 (8 << 2) +#define EXYNOS_WINCON_BPPMODE_18BPP_A665 (9 << 2) +#define EXYNOS_WINCON_BPPMODE_24BPP_888 (0xb << 2) +#define EXYNOS_WINCON_BPPMODE_24BPP_A887 (0xc << 2) +#define EXYNOS_WINCON_BPPMODE_32BPP (0xd << 2) +#define EXYNOS_WINCON_BPPMODE_16BPP_A444 (0xe << 2) +#define EXYNOS_WINCON_BPPMODE_15BPP_555 (0xf << 2) +#define EXYNOS_WINCON_BPPMODE_MASK (0xf << 2) +#define EXYNOS_WINCON_BPPMODE_SHIFT (2) +#define EXYNOS_WINCON_ALPHA0_SEL (0 << 1) +#define EXYNOS_WINCON_ALPHA1_SEL (1 << 1) +#define EXYNOS_WINCON_ALPHA_SEL_MASK (1 << 1) +#define EXYNOS_WINCON_ENWIN_DISABLE (0 << 0) +#define EXYNOS_WINCON_ENWIN_ENABLE (1 << 0) + +/* WINCON1 special */ +#define EXYNOS_WINCON1_VP_DISABLE (0 << 24) +#define EXYNOS_WINCON1_VP_ENABLE (1 << 24) +#define EXYNOS_WINCON1_LOCALSEL_FIMC1 (0 << 23) +#define EXYNOS_WINCON1_LOCALSEL_VP (1 << 23) +#define EXYNOS_WINCON1_LOCALSEL_MASK (1 << 23) + +/* WINSHMAP */ +#define EXYNOS_WINSHMAP_PROTECT(x) (((x) & 0x1f) << 10) +#define EXYNOS_WINSHMAP_CH_ENABLE(x) (1 << (x)) +#define EXYNOS_WINSHMAP_CH_DISABLE(x) (1 << (x)) +#define EXYNOS_WINSHMAP_LOCAL_ENABLE(x) (0x20 << (x)) +#define EXYNOS_WINSHMAP_LOCAL_DISABLE(x) (0x20 << (x)) + +/* VIDOSDxA, VIDOSDxB */ +#define EXYNOS_VIDOSD_LEFT_X(x) (((x) & 0x7ff) << 11) +#define EXYNOS_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0) +#define EXYNOS_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11) +#define EXYNOS_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0) + +/* VIDOSD0C, VIDOSDxD */ +#define EXYNOS_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0) + +/* VIDOSDxC (1~4) */ +#define EXYNOS_VIDOSD_ALPHA0_R(x) (((x) & 0xf) << 20) +#define EXYNOS_VIDOSD_ALPHA0_G(x) (((x) & 0xf) << 16) +#define EXYNOS_VIDOSD_ALPHA0_B(x) (((x) & 0xf) << 12) +#define EXYNOS_VIDOSD_ALPHA1_R(x) (((x) & 0xf) << 8) +#define EXYNOS_VIDOSD_ALPHA1_G(x) (((x) & 0xf) << 4) +#define EXYNOS_VIDOSD_ALPHA1_B(x) (((x) & 0xf) << 0) +#define EXYNOS_VIDOSD_ALPHA0_SHIFT (12) +#define EXYNOS_VIDOSD_ALPHA1_SHIFT (0) + +/* Start Address */ +#define EXYNOS_VIDADDR_START_VBANK(x) (((x) & 0xff) << 24) +#define EXYNOS_VIDADDR_START_VBASEU(x) (((x) & 0xffffff) << 0) + +/* End Address */ +#define EXYNOS_VIDADDR_END_VBASEL(x) (((x) & 0xffffff) << 0) + +/* Buffer Size */ +#define EXYNOS_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13) +#define EXYNOS_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0) + +/* WIN Color Map */ +#define EXYNOS_WINMAP_COLOR(x) ((x) & 0xffffff) + +/* VIDINTCON0 */ +#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19) +#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19) +#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18) +#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18) +#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17) +#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17) +#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK (0 << 15) +#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15) +#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15) +#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT (3 << 15) +#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK (3 << 15) +#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE (0 << 13) +#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK (1 << 13) +#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13) +#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT (3 << 13) +#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE (0 << 12) +#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE (1 << 12) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4 (1 << 11) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3 (1 << 10) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2 (1 << 9) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1 (1 << 6) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0 (1 << 5) +#define EXYNOS_VIDINTCON0_FIFOSEL_ALL (0x73 << 5) +#define EXYNOS_VIDINTCON0_FIFOSEL_MASK (0x73 << 5) +#define EXYNOS_VIDINTCON0_FIFOLEVEL_25 (0 << 2) +#define EXYNOS_VIDINTCON0_FIFOLEVEL_50 (1 << 2) +#define EXYNOS_VIDINTCON0_FIFOLEVEL_75 (2 << 2) +#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2) +#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL (4 << 2) +#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK (7 << 2) +#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE (0 << 1) +#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE (1 << 1) +#define EXYNOS_VIDINTCON0_INT_DISABLE (0 << 0) +#define EXYNOS_VIDINTCON0_INT_ENABLE (1 << 0) +#define EXYNOS_VIDINTCON0_INT_MASK (1 << 0) + +/* VIDINTCON1 */ +#define EXYNOS_VIDINTCON1_INTVPPEND (1 << 5) +#define EXYNOS_VIDINTCON1_INTI80PEND (1 << 2) +#define EXYNOS_VIDINTCON1_INTFRMPEND (1 << 1) +#define EXYNOS_VIDINTCON1_INTFIFOPEND (1 << 0) + +/* WINMAP */ +#define EXYNOS_WINMAP_ENABLE (1 << 24) + +/* WxKEYCON0 (1~4) */ +#define EXYNOS_KEYCON0_KEYBLEN_DISABLE (0 << 26) +#define EXYNOS_KEYCON0_KEYBLEN_ENABLE (1 << 26) +#define EXYNOS_KEYCON0_KEY_DISABLE (0 << 25) +#define EXYNOS_KEYCON0_KEY_ENABLE (1 << 25) +#define EXYNOS_KEYCON0_DIRCON_MATCH_FG (0 << 24) +#define EXYNOS_KEYCON0_DIRCON_MATCH_BG (1 << 24) +#define EXYNOS_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0) + +/* WxKEYCON1 (1~4) */ +#define EXYNOS_KEYCON1_COLVAL(x) (((x) & 0xffffff) << 0) + +/* DUALRGB */ +#define EXYNOS_DUALRGB_BYPASS_SINGLE (0x00 << 0) +#define EXYNOS_DUALRGB_BYPASS_DUAL (0x01 << 0) +#define EXYNOS_DUALRGB_MIE_DUAL (0x10 << 0) +#define EXYNOS_DUALRGB_MIE_SINGLE (0x11 << 0) +#define EXYNOS_DUALRGB_LINESPLIT (0x0 << 2) +#define EXYNOS_DUALRGB_FRAMESPLIT (0x1 << 2) +#define EXYNOS_DUALRGB_SUB_CNT(x) ((x & 0xfff) << 4) +#define EXYNOS_DUALRGB_VDEN_EN_DISABLE (0x0 << 16) +#define EXYNOS_DUALRGB_VDEN_EN_ENABLE (0x1 << 16) +#define EXYNOS_DUALRGB_MAIN_CNT(x) ((x & 0xfff) << 18) + +/* I80IFCONA0 and I80IFCONA1 */ +#define EXYNOS_LCD_CS_SETUP(x) (((x) & 0xf) << 16) +#define EXYNOS_LCD_WR_SETUP(x) (((x) & 0xf) << 12) +#define EXYNOS_LCD_WR_ACT(x) (((x) & 0xf) << 8) +#define EXYNOS_LCD_WR_HOLD(x) (((x) & 0xf) << 4) +#define EXYNOS_RSPOL_LOW (0 << 2) +#define EXYNOS_RSPOL_HIGH (1 << 2) +#define EXYNOS_I80IFEN_DISABLE (0 << 0) +#define EXYNOS_I80IFEN_ENABLE (1 << 0) + +/* TRIGCON */ +#define EXYNOS_I80SOFT_TRIG_EN (1 << 0) +#define EXYNOS_I80START_TRIG (1 << 1) +#define EXYNOS_I80STATUS_TRIG_DONE (1 << 2) + +#endif /* _REGS_FB_H */ diff --git a/arch/arm/include/asm/arch-exynos/mipi_dsim.h b/arch/arm/include/asm/arch-exynos/mipi_dsim.h new file mode 100644 index 0000000000..ef6a3d1123 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/mipi_dsim.h @@ -0,0 +1,380 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: InKi Dae <inki.dae@samsung.com> + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DSIM_H +#define _DSIM_H + +#include <linux/list.h> +#include <linux/fb.h> + +#define PANEL_NAME_SIZE (32) + +enum mipi_dsim_interface_type { + DSIM_COMMAND, + DSIM_VIDEO +}; + +enum mipi_dsim_virtual_ch_no { + DSIM_VIRTUAL_CH_0, + DSIM_VIRTUAL_CH_1, + DSIM_VIRTUAL_CH_2, + DSIM_VIRTUAL_CH_3 +}; + +enum mipi_dsim_burst_mode_type { + DSIM_NON_BURST_SYNC_EVENT, + DSIM_BURST_SYNC_EVENT, + DSIM_NON_BURST_SYNC_PULSE, + DSIM_BURST, + DSIM_NON_VIDEO_MODE +}; + +enum mipi_dsim_no_of_data_lane { + DSIM_DATA_LANE_1, + DSIM_DATA_LANE_2, + DSIM_DATA_LANE_3, + DSIM_DATA_LANE_4 +}; + +enum mipi_dsim_byte_clk_src { + DSIM_PLL_OUT_DIV8, + DSIM_EXT_CLK_DIV8, + DSIM_EXT_CLK_BYPASS +}; + +enum mipi_dsim_pixel_format { + DSIM_CMD_3BPP, + DSIM_CMD_8BPP, + DSIM_CMD_12BPP, + DSIM_CMD_16BPP, + DSIM_VID_16BPP_565, + DSIM_VID_18BPP_666PACKED, + DSIM_18BPP_666LOOSELYPACKED, + DSIM_24BPP_888 +}; + +/* MIPI DSI Processor-to-Peripheral transaction types */ +enum { + MIPI_DSI_V_SYNC_START = 0x01, + MIPI_DSI_V_SYNC_END = 0x11, + MIPI_DSI_H_SYNC_START = 0x21, + MIPI_DSI_H_SYNC_END = 0x31, + + MIPI_DSI_COLOR_MODE_OFF = 0x02, + MIPI_DSI_COLOR_MODE_ON = 0x12, + MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, + MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, + + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, + + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, + + MIPI_DSI_DCS_SHORT_WRITE = 0x05, + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, + + MIPI_DSI_DCS_READ = 0x06, + + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, + + MIPI_DSI_END_OF_TRANSMISSION = 0x08, + + MIPI_DSI_NULL_PACKET = 0x09, + MIPI_DSI_BLANKING_PACKET = 0x19, + MIPI_DSI_GENERIC_LONG_WRITE = 0x29, + MIPI_DSI_DCS_LONG_WRITE = 0x39, + + MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, + + MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, + MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, + + MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, + MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, + MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, + MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, +}; + +/* + * struct mipi_dsim_config - interface for configuring mipi-dsi controller. + * + * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse. + * @eot_disable: enable or disable EoT packet in HS mode. + * @auto_vertical_cnt: specifies auto vertical count mode. + * in Video mode, the vertical line transition uses line counter + * configured by VSA, VBP, and Vertical resolution. + * If this bit is set to '1', the line counter does not use VSA and VBP + * registers.(in command mode, this variable is ignored) + * @hse: set horizontal sync event mode. + * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC + * start packet to MIPI DSI slave at MIPI DSI spec1.1r02. + * this bit transfers HSYNC end packet in VSYNC pulse and Vporch area + * (in mommand mode, this variable is ignored) + * @hfp: specifies HFP disable mode. + * if this variable is set, DSI master ignores HFP area in VIDEO mode. + * (in command mode, this variable is ignored) + * @hbp: specifies HBP disable mode. + * if this variable is set, DSI master ignores HBP area in VIDEO mode. + * (in command mode, this variable is ignored) + * @hsa: specifies HSA disable mode. + * if this variable is set, DSI master ignores HSA area in VIDEO mode. + * (in command mode, this variable is ignored) + * @e_interface: specifies interface to be used.(CPU or RGB interface) + * @e_virtual_ch: specifies virtual channel number that main or + * sub diaplsy uses. + * @e_pixel_format: specifies pixel stream format for main or sub display. + * @e_burst_mode: selects Burst mode in Video mode. + * in Non-burst mode, RGB data area is filled with RGB data and NULL + * packets, according to input bandwidth of RGB interface. + * In Burst mode, RGB data area is filled with RGB data only. + * @e_no_data_lane: specifies data lane count to be used by Master. + * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8) + * DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported. + * @pll_stable_time: specifies the PLL Timer for stability of the ganerated + * clock(System clock cycle base) + * if the timer value goes to 0x00000000, the clock stable bit of status + * and interrupt register is set. + * @esc_clk: specifies escape clock frequency for getting the escape clock + * prescaler value. + * @stop_holding_cnt: specifies the interval value between transmitting + * read packet(or write "set_tear_on" command) and BTA request. + * after transmitting read packet or write "set_tear_on" command, + * BTA requests to D-PHY automatically. this counter value specifies + * the interval between them. + * @bta_timeout: specifies the timer for BTA. + * this register specifies time out from BTA request to change + * the direction with respect to Tx escape clock. + * @rx_timeout: specifies the timer for LP Rx mode timeout. + * this register specifies time out on how long RxValid deasserts, + * after RxLpdt asserts with respect to Tx escape clock. + * - RxValid specifies Rx data valid indicator. + * - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode. + * - RxValid and RxLpdt specifies signal from D-PHY. + */ +struct mipi_dsim_config { + unsigned char auto_flush; + unsigned char eot_disable; + + unsigned char auto_vertical_cnt; + unsigned char hse; + unsigned char hfp; + unsigned char hbp; + unsigned char hsa; + + enum mipi_dsim_interface_type e_interface; + enum mipi_dsim_virtual_ch_no e_virtual_ch; + enum mipi_dsim_pixel_format e_pixel_format; + enum mipi_dsim_burst_mode_type e_burst_mode; + enum mipi_dsim_no_of_data_lane e_no_data_lane; + enum mipi_dsim_byte_clk_src e_byte_clk; + + /* + * =========================================== + * | P | M | S | MHz | + * ------------------------------------------- + * | 3 | 100 | 3 | 100 | + * | 3 | 100 | 2 | 200 | + * | 3 | 63 | 1 | 252 | + * | 4 | 100 | 1 | 300 | + * | 4 | 110 | 1 | 330 | + * | 12 | 350 | 1 | 350 | + * | 3 | 100 | 1 | 400 | + * | 4 | 150 | 1 | 450 | + * | 6 | 118 | 1 | 472 | + * | 3 | 120 | 1 | 480 | + * | 12 | 250 | 0 | 500 | + * | 4 | 100 | 0 | 600 | + * | 3 | 81 | 0 | 648 | + * | 3 | 88 | 0 | 704 | + * | 3 | 90 | 0 | 720 | + * | 3 | 100 | 0 | 800 | + * | 12 | 425 | 0 | 850 | + * | 4 | 150 | 0 | 900 | + * | 12 | 475 | 0 | 950 | + * | 6 | 250 | 0 | 1000 | + * ------------------------------------------- + */ + + /* + * pms could be calculated as the following. + * M * 24 / P * 2 ^ S = MHz + */ + unsigned char p; + unsigned short m; + unsigned char s; + + unsigned int pll_stable_time; + unsigned long esc_clk; + + unsigned short stop_holding_cnt; + unsigned char bta_timeout; + unsigned short rx_timeout; +}; + +/* + * struct mipi_dsim_device - global interface for mipi-dsi driver. + * + * @dsim_config: infomation for configuring mipi-dsi controller. + * @master_ops: callbacks to mipi-dsi operations. + * @dsim_lcd_dev: pointer to activated ddi device. + * (it would be registered by mipi-dsi driver.) + * @dsim_lcd_drv: pointer to activated_ddi driver. + * (it would be registered by mipi-dsi driver.) + * @state: specifies status of MIPI-DSI controller. + * the status could be RESET, INIT, STOP, HSCLKEN and ULPS. + * @data_lane: specifiec enabled data lane number. + * this variable would be set by driver according to e_no_data_lane + * automatically. + * @e_clk_src: select byte clock source. + * @pd: pointer to MIPI-DSI driver platform data. + */ +struct mipi_dsim_device { + struct mipi_dsim_config *dsim_config; + struct mipi_dsim_master_ops *master_ops; + struct mipi_dsim_lcd_device *dsim_lcd_dev; + struct mipi_dsim_lcd_driver *dsim_lcd_drv; + + unsigned int state; + unsigned int data_lane; + enum mipi_dsim_byte_clk_src e_clk_src; + + struct exynos_platform_mipi_dsim *pd; +}; + +/* + * struct exynos_platform_mipi_dsim - interface to platform data + * for mipi-dsi driver. + * + * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver. + * lcd panel driver searched would be actived. + * @dsim_config: pointer of structure for configuring mipi-dsi controller. + * @lcd_panel_info: pointer for lcd panel specific structure. + * this structure specifies width, height, timing and polarity and so on. + * @lcd_power: callback pointer for enabling or disabling lcd power. + * @mipi_power: callback pointer for enabling or disabling mipi power. + * @phy_enable: pointer to a callback controlling D-PHY enable/reset + */ +struct exynos_platform_mipi_dsim { + char lcd_panel_name[PANEL_NAME_SIZE]; + + struct mipi_dsim_config *dsim_config; + void *lcd_panel_info; + + int (*lcd_power)(void); + int (*mipi_power)(void); + void (*phy_enable)(unsigned int dev_index, unsigned int enable); +}; + +/* + * struct mipi_dsim_master_ops - callbacks to mipi-dsi operations. + * + * @cmd_write: transfer command to lcd panel at LP mode. + * @cmd_read: read command from rx register. + * @get_dsim_frame_done: get the status that all screen data have been + * transferred to mipi-dsi. + * @clear_dsim_frame_done: clear frame done status. + * @get_fb_frame_done: get frame done status of display controller. + * @trigger: trigger display controller. + * - this one would be used only in case of CPU mode. + */ +struct mipi_dsim_master_ops { + int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id, + unsigned int data0, unsigned int data1); + int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id, + unsigned int data0, unsigned int data1); + int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim); + int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim); + + int (*get_fb_frame_done)(void); + void (*trigger)(struct fb_info *info); +}; + +/* + * device structure for mipi-dsi based lcd panel. + * + * @name: name of the device to use with this device, or an + * alias for that name. + * @id: id of device to be registered. + * @bus_id: bus id for identifing connected bus + * and this bus id should be same as id of mipi_dsim_device. + * @master: pointer to mipi-dsi master device object. + * @platform_data: lcd panel specific platform data. + */ +struct mipi_dsim_lcd_device { + char *name; + int id; + int bus_id; + + struct mipi_dsim_device *master; + void *platform_data; +}; + +/* + * driver structure for mipi-dsi based lcd panel. + * + * this structure should be registered by lcd panel driver. + * mipi-dsi driver seeks lcd panel registered through name field + * and calls these callback functions in appropriate time. + * + * @name: name of the driver to use with this device, or an + * alias for that name. + * @id: id of driver to be registered. + * this id would be used for finding device object registered. + * @mipi_panel_init: callback pointer for initializing lcd panel based on mipi + * dsi interface. + * @mipi_display_on: callback pointer for lcd panel display on. + */ +struct mipi_dsim_lcd_driver { + char *name; + int id; + + int (*mipi_panel_init)(struct mipi_dsim_device *dsim_dev); + void (*mipi_display_on)(struct mipi_dsim_device *dsim_dev); +}; + +int exynos_mipi_dsi_init(void); + +/* + * register mipi_dsim_lcd_driver object defined by lcd panel driver + * to mipi-dsi driver. + */ +int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver + *lcd_drv); + +/* + * register mipi_dsim_lcd_device to mipi-dsi master. + */ +int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device + *lcd_dev); + +void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd); + +/* panel driver init based on mipi dsi interface */ +void s6e8ax0_init(void); + +#endif /* _DSIM_H */ diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h index 30f82b8aaf..0f701c9012 100644 --- a/arch/arm/include/asm/arch-exynos/mmc.h +++ b/arch/arm/include/asm/arch-exynos/mmc.h @@ -21,53 +21,54 @@ #ifndef __ASM_ARCH_MMC_H_ #define __ASM_ARCH_MMC_H_ -#ifndef __ASSEMBLY__ -struct s5p_mmc { - unsigned int sysad; - unsigned short blksize; - unsigned short blkcnt; - unsigned int argument; - unsigned short trnmod; - unsigned short cmdreg; - unsigned int rspreg0; - unsigned int rspreg1; - unsigned int rspreg2; - unsigned int rspreg3; - unsigned int bdata; - unsigned int prnsts; - unsigned char hostctl; - unsigned char pwrcon; - unsigned char blkgap; - unsigned char wakcon; - unsigned short clkcon; - unsigned char timeoutcon; - unsigned char swrst; - unsigned int norintsts; /* errintsts */ - unsigned int norintstsen; /* errintstsen */ - unsigned int norintsigen; /* errintsigen */ - unsigned short acmd12errsts; - unsigned char res1[2]; - unsigned int capareg; - unsigned char res2[4]; - unsigned int maxcurr; - unsigned char res3[0x34]; - unsigned int control2; - unsigned int control3; - unsigned char res4[4]; - unsigned int control4; - unsigned char res5[0x6e]; - unsigned short hcver; - unsigned char res6[0xFF00]; -}; +#define SDHCI_CONTROL2 0x80 +#define SDHCI_CONTROL3 0x84 +#define SDHCI_CONTROL4 0x8C -struct mmc_host { - struct s5p_mmc *reg; - unsigned int version; /* SDHCI spec. version */ - unsigned int clock; /* Current clock (MHz) */ - int dev_index; -}; +#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) +#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) +#define SDHCI_CTRL2_CDINVRXD3 (1 << 29) +#define SDHCI_CTRL2_SLCARDOUT (1 << 28) -int s5p_mmc_init(int dev_index, int bus_width); +#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) +#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) +#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) -#endif /* __ASSEMBLY__ */ +#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) +#define SDHCI_CTRL2_LVLDAT_SHIFT (16) +#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) + +#define SDHCI_CTRL2_ENFBCLKTX (1 << 15) +#define SDHCI_CTRL2_ENFBCLKRX (1 << 14) +#define SDHCI_CTRL2_SDCDSEL (1 << 13) +#define SDHCI_CTRL2_SDSIGPC (1 << 12) +#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) + +#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9) +#define SDHCI_CTRL2_DFCNT_SHIFT (9) + +#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) +#define SDHCI_CTRL2_RWAITMODE (1 << 7) +#define SDHCI_CTRL2_DISBUFRD (1 << 6) +#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4) +#define SDHCI_CTRL2_SELBASECLK_SHIFT (4) +#define SDHCI_CTRL2_PWRSYNC (1 << 3) +#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) +#define SDHCI_CTRL2_HWINITFIN (1 << 0) + +#define SDHCI_CTRL3_FCSEL3 (1 << 31) +#define SDHCI_CTRL3_FCSEL2 (1 << 23) +#define SDHCI_CTRL3_FCSEL1 (1 << 15) +#define SDHCI_CTRL3_FCSEL0 (1 << 7) + +#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) +#define SDHCI_CTRL4_DRIVE_SHIFT (16) + +int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); + +static inline unsigned int s5p_mmc_init(int index, int bus_width) +{ + unsigned int base = samsung_get_base_mmc() + (0x10000 * index); + return s5p_sdhci_init(base, 52000000, 400000, index); +} #endif diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index fb442f7f1f..6444fd04ec 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -227,4 +227,10 @@ struct exynos4_power { }; #endif /* __ASSEMBLY__ */ +void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); + +#define EXYNOS_MIPI_PHY_ENABLE (1 << 0) +#define EXYNOS_MIPI_PHY_SRESETN (1 << 1) +#define EXYNOS_MIPI_PHY_MRESETN (1 << 2) + #endif diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h new file mode 100644 index 0000000000..c85f949da4 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/system.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2012 Samsung Electronics + * Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_SYSTEM_H_ +#define __ASM_ARM_ARCH_SYSTEM_H_ + +#ifndef __ASSEMBLY__ +struct exynos4_sysreg { + unsigned char res1[0x210]; + unsigned int display_ctrl; + unsigned int display_ctrl2; + unsigned int camera_control; + unsigned int audio_endian; + unsigned int jtag_con; +}; + +struct exynos5_sysreg { + unsigned char res1[0x214]; + unsigned int disp1blk_cfg; + unsigned int disp2blk_cfg; + unsigned int hdcp_e_fuse; + unsigned int gsclblk_cfg0; + unsigned int gsclblk_cfg1; + unsigned int reserved; + unsigned int ispblk_cfg; + unsigned int usb20phy_cfg; + unsigned int mipi_dphy; + unsigned int dptx_dphy; + unsigned int phyclk_sel; +}; +#endif + +void set_system_display_ctrl(void); + +#endif /* _EXYNOS4_SYSTEM_H */ diff --git a/arch/arm/include/asm/arch-exynos/tzpc.h b/arch/arm/include/asm/arch-exynos/tzpc.h index 2c9a07be45..c5eb4b1cc2 100644 --- a/arch/arm/include/asm/arch-exynos/tzpc.h +++ b/arch/arm/include/asm/arch-exynos/tzpc.h @@ -22,7 +22,7 @@ #define __TZPC_H_ #ifndef __ASSEMBLY__ -struct exynos5_tzpc { +struct exynos_tzpc { unsigned int r0size; char res1[0x7FC]; unsigned int decprot0stat; diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h new file mode 100644 index 0000000000..c1dad0a444 --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef _LPC32XX_CLK_H +#define _LPC32XX_CLK_H + +#include <asm/types.h> + +#define OSC_CLK_FREQUENCY 13000000 +#define RTC_CLK_FREQUENCY 32768 + +/* Clocking and Power Control Registers */ +struct clk_pm_regs { + u32 reserved0[5]; + u32 boot_map; /* Boot Map Control Register */ + u32 p0_intr_er; /* Port 0/1 Start and Interrupt Enable */ + u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */ + /* Internal Start Signal Sources Registers */ + u32 start_er_int; /* Start Enable Register */ + u32 start_rsr_int; /* Start Raw Status Register */ + u32 start_sr_int; /* Start Status Register */ + u32 start_apr_int; /* Start Activation Polarity Register */ + /* Device Pin Start Signal Sources Registers */ + u32 start_er_pin; /* Start Enable Register */ + u32 start_rsr_pin; /* Start Raw Status Register */ + u32 start_sr_pin; /* Start Status Register */ + u32 start_apr_pin; /* Start Activation Polarity Register */ + /* Clock Control Registers */ + u32 hclkdiv_ctrl; /* HCLK Divider Control Register */ + u32 pwr_ctrl; /* Power Control Register */ + u32 pll397_ctrl; /* PLL397 Control Register */ + u32 osc_ctrl; /* Main Oscillator Control Register */ + u32 sysclk_ctrl; /* SYSCLK Control Register */ + u32 lcdclk_ctrl; /* LCD Clock Control Register */ + u32 hclkpll_ctrl; /* HCLK PLL Control Register */ + u32 reserved1; + u32 adclk_ctrl1; /* ADC Clock Control1 Register */ + u32 usb_ctrl; /* USB Control Register */ + u32 sdramclk_ctrl; /* SDRAM Clock Control Register */ + u32 ddr_lap_nom; /* DDR Calibration Nominal Value */ + u32 ddr_lap_count; /* DDR Calibration Measured Value */ + u32 ddr_cal_delay; /* DDR Calibration Delay Value */ + u32 ssp_ctrl; /* SSP Control Register */ + u32 i2s_ctrl; /* I2S Clock Control Register */ + u32 ms_ctrl; /* Memory Card Control Register */ + u32 reserved2[3]; + u32 macclk_ctrl; /* Ethernet MAC Clock Control Register */ + u32 reserved3[4]; + u32 test_clk; /* Test Clock Selection Register */ + u32 sw_int; /* Software Interrupt Register */ + u32 i2cclk_ctrl; /* I2C Clock Control Register */ + u32 keyclk_ctrl; /* Keyboard Scan Clock Control Register */ + u32 adclk_ctrl; /* ADC Clock Control Register */ + u32 pwmclk_ctrl; /* PWM Clock Control Register */ + u32 timclk_ctrl; /* Watchdog and Highspeed Timer Control */ + u32 timclk_ctrl1; /* Motor and Timer Clock Control */ + u32 spi_ctrl; /* SPI Control Register */ + u32 flashclk_ctrl; /* NAND Flash Clock Control Register */ + u32 reserved4; + u32 u3clk; /* UART 3 Clock Control Register */ + u32 u4clk; /* UART 4 Clock Control Register */ + u32 u5clk; /* UART 5 Clock Control Register */ + u32 u6clk; /* UART 6 Clock Control Register */ + u32 irdaclk; /* IrDA Clock Control Register */ + u32 uartclk_ctrl; /* UART Clock Control Register */ + u32 dmaclk_ctrl; /* DMA Clock Control Register */ + u32 autoclk_ctrl; /* Autoclock Control Register */ +}; + +/* HCLK Divider Control Register bits */ +#define CLK_HCLK_DDRAM_HALF (0x2 << 7) +#define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7) +#define CLK_HCLK_DDRAM_STOPPED (0x0 << 7) +#define CLK_HCLK_PERIPH_DIV_MASK (0x1F << 2) +#define CLK_HCLK_PERIPH_DIV(n) ((((n) - 1) & 0x1F) << 2) +#define CLK_HCLK_ARM_PLL_DIV_MASK (0x3 << 0) +#define CLK_HCLK_ARM_PLL_DIV_4 (0x2 << 0) +#define CLK_HCLK_ARM_PLL_DIV_2 (0x1 << 0) +#define CLK_HCLK_ARM_PLL_DIV_1 (0x0 << 0) + +/* Power Control Register bits */ +#define CLK_PWR_HCLK_RUN_PERIPH (1 << 10) +#define CLK_PWR_EMC_SREFREQ (1 << 9) +#define CLK_PWR_EMC_SREFREQ_UPDATE (1 << 8) +#define CLK_PWR_SDRAM_SREFREQ (1 << 7) +#define CLK_PWR_HIGHCORE_LEVEL (1 << 5) +#define CLK_PWR_SYSCLKEN_LEVEL (1 << 4) +#define CLK_PWR_SYSCLKEN_CTRL (1 << 3) +#define CLK_PWR_NORMAL_RUN (1 << 2) +#define CLK_PWR_HIGHCORE_CTRL (1 << 1) +#define CLK_PWR_STOP_MODE (1 << 0) + +/* SYSCLK Control Register bits */ +#define CLK_SYSCLK_PLL397 (1 << 1) +#define CLK_SYSCLK_MUX (1 << 0) + +/* HCLK PLL Control Register bits */ +#define CLK_HCLK_PLL_OPERATING (1 << 16) +#define CLK_HCLK_PLL_BYPASS (1 << 15) +#define CLK_HCLK_PLL_DIRECT (1 << 14) +#define CLK_HCLK_PLL_FEEDBACK (1 << 13) +#define CLK_HCLK_PLL_POSTDIV_MASK (0x3 << 11) +#define CLK_HCLK_PLL_POSTDIV_16 (0x3 << 11) +#define CLK_HCLK_PLL_POSTDIV_8 (0x2 << 11) +#define CLK_HCLK_PLL_POSTDIV_4 (0x1 << 11) +#define CLK_HCLK_PLL_POSTDIV_2 (0x0 << 11) +#define CLK_HCLK_PLL_PREDIV_MASK (0x3 << 9) +#define CLK_HCLK_PLL_PREDIV_4 (0x3 << 9) +#define CLK_HCLK_PLL_PREDIV_3 (0x2 << 9) +#define CLK_HCLK_PLL_PREDIV_2 (0x1 << 9) +#define CLK_HCLK_PLL_PREDIV_1 (0x0 << 9) +#define CLK_HCLK_PLL_FEEDBACK_DIV_MASK (0xFF << 1) +#define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1) +#define CLK_HCLK_PLL_LOCKED (1 << 0) + +/* Ethernet MAC Clock Control Register bits */ +#define CLK_MAC_RMII (0x3 << 3) +#define CLK_MAC_MII (0x1 << 3) +#define CLK_MAC_MASTER (1 << 2) +#define CLK_MAC_SLAVE (1 << 1) +#define CLK_MAC_REG (1 << 0) + +/* Timer Clock Control1 Register bits */ +#define CLK_TIMCLK_MOTOR (1 << 6) +#define CLK_TIMCLK_TIMER3 (1 << 5) +#define CLK_TIMCLK_TIMER2 (1 << 4) +#define CLK_TIMCLK_TIMER1 (1 << 3) +#define CLK_TIMCLK_TIMER0 (1 << 2) +#define CLK_TIMCLK_TIMER5 (1 << 1) +#define CLK_TIMCLK_TIMER4 (1 << 0) + +/* Timer Clock Control Register bits */ +#define CLK_TIMCLK_HSTIMER (1 << 1) +#define CLK_TIMCLK_WATCHDOG (1 << 0) + +/* UART Clock Control Register bits */ +#define CLK_UART(n) (1 << ((n) - 3)) + +/* UARTn Clock Select Registers bits */ +#define CLK_UART_HCLK (1 << 16) +#define CLK_UART_X_DIV(n) (((n) & 0xFF) << 8) +#define CLK_UART_Y_DIV(n) (((n) & 0xFF) << 0) + +/* DMA Clock Control Register bits */ +#define CLK_DMA_ENABLE (1 << 0) + +unsigned int get_sys_clk_rate(void); +unsigned int get_hclk_pll_rate(void); +unsigned int get_hclk_clk_div(void); +unsigned int get_hclk_clk_rate(void); +unsigned int get_periph_clk_div(void); +unsigned int get_periph_clk_rate(void); + +#endif /* _LPC32XX_CLK_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h new file mode 100644 index 0000000000..41fcd323be --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -0,0 +1,76 @@ +/* + * Common definitions for LPC32XX board configurations + * + * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef _LPC32XX_CONFIG_H +#define _LPC32XX_CONFIG_H + +/* Basic CPU architecture */ +#define CONFIG_ARM926EJS +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_NR_DRAM_BANKS_MAX 2 + +/* 1KHz clock tick */ +#define CONFIG_SYS_HZ 1000 + +/* UART configuration */ +#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6) +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2) +#elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ + (CONFIG_SYS_LPC32XX_UART == 7) +#define CONFIG_LPC32XX_HSUART +#else +#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7" +#endif + +#if defined(CONFIG_SYS_NS16550_SERIAL) +#define CONFIG_SYS_NS16550 + +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + +#define CONFIG_SYS_NS16550_COM1 UART3_BASE +#define CONFIG_SYS_NS16550_COM2 UART4_BASE +#define CONFIG_SYS_NS16550_COM3 UART5_BASE +#define CONFIG_SYS_NS16550_COM4 UART6_BASE +#endif + +#if defined(CONFIG_LPC32XX_HSUART) +#if CONFIG_SYS_LPC32XX_UART == 1 +#define HS_UART_BASE HS_UART1_BASE +#elif CONFIG_SYS_LPC32XX_UART == 2 +#define HS_UART_BASE HS_UART2_BASE +#else /* CONFIG_SYS_LPC32XX_UART == 7 */ +#define HS_UART_BASE HS_UART7_BASE +#endif +#endif + +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } + +/* NOR Flash */ +#if defined(CONFIG_SYS_FLASH_CFI) +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_PROTECTION +#endif + +#endif /* _LPC32XX_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h new file mode 100644 index 0000000000..c5343c36e5 --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef _LPC32XX_CPU_H +#define _LPC32XX_CPU_H + +/* LPC32XX Memory map */ + +/* AHB physical base addresses */ +#define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */ +#define SSP0_BASE 0x20084000 /* SSP0 registers base */ +#define SD_CARD_BASE 0x20098000 /* SD card interface registers base */ +#define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */ +#define DMA_BASE 0x31000000 /* DMA controller registers base */ +#define USB_BASE 0x31020000 /* USB registers base */ +#define LCD_BASE 0x31040000 /* LCD registers base */ +#define ETHERNET_BASE 0x31060000 /* Ethernet registers base */ +#define EMC_BASE 0x31080000 /* EMC configuration registers base */ + +/* FAB peripherals base addresses */ +#define CLK_PM_BASE 0x40004000 /* System control registers base */ +#define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */ +#define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */ +#define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ +#define RTC_BASE 0x40024000 /* RTC registers base */ +#define GPIO_BASE 0x40028000 /* GPIO registers base */ +#define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ +#define TIMER0_BASE 0x40044000 /* Timer0 registers base */ +#define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ +#define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */ + +/* APB peripherals base addresses */ +#define UART3_BASE 0x40080000 /* UART 3 registers base */ +#define UART4_BASE 0x40088000 /* UART 4 registers base */ +#define UART5_BASE 0x40090000 /* UART 5 registers base */ +#define UART6_BASE 0x40098000 /* UART 6 registers base */ + +/* External SDRAM Memory Bank base addresses */ +#define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ +#define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */ + +/* External Static Memory Bank base addresses */ +#define EMC_CS0_BASE 0xE0000000 +#define EMC_CS1_BASE 0xE1000000 +#define EMC_CS2_BASE 0xE2000000 +#define EMC_CS3_BASE 0xE3000000 + +#endif /* _LPC32XX_CPU_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h new file mode 100644 index 0000000000..feb03bd069 --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/emc.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef _LPC32XX_EMC_H +#define _LPC32XX_EMC_H + +#include <asm/types.h> + +/* EMC Registers */ +struct emc_regs { + u32 ctrl; /* Controls operation of the EMC */ + u32 status; /* Provides EMC status information */ + u32 config; /* Configures operation of the EMC */ + u32 reserved0[5]; + u32 control; /* Controls dyn memory operation */ + u32 refresh; /* Configures dyn memory refresh operation */ + u32 read_config; /* Configures the dyn memory read strategy */ + u32 reserved1; + u32 t_rp; /* Precharge command period */ + u32 t_ras; /* Active to precharge command period */ + u32 t_srex; /* Self-refresh exit time */ + u32 reserved2[2]; + u32 t_wr; /* Write recovery time */ + u32 t_rc; /* Active to active command period */ + u32 t_rfc; /* Auto-refresh period */ + u32 t_xsr; /* Exit self-refresh to active command time */ + u32 t_rrd; /* Active bank A to active bank B latency */ + u32 t_mrd; /* Load mode register to active command time */ + u32 t_cdlr; /* Last data in to read command time */ + u32 reserved3[8]; + u32 extended_wait; /* time for static memory rd/wr transfers */ + u32 reserved4[31]; + u32 config0; /* Configuration information for the SDRAM */ + u32 rascas0; /* RAS and CAS latencies for the SDRAM */ + u32 reserved5[6]; + u32 config1; /* Configuration information for the SDRAM */ + u32 rascas1; /* RAS and CAS latencies for the SDRAM */ + u32 reserved6[54]; + struct emc_stat_t { + u32 config; /* Static memory configuration */ + u32 waitwen; /* Delay from chip select to write enable */ + u32 waitoen; /* Delay to output enable */ + u32 waitrd; /* Delay to a read access */ + u32 waitpage; /* Delay for async page mode read */ + u32 waitwr; /* Delay to a write access */ + u32 waitturn; /* Number of bus turnaround cycles */ + u32 reserved; + } stat[4]; + u32 reserved7[96]; + struct emc_ahb_t { + u32 control; /* Control register for AHB */ + u32 status; /* Status register for AHB */ + u32 timeout; /* Timeout register for AHB */ + u32 reserved[5]; + } ahb[5]; +}; + +/* Static Memory Configuration Register bits */ +#define EMC_STAT_CONFIG_WP (1 << 20) +#define EMC_STAT_CONFIG_EW (1 << 8) +#define EMC_STAT_CONFIG_PB (1 << 7) +#define EMC_STAT_CONFIG_PC (1 << 6) +#define EMC_STAT_CONFIG_PM (1 << 3) +#define EMC_STAT_CONFIG_32BIT (2 << 0) +#define EMC_STAT_CONFIG_16BIT (1 << 0) +#define EMC_STAT_CONFIG_8BIT (0 << 0) + +/* Static Memory Delay Registers */ +#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F) +#define EMC_STAT_WAITOEN(n) (((n) - 1) & 0x0F) +#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F) +#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F) +#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F) +#define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F) + +#endif /* _LPC32XX_EMC_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h new file mode 100644 index 0000000000..b2cbfcd66d --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef _LPC32XX_SYS_PROTO_H +#define _LPC32XX_SYS_PROTO_H + +void lpc32xx_uart_init(unsigned int uart_id); + +#endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/timer.h b/arch/arm/include/asm/arch-lpc32xx/timer.h new file mode 100644 index 0000000000..7d637637ef --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/timer.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef _LPC32XX_TIMER_H +#define _LPC32XX_TIMER_H + +#include <asm/types.h> + +/* Timer/Counter Registers */ +struct timer_regs { + u32 ir; /* Interrupt Register */ + u32 tcr; /* Timer Control Register */ + u32 tc; /* Timer Counter */ + u32 pr; /* Prescale Register */ + u32 pc; /* Prescale Counter */ + u32 mcr; /* Match Control Register */ + u32 mr[4]; /* Match Registers */ + u32 ccr; /* Capture Control Register */ + u32 cr[4]; /* Capture Registers */ + u32 emr; /* External Match Register */ + u32 reserved[12]; + u32 ctcr; /* Count Control Register */ +}; + +/* Timer/Counter Interrupt Register bits */ +#define TIMER_IR_CR(n) (1 << ((n) + 4)) +#define TIMER_IR_MR(n) (1 << (n)) + +/* Timer/Counter Timer Control Register bits */ +#define TIMER_TCR_COUNTER_RESET (1 << 1) +#define TIMER_TCR_COUNTER_ENABLE (1 << 0) +#define TIMER_TCR_COUNTER_DISABLE (0 << 0) + +/* Timer/Counter Match Control Register bits */ +#define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2)) +#define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1)) +#define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n))) + +/* Timer/Counter Capture Control Register bits */ +#define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2)) +#define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1)) +#define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n))) + +/* Timer/Counter External Match Register bits */ +#define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4)) +#define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4)) +#define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4)) +#define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4)) +#define TIMER_EMR_EM(n) (1 << (n)) + +/* Timer/Counter Count Control Register bits */ +#define TIMER_CTCR_INPUT(n) ((n) << 2) +#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0) +#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0) +#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) +#define TIMER_CTCR_MODE_TIMER (0x0 << 0) + +#endif /* _LPC32XX_TIMER_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/uart.h b/arch/arm/include/asm/arch-lpc32xx/uart.h new file mode 100644 index 0000000000..ec12893236 --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/uart.h @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef _LPC32XX_UART_H +#define _LPC32XX_UART_H + +#include <asm/types.h> + +/* 14-clock UART Registers */ +struct hsuart_regs { + union { + u32 rx; /* Receiver FIFO */ + u32 tx; /* Transmitter FIFO */ + }; + u32 level; /* FIFO Level Register */ + u32 iir; /* Interrupt ID Register */ + u32 ctrl; /* Control Register */ + u32 rate; /* Rate Control Register */ +}; + +/* 14-clock UART Receiver FIFO Register bits */ +#define HSUART_RX_BREAK (1 << 10) +#define HSUART_RX_ERROR (1 << 9) +#define HSUART_RX_EMPTY (1 << 8) +#define HSUART_RX_DATA (0xff << 0) + +/* 14-clock UART Level Register bits */ +#define HSUART_LEVEL_TX (0xff << 8) +#define HSUART_LEVEL_RX (0xff << 0) + +/* 14-clock UART Interrupt Identification Register bits */ +#define HSUART_IIR_TX_INT_SET (1 << 6) +#define HSUART_IIR_RX_OE (1 << 5) +#define HSUART_IIR_BRK (1 << 4) +#define HSUART_IIR_FE (1 << 3) +#define HSUART_IIR_RX_TIMEOUT (1 << 2) +#define HSUART_IIR_RX_TRIG (1 << 1) +#define HSUART_IIR_TX (1 << 0) + +/* 14-clock UART Control Register bits */ +#define HSUART_CTRL_HRTS_INV (1 << 21) +#define HSUART_CTRL_HRTS_TRIG_48 (0x3 << 19) +#define HSUART_CTRL_HRTS_TRIG_32 (0x2 << 19) +#define HSUART_CTRL_HRTS_TRIG_16 (0x1 << 19) +#define HSUART_CTRL_HRTS_TRIG_8 (0x0 << 19) +#define HSUART_CTRL_HRTS_EN (1 << 18) +#define HSUART_CTRL_TMO_16 (0x3 << 16) +#define HSUART_CTRL_TMO_8 (0x2 << 16) +#define HSUART_CTRL_TMO_4 (0x1 << 16) +#define HSUART_CTRL_TMO_DISABLED (0x0 << 16) +#define HSUART_CTRL_HCTS_INV (1 << 15) +#define HSUART_CTRL_HCTS_EN (1 << 14) +#define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9) +#define HSUART_CTRL_HSU_BREAK (1 << 8) +#define HSUART_CTRL_HSU_ERR_INT_EN (1 << 7) +#define HSUART_CTRL_HSU_RX_INT_EN (1 << 6) +#define HSUART_CTRL_HSU_TX_INT_EN (1 << 5) +#define HSUART_CTRL_HSU_RX_TRIG_48 (0x5 << 2) +#define HSUART_CTRL_HSU_RX_TRIG_32 (0x4 << 2) +#define HSUART_CTRL_HSU_RX_TRIG_16 (0x3 << 2) +#define HSUART_CTRL_HSU_RX_TRIG_8 (0x2 << 2) +#define HSUART_CTRL_HSU_RX_TRIG_4 (0x1 << 2) +#define HSUART_CTRL_HSU_RX_TRIG_1 (0x0 << 2) +#define HSUART_CTRL_HSU_TX_TRIG_16 (0x3 << 0) +#define HSUART_CTRL_HSU_TX_TRIG_8 (0x2 << 0) +#define HSUART_CTRL_HSU_TX_TRIG_4 (0x1 << 0) +#define HSUART_CTRL_HSU_TX_TRIG_0 (0x0 << 0) + +/* UART Control Registers */ +struct uart_ctrl_regs { + u32 ctrl; /* Control Register */ + u32 clkmode; /* Clock Mode Register */ + u32 loop; /* Loopback Control Register */ +}; + +/* UART Control Register bits */ +#define UART_CTRL_UART3_MD_CTRL (1 << 11) +#define UART_CTRL_HDPX_INV (1 << 10) +#define UART_CTRL_HDPX_EN (1 << 9) +#define UART_CTRL_UART6_IRDA (1 << 5) +#define UART_CTRL_IR_TX6_INV (1 << 4) +#define UART_CTRL_IR_RX6_INV (1 << 3) +#define UART_CTRL_IR_RX_LENGTH (1 << 2) +#define UART_CTRL_IR_TX_LENGTH (1 << 1) +#define UART_CTRL_UART5_USB_MODE (1 << 0) + +/* UART Clock Mode Register bits */ +#define UART_CLKMODE_STATX(n) (1 << ((n) + 16)) +#define UART_CLKMODE_STAT (1 << 14) +#define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2)) +#define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2)) +#define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2)) +#define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2)) + +/* UART Loopback Control Register bits */ +#define UART_LOOPBACK(n) (1 << ((n) - 1)) + +#endif /* _LPC32XX_UART_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/wdt.h b/arch/arm/include/asm/arch-lpc32xx/wdt.h new file mode 100644 index 0000000000..133f29fc4b --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/wdt.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef _LPC32XX_WDT_H +#define _LPC32XX_WDT_H + +#include <asm/types.h> + +/* Watchdog Timer Registers */ +struct wdt_regs { + u32 isr; /* Interrupt Status Register */ + u32 ctrl; /* Control Register */ + u32 counter; /* Counter Value Register */ + u32 mctrl; /* Match Control Register */ + u32 match0; /* Match 0 Register */ + u32 emr; /* External Match Control Register */ + u32 pulse; /* Reset Pulse Length Register */ + u32 res; /* Reset Source Register */ +}; + +/* Watchdog Timer Control Register bits */ +#define WDTIM_CTRL_PAUSE_EN (1 << 2) +#define WDTIM_CTRL_RESET_COUNT (1 << 1) +#define WDTIM_CTRL_COUNT_ENAB (1 << 0) + +/* Watchdog Timer Match Control Register bits */ +#define WDTIM_MCTRL_RESFRC2 (1 << 6) +#define WDTIM_MCTRL_RESFRC1 (1 << 5) +#define WDTIM_MCTRL_M_RES2 (1 << 4) +#define WDTIM_MCTRL_M_RES1 (1 << 3) +#define WDTIM_MCTRL_STOP_COUNT0 (1 << 2) +#define WDTIM_MCTRL_RESET_COUNT0 (1 << 1) +#define WDTIM_MCTRL_MR0_INT (1 << 0) + +#endif /* _LPC32XX_WDT_H */ diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h index c59f588570..0f47eaf053 100644 --- a/arch/arm/include/asm/arch-mx25/clock.h +++ b/arch/arm/include/asm/arch-mx25/clock.h @@ -26,11 +26,34 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +enum mxc_clock { + MXC_CSI_CLK, + MXC_EPIT_CLK, + MXC_ESAI_CLK, + MXC_ESDHC1_CLK, + MXC_ESDHC2_CLK, + MXC_GPT_CLK, + MXC_I2C_CLK, + MXC_LCDC_CLK, + MXC_NFC_CLK, + MXC_OWIRE_CLK, + MXC_PWM_CLK, + MXC_SIM1_CLK, + MXC_SIM2_CLK, + MXC_SSI1_CLK, + MXC_SSI2_CLK, + MXC_UART_CLK, + MXC_ARM_CLK, + MXC_FEC_CLK, + MXC_CLK_NUM +}; + ulong imx_get_perclk(int clk); ulong imx_get_ahbclk(void); #define imx_get_uartclk() imx_get_perclk(15) #define imx_get_fecclk() (imx_get_ahbclk()/2) +unsigned int mxc_get_clock(enum mxc_clock clk); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 7f9449b2d0..cf925d70d5 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -34,6 +34,9 @@ #define _IMX_REGS_H #ifndef __ASSEMBLY__ + +#include <asm/types.h> + #ifdef CONFIG_FEC_MXC extern void mx25_fec_init_pins(void); #endif diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h b/arch/arm/include/asm/arch-mx28/imx-regs.h index f9e6c535f2..37d0a93768 100644 --- a/arch/arm/include/asm/arch-mx28/imx-regs.h +++ b/arch/arm/include/asm/arch-mx28/imx-regs.h @@ -30,6 +30,8 @@ #include <asm/arch/regs-digctl.h> #include <asm/arch/regs-gpmi.h> #include <asm/arch/regs-i2c.h> +#include <asm/arch/regs-lcdif.h> +#include <asm/arch/regs-lradc.h> #include <asm/arch/regs-ocotp.h> #include <asm/arch/regs-pinctrl.h> #include <asm/arch/regs-power.h> diff --git a/arch/arm/include/asm/arch-mx28/regs-lcdif.h b/arch/arm/include/asm/arch-mx28/regs-lcdif.h new file mode 100644 index 0000000000..cb47e41fdc --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-lcdif.h @@ -0,0 +1,212 @@ +/* + * Freescale i.MX28 LCDIF Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_LCDIF_H__ +#define __MX28_REGS_LCDIF_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_lcdif_regs { + mx28_reg_32(hw_lcdif_ctrl) /* 0x00 */ + mx28_reg_32(hw_lcdif_ctrl1) /* 0x10 */ + mx28_reg_32(hw_lcdif_ctrl2) /* 0x20 */ + mx28_reg_32(hw_lcdif_transfer_count) /* 0x30 */ + mx28_reg_32(hw_lcdif_cur_buf) /* 0x40 */ + mx28_reg_32(hw_lcdif_next_buf) /* 0x50 */ + mx28_reg_32(hw_lcdif_timing) /* 0x60 */ + mx28_reg_32(hw_lcdif_vdctrl0) /* 0x70 */ + mx28_reg_32(hw_lcdif_vdctrl1) /* 0x80 */ + mx28_reg_32(hw_lcdif_vdctrl2) /* 0x90 */ + mx28_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */ + mx28_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */ + mx28_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */ + mx28_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */ + mx28_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */ + mx28_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */ + mx28_reg_32(hw_lcdif_dvictrl4) /* 0x100 */ + mx28_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */ + mx28_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */ + mx28_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */ + mx28_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */ + mx28_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */ + mx28_reg_32(hw_lcdif_csc_offset) /* 0x160 */ + mx28_reg_32(hw_lcdif_csc_limit) /* 0x170 */ + mx28_reg_32(hw_lcdif_data) /* 0x180 */ + mx28_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */ + mx28_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ + mx28_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */ + mx28_reg_32(hw_lcdif_version) /* 0x1c0 */ + mx28_reg_32(hw_lcdif_debug0) /* 0x1d0 */ + mx28_reg_32(hw_lcdif_debug1) /* 0x1e0 */ + mx28_reg_32(hw_lcdif_debug2) /* 0x1f0 */ +}; +#endif + +#define LCDIF_CTRL_SFTRST (1 << 31) +#define LCDIF_CTRL_CLKGATE (1 << 30) +#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) +#define LCDIF_CTRL_READ_WRITEB (1 << 28) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) +#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) +#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 +#define LCDIF_CTRL_DVI_MODE (1 << 20) +#define LCDIF_CTRL_BYPASS_COUNT (1 << 19) +#define LCDIF_CTRL_VSYNC_MODE (1 << 18) +#define LCDIF_CTRL_DOTCLK_MODE (1 << 17) +#define LCDIF_CTRL_DATA_SELECT (1 << 16) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) +#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 +#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) +#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) +#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) +#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) +#define LCDIF_CTRL_LCDIF_MASTER (1 << 5) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) +#define LCDIF_CTRL_RUN (1 << 0) + +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) +#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) +#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) +#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) +#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) +#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) +#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) +#define LCDIF_CTRL1_MODE86 (1 << 1) +#define LCDIF_CTRL1_RESET (1 << 0) + +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) +#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 +#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) +#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1 + +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) +#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) +#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0 + +#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff +#define LCDIF_CUR_BUF_ADDR_OFFSET 0 + +#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff +#define LCDIF_NEXT_BUF_ADDR_OFFSET 0 + +#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) +#define LCDIF_TIMING_CMD_HOLD_OFFSET 24 +#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) +#define LCDIF_TIMING_CMD_SETUP_OFFSET 16 +#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) +#define LCDIF_TIMING_DATA_HOLD_OFFSET 8 +#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) +#define LCDIF_TIMING_DATA_SETUP_OFFSET 0 + +#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) +#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) +#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) +#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) +#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) +#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) +#define LCDIF_VDCTRL0_HALF_LINE (1 << 19) +#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 + +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff +#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0 + +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff +#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 + +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) +#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0 + +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 + +#endif /* __MX28_REGS_LCDIF_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-lradc.h b/arch/arm/include/asm/arch-mx28/regs-lradc.h new file mode 100644 index 0000000000..16e2bbf4cb --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-lradc.h @@ -0,0 +1,400 @@ +/* + * Freescale i.MX28 LRADC Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_LRADC_H__ +#define __MX28_REGS_LRADC_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_lradc_regs { + mx28_reg_32(hw_lradc_ctrl0); + mx28_reg_32(hw_lradc_ctrl1); + mx28_reg_32(hw_lradc_ctrl2); + mx28_reg_32(hw_lradc_ctrl3); + mx28_reg_32(hw_lradc_status); + mx28_reg_32(hw_lradc_ch0); + mx28_reg_32(hw_lradc_ch1); + mx28_reg_32(hw_lradc_ch2); + mx28_reg_32(hw_lradc_ch3); + mx28_reg_32(hw_lradc_ch4); + mx28_reg_32(hw_lradc_ch5); + mx28_reg_32(hw_lradc_ch6); + mx28_reg_32(hw_lradc_ch7); + mx28_reg_32(hw_lradc_delay0); + mx28_reg_32(hw_lradc_delay1); + mx28_reg_32(hw_lradc_delay2); + mx28_reg_32(hw_lradc_delay3); + mx28_reg_32(hw_lradc_debug0); + mx28_reg_32(hw_lradc_debug1); + mx28_reg_32(hw_lradc_conversion); + mx28_reg_32(hw_lradc_ctrl4); + mx28_reg_32(hw_lradc_treshold0); + mx28_reg_32(hw_lradc_treshold1); + mx28_reg_32(hw_lradc_version); +}; +#endif + +#define LRADC_CTRL0_SFTRST (1 << 31) +#define LRADC_CTRL0_CLKGATE (1 << 30) +#define LRADC_CTRL0_ONCHIP_GROUNDREF (1 << 26) +#define LRADC_CTRL0_BUTTON1_DETECT_ENABLE (1 << 25) +#define LRADC_CTRL0_BUTTON0_DETECT_ENABLE (1 << 24) +#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23) +#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22) +#define LRADC_CTRL0_YNLRSW (1 << 21) +#define LRADC_CTRL0_YPLLSW_MASK (0x3 << 19) +#define LRADC_CTRL0_YPLLSW_OFFSET 19 +#define LRADC_CTRL0_XNURSW_MASK (0x3 << 17) +#define LRADC_CTRL0_XNURSW_OFFSET 17 +#define LRADC_CTRL0_XPULSW (1 << 16) +#define LRADC_CTRL0_SCHEDULE_MASK 0xff +#define LRADC_CTRL0_SCHEDULE_OFFSET 0 + +#define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN (1 << 28) +#define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN (1 << 27) +#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN (1 << 26) +#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN (1 << 25) +#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24) +#define LRADC_CTRL1_LRADC7_IRQ_EN (1 << 23) +#define LRADC_CTRL1_LRADC6_IRQ_EN (1 << 22) +#define LRADC_CTRL1_LRADC5_IRQ_EN (1 << 21) +#define LRADC_CTRL1_LRADC4_IRQ_EN (1 << 20) +#define LRADC_CTRL1_LRADC3_IRQ_EN (1 << 19) +#define LRADC_CTRL1_LRADC2_IRQ_EN (1 << 18) +#define LRADC_CTRL1_LRADC1_IRQ_EN (1 << 17) +#define LRADC_CTRL1_LRADC0_IRQ_EN (1 << 16) +#define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12) +#define LRADC_CTRL1_BUTTON0_DETECT_IRQ (1 << 11) +#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ (1 << 10) +#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ (1 << 9) +#define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8) +#define LRADC_CTRL1_LRADC7_IRQ (1 << 7) +#define LRADC_CTRL1_LRADC6_IRQ (1 << 6) +#define LRADC_CTRL1_LRADC5_IRQ (1 << 5) +#define LRADC_CTRL1_LRADC4_IRQ (1 << 4) +#define LRADC_CTRL1_LRADC3_IRQ (1 << 3) +#define LRADC_CTRL1_LRADC2_IRQ (1 << 2) +#define LRADC_CTRL1_LRADC1_IRQ (1 << 1) +#define LRADC_CTRL1_LRADC0_IRQ (1 << 0) + +#define LRADC_CTRL2_DIVIDE_BY_TWO_MASK (0xff << 24) +#define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24 +#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15) +#define LRADC_CTRL2_VTHSENSE_MASK (0x3 << 13) +#define LRADC_CTRL2_VTHSENSE_OFFSET 13 +#define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12) +#define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 (1 << 9) +#define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8) +#define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4) +#define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4 +#define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4) +#define LRADC_CTRL2_TEMP_ISRC1_280 (0xe << 4) +#define LRADC_CTRL2_TEMP_ISRC1_260 (0xd << 4) +#define LRADC_CTRL2_TEMP_ISRC1_240 (0xc << 4) +#define LRADC_CTRL2_TEMP_ISRC1_220 (0xb << 4) +#define LRADC_CTRL2_TEMP_ISRC1_200 (0xa << 4) +#define LRADC_CTRL2_TEMP_ISRC1_180 (0x9 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_160 (0x8 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_140 (0x7 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_120 (0x6 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_100 (0x5 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_80 (0x4 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_60 (0x3 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_40 (0x2 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_20 (0x1 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_ZERO (0x0 << 4) +#define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0) +#define LRADC_CTRL2_TEMP_ISRC0_OFFSET 0 +#define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0) +#define LRADC_CTRL2_TEMP_ISRC0_280 (0xe << 0) +#define LRADC_CTRL2_TEMP_ISRC0_260 (0xd << 0) +#define LRADC_CTRL2_TEMP_ISRC0_240 (0xc << 0) +#define LRADC_CTRL2_TEMP_ISRC0_220 (0xb << 0) +#define LRADC_CTRL2_TEMP_ISRC0_200 (0xa << 0) +#define LRADC_CTRL2_TEMP_ISRC0_180 (0x9 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_160 (0x8 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_140 (0x7 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_120 (0x6 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_100 (0x5 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_80 (0x4 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_60 (0x3 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_40 (0x2 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_20 (0x1 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_ZERO (0x0 << 0) + +#define LRADC_CTRL3_DISCARD_MASK (0x3 << 24) +#define LRADC_CTRL3_DISCARD_OFFSET 24 +#define LRADC_CTRL3_DISCARD_1_SAMPLE (0x1 << 24) +#define LRADC_CTRL3_DISCARD_2_SAMPLES (0x2 << 24) +#define LRADC_CTRL3_DISCARD_3_SAMPLES (0x3 << 24) +#define LRADC_CTRL3_FORCE_ANALOG_PWUP (1 << 23) +#define LRADC_CTRL3_FORCE_ANALOG_PWDN (1 << 22) +#define LRADC_CTRL3_CYCLE_TIME_MASK (0x3 << 8) +#define LRADC_CTRL3_CYCLE_TIME_OFFSET 8 +#define LRADC_CTRL3_CYCLE_TIME_6MHZ (0x0 << 8) +#define LRADC_CTRL3_CYCLE_TIME_4MHZ (0x1 << 8) +#define LRADC_CTRL3_CYCLE_TIME_3MHZ (0x2 << 8) +#define LRADC_CTRL3_CYCLE_TIME_2MHZ (0x3 << 8) +#define LRADC_CTRL3_HIGH_TIME_MASK (0x3 << 4) +#define LRADC_CTRL3_HIGH_TIME_OFFSET 4 +#define LRADC_CTRL3_HIGH_TIME_42NS (0x0 << 4) +#define LRADC_CTRL3_HIGH_TIME_83NS (0x1 << 4) +#define LRADC_CTRL3_HIGH_TIME_125NS (0x2 << 4) +#define LRADC_CTRL3_HIGH_TIME_250NS (0x3 << 4) +#define LRADC_CTRL3_DELAY_CLOCK (1 << 1) +#define LRADC_CTRL3_INVERT_CLOCK (1 << 0) + +#define LRADC_STATUS_BUTTON1_PRESENT (1 << 28) +#define LRADC_STATUS_BUTTON0_PRESENT (1 << 27) +#define LRADC_STATUS_TEMP1_PRESENT (1 << 26) +#define LRADC_STATUS_TEMP0_PRESENT (1 << 25) +#define LRADC_STATUS_TOUCH_PANEL_PRESENT (1 << 24) +#define LRADC_STATUS_CHANNEL7_PRESENT (1 << 23) +#define LRADC_STATUS_CHANNEL6_PRESENT (1 << 22) +#define LRADC_STATUS_CHANNEL5_PRESENT (1 << 21) +#define LRADC_STATUS_CHANNEL4_PRESENT (1 << 20) +#define LRADC_STATUS_CHANNEL3_PRESENT (1 << 19) +#define LRADC_STATUS_CHANNEL2_PRESENT (1 << 18) +#define LRADC_STATUS_CHANNEL1_PRESENT (1 << 17) +#define LRADC_STATUS_CHANNEL0_PRESENT (1 << 16) +#define LRADC_STATUS_BUTTON1_DETECT_RAW (1 << 2) +#define LRADC_STATUS_BUTTON0_DETECT_RAW (1 << 1) +#define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0) + +#define LRADC_CH_TOGGLE (1 << 31) +#define LRADC_CH7_TESTMODE_TOGGLE (1 << 30) +#define LRADC_CH_ACCUMULATE (1 << 29) +#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) +#define LRADC_CH_NUM_SAMPLES_OFFSET 24 +#define LRADC_CH_VALUE_MASK 0x3ffff +#define LRADC_CH_VALUE_OFFSET 0 + +#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24) +#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 +#define LRADC_DELAY_KICK (1 << 20) +#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) +#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 +#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) +#define LRADC_DELAY_LOOP_COUNT_OFFSET 11 +#define LRADC_DELAY_DELAY_MASK 0x7ff +#define LRADC_DELAY_DELAY_OFFSET 0 + +#define LRADC_DEBUG0_READONLY_MASK (0xffff << 16) +#define LRADC_DEBUG0_READONLY_OFFSET 16 +#define LRADC_DEBUG0_STATE_MASK (0xfff << 0) +#define LRADC_DEBUG0_STATE_OFFSET 0 + +#define LRADC_DEBUG1_REQUEST_MASK (0xff << 16) +#define LRADC_DEBUG1_REQUEST_OFFSET 16 +#define LRADC_DEBUG1_TESTMODE_COUNT_MASK (0x1f << 8) +#define LRADC_DEBUG1_TESTMODE_COUNT_OFFSET 8 +#define LRADC_DEBUG1_TESTMODE6 (1 << 2) +#define LRADC_DEBUG1_TESTMODE5 (1 << 1) +#define LRADC_DEBUG1_TESTMODE (1 << 0) + +#define LRADC_CONVERSION_AUTOMATIC (1 << 20) +#define LRADC_CONVERSION_SCALE_FACTOR_MASK (0x3 << 16) +#define LRADC_CONVERSION_SCALE_FACTOR_OFFSET 16 +#define LRADC_CONVERSION_SCALE_FACTOR_NIMH (0x0 << 16) +#define LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH (0x1 << 16) +#define LRADC_CONVERSION_SCALE_FACTOR_LI_ION (0x2 << 16) +#define LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION (0x3 << 16) +#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK 0x3ff +#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET 0 + +#define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28) +#define LRADC_CTRL4_LRADC7SELECT_OFFSET 28 +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL0 (0x0 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL1 (0x1 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL2 (0x2 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL3 (0x3 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL4 (0x4 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL5 (0x5 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL6 (0x6 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL7 (0x7 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL8 (0x8 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL9 (0x9 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL10 (0xa << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL11 (0xb << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL12 (0xc << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL13 (0xd << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL14 (0xe << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28) +#define LRADC_CTRL4_LRADC6SELECT_MASK (0xf << 24) +#define LRADC_CTRL4_LRADC6SELECT_OFFSET 24 +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL0 (0x0 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL1 (0x1 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL2 (0x2 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL3 (0x3 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL4 (0x4 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL5 (0x5 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL6 (0x6 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL7 (0x7 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL8 (0x8 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL9 (0x9 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL10 (0xa << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL11 (0xb << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL12 (0xc << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL13 (0xd << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL14 (0xe << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL15 (0xf << 24) +#define LRADC_CTRL4_LRADC5SELECT_MASK (0xf << 20) +#define LRADC_CTRL4_LRADC5SELECT_OFFSET 20 +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL0 (0x0 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL1 (0x1 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL2 (0x2 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL3 (0x3 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL4 (0x4 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL5 (0x5 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL6 (0x6 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL7 (0x7 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL8 (0x8 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL9 (0x9 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL10 (0xa << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL11 (0xb << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL12 (0xc << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL13 (0xd << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL14 (0xe << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL15 (0xf << 20) +#define LRADC_CTRL4_LRADC4SELECT_MASK (0xf << 16) +#define LRADC_CTRL4_LRADC4SELECT_OFFSET 16 +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL0 (0x0 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL1 (0x1 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL2 (0x2 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL3 (0x3 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL4 (0x4 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL5 (0x5 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL6 (0x6 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL7 (0x7 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL8 (0x8 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL9 (0x9 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL10 (0xa << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL11 (0xb << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL12 (0xc << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL13 (0xd << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL14 (0xe << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL15 (0xf << 16) +#define LRADC_CTRL4_LRADC3SELECT_MASK (0xf << 12) +#define LRADC_CTRL4_LRADC3SELECT_OFFSET 12 +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL0 (0x0 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL1 (0x1 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL2 (0x2 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL3 (0x3 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL4 (0x4 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL5 (0x5 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL6 (0x6 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL7 (0x7 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL8 (0x8 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL9 (0x9 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL10 (0xa << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL11 (0xb << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL12 (0xc << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL13 (0xd << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL14 (0xe << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL15 (0xf << 12) +#define LRADC_CTRL4_LRADC2SELECT_MASK (0xf << 8) +#define LRADC_CTRL4_LRADC2SELECT_OFFSET 8 +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL0 (0x0 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL1 (0x1 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL2 (0x2 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL3 (0x3 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL4 (0x4 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL5 (0x5 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL6 (0x6 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL7 (0x7 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL8 (0x8 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL9 (0x9 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL10 (0xa << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL11 (0xb << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL12 (0xc << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL13 (0xd << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL14 (0xe << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL15 (0xf << 8) +#define LRADC_CTRL4_LRADC1SELECT_MASK (0xf << 4) +#define LRADC_CTRL4_LRADC1SELECT_OFFSET 4 +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL0 (0x0 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL1 (0x1 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL2 (0x2 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL3 (0x3 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL4 (0x4 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL5 (0x5 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL6 (0x6 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL7 (0x7 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL8 (0x8 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL9 (0x9 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL10 (0xa << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL11 (0xb << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL12 (0xc << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL13 (0xd << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL14 (0xe << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL15 (0xf << 4) +#define LRADC_CTRL4_LRADC0SELECT_MASK 0xf +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL0 (0x0 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL1 (0x1 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL2 (0x2 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL3 (0x3 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL4 (0x4 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL5 (0x5 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL6 (0x6 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL7 (0x7 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL8 (0x8 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL9 (0x9 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL10 (0xa << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL11 (0xb << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL12 (0xc << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL13 (0xd << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL14 (0xe << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL15 (0xf << 0) + +#define LRADC_THRESHOLD_ENABLE (1 << 24) +#define LRADC_THRESHOLD_BATTCHRG_DISABLE (1 << 23) +#define LRADC_THRESHOLD_CHANNEL_SEL_MASK (0x7 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_OFFSET 20 +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0 (0x0 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1 (0x1 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2 (0x2 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3 (0x3 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4 (0x4 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5 (0x5 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6 (0x6 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7 (0x7 << 20) +#define LRADC_THRESHOLD_SETTING_MASK (0x3 << 18) +#define LRADC_THRESHOLD_SETTING_OFFSET 18 +#define LRADC_THRESHOLD_SETTING_NO_COMPARE (0x0 << 18) +#define LRADC_THRESHOLD_SETTING_DETECT_LOW (0x1 << 18) +#define LRADC_THRESHOLD_SETTING_DETECT_HIGH (0x2 << 18) +#define LRADC_THRESHOLD_SETTING_RESERVED (0x3 << 18) +#define LRADC_THRESHOLD_VALUE_MASK 0x3ffff +#define LRADC_THRESHOLD_VALUE_OFFSET 0 + +#define LRADC_VERSION_MAJOR_MASK (0xff << 24) +#define LRADC_VERSION_MAJOR_OFFSET 24 +#define LRADC_VERSION_MINOR_MASK (0xff << 16) +#define LRADC_VERSION_MINOR_OFFSET 16 +#define LRADC_VERSION_STEP_MASK 0xffff +#define LRADC_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_LRADC_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h index 15d8de31ee..e701c6409e 100644 --- a/arch/arm/include/asm/arch-mx28/sys_proto.h +++ b/arch/arm/include/asm/arch-mx28/sys_proto.h @@ -39,6 +39,36 @@ void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, const unsigned int iomux_size); #endif +struct mx28_pair { + uint8_t boot_pads; + uint8_t boot_mask; + const char *mode; +}; + +static const struct mx28_pair mx28_boot_modes[] = { + { 0x00, 0x0f, "USB #0" }, + { 0x01, 0x1f, "I2C #0, master, 3V3" }, + { 0x11, 0x1f, "I2C #0, master, 1V8" }, + { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" }, + { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" }, + { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" }, + { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, + { 0x04, 0x1f, "NAND, 3V3" }, + { 0x14, 0x1f, "NAND, 1V8" }, + { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, + { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, + { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, + { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" }, + { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" }, + { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" }, + { 0x00, 0x00, "Reserved/Unknown/Wrong" }, +}; + +struct mx28_spl_data { + uint8_t boot_mode_idx; + uint32_t mem_dram_size; +}; + int mx28_dram_init(void); #endif /* __MX28_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index ea972a3985..35ee8155de 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -32,6 +32,10 @@ enum mxc_clock { MXC_UART_CLK, MXC_CSPI_CLK, MXC_FEC_CLK, + MXC_SATA_CLK, + MXC_DDR_CLK, + MXC_NFC_CLK, + MXC_PERIPH_CLK, }; unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); @@ -39,10 +43,11 @@ unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); - +int mxc_set_clock(u32 ref, u32 freq, u32 clk_type); void set_usb_phy2_clk(void); void enable_usb_phy2_clk(unsigned char enable); void set_usboh3_clk(void); void enable_usboh3_clk(unsigned char enable); +void mxc_set_sata_internal_clock(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index bdeafbc0df..4e0fc1bc1d 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -76,6 +76,9 @@ struct mxc_ccm_reg { u32 CCGR4; u32 CCGR5; u32 CCGR6; /* 0x0080 */ +#ifdef CONFIG_MX53 + u32 CCGR7; /* 0x0084 */ +#endif u32 cmeor; }; @@ -84,6 +87,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 /* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 4fa66587a0..cef419077e 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -43,6 +43,7 @@ #define NFC_BASE_ADDR_AXI 0xF7FF0000 #define IRAM_BASE_ADDR 0xF8000000 #define CS1_BASE_ADDR 0xF4000000 +#define SATA_BASE_ADDR 0x10000000 #else #error "CPU_TYPE not defined" #endif @@ -93,6 +94,7 @@ #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) +#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) #endif /* * AIPS 2 @@ -133,6 +135,10 @@ #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) +#if defined(CONFIG_MX53) +#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) +#endif + /* * WEIM CSnGCR1 */ @@ -485,6 +491,11 @@ struct iim_regs { } bank[4]; }; +struct fuse_bank0_regs { + u32 fuse0_23[24]; + u32 gp[8]; +}; + struct fuse_bank1_regs { u32 fuse0_8[9]; u32 mac_addr[6]; diff --git a/arch/arm/include/asm/arch-mx5/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h index 760371b48f..e3765a37e3 100644 --- a/arch/arm/include/asm/arch-mx5/iomux.h +++ b/arch/arm/include/asm/arch-mx5/iomux.h @@ -66,8 +66,8 @@ typedef enum iomux_pad_config { PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */ PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */ PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */ - PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */ - PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */ + PAD_CTL_DRV_VOT_LOW = 0x1 << 13, /* Low voltage mode */ + PAD_CTL_DRV_VOT_HIGH = 0x0 << 13,/* High voltage mode */ } iomux_pad_config_t; /* various IOMUX input functions */ diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index 13d12ee1a4..7b5246eea6 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -35,5 +35,8 @@ void set_chipselect_size(int const); */ int fecmxc_initialize(bd_t *bis); +u32 get_ahb_clk(void); +u32 get_periph_clk(void); +char *get_reset_cause(void); #endif diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 613809bdd6..b91d8bf450 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -47,5 +47,6 @@ u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); void enable_usboh3_clk(unsigned char enable); +int enable_sata_clock(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/ccm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 4af0b90164..0e605c26f5 100644 --- a/arch/arm/include/asm/arch-mx6/ccm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -20,7 +20,7 @@ #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ -struct imx_ccm_reg { +struct mxc_ccm_reg { u32 ccr; /* 0x0000 */ u32 ccdr; u32 csr; diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 6d25c8d983..e165810ddc 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -436,5 +436,14 @@ struct anatop_regs { u32 digprog; /* 0x260 */ }; +struct iomuxc_base_regs { + u32 gpr[14]; /* 0x000 */ + u32 obsrv[5]; /* 0x038 */ + u32 swmux_ctl[197]; /* 0x04c */ + u32 swpad_ctl[250]; /* 0x360 */ + u32 swgrp[26]; /* 0x748 */ + u32 daisy[104]; /* 0x7b0..94c */ +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/iomux-v3.h b/arch/arm/include/asm/arch-mx6/iomux-v3.h index 4558f4fba2..788b413219 100644 --- a/arch/arm/include/asm/arch-mx6/iomux-v3.h +++ b/arch/arm/include/asm/arch-mx6/iomux-v3.h @@ -100,4 +100,115 @@ typedef u64 iomux_v3_cfg_t; int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); +/* + * IOMUXC_GPR13 bit fields + */ +#define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30) +#define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29) +#define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28) +#define IOMUXC_GPR13_ENET_STOP_REQ (1<<27) +#define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24) +#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19) +#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16 +#define IOMUXC_GPR13_SATA_PHY_6_MASK (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) +#define IOMUXC_GPR13_SATA_SPEED_MASK (1<<15) +#define IOMUXC_GPR13_SATA_PHY_5_MASK (1<<14) +#define IOMUXC_GPR13_SATA_PHY_4_MASK (7<<11) +#define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f<<7) +#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2) +#define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0) + +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111<<24) + +#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19) + +#define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15) +#define IOMUXC_GPR13_SATA_SPEED_3G (1<<15) + +#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0<<14) +#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1<<14) + +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0<<11) +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1<<11) +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2<<11) +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3<<11) +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11) +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11) + +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111<<7) + +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111<<2) + +#define IOMUXC_GPR13_SATA_PHY_1_FAST 0 +#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1 +#define IOMUXC_GPR13_SATA_PHY_1_SLOW 2 + +#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \ + |IOMUXC_GPR13_SATA_PHY_7_MASK \ + |IOMUXC_GPR13_SATA_PHY_6_MASK \ + |IOMUXC_GPR13_SATA_SPEED_MASK \ + |IOMUXC_GPR13_SATA_PHY_5_MASK \ + |IOMUXC_GPR13_SATA_PHY_4_MASK \ + |IOMUXC_GPR13_SATA_PHY_3_MASK \ + |IOMUXC_GPR13_SATA_PHY_2_MASK \ + |IOMUXC_GPR13_SATA_PHY_1_MASK) + #endif /* __MACH_IOMUX_V3_H__*/ diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 668e77af6a..711b30dfe2 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -28,11 +28,14 @@ u32 get_cpu_rev(void); +void set_vddsoc(u32 mv); + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() */ int fecmxc_initialize(bd_t *bis); - +u32 get_ahb_clk(void); +u32 get_periph_clk(void); #endif diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 84308e04b3..457f99d2c5 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -474,12 +474,11 @@ struct prm { u8 res3[0x1c]; u32 clksrc_ctrl; /* 0x1270 */ }; -#else /* __ASSEMBLY__ */ -#define PRM_RSTCTRL 0x48307250 -#define PRM_RSTCTRL_RESET 0x04 #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ +#define PRM_RSTCTRL 0x48307250 +#define PRM_RSTCTRL_RESET 0x04 #define SYSCLKDIV_1 (0x1 << 6) #define SYSCLKDIV_2 (0x1 << 7) diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h index f8c42c0d20..3ce1f07b8a 100644 --- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h @@ -33,7 +33,9 @@ typedef struct t2 { unsigned int devconf0; /* 0x274 */ unsigned char res2[0x060]; /* 0x278 */ unsigned int devconf1; /* 0x2D8 */ - unsigned char res3[0x244]; /* 0x2DC */ + unsigned char res3[0x16C]; /* 0x2DC */ + unsigned int ctl_prog_io1; /* 0x448 */ + unsigned char res4[0x0D4]; /* 0x44C */ unsigned int pbias_lite; /* 0x520 */ } t2_t; @@ -48,6 +50,8 @@ typedef struct t2 { #define PBIASSPEEDCTRL0 (1 << 2) #define PBIASLITEPWRDNZ1 (1 << 9) +#define CTLPROGIO1SPEEDCTRL (1 << 20) + /* * OMAP HSMMC register definitions */ @@ -191,6 +195,6 @@ struct hsmmc { #define mmc_reg_out(addr, mask, val)\ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) -int omap_mmc_init(int dev_index); +int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index 6daef49e97..71f183de8d 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h @@ -445,6 +445,12 @@ #define CONTROL_PADCONF_STRBEN_DLY1 0x0224 #define CONTROL_PADCONF_SYS_BOOT8 0x0226 +/* AM/DM37xx specific */ +#define CONTROL_PADCONF_GPIO127 0x0A54 +#define CONTROL_PADCONF_GPIO126 0x0A56 +#define CONTROL_PADCONF_GPIO128 0x0A58 +#define CONTROL_PADCONF_GPIO129 0x0A5A + #define MUX_VAL(OFFSET,VALUE)\ writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index cd304e8684..617729c32b 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -652,23 +652,9 @@ struct omap4_scrm_regs { #define OMAP_SYS_CLK_IND_38_4_MHZ 6 #define OMAP_32K_CLK_FREQ 32768 -/* PRM_VC_CFG_I2C_CLK */ -#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 -#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF -#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 -#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) - /* PRM_VC_VAL_BYPASS */ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 -#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000 -#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 -#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F -#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 -#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF -#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 -#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF - /* SMPS */ #define SMPS_I2C_SLAVE_ADDR 0x12 #define SMPS_REG_ADDR_VCORE1 0x55 @@ -754,10 +740,10 @@ extern struct omap4_prcm_regs *const prcm; extern const u32 sys_clk_array[8]; void scale_vcores(void); -void do_scale_tps62361(u32 reg, u32 volt_mv); +void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv); +u32 get_offset_code(u32 offset); u32 omap_ddr_clk(void); void do_scale_vcore(u32 vcore_reg, u32 volt_mv); -void setup_sri2c(void); void setup_post_dividers(u32 *const base, const struct dpll_params *params); u32 get_sys_clk_index(void); void enable_basic_clocks(void); diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index 08b9c99353..feddb7de51 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -168,4 +168,15 @@ struct watchdog { #define OMAP_GPIO_CLEARDATAOUT 0x0190 #define OMAP_GPIO_SETDATAOUT 0x0194 +/* + * PRCM + */ + +/* PRM */ +#define PRM_BASE 0x4A306000 +#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) + +#define PRM_RSTCTRL PRM_DEVICE_BASE +#define PRM_RSTCTRL_RESET 0x01 + #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h index ce1bce1fdd..2114046e71 100644 --- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h @@ -169,6 +169,6 @@ struct hsmmc { #define mmc_reg_out(addr, mask, val)\ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) -int omap_mmc_init(int dev_index); +int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap4/mux_omap4.h b/arch/arm/include/asm/arch-omap4/mux_omap4.h index 30bfad7c20..4de7c70bf6 100644 --- a/arch/arm/include/asm/arch-omap4/mux_omap4.h +++ b/arch/arm/include/asm/arch-omap4/mux_omap4.h @@ -34,7 +34,7 @@ struct pad_conf_entry { u16 val; -} __attribute__ ((packed)); +}; #ifdef CONFIG_OFF_PADCONF #define OFF_PD (1 << 12) diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 416c6de314..47c5883025 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -101,17 +101,6 @@ #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) -/* - * PRCM - */ - -/* PRM */ -#define PRM_BASE 0x4A306000 -#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) - -#define PRM_RSTCTRL PRM_DEVICE_BASE -#define PRM_RSTCTRL_RESET 0x01 - /* Control Module */ #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f @@ -139,18 +128,24 @@ struct s32ktimer { unsigned int s32k_cr; /* 0x10 */ }; -struct omap4_sys_ctrl_regs { +#define DEVICE_TYPE_SHIFT (0x8) +#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) +#define DEVICE_GP 0x3 + +struct omap_sys_ctrl_regs { unsigned int pad1[129]; unsigned int control_id_code; /* 0x4A002204 */ unsigned int pad11[22]; unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */ - unsigned int pad2[47]; + unsigned int pad2[24]; /* 0x4a002264 */ + unsigned int control_status; /* 0x4a0022c4 */ + unsigned int pad3[22]; /* 0x4a0022c8 */ unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */ unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */ unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */ - unsigned int pad3[260277]; + unsigned int pad4[260277]; unsigned int control_pbiaslite; /* 0x4A100600 */ - unsigned int pad4[63]; + unsigned int pad5[63]; unsigned int control_efuse_1; /* 0x4A100700 */ unsigned int control_efuse_2; /* 0x4A100704 */ }; diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index b8dbc2c9a2..c6e3ad26ff 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -55,6 +55,8 @@ u32 omap_sdram_size(void); u32 cortex_rev(void); void init_omap_revision(void); void do_io_settings(void); +void omap_vc_init(u16 speed_khz); +int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); /* * This is used to verify if the configuration header * was executed by Romcode prior to control of transfer @@ -112,10 +114,4 @@ static inline u32 omap_hw_init_context(void) #endif } -static inline u32 omap_revision(void) -{ - extern u32 *const omap4_revision; - return *omap4_revision; -} - #endif diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index d0e6dd68da..f32cf3eeef 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -473,9 +473,11 @@ struct omap5_prcm_regs { u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */ u32 pad214; /* 4ae07884 */ u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */ - u32 pad215[197]; /* 4ae0788c */ + u32 pad215[1]; /* 4ae0788c */ + u32 cm_wkupaon_scrm_clkctrl; /* 4ae07890 */ + u32 pad216[195]; u32 prm_vc_val_bypass; /* 4ae07ba0 */ - u32 pad216[4]; + u32 pad217[4]; u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */ u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */ }; @@ -514,6 +516,10 @@ struct omap5_prcm_regs { /* CM_IDLEST_DPLL fields */ #define ST_DPLL_CLK_MASK 1 +/* SGX */ +#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) +#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) + /* CM_CLKSEL_DPLL */ #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) @@ -591,6 +597,7 @@ struct omap5_prcm_regs { /* CM_L3INIT_HSMMCn_CLKCTRL */ #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) +#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) /* CM_WKUP_GPTIMER1_CLKCTRL */ #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) @@ -610,36 +617,33 @@ struct omap5_prcm_regs { #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) +/* CM_WKUPAON_SCRM_CLKCTRL */ +#define OPTFCLKEN_SCRM_PER_SHIFT 9 +#define OPTFCLKEN_SCRM_PER_MASK (1 << 9) +#define OPTFCLKEN_SCRM_CORE_SHIFT 8 +#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) + /* Clock frequencies */ #define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 #define OMAP_32K_CLK_FREQ 32768 -/* PRM_VC_CFG_I2C_CLK */ -#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 -#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF -#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 -#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) - /* PRM_VC_VAL_BYPASS */ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 -#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000 -#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 -#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F -#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 -#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF -#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 -#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF - /* SMPS */ #define SMPS_I2C_SLAVE_ADDR 0x12 -#define SMPS_REG_ADDR_VCORE1 0x55 -#define SMPS_REG_ADDR_VCORE2 0x5B -#define SMPS_REG_ADDR_VCORE3 0x61 +#define SMPS_REG_ADDR_12_MPU 0x23 +#define SMPS_REG_ADDR_45_IVA 0x2B +#define SMPS_REG_ADDR_8_CORE 0x37 + +/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ +#define VDD_MPU 1000 +#define VDD_MM 1000 +#define VDD_CORE 1040 -#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 -#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 +/* Standard offset is 0.5v expressed in uv */ +#define PALMAS_SMPS_BASE_VOLT_UV 500000 /* TPS */ #define TPS62361_I2C_SLAVE_ADDR 0x60 @@ -677,7 +681,7 @@ struct dpll_regs { u32 cm_div_h12_dpll; u32 cm_div_h13_dpll; u32 cm_div_h14_dpll; - u32 reserved[2]; + u32 reserved[3]; u32 cm_div_h22_dpll; u32 cm_div_h23_dpll; }; @@ -700,10 +704,10 @@ extern struct omap5_prcm_regs *const prcm; extern const u32 sys_clk_array[8]; void scale_vcores(void); -void do_scale_tps62361(u32 reg, u32 volt_mv); +void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv); +u32 get_offset_code(u32 offset); u32 omap_ddr_clk(void); void do_scale_vcore(u32 vcore_reg, u32 volt_mv); -void setup_sri2c(void); void setup_post_dividers(u32 *const base, const struct dpll_params *params); u32 get_sys_clk_index(void); void enable_basic_clocks(void); diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 0697a732de..8ef17c9a14 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -172,4 +172,15 @@ struct watchdog { #define OMAP_GPIO_CLEARDATAOUT 0x0190 #define OMAP_GPIO_SETDATAOUT 0x0194 +/* + * PRCM + */ + +/* PRM */ +#define PRM_BASE 0x4AE06000 +#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) + +#define PRM_RSTCTRL PRM_DEVICE_BASE +#define PRM_RSTCTRL_RESET 0x01 + #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h index ce1bce1fdd..2114046e71 100644 --- a/arch/arm/include/asm/arch-omap5/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h @@ -169,6 +169,6 @@ struct hsmmc { #define mmc_reg_out(addr, mask, val)\ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) -int omap_mmc_init(int dev_index); +int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h index b8c21853f0..4a6ed8b455 100644 --- a/arch/arm/include/asm/arch-omap5/mux_omap5.h +++ b/arch/arm/include/asm/arch-omap5/mux_omap5.h @@ -34,7 +34,7 @@ struct pad_conf_entry { u16 val; -} __attribute__ ((__packed__)); +}; #ifdef CONFIG_OFF_PADCONF #define OFF_PD (1 << 12) @@ -87,258 +87,256 @@ struct pad_conf_entry { #define CORE_REVISION 0x0000 #define CORE_HWINFO 0x0004 #define CORE_SYSCONFIG 0x0010 -#define GPMC_AD0 0x0040 -#define GPMC_AD1 0x0042 -#define GPMC_AD2 0x0044 -#define GPMC_AD3 0x0046 -#define GPMC_AD4 0x0048 -#define GPMC_AD5 0x004A -#define GPMC_AD6 0x004C -#define GPMC_AD7 0x004E -#define GPMC_AD8 0x0050 -#define GPMC_AD9 0x0052 -#define GPMC_AD10 0x0054 -#define GPMC_AD11 0x0056 -#define GPMC_AD12 0x0058 -#define GPMC_AD13 0x005A -#define GPMC_AD14 0x005C -#define GPMC_AD15 0x005E -#define GPMC_A16 0x0060 -#define GPMC_A17 0x0062 -#define GPMC_A18 0x0064 -#define GPMC_A19 0x0066 -#define GPMC_A20 0x0068 -#define GPMC_A21 0x006A -#define GPMC_A22 0x006C -#define GPMC_A23 0x006E -#define GPMC_A24 0x0070 -#define GPMC_A25 0x0072 -#define GPMC_NCS0 0x0074 -#define GPMC_NCS1 0x0076 -#define GPMC_NCS2 0x0078 -#define GPMC_NCS3 0x007A -#define GPMC_NWP 0x007C -#define GPMC_CLK 0x007E -#define GPMC_NADV_ALE 0x0080 -#define GPMC_NOE 0x0082 -#define GPMC_NWE 0x0084 -#define GPMC_NBE0_CLE 0x0086 -#define GPMC_NBE1 0x0088 -#define GPMC_WAIT0 0x008A -#define GPMC_WAIT1 0x008C -#define C2C_DATA11 0x008E -#define C2C_DATA12 0x0090 -#define C2C_DATA13 0x0092 -#define C2C_DATA14 0x0094 -#define C2C_DATA15 0x0096 -#define HDMI_HPD 0x0098 -#define HDMI_CEC 0x009A -#define HDMI_DDC_SCL 0x009C -#define HDMI_DDC_SDA 0x009E -#define CSI21_DX0 0x00A0 -#define CSI21_DY0 0x00A2 -#define CSI21_DX1 0x00A4 -#define CSI21_DY1 0x00A6 -#define CSI21_DX2 0x00A8 -#define CSI21_DY2 0x00AA -#define CSI21_DX3 0x00AC -#define CSI21_DY3 0x00AE -#define CSI21_DX4 0x00B0 -#define CSI21_DY4 0x00B2 -#define CSI22_DX0 0x00B4 -#define CSI22_DY0 0x00B6 -#define CSI22_DX1 0x00B8 -#define CSI22_DY1 0x00BA -#define CAM_SHUTTER 0x00BC -#define CAM_STROBE 0x00BE -#define CAM_GLOBALRESET 0x00C0 -#define USBB1_ULPITLL_CLK 0x00C2 -#define USBB1_ULPITLL_STP 0x00C4 -#define USBB1_ULPITLL_DIR 0x00C6 -#define USBB1_ULPITLL_NXT 0x00C8 -#define USBB1_ULPITLL_DAT0 0x00CA -#define USBB1_ULPITLL_DAT1 0x00CC -#define USBB1_ULPITLL_DAT2 0x00CE -#define USBB1_ULPITLL_DAT3 0x00D0 -#define USBB1_ULPITLL_DAT4 0x00D2 -#define USBB1_ULPITLL_DAT5 0x00D4 -#define USBB1_ULPITLL_DAT6 0x00D6 -#define USBB1_ULPITLL_DAT7 0x00D8 -#define USBB1_HSIC_DATA 0x00DA -#define USBB1_HSIC_STROBE 0x00DC -#define USBC1_ICUSB_DP 0x00DE -#define USBC1_ICUSB_DM 0x00E0 -#define SDMMC1_CLK 0x00E2 -#define SDMMC1_CMD 0x00E4 -#define SDMMC1_DAT0 0x00E6 -#define SDMMC1_DAT1 0x00E8 -#define SDMMC1_DAT2 0x00EA -#define SDMMC1_DAT3 0x00EC -#define SDMMC1_DAT4 0x00EE -#define SDMMC1_DAT5 0x00F0 -#define SDMMC1_DAT6 0x00F2 -#define SDMMC1_DAT7 0x00F4 -#define ABE_MCBSP2_CLKX 0x00F6 -#define ABE_MCBSP2_DR 0x00F8 -#define ABE_MCBSP2_DX 0x00FA -#define ABE_MCBSP2_FSX 0x00FC -#define ABE_MCBSP1_CLKX 0x00FE -#define ABE_MCBSP1_DR 0x0100 -#define ABE_MCBSP1_DX 0x0102 -#define ABE_MCBSP1_FSX 0x0104 -#define ABE_PDM_UL_DATA 0x0106 -#define ABE_PDM_DL_DATA 0x0108 -#define ABE_PDM_FRAME 0x010A -#define ABE_PDM_LB_CLK 0x010C -#define ABE_CLKS 0x010E -#define ABE_DMIC_CLK1 0x0110 -#define ABE_DMIC_DIN1 0x0112 -#define ABE_DMIC_DIN2 0x0114 -#define ABE_DMIC_DIN3 0x0116 -#define UART2_CTS 0x0118 -#define UART2_RTS 0x011A -#define UART2_RX 0x011C -#define UART2_TX 0x011E -#define HDQ_SIO 0x0120 -#define I2C1_SCL 0x0122 -#define I2C1_SDA 0x0124 -#define I2C2_SCL 0x0126 -#define I2C2_SDA 0x0128 -#define I2C3_SCL 0x012A -#define I2C3_SDA 0x012C -#define I2C4_SCL 0x012E -#define I2C4_SDA 0x0130 -#define MCSPI1_CLK 0x0132 -#define MCSPI1_SOMI 0x0134 -#define MCSPI1_SIMO 0x0136 -#define MCSPI1_CS0 0x0138 -#define MCSPI1_CS1 0x013A -#define MCSPI1_CS2 0x013C -#define MCSPI1_CS3 0x013E -#define UART3_CTS_RCTX 0x0140 -#define UART3_RTS_SD 0x0142 -#define UART3_RX_IRRX 0x0144 -#define UART3_TX_IRTX 0x0146 -#define SDMMC5_CLK 0x0148 -#define SDMMC5_CMD 0x014A -#define SDMMC5_DAT0 0x014C -#define SDMMC5_DAT1 0x014E -#define SDMMC5_DAT2 0x0150 -#define SDMMC5_DAT3 0x0152 -#define MCSPI4_CLK 0x0154 -#define MCSPI4_SIMO 0x0156 -#define MCSPI4_SOMI 0x0158 -#define MCSPI4_CS0 0x015A -#define UART4_RX 0x015C -#define UART4_TX 0x015E -#define USBB2_ULPITLL_CLK 0x0160 -#define USBB2_ULPITLL_STP 0x0162 -#define USBB2_ULPITLL_DIR 0x0164 -#define USBB2_ULPITLL_NXT 0x0166 -#define USBB2_ULPITLL_DAT0 0x0168 -#define USBB2_ULPITLL_DAT1 0x016A -#define USBB2_ULPITLL_DAT2 0x016C -#define USBB2_ULPITLL_DAT3 0x016E -#define USBB2_ULPITLL_DAT4 0x0170 -#define USBB2_ULPITLL_DAT5 0x0172 -#define USBB2_ULPITLL_DAT6 0x0174 -#define USBB2_ULPITLL_DAT7 0x0176 -#define USBB2_HSIC_DATA 0x0178 -#define USBB2_HSIC_STROBE 0x017A -#define UNIPRO_TX0 0x017C -#define UNIPRO_TY0 0x017E -#define UNIPRO_TX1 0x0180 -#define UNIPRO_TY1 0x0182 -#define UNIPRO_TX2 0x0184 -#define UNIPRO_TY2 0x0186 -#define UNIPRO_RX0 0x0188 -#define UNIPRO_RY0 0x018A -#define UNIPRO_RX1 0x018C -#define UNIPRO_RY1 0x018E -#define UNIPRO_RX2 0x0190 -#define UNIPRO_RY2 0x0192 -#define USBA0_OTG_CE 0x0194 -#define USBA0_OTG_DP 0x0196 -#define USBA0_OTG_DM 0x0198 -#define FREF_CLK1_OUT 0x019A -#define FREF_CLK2_OUT 0x019C -#define SYS_NIRQ1 0x019E -#define SYS_NIRQ2 0x01A0 -#define SYS_BOOT0 0x01A2 -#define SYS_BOOT1 0x01A4 -#define SYS_BOOT2 0x01A6 -#define SYS_BOOT3 0x01A8 -#define SYS_BOOT4 0x01AA -#define SYS_BOOT5 0x01AC -#define DPM_EMU0 0x01AE -#define DPM_EMU1 0x01B0 -#define DPM_EMU2 0x01B2 -#define DPM_EMU3 0x01B4 -#define DPM_EMU4 0x01B6 -#define DPM_EMU5 0x01B8 -#define DPM_EMU6 0x01BA -#define DPM_EMU7 0x01BC -#define DPM_EMU8 0x01BE -#define DPM_EMU9 0x01C0 -#define DPM_EMU10 0x01C2 -#define DPM_EMU11 0x01C4 -#define DPM_EMU12 0x01C6 -#define DPM_EMU13 0x01C8 -#define DPM_EMU14 0x01CA -#define DPM_EMU15 0x01CC -#define DPM_EMU16 0x01CE -#define DPM_EMU17 0x01D0 -#define DPM_EMU18 0x01D2 -#define DPM_EMU19 0x01D4 -#define WAKEUPEVENT_0 0x01D8 -#define WAKEUPEVENT_1 0x01DC -#define WAKEUPEVENT_2 0x01E0 -#define WAKEUPEVENT_3 0x01E4 -#define WAKEUPEVENT_4 0x01E8 -#define WAKEUPEVENT_5 0x01EC -#define WAKEUPEVENT_6 0x01F0 +#define EMMC_CLK 0x0040 +#define EMMC_CMD 0x0042 +#define EMMC_DATA0 0x0044 +#define EMMC_DATA1 0x0046 +#define EMMC_DATA2 0x0048 +#define EMMC_DATA3 0x004a +#define EMMC_DATA4 0x004c +#define EMMC_DATA5 0x004e +#define EMMC_DATA6 0x0050 +#define EMMC_DATA7 0x0052 +#define C2C_CLKOUT0 0x0054 +#define C2C_CLKOUT1 0x0056 +#define C2C_CLKIN0 0x0058 +#define C2C_CLKIN1 0x005a +#define C2C_DATAIN0 0x005c +#define C2C_DATAIN1 0x005e +#define C2C_DATAIN2 0x0060 +#define C2C_DATAIN3 0x0062 +#define C2C_DATAIN4 0x0064 +#define C2C_DATAIN5 0x0066 +#define C2C_DATAIN6 0x0068 +#define C2C_DATAIN7 0x006a +#define C2C_DATAOUT0 0x006c +#define C2C_DATAOUT1 0x006e +#define C2C_DATAOUT2 0x0070 +#define C2C_DATAOUT3 0x0072 +#define C2C_DATAOUT4 0x0074 +#define C2C_DATAOUT5 0x0076 +#define C2C_DATAOUT6 0x0078 +#define C2C_DATAOUT7 0x007a +#define C2C_DATA8 0x007c +#define C2C_DATA9 0x007e +#define C2C_DATA10 0x0080 +#define C2C_DATA11 0x0082 +#define C2C_DATA12 0x0084 +#define C2C_DATA13 0x0086 +#define C2C_DATA14 0x0088 +#define C2C_DATA15 0x008a +#define LLIA_WAKEREQOUT 0x008c +#define LLIB_WAKEREQOUT 0x008e +#define HSI1_ACREADY 0x0090 +#define HSI1_CAREADY 0x0092 +#define HSI1_ACWAKE 0x0094 +#define HSI1_CAWAKE 0x0096 +#define HSI1_ACFLAG 0x0098 +#define HSI1_ACDATA 0x009a +#define HSI1_CAFLAG 0x009c +#define HSI1_CADATA 0x009e +#define UART1_TX 0x00a0 +#define UART1_CTS 0x00a2 +#define UART1_RX 0x00a4 +#define UART1_RTS 0x00a6 +#define HSI2_CAREADY 0x00a8 +#define HSI2_ACREADY 0x00aa +#define HSI2_CAWAKE 0x00ac +#define HSI2_ACWAKE 0x00ae +#define HSI2_CAFLAG 0x00b0 +#define HSI2_CADATA 0x00b2 +#define HSI2_ACFLAG 0x00b4 +#define HSI2_ACDATA 0x00b6 +#define UART2_RTS 0x00b8 +#define UART2_CTS 0x00ba +#define UART2_RX 0x00bc +#define UART2_TX 0x00be +#define USBB1_HSIC_STROBE 0x00c0 +#define USBB1_HSIC_DATA 0x00c2 +#define USBB2_HSIC_STROBE 0x00c4 +#define USBB2_HSIC_DATA 0x00c6 +#define TIMER10_PWM_EVT 0x00c8 +#define DSIPORTA_TE0 0x00ca +#define DSIPORTA_LANE0X 0x00cc +#define DSIPORTA_LANE0Y 0x00ce +#define DSIPORTA_LANE1X 0x00d0 +#define DSIPORTA_LANE1Y 0x00d2 +#define DSIPORTA_LANE2X 0x00d4 +#define DSIPORTA_LANE2Y 0x00d6 +#define DSIPORTA_LANE3X 0x00d8 +#define DSIPORTA_LANE3Y 0x00da +#define DSIPORTA_LANE4X 0x00dc +#define DSIPORTA_LANE4Y 0x00de +#define DSIPORTC_LANE0X 0x00e0 +#define DSIPORTC_LANE0Y 0x00e2 +#define DSIPORTC_LANE1X 0x00e4 +#define DSIPORTC_LANE1Y 0x00e6 +#define DSIPORTC_LANE2X 0x00e8 +#define DSIPORTC_LANE2Y 0x00ea +#define DSIPORTC_LANE3X 0x00ec +#define DSIPORTC_LANE3Y 0x00ee +#define DSIPORTC_LANE4X 0x00f0 +#define DSIPORTC_LANE4Y 0x00f2 +#define DSIPORTC_TE0 0x00f4 +#define TIMER9_PWM_EVT 0x00f6 +#define I2C4_SCL 0x00f8 +#define I2C4_SDA 0x00fa +#define MCSPI2_CLK 0x00fc +#define MCSPI2_SIMO 0x00fe +#define MCSPI2_SOMI 0x0100 +#define MCSPI2_CS0 0x0102 +#define RFBI_DATA15 0x0104 +#define RFBI_DATA14 0x0106 +#define RFBI_DATA13 0x0108 +#define RFBI_DATA12 0x010a +#define RFBI_DATA11 0x010c +#define RFBI_DATA10 0x010e +#define RFBI_DATA9 0x0110 +#define RFBI_DATA8 0x0112 +#define RFBI_DATA7 0x0114 +#define RFBI_DATA6 0x0116 +#define RFBI_DATA5 0x0118 +#define RFBI_DATA4 0x011a +#define RFBI_DATA3 0x011c +#define RFBI_DATA2 0x011e +#define RFBI_DATA1 0x0120 +#define RFBI_DATA0 0x0122 +#define RFBI_WE 0x0124 +#define RFBI_CS0 0x0126 +#define RFBI_A0 0x0128 +#define RFBI_RE 0x012a +#define RFBI_HSYNC0 0x012c +#define RFBI_TE_VSYNC0 0x012e +#define GPIO6_182 0x0130 +#define GPIO6_183 0x0132 +#define GPIO6_184 0x0134 +#define GPIO6_185 0x0136 +#define GPIO6_186 0x0138 +#define GPIO6_187 0x013a +#define HDMI_CEC 0x013c +#define HDMI_HPD 0x013e +#define HDMI_DDC_SCL 0x0140 +#define HDMI_DDC_SDA 0x0142 +#define CSIPORTC_LANE0X 0x0144 +#define CSIPORTC_LANE0Y 0x0146 +#define CSIPORTC_LANE1X 0x0148 +#define CSIPORTC_LANE1Y 0x014a +#define CSIPORTB_LANE0X 0x014c +#define CSIPORTB_LANE0Y 0x014e +#define CSIPORTB_LANE1X 0x0150 +#define CSIPORTB_LANE1Y 0x0152 +#define CSIPORTB_LANE2X 0x0154 +#define CSIPORTB_LANE2Y 0x0156 +#define CSIPORTA_LANE0X 0x0158 +#define CSIPORTA_LANE0Y 0x015a +#define CSIPORTA_LANE1X 0x015c +#define CSIPORTA_LANE1Y 0x015e +#define CSIPORTA_LANE2X 0x0160 +#define CSIPORTA_LANE2Y 0x0162 +#define CSIPORTA_LANE3X 0x0164 +#define CSIPORTA_LANE3Y 0x0166 +#define CSIPORTA_LANE4X 0x0168 +#define CSIPORTA_LANE4Y 0x016a +#define CAM_SHUTTER 0x016c +#define CAM_STROBE 0x016e +#define CAM_GLOBALRESET 0x0170 +#define TIMER11_PWM_EVT 0x0172 +#define TIMER5_PWM_EVT 0x0174 +#define TIMER6_PWM_EVT 0x0176 +#define TIMER8_PWM_EVT 0x0178 +#define I2C3_SCL 0x017a +#define I2C3_SDA 0x017c +#define GPIO8_233 0x017e +#define GPIO8_234 0x0180 +#define ABE_CLKS 0x0182 +#define ABEDMIC_DIN1 0x0184 +#define ABEDMIC_DIN2 0x0186 +#define ABEDMIC_DIN3 0x0188 +#define ABEDMIC_CLK1 0x018a +#define ABEDMIC_CLK2 0x018c +#define ABEDMIC_CLK3 0x018e +#define ABESLIMBUS1_CLOCK 0x0190 +#define ABESLIMBUS1_DATA 0x0192 +#define ABEMCBSP2_DR 0x0194 +#define ABEMCBSP2_DX 0x0196 +#define ABEMCBSP2_FSX 0x0198 +#define ABEMCBSP2_CLKX 0x019a +#define ABEMCPDM_UL_DATA 0x019c +#define ABEMCPDM_DL_DATA 0x019e +#define ABEMCPDM_FRAME 0x01a0 +#define ABEMCPDM_LB_CLK 0x01a2 +#define WLSDIO_CLK 0x01a4 +#define WLSDIO_CMD 0x01a6 +#define WLSDIO_DATA0 0x01a8 +#define WLSDIO_DATA1 0x01aa +#define WLSDIO_DATA2 0x01ac +#define WLSDIO_DATA3 0x01ae +#define UART5_RX 0x01b0 +#define UART5_TX 0x01b2 +#define UART5_CTS 0x01b4 +#define UART5_RTS 0x01b6 +#define I2C2_SCL 0x01b8 +#define I2C2_SDA 0x01ba +#define MCSPI1_CLK 0x01bc +#define MCSPI1_SOMI 0x01be +#define MCSPI1_SIMO 0x01c0 +#define MCSPI1_CS0 0x01c2 +#define MCSPI1_CS1 0x01c4 +#define I2C5_SCL 0x01c6 +#define I2C5_SDA 0x01c8 +#define PERSLIMBUS2_CLOCK 0x01ca +#define PERSLIMBUS2_DATA 0x01cc +#define UART6_TX 0x01ce +#define UART6_RX 0x01d0 +#define UART6_CTS 0x01d2 +#define UART6_RTS 0x01d4 +#define UART3_CTS_RCTX 0x01d6 +#define UART3_RTS_IRSD 0x01d8 +#define UART3_TX_IRTX 0x01da +#define UART3_RX_IRRX 0x01dc +#define USBB3_HSIC_STROBE 0x01de +#define USBB3_HSIC_DATA 0x01e0 +#define SDCARD_CLK 0x01e2 +#define SDCARD_CMD 0x01e4 +#define SDCARD_DATA2 0x01e6 +#define SDCARD_DATA3 0x01e8 +#define SDCARD_DATA0 0x01ea +#define SDCARD_DATA1 0x01ec +#define USBD0_HS_DP 0x01ee +#define USBD0_HS_DM 0x01f0 +#define I2C1_PMIC_SCL 0x01f2 +#define I2C1_PMIC_SDA 0x01f4 +#define USBD0_SS_RX 0x01f6 -#define WKUP_REVISION 0x0000 -#define WKUP_HWINFO 0x0004 -#define WKUP_SYSCONFIG 0x0010 -#define PAD0_SIM_IO 0x0040 -#define PAD1_SIM_CLK 0x0042 -#define PAD0_SIM_RESET 0x0044 -#define PAD1_SIM_CD 0x0046 -#define PAD0_SIM_PWRCTRL 0x0048 -#define PAD1_SR_SCL 0x004A -#define PAD0_SR_SDA 0x004C -#define PAD1_FREF_XTAL_IN 0x004E -#define PAD0_FREF_SLICER_IN 0x0050 -#define PAD1_FREF_CLK_IOREQ 0x0052 -#define PAD0_FREF_CLK0_OUT 0x0054 -#define PAD1_FREF_CLK3_REQ 0x0056 -#define PAD0_FREF_CLK3_OUT 0x0058 -#define PAD1_FREF_CLK4_REQ 0x005A -#define PAD0_FREF_CLK4_OUT 0x005C -#define PAD1_SYS_32K 0x005E -#define PAD0_SYS_NRESPWRON 0x0060 -#define PAD1_SYS_NRESWARM 0x0062 -#define PAD0_SYS_PWR_REQ 0x0064 -#define PAD1_SYS_PWRON_RESET 0x0066 -#define PAD0_SYS_BOOT6 0x0068 -#define PAD1_SYS_BOOT7 0x006A -#define PAD0_JTAG_NTRST 0x006C -#define PAD1_JTAG_TCK 0x006D -#define PAD0_JTAG_RTCK 0x0070 -#define PAD1_JTAG_TMS_TMSC 0x0072 -#define PAD0_JTAG_TDI 0x0074 -#define PAD1_JTAG_TDO 0x0076 -#define PADCONF_WAKEUPEVENT_0 0x007C -#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 -#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 -#define PADCONF_MODE 0x05A8 -#define CONTROL_XTAL_OSCILLATOR 0x05AC -#define CONTROL_CONTROL_I2C_2 0x0604 -#define CONTROL_CONTROL_JTAG 0x0608 -#define CONTROL_CONTROL_SYS 0x060C -#define CONTROL_SPARE_RW 0x0614 -#define CONTROL_SPARE_R 0x0618 -#define CONTROL_SPARE_R_C0 0x061C +#define LLIA_WAKEREQIN 0x0040 +#define LLIB_WAKEREQIN 0x0042 +#define DRM_EMU0 0x0044 +#define DRM_EMU1 0x0046 +#define JTAG_NTRST 0x0048 +#define JTAG_TCK 0x004a +#define JTAG_RTCK 0x004c +#define JTAG_TMSC 0x004e +#define JTAG_TDI 0x0050 +#define JTAG_TDO 0x0052 +#define SYS_32K 0x0054 +#define FREF_CLK_IOREQ 0x0056 +#define FREF_CLK0_OUT 0x0058 +#define FREF_CLK1_OUT 0x005a +#define FREF_CLK2_OUT 0x005c +#define FREF_CLK2_REQ 0x005e +#define FREF_CLK1_REQ 0x0060 +#define SYS_NRESPWRON 0x0062 +#define SYS_NRESWARM 0x0064 +#define SYS_PWR_REQ 0x0066 +#define SYS_NIRQ1 0x0068 +#define SYS_NIRQ2 0x006a +#define SR_PMIC_SCL 0x006c +#define SR_PMIC_SDA 0x006e +#define SYS_BOOT0 0x0070 +#define SYS_BOOT1 0x0072 +#define SYS_BOOT2 0x0074 +#define SYS_BOOT3 0x0076 +#define SYS_BOOT4 0x0078 +#define SYS_BOOT5 0x007a #endif /* _MUX_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index d811d6ec23..e3f55d2020 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -98,17 +98,6 @@ #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) -/* - * PRCM - */ - -/* PRM */ -#define PRM_BASE 0x4AE06000 -#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) - -#define PRM_RSTCTRL PRM_DEVICE_BASE -#define PRM_RSTCTRL_RESET 0x01 - /* Control Module */ #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f @@ -125,9 +114,10 @@ /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 -#define MMC1_PWRDNZ (1 << 26) -#define MMC1_PBIASLITE_PWRDNZ (1 << 22) -#define MMC1_PBIASLITE_VMODE (1 << 21) +#define SDCARD_PWRDNZ (1 << 26) +#define SDCARD_BIAS_HIZ_MODE (1 << 25) +#define SDCARD_BIAS_PWRDNZ (1 << 22) +#define SDCARD_PBIASLITE_VMODE (1 << 21) #ifndef __ASSEMBLY__ @@ -136,32 +126,117 @@ struct s32ktimer { unsigned int s32k_cr; /* 0x10 */ }; -struct omap4_sys_ctrl_regs { - unsigned int pad1[129]; - unsigned int control_id_code; /* 0x4A002204 */ - unsigned int pad11[22]; - unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */ - unsigned int pad2[47]; - unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */ - unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */ - unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */ - unsigned int pad3[260277]; - unsigned int control_pbiaslite; /* 0x4A100600 */ - unsigned int pad4[63]; - unsigned int control_efuse_1; /* 0x4A100700 */ - unsigned int control_efuse_2; /* 0x4A100704 */ +#define DEVICE_TYPE_SHIFT 0x6 +#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) +#define DEVICE_GP 0x3 + +struct omap_sys_ctrl_regs { + u32 pad0[77]; /* 0x4A002000 */ + u32 control_status; /* 0x4A002134 */ + u32 pad1[794]; /* 0x4A002138 */ + u32 control_paconf_global; /* 0x4A002DA0 */ + u32 control_paconf_mode; /* 0x4A002DA4 */ + u32 control_smart1io_padconf_0; /* 0x4A002DA8 */ + u32 control_smart1io_padconf_1; /* 0x4A002DAC */ + u32 control_smart1io_padconf_2; /* 0x4A002DB0 */ + u32 control_smart2io_padconf_0; /* 0x4A002DB4 */ + u32 control_smart2io_padconf_1; /* 0x4A002DB8 */ + u32 control_smart2io_padconf_2; /* 0x4A002DBC */ + u32 control_smart3io_padconf_0; /* 0x4A002DC0 */ + u32 control_smart3io_padconf_1; /* 0x4A002DC4 */ + u32 pad2[14]; + u32 control_pbias; /* 0x4A002E00 */ + u32 control_i2c_0; /* 0x4A002E04 */ + u32 control_camera_rx; /* 0x4A002E08 */ + u32 control_hdmi_tx_phy; /* 0x4A002E0C */ + u32 control_uniportm; /* 0x4A002E10 */ + u32 control_dsiphy; /* 0x4A002E14 */ + u32 control_mcbsplp; /* 0x4A002E18 */ + u32 control_usb2phycore; /* 0x4A002E1C */ + u32 control_hdmi_1; /*0x4A002E20*/ + u32 control_hsi; /*0x4A002E24*/ + u32 pad3[2]; + u32 control_ddr3ch1_0; /*0x4A002E30*/ + u32 control_ddr3ch2_0; /*0x4A002E34*/ + u32 control_ddrch1_0; /*0x4A002E38*/ + u32 control_ddrch1_1; /*0x4A002E3C*/ + u32 control_ddrch2_0; /*0x4A002E40*/ + u32 control_ddrch2_1; /*0x4A002E44*/ + u32 control_lpddr2ch1_0; /*0x4A002E48*/ + u32 control_lpddr2ch1_1; /*0x4A002E4C*/ + u32 control_ddrio_0; /*0x4A002E50*/ + u32 control_ddrio_1; /*0x4A002E54*/ + u32 control_ddrio_2; /*0x4A002E58*/ + u32 control_hyst_1; /*0x4A002E5C*/ + u32 control_usbb_hsic_control; /*0x4A002E60*/ + u32 control_c2c; /*0x4A002E64*/ + u32 control_core_control_spare_rw; /*0x4A002E68*/ + u32 control_core_control_spare_r; /*0x4A002E6C*/ + u32 control_core_control_spare_r_c0; /*0x4A002E70*/ + u32 control_srcomp_north_side; /*0x4A002E74*/ + u32 control_srcomp_south_side; /*0x4A002E78*/ + u32 control_srcomp_east_side; /*0x4A002E7C*/ + u32 control_srcomp_west_side; /*0x4A002E80*/ + u32 control_srcomp_code_latch; /*0x4A002E84*/ + u32 pad4[3680198]; + u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */ + u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */ + u32 control_padconf_mode; /* 0x4AE0CDA8 */ + u32 control_xtal_oscillator; /* 0x4AE0CDAC */ + u32 control_i2c_2; /* 0x4AE0CDB0 */ + u32 control_ckobuffer; /* 0x4AE0CDB4 */ + u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */ + u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */ + u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */ + u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */ + u32 control_efuse_1; /* 0x4AE0CDC8 */ + u32 control_efuse_2; /* 0x4AE0CDCC */ + u32 control_efuse_3; /* 0x4AE0CDD0 */ + u32 control_efuse_4; /* 0x4AE0CDD4 */ + u32 control_efuse_5; /* 0x4AE0CDD8 */ + u32 control_efuse_6; /* 0x4AE0CDDC */ + u32 control_efuse_7; /* 0x4AE0CDE0 */ + u32 control_efuse_8; /* 0x4AE0CDE4 */ + u32 control_efuse_9; /* 0x4AE0CDE8 */ + u32 control_efuse_10; /* 0x4AE0CDEC */ + u32 control_efuse_11; /* 0x4AE0CDF0 */ + u32 control_efuse_12; /* 0x4AE0CDF4 */ + u32 control_efuse_13; /* 0x4AE0CDF8 */ }; -struct control_lpddr2io_regs { - unsigned int control_lpddr2io1_0; - unsigned int control_lpddr2io1_1; - unsigned int control_lpddr2io1_2; - unsigned int control_lpddr2io1_3; - unsigned int control_lpddr2io2_0; - unsigned int control_lpddr2io2_1; - unsigned int control_lpddr2io2_2; - unsigned int control_lpddr2io2_3; -}; +/* Output impedance control */ +#define ds_120_ohm 0x0 +#define ds_60_ohm 0x1 +#define ds_45_ohm 0x2 +#define ds_30_ohm 0x3 +#define ds_mask 0x3 + +/* Slew rate control */ +#define sc_slow 0x0 +#define sc_medium 0x1 +#define sc_fast 0x2 +#define sc_na 0x3 +#define sc_mask 0x3 + +/* Target capacitance control */ +#define lb_5_12_pf 0x0 +#define lb_12_25_pf 0x1 +#define lb_25_50_pf 0x2 +#define lb_50_80_pf 0x3 +#define lb_mask 0x3 + +#define usb_i_mask 0x7 + +#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082 +#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200 +#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421 +#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 +#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 + +#define EFUSE_1 0x45145100 +#define EFUSE_2 0x45145100 +#define EFUSE_3 0x45145100 +#define EFUSE_4 0x45145100 #endif /* __ASSEMBLY__ */ /* @@ -169,7 +244,7 @@ struct control_lpddr2io_regs { * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE * at 0x40304000(EMU base) so that our code works for both EMU and GP */ -#define NON_SECURE_SRAM_START 0x40304000 +#define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 40a7c57489..8396a22141 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -55,6 +55,8 @@ u32 omap_sdram_size(void); u32 cortex_rev(void); void init_omap_revision(void); void do_io_settings(void); +void omap_vc_init(u16 speed_khz); +int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); /* * This is used to verify if the configuration header @@ -113,10 +115,4 @@ static inline u32 omap_hw_init_context(void) #endif } -static inline u32 omap_revision(void) -{ - extern u32 *const omap5_revision; - return *omap5_revision; -} - #endif diff --git a/arch/arm/include/asm/arch-rda/chip_id.h b/arch/arm/include/asm/arch-rda/chip_id.h new file mode 100644 index 0000000000..765b43d9d6 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/chip_id.h @@ -0,0 +1,46 @@ +///////////////////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2003-2007, Coolsand Technologies, Inc. // +// All Rights Reserved // +// // +// This source code is the property of Coolsand Technologies and is // +// confidential. Any modification, distribution, reproduction or // +// exploitation of any content of this file is totally forbidden, // +// except with the written permission of Coolsand Technologies. // +// // +//////////////////////////////////////////////////////////////////////////////// +// // +// $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/defs/include/chip_id.h $ // +// $Author: huazeng $ // +// $Date: 2013-04-16 15:10:28 +0800 (Tue, 16 Apr 2013) $ // +// $Revision: 20171 $ // +// // +//////////////////////////////////////////////////////////////////////////////// +// // +/// @file chip_id.h +/// This file contains the ID of the supported chips +// // +//////////////////////////////////////////////////////////////////////////////// + +#ifndef _CHIP_ID_H_ +#define _CHIP_ID_H_ + +#define CHIP_ASIC_ID_DEPRECATED_JADE 1 +#define CHIP_ASIC_ID_DEPRECATED_GRANITE 2 +#define CHIP_ASIC_ID_GREENSTONE 3 +#define CHIP_ASIC_ID_DEPRECATED_NEPHRITE 4 +#define CHIP_ASIC_ID_DEPRECATED_EMERALD 5 +#define CHIP_ASIC_ID_GALLITE 6 +#define CHIP_ASIC_ID_DEPRECATED_ESPERITE 7 +#define CHIP_ASIC_ID_8808 8 +#define CHIP_ASIC_ID_8809 9 +#define CHIP_ASIC_ID_8810 10 +#define CHIP_ASIC_ID_8809P 11 +#define CHIP_ASIC_ID_8810E 12 +#define CHIP_ASIC_ID_8850 13 + +#define CHIP_ASIC_ID_QTY 13 + +#endif // _CHIP_ID_H_ + + diff --git a/arch/arm/include/asm/arch-rda/cs_types.h b/arch/arm/include/asm/arch-rda/cs_types.h new file mode 100644 index 0000000000..de3ade7ea3 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/cs_types.h @@ -0,0 +1,281 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2002-2006, Coolsand Technologies, Inc. +// All Rights Reserved +// +// This source code is property of Coolsand. The information contained in this +// file is confidential. Distribution, reproduction, as well as exploitation, +// or transmisison of any content of this file is not allowed except if +// expressly permitted.Infringements result in damage claims! +// +// FILENAME: cs_types.h +// +// DESCRIPTION: +// This file defines all basic data types used by all files in Coolsand +// development environment. +// +// REVISION HISTORY: +// NAME DATE REMAKS +// SHK 2006-10-29 Created initial version 1.0 +// Romuald 2007-04-25 Added PRIVATE, PROTECTED, REG16 and REG32 +// zhaoyong 2008-08-08 clean up +//////////////////////////////////////////////////////////////////////////////// + +#ifndef __CS_TYPE_H__ +#define __CS_TYPE_H__ + +#define MAX_INT8 127 +#define MIN_INT8 (-MAX_INT8 - 1) +#define MAX_UINT8 255 +#define MIN_UINT8 0 +#define MAX_INT16 32767 +#define MIN_INT16 (-MAX_INT16 - 1) +#define MAX_UINT16 65535 +#define MIN_UINT16 0 +#define MAX_INT32 2147483647L +#define MIN_INT32 (-MAX_INT32 - 1) +#define MAX_UINT32 4294967295U +#define MIN_UINT32 0U +#ifdef WITH_LONG_LONG +#define INTMAX_MAX 0x7fffffffffffffff +#define INTMAX_MIN -(0x7fffffffffffffff-1) +#define UINTMAX_MAX 0xffffffffffffffff +#else +#define INTMAX_MAX 0x7fffffff +#define INTMAX_MIN -(0x7fffffff-1) +#define UINTMAX_MAX 0xffffffff +#endif +#define INT_MAX (char *)(1<<31) +#define LONG_MAX 0x7fffffff +#define LONG_MIN -(0x7fffffff-1) +#define ULONG_MAX 0xffffffff + + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +//typedef char s8; +typedef short s16; +//typedef long s32; +#ifdef __cplusplus +#else +typedef unsigned char bool; +#endif + +typedef char ascii; +typedef unsigned char byte; /* unsigned 8-bit data */ +typedef unsigned short word; /* unsigned 16-bit data */ +typedef unsigned long dword; /* unsigned 32-bit data */ +typedef unsigned char uint8; +typedef signed char int8; +typedef unsigned short int uint16; +typedef signed short int int16; +typedef unsigned int uint32; +typedef signed int int32; +typedef char boolean; +typedef unsigned int size_t; +typedef int ssize_t; +#ifdef WITH_LONG_LONG +typedef unsigned long long uintmax_t; +typedef long long intmax_t; +#else +typedef unsigned long uintmax_t; +typedef long intmax_t; +#endif + +typedef unsigned long UINT32; +typedef unsigned short UINT16; +typedef long INT32; +typedef short INT16; +typedef unsigned char UINT8; +typedef char INT8; +#if defined(_M_IX86) +#pragma warning(disable:4142) +typedef __int64 UINT64; +typedef __int64 INT64; +#else +typedef unsigned long long UINT64; +typedef long long INT64; +#endif +typedef unsigned char BOOL; +typedef short WCHAR; +typedef char CHAR; +typedef unsigned char BYTE; +typedef float FLOAT; +typedef double DOUBLE; +typedef UINT32 HANDLE; +typedef UINT8* PUINT8; +typedef UINT32* PUINT32; +typedef INT32* PINT32; +typedef UINT16* PUINT16; +typedef INT16* PINT16; +typedef CHAR * PCHAR; +typedef void* PVOID; +typedef unsigned short WORD; +typedef unsigned long DWORD; /* actually long, but this should be okay */ +typedef volatile unsigned char REG8; +typedef volatile unsigned short REG16; +typedef volatile unsigned int REG32; +typedef int INT; +typedef char S8; +typedef char * PS8; +typedef unsigned char U8; +typedef unsigned char * PU8; +typedef unsigned short pBOOL; +typedef short int S16; +typedef short int * PS16; +typedef unsigned short int U16; +typedef unsigned short int * PU16; +typedef int S32; +typedef int * PS32; +typedef unsigned int U32; +typedef unsigned int * PU32; +typedef float float32; +typedef unsigned long long U64; +typedef long long S64; + +#define PUBLIC +#define SRVAPI +#define PROTECTED +#define LOCAL static +#define PRIVATE static +#define EXPORT extern +#define REG register +#define CONST const +#define VOLATILE volatile +#define VOID void +#define INLINE static inline // Do compiler directives + +#ifdef ENABLE_DEPRECATED +#define DEPRECATED __attribute__ ((deprecated)) +#else +#define DEPRECATED +#endif /* ENABLE_DEPRECATED */ + +#define TRUE (1==1) +#define FALSE (1==0) +//#define NULL 0 +#define CS_NULL (void*)0 +#define NIL 0 +#define CS_NIL 0 +#define HNULL 0 +#define NULL_CHAR '\0' + +#define OFFSETOF(s,m) ((UINT32)&(((s *)0)->m)) // Get the address offset of the specified member. +//#define ALIGN(val,exp) (((val) + ((exp)-1)) & ~((exp)-1)) +//#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0])) +#define LAST_ELEMENT(x) (&x[ARRAY_SIZE(x)-1]) +#define TCHAR_SIZEOF(sz) (sizeof(sz)/sizeof(TCHAR)) +#define BOUND(x, min, max) ( (x) < (min) ? (min) : ((x) > (max) ? (max):(x)) ) +#define ROUND_SIZEOF(t) ((sizeof(t)+sizeof(int)-1)&~(sizeof(int)-1)) +#define IS_32BIT_ALIGN(nAdd) ((UINT32)(((UINT32)(nAdd)) & 0x3)==0) +#define IS_16_ALIGN(nSize) ((UINT32)(((UINT32)(nSize))& 0x0f) == 0) +#define S_LAST_MEMBER_ADDR(ptr, type) ((UINT8*)(ptr) + SIZEOF(type)) +#define S_MEMBER_ADDR(s_prt, offset) ((UINT8*)(s_prt) + offset) +#define MSB(x) (((x) >> 8) & 0xff) // most signif byte of 2-byte integer +#define LSB(x) ((x) & 0xff) // least signif byte of 2-byte integer +#define MAKE_WORD(p) (((UINT16)(p)[0] << 8) | (UINT16)(p)[1]) +#define MAKE_DWORD(p) (((UINT32)(p)[0] << 24) | ((UINT32)(p)[1] << 16) | ((UINT32)(p)[2] << 8) | (UINT32)(p)[3]) +#define SWAP16(p) (((UINT16)((UINT16*)(p))[1] << 8) | (UINT16)((UINT16*)(p))[0]) +#define SWAP32(p) (((UINT32)((UINT32*)(p))[3] << 24) | ((UINT32)((UINT32*)(p))[2] << 16) | ((UINT32)((UINT32*)(p))[1] << 8) | (UINT32)((UINT32*)(p))[0]) +#define SWAPT(v1,v2,typ) {typ v; v = v1; v1 = v2; v2 = v;} + +/* align size withe the specified bits.*/ +#define ALIGN_SIZE(x, align) (((UINT32)(x)+align-1)&~(align-1)) +#define Arg(arg, type) (*(type *)(arg)) +#define NextArg(arg, type) ((arg) = (TCHAR *)(arg) + roundedsizeof(type)) +// Get the data from "arg" to "in". +#define ARG_IN(r,arg,type) (memcpy(&(r), (type *) (arg), sizeof (arg))) +// Put the data from "w" to "arg". +#define ARG_OUT(arg, w, type) (memcpy((type *) (arg), &(w), sizeof (w))) +#define ABS(x) ((x<0)?(-(x)):(x)) +//#define MAX(a,b) (((a) > (b)) ? (a) : (b)) +//#define MIN(a,b) (((a) < (b)) ? (a) : (b)) +#define MAKEINT16(a, b) ((INT16)(((UINT8)(a)) | ((INT16)((UINT8)(b))) << 8)) +#define MAKEINT32(a, b) ((INT32)(((UINT16)(a)) | ((INT32)((UINT16)(b))) << 16)) +#define MAKEUINT16(a, b) ((UINT16)(((UINT8)(a)) | ((UINT16)((UINT8)(b))) << 8)) +#define MAKEUINT32(a, b) ((UINT32)(((UINT16)(a)) | ((UINT32)((UINT16)(b))) << 16)) +#define LOINT8(w) ((INT8)(w)) +#define HIINT8(w) ((INT8)((UINT16)(w) >> 8)) +#define LOUINT8(w) ((UINT8)(w)) +#define HIUINT8(w) ((UINT8)((UINT16)(w) >> 8)) +#define LOINT16(l) ((INT16)(l)) +#define HIINT16(l) ((INT16)((UINT32)(l) >> 16)) +#define LOUINT16(l) ((UINT16)(l)) +#define HIUINT16(l) ((UINT16)((UINT32)(l) >> 16)) +//#define offsetof(TYPE, MEMBER) ((u32) &((TYPE *)0)->MEMBER) +#define offsetofvar(VAR, MEMBER) (((u32) &(VAR.MEMBER)) - ((u32) &VAR)) +/* Remove const cast-away warnings from gcc -Wcast-qual */ +#define __UNCONST(a) ((void *)(unsigned long)(const void *)(a)) +#define __P(protos) protos +//#define ALIGN(val,exp) (((val) + ((exp)-1)) & ~((exp)-1)) +//#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0])) +#define LAST_ELEMENT(x) (&x[ARRAY_SIZE(x)-1]) +#define TCHAR_SIZEOF(sz) (sizeof(sz)/sizeof(TCHAR)) +#define BOUND(x, min, max) ( (x) < (min) ? (min) : ((x) > (max) ? (max):(x)) ) +#define roundedsizeof(t) ((sizeof(t)+sizeof(int)-1)&~(sizeof(int)-1)) +#define IS_32BIT_ALIGN(nAdd) ((UINT32)(((UINT32)(nAdd)) & 0x3)==0) +#define IS_16_ALIGN(nSize) ((UINT32)(((UINT32)(nSize))& 0x0f) == 0) +#define ABS(x) ((x<0)?(-(x)):(x)) + +// Set a breakpoint, to enter GDB. +#define BREAKPOINT asm volatile("break 1\n\tnop\n\tnop\n\tnop") +#define BKPT BREAKPOINT; +#define GDB_FUNC_IN_RAM __attribute__((section(".ram"))) + +// Preprocessor macros. +#define STRINGIFY_VALUE(s) STRINGIFY(s) +#define STRINGIFY(s) #s + +//#define cpu_to_le32(x) (x) +//#define le32_to_cpu(x) (x) + +#if defined(UNICODE) +#undef SIZEOF +#define SIZEOF(type) (sizeof(type)/sizeof(UINT16)) +typedef UINT16* PSTR; +typedef CONST UINT16* PCSTR; +typedef UINT16 TCHAR; +#undef TEXT +#define TEXT(x) L ## x +#else +#undef SIZEOF +#define SIZEOF(type) sizeof(type) +typedef UINT8* PSTR; +typedef CONST UINT8* PCSTR; +typedef UINT8 TCHAR; +typedef UINT8* PTCHAR; +#undef TEXT +#define TEXT(x) x +#endif + +#define CPP_START extern "C" { +#define CPP_END } +#define TSTXT(x) x + +/// From http://www.ibm.com/developerworks/linux/library/l-gcc-hacks/ +/// Macro to use in a if statement to tell the compiler this branch +/// is likely taken, and optimize accordingly. +#define LIKELY(x) __builtin_expect(!!(x), 1) +/// Macro to use in a if statement to tell the compiler this branch +/// is unlikely take, and optimize accordingly. +#define UNLIKELY(x) __builtin_expect(!!(x), 0) + + +/// For packing structure +#define PACKED __attribute__((packed)) + +/// To describe alignment +#define ALIGNED(a) __attribute__((aligned(a))) + +// C++ needs to know that types and declarations are C, not C++. +#ifdef __cplusplus +# define EXTERN_C_START extern "C" { +# define EXTERN_C_END } +#else +# define EXTERN_C_START +# define EXTERN_C_END +#endif + + +#endif // __CS_TYPE_H__ + diff --git a/arch/arm/include/asm/arch-rda/defs_mdcom.h b/arch/arm/include/asm/arch-rda/defs_mdcom.h new file mode 100644 index 0000000000..748b743fcf --- /dev/null +++ b/arch/arm/include/asm/arch-rda/defs_mdcom.h @@ -0,0 +1,160 @@ +#ifndef _DEFS_MDCOM_H_ +#define _DEFS_MDCOM_H_ + +#include <asm/arch/hardware.h> + +#ifdef RDA_MDCOM_DEBUG +#define rdamddbg(fmt,args...) printf (fmt ,##args) +#else +#define rdamddbg(fmt,args...) +#endif /* RDA_MDCOM_DEBUG */ + +/* + * Convert modem address to AP address + */ +#define RDA_ADD_M2A(x) (((x) & 0x0FFFFFFF) | 0x10000000) + +/* + * Modem boot context address + */ +#define RDA_BOOT_CTX_ADD 0x11C00100 + +/* + * Modem map pointer + */ +#define RDA_MODEM_MAP_PTR 0x11C0027C +#define RDA_MODEM_MAP_QTY 0x1A + +/* + * Modem RAM info + */ +#if defined(_TGT_MODEM_MEM_SIZE) && (_TGT_MODEM_MEM_SIZE > 0) +#define RDA_MODEM_RAM_BASE (PHYS_SDRAM_1 + ((_TGT_MODEM_MEM_BASE) << 20)) +#define RDA_MODEM_RAM_SIZE (_TGT_MODEM_MEM_SIZE << 20) +#define RDA_GSM_MODEM_RAM_END (RDA_MODEM_RAM_BASE + (_TGT_MODEM_GSM_MEM_SIZE << 20)) +#define RDA_MODEM_RAM_END RDA_GSM_MODEM_RAM_END +#ifdef _TGT_MODEM_WCDMA_MEM_SIZE +#define RDA_WCDMA_MODEM_RAM_END (RDA_GSM_MODEM_RAM_END + (_TGT_MODEM_WCDMA_MEM_SIZE << 20)) +#endif +#else +#define RDA_MODEM_RAM_BASE RDA_MD_PSRAM_BASE +#define RDA_MODEM_RAM_SIZE RDA_MD_PSRAM_SIZE +#define RDA_MODEM_RAM_END (RDA_MODEM_RAM_BASE + RDA_MODEM_RAM_SIZE) +#endif + +#define RDA_MODEM_INTSRAM_BASE (0x11C00000) +#define RDA_MODEM_INTSRAM_SIZE (0x18000) +#define RDA_MODEM_INTSRAM_END \ + (RDA_MODEM_INTSRAM_BASE + RDA_MODEM_INTSRAM_SIZE) + +/* + * HEARTBEAT data + */ +#define RDA_AP_MBX_HEARTBEAT_ADD (RDA_MD_MAILBOX_BASE + 0) + +/* + * CHANNEL + */ +#define RDA_MDCOM_CHN_AT_HEAD_ADD_READ 0x00200430 +#define RDA_MDCOM_CHN_AT_HEAD_ADD_WRITE 0x00200C40 +#define RDA_MDCOM_CHN_AT_BUF_ADD_READ 0x00200440 +#define RDA_MDCOM_CHN_AT_BUF_ADD_WRITE 0x00200C50 +#define RDA_MDCOM_CHN_AT_BUF_LEN_READ 2048 +#define RDA_MDCOM_CHN_AT_BUF_LEN_WRITE 2048 + +#define RDA_MDCOM_CHN_SYS_HEAD_ADD_READ 0x00200010 +#define RDA_MDCOM_CHN_SYS_HEAD_ADD_WRITE 0x00200220 +#define RDA_MDCOM_CHN_SYS_BUF_ADD_READ 0x00200020 +#define RDA_MDCOM_CHN_SYS_BUF_ADD_WRITE 0x00200230 +#define RDA_MDCOM_CHN_SYS_BUF_LEN_READ 512 +#define RDA_MDCOM_CHN_SYS_BUF_LEN_WRITE 512 + +#define RDA_MDCOM_CHN_TRACE_HEAD_ADD_READ 0x00201450 +#define RDA_MDCOM_CHN_TRACE_HEAD_ADD_WRITE 0x00201860 +#define RDA_MDCOM_CHN_TRACE_BUF_ADD_READ 0x00201460 +#define RDA_MDCOM_CHN_TRACE_BUF_ADD_WRITE 0x00201870 +#define RDA_MDCOM_CHN_TRACE_BUF_LEN_READ 1024 +#define RDA_MDCOM_CHN_TRACE_BUF_LEN_WRITE 512 + +/* + * MAGIC NUMBER + */ +#define RDA_AP_MBX_MAGIC_NUMBER_ADD (RDA_MD_MAILBOX_BASE + 0x1A70) +#define RDA_MAGIC_SYSTEM_STARTED_FLAG 0x057a67ed +#define RDA_MAGIC_MODEM_CRASH_FLAG 0x9db09db0 +#define RDA_MAGIC_FACT_UPD_CMD_FLAG 0xfac40c3d +#define RDA_MAGIC_FACT_UPD_TYPE_FLAG 0x496efa00 +#define RDA_MAGIC_FACT_UPD_TYPE_FLAG_MASK 0xFFFFFF00 +#define RDA_MAGIC_FACT_UPD_TYPE_CALIB 0x1 +#define RDA_MAGIC_FACT_UPD_TYPE_FACT 0x2 +#define RDA_MAGIC_FACT_UPD_TYPE_AP_FACT 0x4 + +/* + * LOG BUFFER INFO + */ +#define RDA_AP_MBX_LOG_BUF_INFO_ADD (RDA_MD_MAILBOX_BASE + 0x1A80) +#define RDA_AP_MBX_MAX_MODEM_LOG_LEN 0x10000 +#define RDA_AP_MBX_MAX_MODEM_EXC_LEN 0x1000 + + +/* + * BOOT_HST_MONITOR_X_CTX_T + * This structure is used by the HOST execution command + * It can store PC, SP, param ptr and returned value ptr + * The command type field could reveal itself as really + * relevant in the future + */ +typedef volatile struct { + u32 cmdType; // 0x00000000 + u32 pc; // 0x00000004 + u32 sp; // 0x00000008 + void* param; // 0x0000000c + void* returnedValue; // 0x00000010 +} RDA_BOOT_HST_MONITOR_X_CTX_T; + +typedef struct +{ + u32 revision; //0x00000000 + u32 number; //0x00000004 + u32 date; //0x00000008 + u8* string; //0x0000000C +} RDA_MODEM_MAP_VERSION_T; //Size : 0x10 + +typedef struct +{ + RDA_MODEM_MAP_VERSION_T* version; //0x00000000 + void* access; //0x00000004 +} RDA_MODEM_MAP_MODULE_T; //Size : 0x8 + +typedef struct +{ + /* Modem heartbeat counter */ + volatile u32 bpCounter; + /* AP heartbeat counter */ + volatile u32 apCounter; + /* System reset cause */ + u32 resetCause; + /* Communication interface version */ + u32 version; +} RDA_AP_MBX_HEARTBEAT_T; + +typedef struct { + u32 sysStarted; + u32 modemCrashed; + u32 factUpdateCmd; + u32 factUpdateType; +} RDA_AP_MBX_MAGIC_NUMBER_T; + +typedef struct { + u32 modemAddr; + u32 modemLen; + u32 modemExcAddr; + u32 modemExcLen; + struct { + u32 apAddr; + u32 apLen; + u32 reserved[2]; + } apLog[5]; +} RDA_AP_MBX_LOG_BUF_INFO_T; + +#endif // _DEFS_MDCOM_H_ diff --git a/arch/arm/include/asm/arch-rda/dma.h b/arch/arm/include/asm/arch-rda/dma.h new file mode 100644 index 0000000000..8b8f553b2a --- /dev/null +++ b/arch/arm/include/asm/arch-rda/dma.h @@ -0,0 +1,73 @@ +/*************************************************************** +* +* Copyright(C) RDA Micro Company.,2012 +* All Rights Reserved. Confidential +* +**************************************************************** +* +* Project: RDA8810 +* File Name: arch/arm/include/asm/dma.h +* +* Author: Jason Tao +* Creation Date: 2012-11-15 +* +***************************************************************** +* +* Definition of registers of DMA +* +***************************************************************** +*/ + + +#ifndef __DMA_H__ +#define __DMA_H__ + +#include <asm/types.h> + +#define BIT(x) (1UL << (x)) + +#define RDA_DMA_CHAN_REG 0x00 + +#define RDA_DMA_STATUS_REG 0x04 +#define RDA_DMA_STA_INT BIT(2) + +#define RDA_DMA_CTL_REG 0x08 +#define RDA_DMA_CTL_EN BIT(0) +#define RDA_DMA_CTL_INT_MASK BIT(1) +#define RDA_DMA_CTL_INT_CLE BIT(2) +#define RDA_DMA_CTL_SRC_SEL BIT(24) +#define RDA_DMA_CTL_DST_SEL BIT(25) + +#define RDA_DMA_SRC_REG 0x0C +#define RDA_DMA_DST_REG 0x10 +#define RDA_DMA_XFER_SIZE_REG 0x18 + +/* In general, data will be transisted via AXI bus. */ +#define RDA_DMA_NOR_MODE (0x00000000) +/* Fast write mode : bit25 is for control writing via sram port. */ +#define RDA_DMA_FW_MODE RDA_DMA_CTL_DST_SEL +/* Fast read mode : bit24 is for control reading via sram port. */ +#define RDA_DMA_FR_MODE RDA_DMA_CTL_SRC_SEL +#define RDA_DMA_MODE_MASK (RDA_DMA_CTL_SRC_SEL | RDA_DMA_CTL_DST_SEL) + +struct rda_dma_chan_params { + u32 src_addr; + u32 dst_addr; + u32 xfer_size; + u32 dma_mode; +}; + +int rda_set_dma_params(u8 ch, struct rda_dma_chan_params *params); + +void rda_start_dma(u8 ch); + +void rda_stop_dma(u8 ch); + +void rda_poll_dma(u8 ch); + +int rda_request_dma(u8 *dma_ch_out); + +void rda_free_dma(u8 ch); + +#endif /* __DMA_H__ */ + diff --git a/arch/arm/include/asm/arch-rda/factory.h b/arch/arm/include/asm/arch-rda/factory.h new file mode 100644 index 0000000000..45b9227f04 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/factory.h @@ -0,0 +1,104 @@ +#ifndef __FACTORY_DATA_H__ +#define __FACTORY_DATA_H__ + +#include "defs_mdcom.h" + +/* data size define */ +#define RDA_MODEM_CAL_LEN 8192 /* rf/audio calibration data */ +#define RDA_MODEM_FACT_LEN 4096 /* modem factory info */ +#define RDA_AP_FACT_LEN 4096 /* ap factory info */ +#define RDA_MODEM_EXT_CAL_LEN 16384 /* extended rf/audio calibration data, includes wcdma data */ +#define RDA_FACT_TOTAL_LEN \ + (RDA_MODEM_CAL_LEN + RDA_MODEM_FACT_LEN + RDA_AP_FACT_LEN \ + + RDA_MODEM_EXT_CAL_LEN) + +/* loading addresses */ +/* extended calibration data loading address */ +#define RDA_MODEM_EXT_CAL_ADDR (RDA_MODEM_RAM_END - RDA_FACT_TOTAL_LEN) +/* calibration data loading address */ +#define RDA_MODEM_CAL_ADDR (RDA_MODEM_EXT_CAL_ADDR + RDA_MODEM_EXT_CAL_LEN) +/* modem factory info loading address */ +#define RDA_MODEM_FACT_ADDR (RDA_MODEM_CAL_ADDR + RDA_MODEM_CAL_LEN) +/* ap factory info loading address */ +#define RDA_AP_FACT_ADDR (RDA_MODEM_FACT_ADDR + RDA_MODEM_FACT_LEN) + +/* version define & magic number */ +#define AP_FACTORY_MAJOR_VERSION 2 +#define AP_FACTORY_MINOR_VERSION 1 /* always be 1 */ +#define AP_FACTORY_MARK_VERSION 0xFAC40000 +#define AP_FACTORY_VERSION_NUMBER (AP_FACTORY_MARK_VERSION | \ + (AP_FACTORY_MAJOR_VERSION << 8) | AP_FACTORY_MINOR_VERSION) +#define AP_FACTORY_CLOCK_MAGIC 0x55515263 + +/* old version compatibility */ +#define AP_FACTORY_MAJOR_VERSION_1 1 +#define AP_FACTORY_VERSION_1_LEN (RDA_MODEM_CAL_LEN + \ + RDA_MODEM_FACT_LEN + RDA_AP_FACT_LEN) +#define AP_FACTORY_VERSION_1_NUMBER (AP_FACTORY_MARK_VERSION | \ + (AP_FACTORY_MAJOR_VERSION_1 << 8) | AP_FACTORY_MINOR_VERSION) + +#define FACT_NAME_LEN 128 +#define AP_FACTORY_CLOCK_CFG_LEN 1024 +#define GS_CALI_DATA_LEN 32 + +struct ap_factory_config { + unsigned int version; + unsigned int crc; + unsigned char lcd_name[FACT_NAME_LEN]; + unsigned char bootlogo_name[FACT_NAME_LEN]; + unsigned char clock_config[AP_FACTORY_CLOCK_CFG_LEN]; + unsigned char gs_cali_data[GS_CALI_DATA_LEN]; +}; + +struct factory_data_sector { + unsigned char modem_calib_data[RDA_MODEM_CAL_LEN]; + unsigned char modem_factory_data[RDA_MODEM_FACT_LEN]; + unsigned char ap_factory_data[RDA_AP_FACT_LEN]; + unsigned char modem_ext_calib_data[RDA_MODEM_EXT_CAL_LEN]; +}; + +int factory_load(void); +unsigned long factory_get_all(unsigned char *buf); +const unsigned char* factory_get_ap_factory(void); +const unsigned char* factory_get_modem_calib(void); +const unsigned char* factory_get_modem_ext_calib(void); +const unsigned char* factory_get_modem_factory(void); +const unsigned char* factory_get_lcd_name(void); +const unsigned char* factory_get_bootlogo_name(void); +int factory_set_ap_factory(unsigned char *data); +int factory_set_modem_calib(unsigned char *data); +int factory_set_modem_ext_calib(unsigned char *data); +int factory_set_modem_factory(unsigned char *data); +int factory_burn(void); +int factory_update_modem_calib(unsigned char *data); +int factory_update_modem_ext_calib(unsigned char *data); +int factory_update_modem_factory(unsigned char *data); +int factory_update_ap_factory(unsigned char *data); +int factory_update_all(unsigned char *data, unsigned long size); +int factory_copy_from_mem(const u8 *buf); + + +/* Define a simple message function, for PC calib tool and u-boot. + Borrow ap_factory_data top 1024 bytes to send and receive message. */ +#define RDA_AP_CALIB_MSG_MAGIC 0xca1b5353 +#define RDA_AP_CALIB_MSG_LEN 1024 +#define RDA_AP_CALIB_MSG_ADDR (RDA_AP_FACT_ADDR + RDA_AP_FACT_LEN - RDA_AP_CALIB_MSG_LEN) + +#define RDA_AP_CALIB_MSG_DATA_LEN 1012 +struct ap_calib_message { + unsigned int magic; /* must be RDA_AP_CALIB_MSG_MAGIC */ + unsigned int id; /* see below defines */ + unsigned int size; /* the size of message data */ + unsigned char data[RDA_AP_CALIB_MSG_DATA_LEN]; +}; + +/* PC calib tool -> u-boot */ +#define RDA_AP_CALIB_MSG_SET_PRDINFO 0x1 +int factory_get_ap_calib_msg(unsigned int *id, unsigned int *size, unsigned char *data); + +/* u-boot -> PC calib tool */ +#define RDA_AP_CALIB_MSG_GET_PRDINFO 0x80000001 +int factory_set_ap_calib_msg(unsigned int id, unsigned int size, unsigned char *data); + + +#endif diff --git a/arch/arm/include/asm/arch-rda/global_macros.h b/arch/arm/include/asm/arch-rda/global_macros.h new file mode 100644 index 0000000000..10bb7ecce3 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/global_macros.h @@ -0,0 +1,67 @@ +//============================================================================== +// +// Copyright (C) 2012-2013, RDA Microelectronics. +// All Rights Reserved +// +// This source code is the property of RDA Microelectronics and is +// confidential. Any modification, distribution, reproduction or +// exploitation of any content of this file is totally forbidden, +// except with the written permission of RDA Microelectronics. +// +//============================================================================== +// +// THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML. +// +// !!! PLEASE DO NOT EDIT !!! +// +// $HeadURL$ +// $Author$ +// $Date$ +// $Revision$ +// +//============================================================================== +// +/// @file +// +//============================================================================== + +#ifndef _GLOBAL_MACROS_H_ +#define _GLOBAL_MACROS_H_ + + + +// ============================================================================= +// MACROS +// ============================================================================= + +// ============================================================================= +// TYPES +// ============================================================================= + + + + +//#define KSEG0(addr) ( (addr) | 0x80000000 ) +//#define KSEG1(addr) ( (addr) | 0xa0000000 ) +#define KSEG0(addr) ( (addr) ) +#define KSEG1(addr) ( (addr) ) + + +/* Define access cached or uncached */ +#define MEM_ACCESS_CACHED(addr) ((UINT32*)((UINT32)(addr)&0xdfffffff)) +#define MEM_ACCESS_UNCACHED(addr) ((UINT32*)((UINT32)(addr)|0x20000000)) + +/* Register access for assembly */ +#define BASE_HI(val) (((0xa0000000 | val) & 0xffff8000) + (val & 0x8000)) +#define BASE_LO(val) (((val) & 0x7fff) - (val & 0x8000)) + + +/* to extract bitfield from register value */ +#define GET_BITFIELD(dword, bitfield) (((dword) & (bitfield ## _MASK)) >> (bitfield ## _SHIFT)) + +#define EXP2(n) (1<<(n)) + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/hardware.h b/arch/arm/include/asm/arch-rda/hardware.h new file mode 100644 index 0000000000..f498734273 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/hardware.h @@ -0,0 +1,19 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <config.h> +#include <asm/sizes.h> + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int REG32; +typedef unsigned char BOOL; + +#define TRUE (1==1) +#define FALSE (1==0) +#endif + +/* to extract bitfield from register value */ +#define GET_BITFIELD(dword, bitfield) (((dword) & (bitfield ## _MASK)) >> (bitfield ## _SHIFT)) +#define SET_BITFIELD(dword, bitfield, value) (((dword) & ~(bitfield ## _MASK)) | (bitfield(value))) + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-rda/hw_test.h b/arch/arm/include/asm/arch-rda/hw_test.h new file mode 100644 index 0000000000..5dec670f6c --- /dev/null +++ b/arch/arm/include/asm/arch-rda/hw_test.h @@ -0,0 +1,61 @@ +#ifndef __RDA_HW_TEST_H__ +#define __RDA_HW_TEST_H__ + +#ifdef CONFIG_VPU_TEST +extern void vpu_sta_test(int times); +extern int vpu_md5_test(int times); +#else +static inline void vpu_sta_test(int times){}; +static inline int vpu_md5_test(int times){return 0;}; +#endif /* CONFIG_VPU_TEST */ + +#ifdef CONFIG_CPU_TEST +extern void cpu_pll_test(int times); +#else +static inline void cpu_pll_test(int times){}; +#endif /*CONFIG_CPU_TEST */ + +#ifdef CONFIG_DDR_TEST +extern int ddr_mem_copy_test(int times,unsigned int src_addr, unsigned int des_addr, unsigned int nword); +#else +static inline int ddr_mem_copy_test(int times,unsigned int src_addr, unsigned int des_addr, unsigned int nword){return 0;} +#endif /* CONFIG_DDR_TEST */ + +#ifdef CONFIG_TIMER_TEST +extern int tim_test(int timer_id,int times); +#else +static inline int tim_test(int timer_id,int times){ return 0;} +#endif /* CONFIG_TIMER_TEST */ + +#ifdef CONFIG_UART_TEST +extern int uart_test(int uart_id,int times); +#else +static inline int uart_test(int uart_id,int times){ return 0;} +#endif /* CONFIG_UART_TEST */ + +#ifdef CONFIG_GIC_TEST +extern int gic_test(int times); +#else +static inline int gic_test(int times){ return 0;} +#endif /* CONFIG_GIC_TEST */ + +#ifdef CONFIG_CACHE_TEST +extern int cpu_cache_test(int times); +#else +static inline int cpu_cache_test(int times){ return 0;} +#endif /* CONFIG_CACHE_TEST */ + +#ifdef CONFIG_MIPI_LOOP_TEST +extern int test_dsi_csi_loop(int times); +#else +static inline int test_dsi_csi_loop(int times) {return 0;}; +#endif /* CONFIG_MIPI_LOOP_TEST */ + +#ifdef CONFIG_I2C_TEST +extern int test_i2c(int id,int times); +#else +static inline int test_i2c(int id,int times){ return 0;} +#endif /* CONFIG_I2C_TEST */ + + +#endif /*__RDA_HW_TEST_H__*/ diff --git a/arch/arm/include/asm/arch-rda/hwcfg.h b/arch/arm/include/asm/arch-rda/hwcfg.h new file mode 100644 index 0000000000..aee369e7bb --- /dev/null +++ b/arch/arm/include/asm/arch-rda/hwcfg.h @@ -0,0 +1,64 @@ +#ifndef __RDA_HWCFG_H +#define __RDA_HWCFG_H + +/* + * HW BOOT MODE + * BIT_15: 1 - force download + * BIT_14: 1 - volume up + * BIT_13: 1 - volume down + * BIT_12: 1 - key on (power on key) + * BIT_11: 1 - force DL (skip NAND loading) + * BIT_10: 1 - to skip USB init (for cases USB init may fail) + * (in bootloader, this bit is used for calibration and driver test) + * BIT_7 : if BIT_3 == 1 (SPI FLASH): 1 - SDMMC, 1 - SPI FLASH + * if BIT_3 == 0 (NAND/eMMC): 1 - 4K SLC/8K MLC, 0 - 2K SLC/4K MLC + * BIT_4 : if BIT_3 == 1 (SPI FLASH): 1 - SPI NAND, 0 - SPI NOR + * if BIT_3 == 0 (NAND/eMMC): 1 - SDMMC, 0 - NAND/eMMC + * BIT_3 : 1 - use SPI NAND, 0 - use NAND/eMMC + * BIT_2 : 1 - use eMMC, 0 - use NAND + * BIT_1 : 1 - 8bit NAND, 0 - 16bit NAND + * BIT_0 : 1 - MLC, 0 - SLC + */ +#define RDA_HW_CFG_BIT_15 (1 << 15) +#define RDA_HW_CFG_BIT_14 (1 << 14) +#define RDA_HW_CFG_BIT_13 (1 << 13) +#define RDA_HW_CFG_BIT_12 (1 << 12) +#define RDA_HW_CFG_BIT_11 (1 << 11) +#define RDA_HW_CFG_BIT_10 (1 << 10) +#define RDA_HW_CFG_BIT_7 (1 << 7) +#define RDA_HW_CFG_BIT_4 (1 << 4) +#define RDA_HW_CFG_BIT_3 (1 << 3) +#define RDA_HW_CFG_BIT_2 (1 << 2) +#define RDA_HW_CFG_BIT_1 (1 << 1) +#define RDA_HW_CFG_BIT_0 (1 << 0) + +/* + * SW BOOT MODE + * BIT_6 : PDL2 + * BIT_5 : Autocall + * BIT_4 : Calib + * BIT_3 : Recovery + * BIT_2 : Fastboot + * BIT_1 : ROM force run + * BIT_0 : Modem EBC valid + */ +#define RDA_SW_CFG_BIT_6 (1 << 6) +#define RDA_SW_CFG_BIT_5 (1 << 5) +#define RDA_SW_CFG_BIT_4 (1 << 4) +#define RDA_SW_CFG_BIT_3 (1 << 3) +#define RDA_SW_CFG_BIT_2 (1 << 2) +#define RDA_SW_CFG_BIT_1 (1 << 1) +#define RDA_SW_CFG_BIT_0 (1 << 0) + +void rda_hwcfg_reg_set(u16); +u16 rda_hwcfg_reg_get(void); +u16 rda_hwcfg_get(void); +void rda_swcfg_reg_set(u16); +u16 rda_swcfg_reg_get(void); +u16 rda_swcfg_get(void); +u16 rda_prod_id_get(void); +u16 rda_metal_id_get(void); +u16 rda_bond_id_get(void); +void rda_nand_iodrive_set(void); + +#endif // __RDA_HWCFG_H diff --git a/arch/arm/include/asm/arch-rda/ifc.h b/arch/arm/include/asm/arch-rda/ifc.h new file mode 100644 index 0000000000..099d4a1020 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/ifc.h @@ -0,0 +1,55 @@ +#ifndef _IFC_H_ +#define _IFC_H_ + +#include <asm/arch/hardware.h> + +#define HAL_UNKNOWN_CHANNEL 0xff + +typedef enum { + HAL_IFC_UART_TX, + HAL_IFC_UART_RX, + HAL_IFC_UART2_TX, + HAL_IFC_UART2_RX, + HAL_IFC_SPI_TX, + HAL_IFC_SPI_RX, + HAL_IFC_SPI2_TX, + HAL_IFC_SPI2_RX, + HAL_IFC_SPI3_TX, + HAL_IFC_SPI3_RX, + HAL_IFC_SDMMC_TX, + HAL_IFC_SDMMC_RX, + HAL_IFC_SDMMC2_TX, + HAL_IFC_SDMMC2_RX, + HAL_IFC_SDMMC3_TX, + HAL_IFC_SDMMC3_RX, + HAL_IFC_NFSC_TX, + HAL_IFC_NFSC_RX, + HAL_IFC_UART3_TX, + HAL_IFC_UART3_RX, + HAL_IFC_NO_REQWEST +} HAL_IFC_REQUEST_ID_T; + +// ============================================================================= +// HAL_IFC_MODE_T +// ----------------------------------------------------------------------------- +/// Define the mode used to configure an IFC transfer. This enum describes +/// the width (8 or 32 bits) and if the transfer is autodisabled or manually +/// disabled. +// ============================================================================= +typedef enum +{ + HAL_IFC_SIZE_8_MODE_MANUAL = (0 | 0), + HAL_IFC_SIZE_8_MODE_AUTO = (0 | SYS_IFC_AUTODISABLE), + HAL_IFC_SIZE_32_MODE_MANUAL = (SYS_IFC_SIZE_WORD | 0), + HAL_IFC_SIZE_32_MODE_AUTO = (SYS_IFC_SIZE_WORD | SYS_IFC_AUTODISABLE), +} HAL_IFC_MODE_T; + +void hal_IfcOpen(void); +HAL_IFC_REQUEST_ID_T hal_IfcGetOwner(u8 channel); +void hal_IfcChannelRelease(HAL_IFC_REQUEST_ID_T requestId, u8 channel); +void hal_IfcChannelFlush(HAL_IFC_REQUEST_ID_T requestId, u8 channel); +BOOL hal_IfcChannelIsFifoEmpty(HAL_IFC_REQUEST_ID_T requestId, u8 channel); +u8 hal_IfcTransferStart(HAL_IFC_REQUEST_ID_T requestId, u8* memStartAddr, u32 xferSize, HAL_IFC_MODE_T ifcMode); + +#endif // _IFC_H + diff --git a/arch/arm/include/asm/arch-rda/iomap_rda8810.h b/arch/arm/include/asm/arch-rda/iomap_rda8810.h new file mode 100644 index 0000000000..256b189b30 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/iomap_rda8810.h @@ -0,0 +1,162 @@ +#ifndef __IOMAP_RDA8810_H +#define __IOMAP_RDA8810_H + +#include <asm/sizes.h> + +#define RDA_SRAM_BASE 0x00100000 +#define RDA_SRAM_SIZE SZ_64K + +#define RDA_MD_MAILBOX_BASE 0x00200000 +#define RDA_MD_MAILBOX_SIZE SZ_8K + +#define RDA_MODEM_BASE 0x10000000 +#define RDA_MODEM_SIZE SZ_256M + +#define RDA_MD_SYSCTRL_BASE 0x11A00000 +#define RDA_MD_SYSCTRL_SIZE SZ_4K + +#define RDA_GPIO_BASE 0x11A08000 +#define RDA_GPIO_SIZE SZ_4K + +#define RDA_CFG_REGS_BASE 0x11A09000 +#define RDA_CFG_REGS_SIZE SZ_4K + +#define RDA_MODEM_SPI2_BASE 0x11A14000 +#define RDA_MODEM_SPI2_SIZE SZ_4K + +#define RDA_MODEM_XCPU_BASE 0x11A16000 +#define RDA_MODEM_XCPU_SIZE SZ_4K + +#define RDA_MODEM_BCPU_BASE 0x11909000 +#define RDA_MODEM_BCPU_SIZE SZ_4K + +#define RDA_MD_PSRAM_BASE (RDA_MODEM_BASE + 0x02000000) +#define RDA_MD_PSRAM_SIZE SZ_4M + +#define RDA_CAMERA_BASE 0x20000000 +#define RDA_CAMERA_SIZE SZ_256K + +#define RDA_GOUDA_MEM_BASE 0x20040000 +#define RDA_GOUDA_MEM_SIZE SZ_256K + +#define RDA_GPU_BASE 0x20080000 +#define RDA_GPU_SIZE SZ_256K + +#define RDA_VOC_BASE 0x200C0000 +#define RDA_VOC_SIZE SZ_256K + +#define RDA_USB_BASE 0x20400000 +#define RDA_USB_SIZE SZ_256K + +#define RDA_SPIFLASH_BASE 0x20440000 +#define RDA_SPIFLASH_SIZE SZ_256K + +#define RDA_CONNECT_BASE 0x21000000 +#define RDA_CONNECT_SIZE SZ_4K + +#define RDA_L2CC_BASE 0x21100000 +#define RDA_L2CC_SIZE SZ_4K + +/* APB0 */ +#define RDA_INTC_BASE 0x20800000 +#define RDA_INTC_SIZE SZ_4K + +#define RDA_IMEM_BASE 0x20810000 +#define RDA_IMEM_SIZE SZ_4K + +#define RDA_DMA_BASE 0x20820000 +#define RDA_DMA_SIZE SZ_4K + +#define RDA_VPU_BASE 0x20830000 +#define RDA_VPU_SIZE SZ_4K + +#define RDA_GOUDA_BASE 0x20840000 +#define RDA_GOUDA_SIZE SZ_4K + +#define RDA_CAMERA_DMA_BASE 0x20850000 +#define RDA_CAMERA_DMA_SIZE SZ_4K + +/* APB1 */ +#define RDA_SYSCTRL_BASE 0x20900000 +#define RDA_SYSCTRL_SIZE SZ_4K + +#define RDA_TIMER_BASE 0x20910000 +#define RDA_TIMER_SIZE SZ_4K + +#define RDA_KEYPAD_BASE 0x20920000 +#define RDA_KEYPAD_SIZE SZ_4K + +#define RDA_GPIO_A_BASE 0x20930000 +#define RDA_GPIO_A_SIZE SZ_4K + +#define RDA_GPIO_B_BASE 0x20931000 +#define RDA_GPIO_B_SIZE SZ_4K + +#define RDA_GPIO_D_BASE 0x20932000 +#define RDA_GPIO_D_SIZE SZ_4K + +#define RDA_PWM_BASE 0x20940000 +#define RDA_PWM_SIZE SZ_4K + +#define RDA_I2C1_BASE 0x20950000 +#define RDA_I2C1_SIZE SZ_4K + +#define RDA_I2C2_BASE 0x20960000 +#define RDA_I2C2_SIZE SZ_4K + +#define RDA_I2C3_BASE 0x20970000 +#define RDA_I2C3_SIZE SZ_4K + +#define RDA_COMREGS_BASE 0x20980000 +#define RDA_COMREGS_SIZE SZ_4K + +#define RDA_DMC400_BASE 0x20990000 +#define RDA_DMC400_SIZE SZ_4K + +#define RDA_DDRPHY_BASE 0x209A0000 +#define RDA_DDRPHY_SIZE SZ_4K + +#define RDA_DBGAPB_BASE 0x209B0000 +#define RDA_DBGAPB_SIZE SZ_4K + +#define RDA_AIF_BASE 0x209E0000 +#define RDA_AIF_SIZE SZ_4K + +#define RDA_AUIFC_BASE 0x209F0000 +#define RDA_AUIFC_SIZE SZ_4K + +/* APB2 */ +#define RDA_UART1_BASE 0x20A00000 +#define RDA_UART1_SIZE SZ_4K + +#define RDA_UART2_BASE 0x20A10000 +#define RDA_UART2_SIZE SZ_4K + +#define RDA_SPI1_BASE 0x20A20000 +#define RDA_SPI1_SIZE SZ_4K + +#define RDA_SPI2_BASE 0x20A30000 +#define RDA_SPI2_SIZE SZ_4K + +#define RDA_SPI3_BASE 0x20A40000 +#define RDA_SPI3_SIZE SZ_4K + +#define RDA_SDMMC1_BASE 0x20A50000 +#define RDA_SDMMC1_SIZE SZ_4K + +#define RDA_SDMMC2_BASE 0x20A60000 +#define RDA_SDMMC2_SIZE SZ_4K + +#define RDA_SDMMC3_BASE 0x20A70000 +#define RDA_SDMMC3_SIZE SZ_4K + +#define RDA_NAND_BASE 0x20A80000 +#define RDA_NAND_SIZE SZ_16K + +#define RDA_UART3_BASE 0x20A90000 +#define RDA_UART3_SIZE SZ_16K + +#define RDA_IFC_BASE 0x20AF0000 +#define RDA_IFC_SIZE SZ_4K + +#endif /* __IOMAP_RDA8810_H */ diff --git a/arch/arm/include/asm/arch-rda/iomap_rda8810e.h b/arch/arm/include/asm/arch-rda/iomap_rda8810e.h new file mode 100644 index 0000000000..2b9bcac307 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/iomap_rda8810e.h @@ -0,0 +1,180 @@ +#ifndef __IOMAP_RDA8810E_H +#define __IOMAP_RDA8810E_H + +#include <asm/sizes.h> + +#define RDA_SRAM_BASE 0x00100000 +#define RDA_SRAM_SIZE SZ_64K + +#define RDA_MD_MAILBOX_BASE 0x00200000 +#define RDA_MD_MAILBOX_SIZE SZ_8K + +#define RDA_MODEM_BASE 0x10000000 +#define RDA_MODEM_SIZE SZ_256M + +#define RDA_MD_SYSCTRL_BASE 0x11A00000 +#define RDA_MD_SYSCTRL_SIZE SZ_4K + +#define RDA_GPIO_BASE 0x11A08000 +#define RDA_GPIO_SIZE SZ_4K + +#define RDA_CFG_REGS_BASE 0x11A09000 +#define RDA_CFG_REGS_SIZE SZ_4K + +#define RDA_MODEM_SPI2_BASE 0x11A14000 +#define RDA_MODEM_SPI2_SIZE SZ_4K + +#define RDA_MODEM_XCPU_BASE 0x11A16000 +#define RDA_MODEM_XCPU_SIZE SZ_4K + +#define RDA_MODEM_BCPU_BASE 0x11909000 +#define RDA_MODEM_BCPU_SIZE SZ_4K + +#define RDA_MD_PSRAM_BASE (RDA_MODEM_BASE + 0x02000000) +#define RDA_MD_PSRAM_SIZE SZ_4M + +#define RDA_CAMERA_BASE 0x20000000 +#define RDA_CAMERA_SIZE SZ_256K + +#define RDA_GOUDA_MEM_BASE 0x20040000 +#define RDA_GOUDA_MEM_SIZE SZ_256K + +#define RDA_GPU_BASE 0x20080000 +#define RDA_GPU_SIZE SZ_256K + +#define RDA_VOC_BASE 0x200C0000 +#define RDA_VOC_SIZE SZ_256K + +#define RDA_VOC2_BASE 0x20100000 +#define RDA_VOC2_SIZE SZ_256K + +#define RDA_USB_BASE 0x20400000 +#define RDA_USB_SIZE SZ_256K + +#define RDA_SPIFLASH_BASE 0x20440000 +#define RDA_SPIFLASH_SIZE SZ_256K + +#define RDA_CONNECT_BASE 0x21000000 +#define RDA_CONNECT_SIZE SZ_4K + +#define RDA_L2CC_BASE 0x21100000 +#define RDA_L2CC_SIZE SZ_4K + +/* APB0 */ +#define RDA_INTC_BASE 0x20800000 +#define RDA_INTC_SIZE SZ_4K + +#define RDA_IMEM_BASE 0x20810000 +#define RDA_IMEM_SIZE SZ_4K + +#define RDA_DMA_BASE 0x20820000 +#define RDA_DMA_SIZE SZ_4K + +#define RDA_GOUDA_BASE 0x20840000 +#define RDA_GOUDA_SIZE SZ_4K + +#define RDA_CAMERA_DMA_BASE 0x20850000 +#define RDA_CAMERA_DMA_SIZE SZ_4K + +#define RDA_MMU_GOUDA_BASE 0x20860000 +#define RDA_MMU_GOUDA_SIZE SZ_64K + +#define RDA_MMU_CAMERA_BASE 0x20870000 +#define RDA_MMU_CAMERA_SIZE SZ_64K + +#define RDA_MMU_VOC1_BASE 0x20880000 +#define RDA_MMU_VOC1_SIZE SZ_64K + +#define RDA_MMU_VOC2_BASE 0x20890000 +#define RDA_MMU_VOC2_SIZE SZ_64K + +/* APB1 */ +#define RDA_SYSCTRL_BASE 0x20900000 +#define RDA_SYSCTRL_SIZE SZ_4K + +#define RDA_TIMER_BASE 0x20910000 +#define RDA_TIMER_SIZE SZ_4K + +#define RDA_KEYPAD_BASE 0x20920000 +#define RDA_KEYPAD_SIZE SZ_4K + +#define RDA_GPIO_A_BASE 0x20930000 +#define RDA_GPIO_A_SIZE SZ_4K + +#define RDA_GPIO_B_BASE 0x20931000 +#define RDA_GPIO_B_SIZE SZ_4K + +#define RDA_GPIO_D_BASE 0x20932000 +#define RDA_GPIO_D_SIZE SZ_4K + +#define RDA_GPIO_E_BASE 0x20933000 +#define RDA_GPIO_E_SIZE SZ_4K + +#define RDA_PWM_BASE 0x20940000 +#define RDA_PWM_SIZE SZ_4K + +#define RDA_I2C1_BASE 0x20950000 +#define RDA_I2C1_SIZE SZ_4K + +#define RDA_I2C2_BASE 0x20960000 +#define RDA_I2C2_SIZE SZ_4K + +#define RDA_I2C3_BASE 0x20970000 +#define RDA_I2C3_SIZE SZ_4K + +#define RDA_COMREGS_BASE 0x20980000 +#define RDA_COMREGS_SIZE SZ_4K + +#define RDA_DMC400_BASE 0x20990000 +#define RDA_DMC400_SIZE SZ_4K + +#define RDA_DDRPHY_BASE 0x209A0000 +#define RDA_DDRPHY_SIZE SZ_4K + +#define RDA_DBGAPB_BASE 0x209B0000 +#define RDA_DBGAPB_SIZE SZ_4K + +#define RDA_AIF2_BASE 0x209D0000 +#define RDA_AIF2_SIZE SZ_4K + +#define RDA_AIF_BASE 0x209E0000 +#define RDA_AIF_SIZE SZ_4K + +#define RDA_AUIFC_BASE 0x209F0000 +#define RDA_AUIFC_SIZE SZ_4K + +/* APB2 */ +#define RDA_UART1_BASE 0x20A00000 +#define RDA_UART1_SIZE SZ_4K + +#define RDA_UART2_BASE 0x20A10000 +#define RDA_UART2_SIZE SZ_4K + +#define RDA_SPI1_BASE 0x20A20000 +#define RDA_SPI1_SIZE SZ_4K + +#define RDA_SPI2_BASE 0x20A30000 +#define RDA_SPI2_SIZE SZ_4K + +#define RDA_SPI3_BASE 0x20A40000 +#define RDA_SPI3_SIZE SZ_4K + +#define RDA_SDMMC1_BASE 0x20A50000 +#define RDA_SDMMC1_SIZE SZ_4K + +#define RDA_SDMMC2_BASE 0x20A60000 +#define RDA_SDMMC2_SIZE SZ_4K + +#define RDA_SDMMC3_BASE 0x20A70000 +#define RDA_SDMMC3_SIZE SZ_4K + +#define RDA_NAND_BASE 0x20A80000 +#define RDA_NAND_SIZE SZ_16K + +#define RDA_UART3_BASE 0x20A90000 +#define RDA_UART3_SIZE SZ_16K + +#define RDA_IFC_BASE 0x20AF0000 +#define RDA_IFC_SIZE SZ_4K + +#endif /* __IOMAP_RDA8810E_H */ diff --git a/arch/arm/include/asm/arch-rda/iomap_rda8810h.h b/arch/arm/include/asm/arch-rda/iomap_rda8810h.h new file mode 100644 index 0000000000..200ecf1980 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/iomap_rda8810h.h @@ -0,0 +1,192 @@ +#ifndef __IOMAP_RDA8810H_H +#define __IOMAP_RDA8810H_H + +#include <asm/sizes.h> + +#define RDA_SRAM_BASE 0x00100000 +#define RDA_SRAM_SIZE SZ_64K + +#define RDA_MD_MAILBOX_BASE 0x00200000 +#define RDA_MD_MAILBOX_SIZE SZ_8K + +#define RDA_MODEM_BASE 0x10000000 +#define RDA_MODEM_SIZE SZ_256M + +#define RDA_MD_SYSCTRL_BASE 0x11A00000 +#define RDA_MD_SYSCTRL_SIZE SZ_4K + +#define RDA_GPIO_BASE 0x11A08000 +#define RDA_GPIO_SIZE SZ_4K + +#define RDA_CFG_REGS_BASE 0x11A09000 +#define RDA_CFG_REGS_SIZE SZ_4K + +#define RDA_MODEM_SPI2_BASE 0x11A14000 +#define RDA_MODEM_SPI2_SIZE SZ_4K + +#define RDA_MODEM_XCPU_BASE 0x11A16000 +#define RDA_MODEM_XCPU_SIZE SZ_4K + +#define RDA_MODEM_BCPU_BASE 0x11909000 +#define RDA_MODEM_BCPU_SIZE SZ_4K + +#define RDA_MD_PSRAM_BASE (RDA_MODEM_BASE + 0x02000000) +#define RDA_MD_PSRAM_SIZE SZ_4M + +#define RDA_CAMERA_BASE 0x20000000 +#define RDA_CAMERA_SIZE SZ_256K + +#define RDA_GOUDA_MEM_BASE 0x20040000 +#define RDA_GOUDA_MEM_SIZE SZ_256K + +#define RDA_CAMERA2_BASE 0x20080000 +#define RDA_CAMERA2_SIZE SZ_256K + +#define RDA_VOC_BASE 0x200C0000 +#define RDA_VOC_SIZE SZ_256K + +#define RDA_USB_BASE 0x20400000 +#define RDA_USB_SIZE SZ_256K + +#define RDA_SPIFLASH_BASE 0x20440000 +#define RDA_SPIFLASH_SIZE SZ_256K + +#define RDA_ETHERNET_MAC_BASE 0x20480000 +#define RDA_ETHERNET_MAC_SIZE SZ_256K + +#define RDA_CONNECT_BASE 0x21000000 +#define RDA_CONNECT_SIZE SZ_1M + +#define RDA_L2CC_BASE 0x21100000 +#define RDA_L2CC_SIZE SZ_4K + +/* APB0 */ +#define RDA_INTC_BASE 0x20800000 +#define RDA_INTC_SIZE SZ_64K + +#define RDA_IMEM_BASE 0x20810000 +#define RDA_IMEM_SIZE SZ_64K + +#define RDA_DMA_BASE 0x20820000 +#define RDA_DMA_SIZE SZ_64K + +#define RDA_VPU_BASE 0x20830000 +#define RDA_VPU_SIZE SZ_64K + +#define RDA_GOUDA_BASE 0x20840000 +#define RDA_GOUDA_SIZE SZ_64K + +#define RDA_CAMERA_DMA_BASE 0x20850000 +#define RDA_CAMERA_DMA_SIZE SZ_64K + +#define RDA_MALI_GOUDA_BASE 0x20860000 +#define RDA_MALI_GOUDA_SIZE SZ_64K + +#define RDA_MMU_CAMERA2_BASE 0x20870000 +#define RDA_MMU_CAMERA2_SIZE SZ_64K + +#define RDA_MMU_VOC1_BASE 0x20880000 +#define RDA_MMU_VOC1_SIZE SZ_64K + +/* APB1 */ +#define RDA_SYSCTRL_BASE 0x20900000 +#define RDA_SYSCTRL_SIZE SZ_64K + +#define RDA_TIMER_BASE 0x20910000 +#define RDA_TIMER_SIZE SZ_4K + +#define RDA_TIMER1_BASE 0x20911000 +#define RDA_TIMER1_SIZE SZ_4K + +#define RDA_TIMER2_BASE 0x20912000 +#define RDA_TIMER2_SIZE SZ_4K + +#define RDA_KEYPAD_BASE 0x20920000 +#define RDA_KEYPAD_SIZE SZ_64K + +#define RDA_GPIO_A_BASE 0x20930000 +#define RDA_GPIO_A_SIZE SZ_4K + +#define RDA_GPIO_B_BASE 0x20931000 +#define RDA_GPIO_B_SIZE SZ_4K + +#define RDA_GPIO_D_BASE 0x20932000 +#define RDA_GPIO_D_SIZE SZ_4K + +#define RDA_GPIO_E_BASE 0x20933000 +#define RDA_GPIO_E_SIZE SZ_4K + +#define RDA_PWM_BASE 0x20940000 +#define RDA_PWM_SIZE SZ_64K + +#define RDA_COMREGS_BASE 0x20980000 +#define RDA_COMREGS_SIZE SZ_64K + +#define RDA_DMC400_BASE 0x20990000 +#define RDA_DMC400_SIZE SZ_4K + +#define RDA_DMCPAGESPY_BASE 0x20991000 +#define RDA_DMCPAGESPY_SIZE SZ_4K + +#define RDA_DDRPHY_BASE 0x209A0000 +#define RDA_DDRPHY_SIZE SZ_64K + +#define RDA_DBGAPB_BASE 0x209B0000 +#define RDA_DBGAPB_SIZE SZ_64K + +#define RDA_AIF2_BASE 0x209D0000 +#define RDA_AIF2_SIZE SZ_64K + +#define RDA_AIF_BASE 0x209E0000 +#define RDA_AIF_SIZE SZ_64K + +#define RDA_AUIFC_BASE 0x209F0000 +#define RDA_AUIFC_SIZE SZ_64K + +/* APB2 */ +#define RDA_UART1_BASE 0x20A00000 +#define RDA_UART1_SIZE SZ_4K + +#define RDA_UART2_BASE 0x20A10000 +#define RDA_UART2_SIZE SZ_4K + +#define RDA_SPI1_BASE 0x20A20000 +#define RDA_SPI1_SIZE SZ_4K + +#define RDA_SPI2_BASE 0x20A30000 +#define RDA_SPI2_SIZE SZ_4K + +#define RDA_SPI3_BASE 0x20A40000 +#define RDA_SPI3_SIZE SZ_4K + +#define RDA_SDMMC1_BASE 0x20A50000 +#define RDA_SDMMC1_SIZE SZ_4K + +#define RDA_SDMMC2_BASE 0x20A60000 +#define RDA_SDMMC2_SIZE SZ_4K + +#define RDA_SDMMC3_BASE 0x20A70000 +#define RDA_SDMMC3_SIZE SZ_4K + +#define RDA_NAND_BASE 0x20A80000 +#define RDA_NAND_SIZE SZ_64K + +#define RDA_UART3_BASE 0x20A90000 +#define RDA_UART3_SIZE SZ_16K + +#define RDA_A7MP2APB_BASE 0x20AA0000 +#define RDA_A7MP2APB_SIZE SZ_64K + +#define RDA_I2C1_BASE 0x20AB0000 +#define RDA_I2C1_SIZE SZ_64K + +#define RDA_I2C2_BASE 0x20AC0000 +#define RDA_I2C2_SIZE SZ_64K + +#define RDA_I2C3_BASE 0x20AD0000 +#define RDA_I2C3_SIZE SZ_64K + +#define RDA_IFC_BASE 0x20AF0000 +#define RDA_IFC_SIZE SZ_4K + +#endif /* __IOMAP_RDA8810H_H */ diff --git a/arch/arm/include/asm/arch-rda/iomap_rda8820.h b/arch/arm/include/asm/arch-rda/iomap_rda8820.h new file mode 100644 index 0000000000..b1cfef3381 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/iomap_rda8820.h @@ -0,0 +1,196 @@ +#ifndef __IOMAP_RDA8820_H +#define __IOMAP_RDA8820_H + +#define RDA_SRAM_BASE 0x00100000 +#define RDA_SRAM_SIZE SZ_64K + +#define RDA_MD_MAILBOX_BASE 0x00200000 +#define RDA_MD_MAILBOX_SIZE SZ_8K + +#define RDA_MODEM_BASE 0x10000000 +#define RDA_MODEM_SIZE SZ_256M + +#define RDA_MD_SYSCTRL_BASE 0x11A00000 +#define RDA_MD_SYSCTRL_SIZE SZ_4K + +#define RDA_GPIO_BASE 0x11A08000 +#define RDA_GPIO_SIZE SZ_4K + +#define RDA_CFG_REGS_BASE 0x11A09000 +#define RDA_CFG_REGS_SIZE SZ_4K + +#define RDA_MODEM_SPI2_BASE 0x11A14000 +#define RDA_MODEM_SPI2_SIZE SZ_4K + +#define RDA_MODEM_XCPU_BASE 0x11A17000 +#define RDA_MODEM_XCPU_SIZE SZ_4K + +#define RDA_MODEM_BCPU_BASE 0x11909000 +#define RDA_MODEM_BCPU_SIZE SZ_4K + +#define RDA_MD_PSRAM_BASE (RDA_MODEM_BASE + 0x02000000) +#define RDA_MD_PSRAM_SIZE SZ_16M + +#define RDA_CAMERA_BASE 0x20000000 +#define RDA_CAMERA_SIZE SZ_256K + +#define RDA_GOUDA_MEM_BASE 0x20040000 +#define RDA_GOUDA_MEM_SIZE SZ_256K + +#define RDA_GPU_BASE 0x20080000 +#define RDA_GPU_SIZE SZ_256K + +#define RDA_VOC_BASE 0x200C0000 +#define RDA_VOC_SIZE SZ_256K + +#define RDA_VOC2_BASE 0x20100000 +#define RDA_VOC2_SIZE SZ_256K + +#define RDA_USB_BASE 0x20400000 +#define RDA_USB_SIZE SZ_256K + +#define RDA_SPIFLASH_BASE 0x20440000 +#define RDA_SPIFLASH_SIZE SZ_256K + +#define RDA_CONNECT_BASE 0x21000000 +#define RDA_CONNECT_SIZE SZ_4K + +#define RDA_L2CC_BASE 0x21100000 +#define RDA_L2CC_SIZE SZ_4K + +/* APB0 */ +#define RDA_INTC_BASE 0x20800000 +#define RDA_INTC_SIZE SZ_4K + +#define RDA_IMEM_BASE 0x20810000 +#define RDA_IMEM_SIZE SZ_4K + +#define RDA_DMA_BASE 0x20820000 +#define RDA_DMA_SIZE SZ_4K + +#define RDA_VPU_BASE 0x20830000 +#define RDA_VPU_SIZE SZ_64K + +#define RDA_GOUDA_BASE 0x20840000 +#define RDA_GOUDA_SIZE SZ_4K + +#define RDA_CAMERA_DMA_BASE 0x20850000 +#define RDA_CAMERA_DMA_SIZE SZ_4K + +#define RDA_CAMERA2_DMA_BASE 0x20860000 +#define RDA_CAMERA2_DMA_SIZE SZ_64K + +#define RDA_GPU_BASE 0x20870000 +#define RDA_GPU_SIZE SZ_64K + +#define RDA_AES_BASE 0x20880000 +#define RDA_AES_SIZE SZ_64K + +#define RDA_JPEG_BASE 0x20890000 +#define RDA_JPEG_SIZE SZ_64K + +/* APB1 */ +#define RDA_SYSCTRL_BASE 0x20900000 +#define RDA_SYSCTRL_SIZE SZ_4K + +#define RDA_TIMER_BASE 0x20910000 +#define RDA_TIMER_SIZE SZ_4K + +#define RDA_KEYPAD_BASE 0x20920000 +#define RDA_KEYPAD_SIZE SZ_4K + +#define RDA_GPIO_A_BASE 0x20930000 +#define RDA_GPIO_A_SIZE SZ_4K + +#define RDA_GPIO_B_BASE 0x20931000 +#define RDA_GPIO_B_SIZE SZ_4K + +#define RDA_GPIO_D_BASE 0x20932000 +#define RDA_GPIO_D_SIZE SZ_4K + +#define RDA_GPIO_E_BASE 0x20933000 +#define RDA_GPIO_E_SIZE SZ_4K + +#define RDA_PWM_BASE 0x20940000 +#define RDA_PWM_SIZE SZ_4K + +#define RDA_LVDS_BASE 0x20950000 +#define RDA_LVDS_SIZE SZ_4K + +#define RDA_TVCLK_BASE 0x20960000 +#define RDA_TVCLK_SIZE SZ_4K + +#define RDA_GIC400_BASE 0x20970000 +#define RDA_GIC400_SIZE SZ_4K + +#define RDA_COMREGS_BASE 0x20980000 +#define RDA_COMREGS_SIZE SZ_4K + +#define RDA_DMC400_BASE 0x20990000 +#define RDA_DMC400_SIZE SZ_4K + +#define RDA_DDRPHY_BASE 0x209A0000 +#define RDA_DDRPHY_SIZE SZ_4K + +#define RDA_PDCTRL_BASE 0x209B0000 +#define RDA_PDCTRL_SIZE SZ_4K + +#define RDA_ISP_BASE 0x209C0000 +#define RDA_ISP_SIZE SZ_4K + +#define RDA_AIF2_BASE 0x209D0000 +#define RDA_AIF2_SIZE SZ_4K + +#define RDA_AIF_BASE 0x209E0000 +#define RDA_AIF_SIZE SZ_4K + +#define RDA_AUIFC_BASE 0x209F0000 +#define RDA_AUIFC_SIZE SZ_4K + +/* APB2 */ +#define RDA_UART1_BASE 0x20A00000 +#define RDA_UART1_SIZE SZ_4K + +#define RDA_UART2_BASE 0x20A10000 +#define RDA_UART2_SIZE SZ_4K + +#define RDA_SPI1_BASE 0x20A20000 +#define RDA_SPI1_SIZE SZ_4K + +#define RDA_SPI2_BASE 0x20A30000 +#define RDA_SPI2_SIZE SZ_4K + +#define RDA_SPI3_BASE 0x20A40000 +#define RDA_SPI3_SIZE SZ_4K + +#define RDA_SDMMC1_BASE 0x20A50000 +#define RDA_SDMMC1_SIZE SZ_4K + +#define RDA_SDMMC2_BASE 0x20A60000 +#define RDA_SDMMC2_SIZE SZ_4K + +#define RDA_SDMMC3_BASE 0x20A70000 +#define RDA_SDMMC3_SIZE SZ_4K + +#define RDA_NAND_BASE 0x20A80000 +#define RDA_NAND_SIZE SZ_16K + +#define RDA_UART3_BASE 0x20A90000 +#define RDA_UART3_SIZE SZ_16K + +#define RDA_I2C1_BASE 0x20AB0000 +#define RDA_I2C1_SIZE SZ_4K + +#define RDA_I2C2_BASE 0x20AC0000 +#define RDA_I2C2_SIZE SZ_4K + +#define RDA_I2C3_BASE 0x20AD0000 +#define RDA_I2C3_SIZE SZ_4K + +#define RDA_UART4_BASE 0x20AE0000 +#define RDA_UART4_SIZE SZ_16K + +#define RDA_IFC_BASE 0x20AF0000 +#define RDA_IFC_SIZE SZ_4K + +#endif /* __IOMAP_RDA8820_H */ diff --git a/arch/arm/include/asm/arch-rda/iomap_rda8850.h b/arch/arm/include/asm/arch-rda/iomap_rda8850.h new file mode 100644 index 0000000000..0cfad5dae8 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/iomap_rda8850.h @@ -0,0 +1,163 @@ +#ifndef __IOMAP_RDA8850_H +#define __IOMAP_RDA8850_H + +#define RDA_SRAM_BASE 0x00100000 +#define RDA_SRAM_SIZE SZ_64K + +#define RDA_MD_MAILBOX_BASE 0x00200000 +#define RDA_MD_MAILBOX_SIZE SZ_8K + +#define RDA_MODEM_BASE 0x10000000 +#define RDA_MODEM_SIZE SZ_256M + +#define RDA_MD_SYSCTRL_BASE 0x11A00000 +#define RDA_MD_SYSCTRL_SIZE SZ_4K + +#define RDA_GPIO_BASE 0x11A08000 +#define RDA_GPIO_SIZE SZ_4K + +#define RDA_CFG_REGS_BASE 0x11A09000 +#define RDA_CFG_REGS_SIZE SZ_4K + +#define RDA_MODEM_SPI2_BASE 0x11A14000 +#define RDA_MODEM_SPI2_SIZE SZ_4K + +#define RDA_MODEM_XCPU_BASE 0x11A16000 +#define RDA_MODEM_XCPU_SIZE SZ_4K + +#define RDA_MODEM_BCPU_BASE 0x1190D000 +#define RDA_MODEM_BCPU_SIZE SZ_4K + +#define RDA_MD_PSRAM_BASE (RDA_MODEM_BASE + 0x02000000) +#define RDA_MD_PSRAM_SIZE SZ_16M + +#define RDA_CAMERA_BASE 0x20000000 +#define RDA_CAMERA_SIZE SZ_256K + +#define RDA_GOUDA_MEM_BASE 0x20040000 +#define RDA_GOUDA_MEM_SIZE SZ_256K + +#define RDA_GPU_BASE 0x20080000 +#define RDA_GPU_SIZE SZ_256K + +#define RDA_VOC_BASE 0x200C0000 +#define RDA_VOC_SIZE SZ_256K + +#define RDA_VOC2_BASE 0x20100000 +#define RDA_VOC2_SIZE SZ_256K + +#define RDA_USB_BASE 0x20400000 +#define RDA_USB_SIZE SZ_256K + +#define RDA_SPIFLASH_BASE 0x20440000 +#define RDA_SPIFLASH_SIZE SZ_256K + +#define RDA_CONNECT_BASE 0x21000000 +#define RDA_CONNECT_SIZE SZ_4K + +#define RDA_L2CC_BASE 0x21100000 +#define RDA_L2CC_SIZE SZ_4K + +/* APB0 */ +#define RDA_INTC_BASE 0x20800000 +#define RDA_INTC_SIZE SZ_4K + +#define RDA_IMEM_BASE 0x20810000 +#define RDA_IMEM_SIZE SZ_4K + +#define RDA_DMA_BASE 0x20820000 +#define RDA_DMA_SIZE SZ_4K + +#define RDA_VPU_BASE 0x20830000 +#define RDA_VPU_SIZE SZ_64K + +#define RDA_GOUDA_BASE 0x20840000 +#define RDA_GOUDA_SIZE SZ_4K + +#define RDA_CAMERA_DMA_BASE 0x20850000 +#define RDA_CAMERA_DMA_SIZE SZ_4K + +/* APB1 */ +#define RDA_SYSCTRL_BASE 0x20900000 +#define RDA_SYSCTRL_SIZE SZ_4K + +#define RDA_TIMER_BASE 0x20910000 +#define RDA_TIMER_SIZE SZ_4K + +#define RDA_KEYPAD_BASE 0x20920000 +#define RDA_KEYPAD_SIZE SZ_4K + +#define RDA_GPIO_A_BASE 0x20930000 +#define RDA_GPIO_A_SIZE SZ_4K + +#define RDA_GPIO_B_BASE 0x20931000 +#define RDA_GPIO_B_SIZE SZ_4K + +#define RDA_GPIO_D_BASE 0x20932000 +#define RDA_GPIO_D_SIZE SZ_4K + +#define RDA_PWM_BASE 0x20940000 +#define RDA_PWM_SIZE SZ_4K + +#define RDA_I2C1_BASE 0x20950000 +#define RDA_I2C1_SIZE SZ_4K + +#define RDA_I2C2_BASE 0x20960000 +#define RDA_I2C2_SIZE SZ_4K + +#define RDA_I2C3_BASE 0x20970000 +#define RDA_I2C3_SIZE SZ_4K + +#define RDA_COMREGS_BASE 0x20980000 +#define RDA_COMREGS_SIZE SZ_4K + +#define RDA_DMC400_BASE 0x20990000 +#define RDA_DMC400_SIZE SZ_4K + +#define RDA_DDRPHY_BASE 0x209A0000 +#define RDA_DDRPHY_SIZE SZ_4K + +#define RDA_APDEBUG_BASE 0x209B0000 +#define RDA_APDEBUG_SIZE SZ_4K + +#define RDA_AIF_BASE 0x209E0000 +#define RDA_AIF_SIZE SZ_4K + +#define RDA_AUIFC_BASE 0x209F0000 +#define RDA_AUIFC_SIZE SZ_4K + +/* APB2 */ +#define RDA_UART1_BASE 0x20A00000 +#define RDA_UART1_SIZE SZ_4K + +#define RDA_UART2_BASE 0x20A10000 +#define RDA_UART2_SIZE SZ_4K + +#define RDA_SPI1_BASE 0x20A20000 +#define RDA_SPI1_SIZE SZ_4K + +#define RDA_SPI2_BASE 0x20A30000 +#define RDA_SPI2_SIZE SZ_4K + +#define RDA_SPI3_BASE 0x20A40000 +#define RDA_SPI3_SIZE SZ_4K + +#define RDA_SDMMC1_BASE 0x20A50000 +#define RDA_SDMMC1_SIZE SZ_4K + +#define RDA_SDMMC2_BASE 0x20A60000 +#define RDA_SDMMC2_SIZE SZ_4K + +#define RDA_SDMMC3_BASE 0x20A70000 +#define RDA_SDMMC3_SIZE SZ_4K + +#define RDA_NAND_BASE 0x20A80000 +#define RDA_NAND_SIZE SZ_16K + +#define RDA_UART3_BASE 0x20A90000 +#define RDA_UART3_SIZE SZ_16K + +#define RDA_IFC_BASE 0x20AF0000 +#define RDA_IFC_SIZE SZ_4K + +#endif /* __IOMAP_RDA8850_H */ diff --git a/arch/arm/include/asm/arch-rda/iomap_rda8850e.h b/arch/arm/include/asm/arch-rda/iomap_rda8850e.h new file mode 100644 index 0000000000..dfa6a7e781 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/iomap_rda8850e.h @@ -0,0 +1,184 @@ +#ifndef __IOMAP_RDA8850_H +#define __IOMAP_RDA8850_H + +#define RDA_SRAM_BASE 0x00100000 +#define RDA_SRAM_SIZE SZ_64K + +#define RDA_MD_MAILBOX_BASE 0x00200000 +#define RDA_MD_MAILBOX_SIZE SZ_8K + +#define RDA_MODEM_BASE 0x10000000 +#define RDA_MODEM_SIZE SZ_256M + +#define RDA_MD_SYSCTRL_BASE 0x11A00000 +#define RDA_MD_SYSCTRL_SIZE SZ_4K + +#define RDA_GPIO_BASE 0x11A08000 +#define RDA_GPIO_SIZE SZ_4K + +#define RDA_CFG_REGS_BASE 0x11A09000 +#define RDA_CFG_REGS_SIZE SZ_4K + +#define RDA_CFG_RF_SPI_BASE 0x11A0E000 +#define RDA_CFG_SIZE SZ_4K + +#define RDA_MODEM_SPI2_BASE 0x11A14000 +#define RDA_MODEM_SPI2_SIZE SZ_4K + +#define RDA_MODEM_XCPU_BASE 0x11A16000 +#define RDA_MODEM_XCPU_SIZE SZ_4K + +#define RDA_MODEM_BCPU_BASE 0x11909000 +#define RDA_MODEM_BCPU_SIZE SZ_4K + +#define RDA_MD_PSRAM_BASE (RDA_MODEM_BASE + 0x02000000) +#define RDA_MD_PSRAM_SIZE SZ_4M + +#define RDA_CAMERA_BASE 0x20000000 +#define RDA_CAMERA_SIZE SZ_256K + +#define RDA_GOUDA_MEM_BASE 0x20040000 +#define RDA_GOUDA_MEM_SIZE SZ_256K + +#define RDA_VOC_BASE 0x200C0000 +#define RDA_VOC_SIZE SZ_256K + +#define RDA_USB_BASE 0x20400000 +#define RDA_USB_SIZE SZ_256K + +#define RDA_SPIFLASH_BASE 0x20440000 +#define RDA_SPIFLASH_SIZE SZ_256K + +#define RDA_CONNECT_BASE 0x21000000 +#define RDA_CONNECT_SIZE SZ_4K + +#define RDA_L2CC_BASE 0x21100000 +#define RDA_L2CC_SIZE SZ_4K + +/* APB0 */ +#define RDA_INTC_BASE 0x20800000 +#define RDA_INTC_SIZE SZ_64K + +#define RDA_IMEM_BASE 0x20810000 +#define RDA_IMEM_SIZE SZ_64K + +#define RDA_DMA_BASE 0x20820000 +#define RDA_DMA_SIZE SZ_64K + +#define RDA_VPU_BASE 0x20830000 +#define RDA_VPU_SIZE SZ_64K + +#define RDA_GOUDA_BASE 0x20840000 +#define RDA_GOUDA_SIZE SZ_64K + +#define RDA_CAMERA_DMA_BASE 0x20850000 +#define RDA_CAMERA_DMA_SIZE SZ_64K + +#define RDA_LCDC_BASE 0x20860000 +#define RDA_LCDC_SIZE SZ_664K + +#define RDA_GPU_BASE 0x20870000 +#define RDA_GPU_SIZE SZ_64K + +#define RDA_JPEG_BASE 0x20890000 +#define RDA_JPEG_SIZE SZ_64K + +#define RDA_CPU_DEBUG_BASE 0x208C0000 +#define RDA_CPU_DEBUG_SIZE SZ_256K + +/* APB1 */ +#define RDA_SYSCTRL_BASE 0x20900000 +#define RDA_SYSCTRL_SIZE SZ_64K + +#define RDA_TIMER_BASE 0x20910000 +#define RDA_TIMER_SIZE SZ_64K + +#define RDA_KEYPAD_BASE 0x20920000 +#define RDA_KEYPAD_SIZE SZ_64K + +#define RDA_GPIO_A_BASE 0x20930000 +#define RDA_GPIO_A_SIZE SZ_4K + +#define RDA_GPIO_B_BASE 0x20931000 +#define RDA_GPIO_B_SIZE SZ_4K + +#define RDA_GPIO_D_BASE 0x20932000 +#define RDA_GPIO_D_SIZE SZ_4K + +#define RDA_PWM_BASE 0x20940000 +#define RDA_PWM_SIZE SZ_4K + +#define RDA_TV_CLK_CTRL_BASE 0x20960000 +#define RDA_TV_CLK_CTRL_SIZE SZ_64K + +#define RDA_COMREGS_BASE 0x20980000 +#define RDA_COMREGS_SIZE SZ_4K + +#define RDA_DMC400_BASE 0x20990000 +#define RDA_DMC400_SIZE SZ_4K + +#define RDA_DDRPHY_BASE 0x209A0000 +#define RDA_DDRPHY_SIZE SZ_4K + +#define RDA_APDEBUG_BASE 0x209B0000 +#define RDA_APDEBUG_SIZE SZ_4K + +#define RDA_AIF2_BASE 0x209D0000 +#define RDA_AIF2_SIZE SZ_64K + +#define RDA_AIF_BASE 0x209E0000 +#define RDA_AIF_SIZE SZ_4K + +#define RDA_AUIFC_BASE 0x209F0000 +#define RDA_AUIFC_SIZE SZ_4K + +/* APB2 */ +#define RDA_UART1_BASE 0x20A00000 +#define RDA_UART1_SIZE SZ_4K + +#define RDA_UART2_BASE 0x20A10000 +#define RDA_UART2_SIZE SZ_4K + +#define RDA_SPI1_BASE 0x20A20000 +#define RDA_SPI1_SIZE SZ_4K + +#define RDA_SPI2_BASE 0x20A30000 +#define RDA_SPI2_SIZE SZ_4K + +#define RDA_SPI3_BASE 0x20A40000 +#define RDA_SPI3_SIZE SZ_4K + +#define RDA_SDMMC1_BASE 0x20A50000 +#define RDA_SDMMC1_SIZE SZ_4K + +#define RDA_SDMMC2_BASE 0x20A60000 +#define RDA_SDMMC2_SIZE SZ_4K + +#define RDA_SDMMC3_BASE 0x20A70000 +#define RDA_SDMMC3_SIZE SZ_4K + +#define RDA_NAND_BASE 0x20A80000 +#define RDA_NAND_SIZE SZ_64K + +#define RDA_UART3_BASE 0x20A90000 +#define RDA_UART3_SIZE SZ_16K + +#define RDA_GIC_BASE 0x20AA0000 +#define RDA_GIC_SIZE SZ_64K + +#define RDA_I2C1_BASE 0x20AB0000 +#define RDA_I2C1_SIZE SZ_64K + +#define RDA_I2C2_BASE 0x20AC0000 +#define RDA_I2C2_SIZE SZ_64K + +#define RDA_I2C3_BASE 0x20AD0000 +#define RDA_I2C3_SIZE SZ_64K + +#define RDA_UART4_BASE 0x20AE0000 +#define RDA_UART4_SIZE SZ_64K + +#define RDA_IFC_BASE 0x20AF0000 +#define RDA_IFC_SIZE SZ_4K + +#endif /* __IOMAP_RDA8850_H */ diff --git a/arch/arm/include/asm/arch-rda/iomap_rdaarm926ejs.h b/arch/arm/include/asm/arch-rda/iomap_rdaarm926ejs.h new file mode 100644 index 0000000000..8bc634f72f --- /dev/null +++ b/arch/arm/include/asm/arch-rda/iomap_rdaarm926ejs.h @@ -0,0 +1,48 @@ +#ifndef __IOMAP_RDAARM926EJS_H +#define __IOMAP_RDAARM926EJS_H + +#include <asm/sizes.h> + +#define RDA_INTC_BASE 0x01AF0000 +#define RDA_INTC_SIZE SZ_4K + +#define RDA_TIMER_BASE 0x01A02000 +#define RDA_TIMER_SIZE SZ_4K + +#define RDA_GPIO_BASE 0x01A03000 +#define RDA_GPIO_SIZE SZ_4K + +#define RDA_KEYPAD_BASE 0x01A05000 +#define RDA_KEYPAD_SIZE SZ_4K + +#define RDA_I2C1_BASE 0x01A07000 +#define RDA_I2C1_SIZE SZ_4K + +#define RDA_I2C2_BASE 0x01A22000 +#define RDA_I2C2_SIZE SZ_4K + +#define RDA_I2C3_BASE 0x01A23000 +#define RDA_I2C3_SIZE SZ_4K + +#define RDA_IFC_BASE 0x01A09000 +#define RDA_IFC_SIZE SZ_4K + +#define RDA_UART1_BASE 0x01A15000 +#define RDA_UART1_SIZE SZ_4K + +#define RDA_UART2_BASE 0x01A16000 +#define RDA_UART2_SIZE SZ_4K + +#define RDA_SDMMC1_BASE 0x01A17000 +#define RDA_SDMMC1_SIZE SZ_4K + +#define RDA_GOUDA_BASE 0x01A21000 +#define RDA_GOUDA_SIZE SZ_4K + +#define RDA_NAND_BASE 0x01A26000 +#define RDA_NAND_SIZE SZ_16K + +#define RDA_USB_BASE 0x01A80000 +#define RDA_USB_SIZE SZ_64K + +#endif /* __IOMAP_RDAARM926EJS_H */ diff --git a/arch/arm/include/asm/arch-rda/irqs.h b/arch/arm/include/asm/arch-rda/irqs.h new file mode 100644 index 0000000000..9812d0014d --- /dev/null +++ b/arch/arm/include/asm/arch-rda/irqs.h @@ -0,0 +1,58 @@ +/* include/asm-arm/arch-goldfish/irqs.h +** +** Copyright (C) 2007 Google, Inc. +** +** This software is licensed under the terms of the GNU General Public +** License version 2, as published by the Free Software Foundation, and +** may be copied, distributed, and modified under those terms. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +** +*/ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#define RDA_IRQ_PULSE_DUMMY 0 +#define RDA_IRQ_I2C 1 +#define RDA_IRQ_NAND_NFSC 2 +#define RDA_IRQ_SDMMC1 3 +#define RDA_IRQ_SDMMC2 4 +#define RDA_IRQ_SDMMC3 5 +#define RDA_IRQ_SPI1 6 +#define RDA_IRQ_SPI2 7 +#define RDA_IRQ_SPI3 8 +#define RDA_IRQ_UART1 9 +#define RDA_IRQ_UART2 10 +#define RDA_IRQ_UART3 11 +#define RDA_IRQ_GPIO1 12 +#define RDA_IRQ_GPIO2 13 +#define RDA_IRQ_GPIO3 14 +#define RDA_IRQ_KEYPAD 15 +#define RDA_IRQ_TIMER 16 +#define RDA_IRQ_TIMEROS 17 +#define RDA_IRQ_COMREG0 18 +#define RDA_IRQ_COMREG1 19 +#define RDA_IRQ_USB 20 +#define RDA_IRQ_DMC 21 +#define RDA_IRQ_DMA 22 +#define RDA_IRQ_CAMERA 23 +#define RDA_IRQ_GOUDA 24 +#define RDA_IRQ_GPU 25 +#define RDA_IRQ_VPU_JPG 26 +#define RDA_IRQ_VPU_HOST 27 +#define RDA_IRQ_VOC 28 +#define RDA_IRQ_AUIFC0 29 +#define RDA_IRQ_AUIFC1 30 +#define RDA_IRQ_L2CC 31 + +#define RDA_IRQ_NUM 32 + +#define RDA_IRQ_MASK_ALL 0xFFFFFFFF + +#define NR_IRQS RDA_IRQ_NUM + +#endif diff --git a/arch/arm/include/asm/arch-rda/ispi.h b/arch/arm/include/asm/arch-rda/ispi.h new file mode 100644 index 0000000000..eabec39107 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/ispi.h @@ -0,0 +1,12 @@ +#ifndef __ISPI_H__ +#define __ISPI_H_ + +#define pmu_reg_write ispi_reg_write +#define pmu_reg_read ispi_reg_read + +void ispi_open(int modemSpi); +void ispi_reg_write(u32 regIdx, u32 value); +u32 ispi_reg_read(u32 regIdx); +u16 rda_read_efuse(int page_index); +#endif + diff --git a/arch/arm/include/asm/arch-rda/mdcom.h b/arch/arm/include/asm/arch-rda/mdcom.h new file mode 100644 index 0000000000..ffb520c5c9 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/mdcom.h @@ -0,0 +1,166 @@ +#ifndef _MDCOM_H_ +#define _MDCOM_H_ + +#ifdef RDA_MDCOM_DEBUG +#define rdamddbg(fmt,args...) printf (fmt ,##args) +#else +#define rdamddbg(fmt,args...) +#endif /* RDA_MDCOM_DEBUG */ + +/* + * Note : + * The number of version will be updated according to version of BP. + */ +#define RDA_BP_VER 0x00010001 + + +typedef enum +{ + /* Normal cause, ie power up */ + RDA_RESET_CAUSE_NORMAL = 0x0, + /* The reset was caused by a watchdog */ + RDA_RESET_CAUSE_WATCHDOG = 0x1, + /* The reset was caused by a soft restart, triggered by the function */ + RDA_RESET_CAUSE_RESTART = 0x2, + /* The reset was initiated from the Host Interface. */ + RDA_RESET_CAUSE_HOST_DEBUG = 0x3, + /* The reset was caused by alarm, from the calendar. */ + RDA_RESET_CAUSE_ALARM = 0x4, + + RDA_RESET_CAUSE_CHARGER = 0x80, + + RDA_RESET_CAUSE_QTY + +} RDA_RESET_CAUSE_T; + +/* + * PORT, LINE + */ +typedef enum { + RDA_MDCOM_PORT0, + RDA_MDCOM_PORT1, +} rda_mdcom_port_id_t; + +typedef enum { + RDA_MDCOM_LINE_MODEM_RESET, // inform AP Modem reset done + RDA_MDCOM_LINE_DL_HANDSHAKE, // for AP download BB code + RDA_MDCOM_LINE_CMD_START, // for port1 command start + RDA_MDCOM_LINE_SLEEP_WAKEUP, // for sleep/wakeup status + RDA_MDCOM_LINE_EXCEPTION, // for exception +} rda_mdcom_port0_line_id_t; + +typedef enum { + RDA_MDCOM_LINE_AT_CMD, // for AT command + RDA_MDCOM_LINE_AT_CMD_FC, // for AT command Flow control + RDA_MDCOM_LINE_SYSTEM, // for SYSTEM command + RDA_MDCOM_LINE_SYSTEM_FC, // for AT command Flow control + RDA_MDCOM_LINE_TRACE, // for Trace communciation + RDA_MDCOM_LINE_TRACE_FC, // for Trace communciation Flow control +} rda_mdcom_port1_line_id_t; + +void rda_mdcom_set_logic_base_addr(u32 base); + +u32 rda_mdcom_address_modem2ap(u32 addr); + +int rda_mdcom_setup_run_env(u32 pc, u32 param); + +void rda_mdcom_get_calib_section(u32 *addr, u32 *len); +void rda_mdcom_get_ext_calib_section(u32 *addr, u32 *len); +void rda_mdcom_get_factory_section(u32 *addr, u32 *len); +void rda_mdcom_get_ap_factory_section(u32 *addr, u32 *len); + +u32 rda_mdcom_get_reset_cause(void); +u32 rda_mdcom_get_interface_version(void); + +int rda_mdcom_system_started_before(void); +void rda_mdcom_set_system_started_flag(void); +int rda_mdcom_modem_crashed_before(void); +int rda_mdcom_calib_update_cmd_valid(void); +int rda_mdcom_factory_update_cmd_valid(void); +int rda_mdcom_ap_factory_update_cmd_valid(void); + +void rda_mdcom_init_all_log_info(void); +void rda_mdcom_get_modem_log_info(u32 *addr, u32 *len); +void rda_mdcom_get_modem_exception_info(u32 *addr, u32 *len); + +void rda_mdcom_show_xcpu_info(void); +void rda_mdcom_show_software_version(void); + +int rda_mdcom_init_port(int port_id); + +int rda_mdcom_line_set(int port_id, int line_id); +int rda_mdcom_line_set_check(int port_id, int line_id); +int rda_mdcom_line_set_wait(int port_id, int line_id, int waittime); + +int rda_mdcom_line_clear(int port_id, int line_id); +int rda_mdcom_line_clear_check(int port_id, int line_id); +int rda_mdcom_line_clear_wait(int port_id, int line_id, int waittime); + +void rda_mdcom_port_show(void); + +typedef enum { + RDA_MDCOM_CHANNEL_AT, // for AT command + RDA_MDCOM_CHANNEL_SYSTEM, // for SYSTEM command + RDA_MDCOM_CHANNEL_TRACE, // for Trace communication +} rda_mdcom_channel_id_t; + +struct rda_mdcom_channel_head { + volatile int read_offset; // offset of the read pointer + volatile int write_offset; // offset of the write pointer + volatile int reserved0; // reserved + volatile int reserved1; // reserved +}; + +struct rda_mdcom_channel { + int data_line_id; + int fc_line_id; + + // the address of 16-byte buffer head + struct rda_mdcom_channel_head* read_buf_head; + void* read_buf; // the start address of modem to AP buffer + int read_buf_size_mask; // the mask of modem to AP buffer size + + // the address of 16-byte buffer head + struct rda_mdcom_channel_head* write_buf_head; + void* write_buf; // the start address of AP to modem buffer + int write_buf_size_mask; // the mask of AP to modem buffer size +}; + +int rda_mdcom_channel_init(const unsigned int channel); +int rda_mdcom_channel_all_init(void); +int rda_mdcom_channel_buf_send_stream(const unsigned int channel, void *buf, int size, int waittime); +int rda_mdcom_channel_buf_send_dgram(const unsigned int channel, void *buf, int size, int waittime); +int rda_mdcom_channel_buf_recv_stream(const unsigned int channel, void *buf, int size, int waittime); +int rda_mdcom_channel_buf_recv_dgram(const unsigned int channel, void *buf, int size, int waittime); +int rda_mdcom_channel_buf_send_available(const unsigned int channel); +int rda_mdcom_channel_buf_recv_available(const unsigned int channel); +void rda_mdcom_channel_show(const unsigned int channel); + +/* + * AT COMMAND Channel + */ +/* emulate a tty device */ +int rda_mdcom_tstc(const unsigned int channel); +int rda_mdcom_getc(const unsigned int channel); +void rda_mdcom_putc(const char c, const unsigned int channel); +void rda_mdcom_puts(const char *s, const unsigned int channel); + +/* + * SYSTEM MESSAGE Channel + */ +int rda_mdcom_send_sys_msg( + struct rda_mdcom_channel *channel, + int msg_id, + void *send_msg, int send_size, + void *response, int resp_buf_size, + int *resp_size +); + +int rda_mdcom_parse_sys_msg( + struct rda_mdcom_channel *channel, + int msg_id, + void *send_msg, int send_size, + void *response, int *resp_size +); + +#endif // _MDCOM_H_ diff --git a/arch/arm/include/asm/arch-rda/mtdparts_def.h b/arch/arm/include/asm/arch-rda/mtdparts_def.h new file mode 100644 index 0000000000..57652abdb6 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/mtdparts_def.h @@ -0,0 +1,58 @@ +#ifndef __ASM_ARCH_MTDPARTS_DEF_H +#define __ASM_ARCH_MTDPARTS_DEF_H + +#include <rda/tgt_ap_flash_parts.h> + + +#define SEPARATOR "#" + +#define SYSTEM_PKT_LEN "4096" + +#define DEFAULT_FSIMG_PKT_LEN "4096" + +#define USERDATA_IMAGE_ATTR \ + "userdata(" \ + DEFAULT_FSIMG_PKT_LEN \ + ")" + +#define CUSTOMER_IMAGE_ATTR \ + "customer(" \ + DEFAULT_FSIMG_PKT_LEN \ + ")" + +#define VENDOR_IMAGE_ATTR \ + "vendor(" \ + DEFAULT_FSIMG_PKT_LEN \ + ")" + +#define SYSTEM_IMAGE_ATTR \ + "system(" \ + SYSTEM_PKT_LEN \ + ")" + +#define CACHE_IMAGE_ATTR \ + "cache(" \ + DEFAULT_FSIMG_PKT_LEN \ + ")" + +#define IMAGE_ATTR \ + "pdl(8)" \ + SEPARATOR \ + "bootloader(4096)" \ + SEPARATOR \ + "modem(4096)" \ + SEPARATOR \ + "boot(4096)" \ + SEPARATOR \ + SYSTEM_IMAGE_ATTR \ + SEPARATOR \ + CUSTOMER_IMAGE_ATTR \ + SEPARATOR \ + VENDOR_IMAGE_ATTR \ + SEPARATOR \ + USERDATA_IMAGE_ATTR \ + SEPARATOR \ + CACHE_IMAGE_ATTR \ + SEPARATOR \ + "recovery(4096)" +#endif /* __ASM_ARCH_MTDPARTS_DEF_H */ diff --git a/arch/arm/include/asm/arch-rda/prdinfo.h b/arch/arm/include/asm/arch-rda/prdinfo.h new file mode 100644 index 0000000000..13ee77a5c6 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/prdinfo.h @@ -0,0 +1,62 @@ +#ifndef __PRDINFO_H__ +#define __PRDINFO_H__ + +#define PRDINFO_PART_NAME "misc" +#define PRDINFO_TOTAL_SIZE (16*1024) + +/* 0 ~ 1024, produce infomation, + includes pdl/calibration/test results */ +#define PRDINFO_DATA_OFFSET 0 +#define PRDINFO_DATA_MAX_SIZE 1024 +#define PDL_IMAGE_MAX_NUM 16 +#define PDL_IMAGE_NAME_LEN 31 +#define FACTORY_TAG_NUM 0xFAC12345 +struct prdinfo +{ + uint8_t pdl_result; + uint8_t cali_result; + uint8_t autocall_result; + uint8_t factorytest_result; + + uint32_t pdl_image_count; + struct { + char name[PDL_IMAGE_NAME_LEN]; + uint8_t result; + } pdl_images[PDL_IMAGE_MAX_NUM]; + + uint32_t factory_tag; /* force to factory mode */ + + uint8_t imei_result; + uint8_t psn_result; + uint8_t mbsn_result; + uint8_t macaddr_result; + uint8_t btaddr_result; + + uint8_t reserve[27]; +}; + +/* 1024 ~ (PRDINFO_TOTAL_SIZE - 4), reserved */ + +/* (PRDINFO_TOTAL_SIZE - 4) ~ PRDINFO_TOTAL_SIZE, + crc for all (PRDINFO_TOTAL_SIZE-4) data */ +#define PRDINFO_CRC_OFFSET (PRDINFO_TOTAL_SIZE-4) +#define PRDINFO_CRC_SIZE 4 + + +/* related functions int u-boot */ +int prdinfo_init(char *image_list); +int prdinfo_load(void); +int prdinfo_save(void); +int prdinfo_update_all(char *buf, unsigned long sz); +void prdinfo_dump(void); +int prdinfo_set_data(struct prdinfo *info); +int prdinfo_get_data(struct prdinfo *info); +int prdinfo_set_pdl_result(uint8_t rt, uint32_t ftm_tag); +int prdinfo_set_cali_result(uint8_t rt); +int prdinfo_set_autocall_result(uint8_t rt); +int prdinfo_set_coupling_result(uint8_t rt); +int prdinfo_set_factorytest_result(uint8_t rt); +int prdinfo_set_pdl_image_download_result(char *image_name, uint8_t dl_rt); +uint32_t prdinfo_get_factory_tag(void); + +#endif diff --git a/arch/arm/include/asm/arch-rda/rda_crypto.h b/arch/arm/include/asm/arch-rda/rda_crypto.h new file mode 100644 index 0000000000..db957d2fdd --- /dev/null +++ b/arch/arm/include/asm/arch-rda/rda_crypto.h @@ -0,0 +1,11 @@ +#ifndef __RDA_CRYPTO_H__ + +#include <image.h> +#include <asm/arch/spl_board_info.h> + +int set_security_context(struct spl_security_info *info, const void *image); + +int image_sign_verify_uimage(image_header_t *hdr); +int image_sign_verify(const uint8_t *buffer, uint32_t len); + +#endif diff --git a/arch/arm/include/asm/arch-rda/rda_iomap.h b/arch/arm/include/asm/arch-rda/rda_iomap.h new file mode 100644 index 0000000000..0b71f96d50 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/rda_iomap.h @@ -0,0 +1,25 @@ +#ifndef __IOMAP_H +#define __IOMAP_H + +#include <common.h> + +#ifdef CONFIG_MACH_RDAARM926EJS +#include "iomap_rdaarm926ejs.h" +#elif defined(CONFIG_MACH_RDA8810) +#include "iomap_rda8810.h" +#elif defined(CONFIG_MACH_RDA8810E) +#include "iomap_rda8810e.h" +#elif defined(CONFIG_MACH_RDA8820) +#include "iomap_rda8820.h" +#elif defined(CONFIG_MACH_RDA8850) +#include "iomap_rda8850.h" +#elif defined(CONFIG_MACH_RDA8850E) +#include "iomap_rda8850e.h" +#elif defined(CONFIG_MACH_RDA8810H) +#include "iomap_rda8810h.h" +#else +#error "No MACH defined" +#endif + +#endif // __IOMAP_H + diff --git a/arch/arm/include/asm/arch-rda/rda_sys.h b/arch/arm/include/asm/arch-rda/rda_sys.h new file mode 100644 index 0000000000..8c81a0e473 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/rda_sys.h @@ -0,0 +1,67 @@ +#ifndef __RDA_SYS_H__ +#define __RDA_SYS_H__ + +/*RDA_BOOTMODE_TYPE*/ +#define RDA_MODE_EMMC 0 +#define RDA_MODE_SPINAND 1 +#define RDA_MODE_SPINOR 2 +#define RDA_MODE_TCARD_RUN 3 +#define RDA_MODE_TCARD_UPDATE 4 +#define RDA_MODE_NAND_8BIT 5 +#define RDA_MODE_NAND_16BIT 6 +#define RDA_MODE_RESERVED 7 + +#define RDA_HW_CFG_GET_BM_IDX(r) (((r)>>0)&0x7) + +enum media_type { + MEDIA_NAND = 0x10, + MEDIA_MMC = 0x11, + MEDIA_SPINAND = 0x12, + MEDIA_UNKNOWN = 0xff, +}; +enum media_type rda_media_get(void); +u16 rda_metal_id_get(void); +void shutdown_system(void); + +int rda_bm_is_calib(void); +int rda_bm_is_autocall(void); +int rda_bm_is_download(void); +int rda_bm_download_key_pressed(void); + +enum reboot_type { + REBOOT_TO_NORMAL_MODE, + REBOOT_TO_DOWNLOAD_MODE, + REBOOT_TO_FASTBOOT_MODE, + REBOOT_TO_RECOVERY_MODE, + REBOOT_TO_CALIB_MODE, + REBOOT_TO_PDL2_MODE, +}; +void rda_reboot(enum reboot_type type); + +void enable_vibrator(int enable); +void enable_charger(int enable); + +void rda_dump_buf(char *data, size_t len); +void print_cur_time(void); + +#ifdef CONFIG_CMD_MISC +int usb_cable_connected(void); +int system_rebooted(void); +void save_current_boot_key_state(void); +int get_saved_boot_key_state(void); +enum rda_bm_type +{ + RDA_BM_NORMAL = 0, + RDA_BM_CALIB = 1, + RDA_BM_FACTORY = 2, + RDA_BM_FASTBOOT = 3, + RDA_BM_RECOVERY = 4, + RDA_BM_AUTOCALL = 5, + RDA_BM_FORCEDOWNLOAD = 6, +}; +void rda_bm_init(void); +enum rda_bm_type rda_bm_get(void); +void rda_bm_set(enum rda_bm_type bm); +#endif + +#endif diff --git a/arch/arm/include/asm/arch-rda/reg_camera.h b/arch/arm/include/asm/arch-rda/reg_camera.h new file mode 100644 index 0000000000..5b76edbacd --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_camera.h @@ -0,0 +1,4 @@ +#ifdef CONFIG_MACH_RDA8850E +#include "reg_camera_rda8850e.h" +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_camera_rda8850e.h b/arch/arm/include/asm/arch-rda/reg_camera_rda8850e.h new file mode 100644 index 0000000000..610428b058 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_camera_rda8850e.h @@ -0,0 +1,397 @@ +//============================================================================== +// +// Copyright (C) 2012-2021,RDA, Inc. +// All Rights Reserved +// +// This source code is the property of Coolsand Technologies and is +// confidential. Any modification, distribution, reproduction or +// exploitation of any content of this file is totally forbidden, +// except with the written permission of RDA. +// +//============================================================================== + + +#ifndef _CAMERA_H_ +#define _CAMERA_H_ + +#include "cs_types.h" + +#include "iomap_rda8850e.h" +// ============================================================================= +// MACROS +// ============================================================================= +#define FIFORAM_SIZE (128) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// CAMERA_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +#define REG_CAMERA_BASE RDA_CAMERA_BASE + +typedef volatile struct +{ + REG32 CTRL; //0x00000000 + REG32 STATUS; //0x00000004 + REG32 DATA; //0x00000008 + REG32 IRQ_MASK; //0x0000000C + REG32 IRQ_CLEAR; //0x00000010 + REG32 IRQ_CAUSE; //0x00000014 + REG32 CMD_SET; //0x00000018 + REG32 CMD_CLR; //0x0000001C + REG32 DSTWINCOL; //0x00000020 + REG32 DSTWINROW; //0x00000024 + REG32 CLK_OUT; //0x00000028 + REG32 SCALE_CFG; //0x0000002c + REG32 CAM_SPI_REG_0; //0x00000030 + REG32 CAM_SPI_REG_1; //0x00000034 + REG32 CAM_SPI_REG_2; //0x00000038 + REG32 CAM_SPI_REG_3; //0x0000003c + REG32 CAM_SPI_REG_4; //0x00000040 + REG32 CAM_SPI_REG_5; //0x00000044 + REG32 CAM_SPI_REG_6; //0x00000048 + REG32 CAM_SPI_OBSERVE_REG_0; //0x0000004c, read only + REG32 CAM_SPI_OBSERVE_REG_1; //0x00000050, read only + REG32 CSI_CONFIG_REG0; //0x00000054 + REG32 CSI_CONFIG_REG1; //0x00000058 + REG32 CSI_CONFIG_REG2; //0x0000005C + REG32 CSI_CONFIG_REG3; //0x00000060 + REG32 CSI_CONFIG_REG4; //0x00000064 + REG32 CSI_CONFIG_REG5; //0x00000068 + REG32 CSI_CONFIG_REG6; //0x0000006C + REG32 CSI_CONFIG_REG7; //0x00000070 + REG32 CSI_OBSERVE_REG4; //0x00000074 + REG32 CSI_OBSERVE_REG5; //0x00000078 + REG32 CSI_OBSERVE_REG6; //0x0000007C read only + REG32 CSI_OBSERVE_REG7; //0x00000080 read only + REG32 CSI_ENABLE_PHY; //0x00000084 + REG32 DCT_SHIFTR_Y_REG0; //0x00000088 + REG32 DCT_SHIFTR_Y_REG1; //0x0000008C + REG32 CAM_AXI_CONFIG; //0x00000090 + REG32 CAM_FRAME_START_ADDR; //0x00000094 + REG32 CAM_FRAME_SIZE; //0x00000098 + REG32 CAM_TC_COUNT; //0x0000009C + REG32 CAM_FRAME_START_U_ADDR; //0x000000A0 + REG32 CAM_FRAME_START_V_ADDR; //0x000000A4 + REG32 CAM_FRAME2_START_ADDR; //0x000000A8 + REG32 CAM_FRAME2_START_U_ADDR; //0x000000AC + REG32 CAM_FRAME2_START_V_ADDR; //0x000000B0 + REG32 CFG_CAM_C2CSE; //0x000000B4 +} HWP_CAMERA_T; + +#define hwp_camera ((HWP_CAMERA_T*) (REG_CAMERA_BASE)) + + +//CTRL +#define CAMERA_ENABLE (1<<0) +#define CAMERA_ENABLE_ENABLE (1<<0) +#define CAMERA_ENABLE_DISABLE (0<<0) +#define CAMERA_DCT_ENABLE (1<<1) +#define CAMERA_DCT_DISABLE (0<<1) +#define CAMERA_1_BUFENABLE (1<<2) +#define CAMERA_1_BUFENABLE_ENABLE (1<<2) +#define CAMERA_1_BUFENABLE_DISABLE (0<<2) +#define CAMERA_OUT_CLK_GATE_EN (1 << 3) +#define CAMERA_DATAFORMAT(n) (((n)&3)<<4) +#define CAMERA_DATAFORMAT_RGB565 (0<<4) +#define CAMERA_DATAFORMAT_YUV422 (1<<4) +#define CAMERA_DATAFORMAT_JPEG (2<<4) +#define CAMERA_DATAFORMAT_RESERVE (3<<4) +#define CAMERA_ISP_ENABLE (1 << 6) +#define CAMERA_RGB_RFIST (1 << 7) +#define CAMERA_RESET_POL (1<<8) +#define CAMERA_RESET_POL_INVERT (1<<8) +#define CAMERA_RESET_POL_NORMAL (0<<8) +#define CAMERA_PWDN_POL (1<<9) +#define CAMERA_PWDN_POL_INVERT (1<<9) +#define CAMERA_PWDN_POL_NORMAL (0<<9) +#define CAMERA_VSYNC_POL (1<<10) +#define CAMERA_VSYNC_POL_INVERT (1<<10) +#define CAMERA_VSYNC_POL_NORMAL (0<<10) +#define CAMERA_HREF_POL (1<<11) +#define CAMERA_HREF_POL_INVERT (1<<11) +#define CAMERA_HREF_POL_NORMAL (0<<11) +#define CAMERA_LINEBUF_ISP_ENABLE (1 << 12) +#define CAMERA_LINEBUF_IF (1 << 13) +#define CAMERA_VSYNC_DROP (1<<14) +#define CAMERA_VSYNC_DROP_DROP (1<<14) +#define CAMERA_VSYNC_DROP_NORMAL (0<<14) +#define CAMERA_DECIMFRM(n) (((n)&3)<<16) +#define CAMERA_DECIMFRM_ORIGINAL (0<<16) +#define CAMERA_DECIMFRM_DIV_2 (1<<16) +#define CAMERA_DECIMFRM_DIV_3 (2<<16) +#define CAMERA_DECIMFRM_DIV_4 (3<<16) +#define CAMERA_DECIMCOL(n) (((n)&3)<<18) +#define CAMERA_DECIMCOL_ORIGINAL (0<<18) +#define CAMERA_DECIMCOL_DIV_2 (1<<18) +#define CAMERA_DECIMCOL_DIV_3 (2<<18) +#define CAMERA_DECIMCOL_DIV_4 (3<<18) +#define CAMERA_DECIMROW(n) (((n)&3)<<20) +#define CAMERA_DECIMROW_ORIGINAL (0<<20) +#define CAMERA_DECIMROW_DIV_2 (1<<20) +#define CAMERA_DECIMROW_DIV_3 (2<<20) +#define CAMERA_DECIMROW_DIV_4 (3<<20) +#define CAMERA_REORDER(n) (((n)&7)<<24) +#define CAMERA_CROPEN (1<<28) +#define CAMERA_CROPEN_ENABLE (1<<28) +#define CAMERA_CROPEN_DISABLE (0<<28) +#define CAMERA_BIST_MODE (1<<30) +#define CAMERA_BIST_MODE_BIST (1<<30) +#define CAMERA_BIST_MODE_NORMAL (0<<30) +#define CAMERA_TEST (1<<31) +#define CAMERA_TEST_TEST (1<<31) +#define CAMERA_TEST_NORMAL (0<<31) + +//STATUS +#define CAMERA_OVFL (1<<0) +#define CAMERA_VSYNC_R (1<<1) +#define CAMERA_VSYNC_F (1<<2) +#define CAMERA_DMA_DONE (1<<3) +#define CAMERA_FIFO_EMPTY (1<<4) + +//DATA +#define CAMERA_RX_DATA(n) (((n)&0xFFFFFFFF)<<0) + +//IRQ_MASK +//#define CAMERA_OVFL (1<<0) +//#define CAMERA_VSYNC_R (1<<1) +//#define CAMERA_VSYNC_F (1<<2) +//#define CAMERA_DMA_DONE (1<<3) + +//IRQ_CLEAR +//#define CAMERA_OVFL (1<<0) +//#define CAMERA_VSYNC_R (1<<1) +//#define CAMERA_VSYNC_F (1<<2) +//#define CAMERA_DMA_DONE (1<<3) + +//IRQ_CAUSE +//#define CAMERA_OVFL (1<<0) +//#define CAMERA_VSYNC_R (1<<1) +//#define CAMERA_VSYNC_F (1<<2) +//#define CAMERA_DMA_DONE (1<<3) + +//CMD_SET,modified by xiankuiwei +#define CAMERA_RESET (1<<0) +#define CAMERA_PWDN (1<<4) +#define CAMERA_FIFO_RESET (1<<8) + +//CMD_CLR +//#define CAMERA_PWDN (1<<4) +//#define CAMERA_RESET (1<<0) + +//DSTWINCOL,modified by xiankuiwei +#define CAMERA_DSTWINCOLSTART(n) (((n)&0xFFF)<<16) +#define CAMERA_DSTWINCOLEND(n) (((n)&0xFFF)<<0) + +//DSTWINROW +#define CAMERA_DSTWINROWSTART(n) (((n)&0xFFF)<<16) +#define CAMERA_DSTWINROWEND(n) (((n)&0xFFF)<<0) + +// SCALE CONFIG, no use now +#define CAM_SCALE_EN (1<<0) +#define CAM_SCALE_COL(n) (((n)&0x3)<<8) +#define CAM_SCALE_ROW(n) (((n)&0x3)<<16) + +/*************************************************************/ +/***************** SPI CAMERA CONFIGURATION ********************/ +/*************************************************************/ + +// Here, spi master mode means the sensor works as the SPI master. +// master mode 1 means 1 data ouput with SSN, master mode 2 means the other master modes. + +//-------------------------------- +// camera_spi_reg_0 +//-------------------------------- +// the number of lines per frame +#define CAM_SPI_REG_LINE_PER_FRM(n) (((n)&0x3ff)<<22) +// the number of words(32 bits) per line +#define CAM_SPI_REG_BLK_PER_LINE(n) (((n)&0x3ff)<<12) +// VSYNC high effective +#define CAM_SPI_REG_VSYNC_INV_EN (1<<11) +// HREF low effective +#define CAM_SPI_REG_HREF_INV_EN (1<<10) +// OVFL low effective +#define CAM_SPI_REG_OVFL_INV_EN (1<<9) +// little endian enable +#define CAM_SPI_REG_LITTLE_END_EN (1<<8) +// module reset when ovfl enable +#define CAM_SPI_REG_OVFL_RST_EN (1<<7) +// observe the overflow when vsync effective +#define CAM_SPI_REG_OVFL_OBS (1<<6) +// reset the module when overflow in vsync effective +#define CAM_SPI_REG_OVFL_RST (1<<5) +/************************************************ +YUV data output format + 3'b000: Y0-U0-Y1-V0 3'b001: Y0-V0-Y1-U0 + 3'b010: U0-Y0-V0-Y1 3'b011: U0-Y1-V0-Y0 + 3'b100: V0-Y1-U0-Y0 3'b101: V0-Y0-U0-Y1 + 3'b110: Y1-V0-Y0-U0 3'b111: Y1-U0-Y0-V0 +*************************************************/ +#define CAM_SPI_REG_YUV_OUT_FMT(n) (((n)&0x7)<<2) +// SPI master mode 1 enable +#define CAM_SPI_REG_MASTER_EN (1<<1) +// SPI slave mode enable +#define CAM_SPI_REG_SLAVE_EN (1<<0) + +//-------------------------------- +// camera_spi_reg_1 +//-------------------------------- +#define CAM_SPI_REG_CLK_DIV(n) ((n)&0xffff) // camera clock divider +#define CAM_SPI_REG_SSN_HIGH_EN (1<<17) // SSN high enable, only for master mode 1 + +//-------------------------------- +// camera_spi_reg_2 +//-------------------------------- +// only take effect in slave mode which is not supported yet + +//-------------------------------- +// camera_spi_reg_3 +//-------------------------------- +// only take effect in slave mode which is not supported yet + +//-------------------------------- +// camera_spi_reg_4 +//-------------------------------- +#define CAM_SPI_REG_BLK_PER_PACK(n) (((n)&0x3ff)<<6) +#define CAM_SPI_REG_IMG_WIDTH_FROM_REG (1<<5) +#define CAM_SPI_REG_IMG_HEIGHT_FROM_REG (1<<4) +#define CAM_SPI_REG_PACK_SIZE_FROM_REG (1<<3) +#define CAM_SPI_REG_LINE(n) (((n)&0x3)<<1) +#define CAM_SPI_REG_MASTER2_EN (1<<0) + +//-------------------------------- +// camera_spi_reg_5 +//-------------------------------- +#define CAM_SPI_REG_SYNC_CODE(n) ((n)&0xffffff) + +//-------------------------------- +// camera_spi_reg_6 +//-------------------------------- +// frame_start packet id, only in master mode 2 +#define CAM_SPI_REG_FRM_START_PKT_ID(n) (((n)&0xff)<<24) +// frame_end packet id, only in master mode 2 +#define CAM_SPI_REG_FRM_ENDN_PKT_ID(n) (((n)&0xff)<<16) +// line_start packet id, only in master mode 2 +#define CAM_SPI_REG_LINE_START_PKT_ID(n) (((n)&0xff)<<8) +// data packet id, only in master mode 2 +#define CAM_SPI_REG_DATA_PKT_ID(n) ((n)&0xff) + +//-------------------------------- +// camera_spi_observe_reg_0 (read only) +//-------------------------------- + +//-------------------------------- +// camera_spi_observe_reg_1 (read only) +//-------------------------------- + +//-------------------------------- +// csi_config_reg0 +//-------------------------------- +#define CSI_NUM_D_TERM_EN(n) (((n)&0XFF)<<0) +#define CSI_CUR_FRAME_LINE_NUM(n) (((n)&0X3FF)<<8) +#define CSI_VC_ID_SET(n) (((n)&3)<<18) +#define CSI_DATA_LP_IN_CHOOSE(n) (((n)&3)<<20) +#define CSI_DATA_LP_INV (1<<22) +#define CSI_CLK_LP_INV (1<<23) +#define CSI_TRAIL_DATA_WRONG_CHOOSE (1<<24) +#define CSI_SYNC_BYPASS (1<<25) +#define CSI_RDATA_BIT_INV_EN (1<<26) +#define CSI_HS_SYNC_FIND_EN (1<<27) +#define CSI_LINE_PACKET_ENABLE (1<<28) +#define CSI_ECC_BYPASS (1<<29) +#define CSI_DATA_LANE_CHOOSE (1<<30) +#define CSI_MODULE_ENABLE (1<<31) + +//-------------------------------- +// csi_config_reg01 +//-------------------------------- +#define CSI_NUM_HS_SETTLE(n) (((n)&0XFF)<<0) +#define CSI_LP_DATA_LENGTH_CHOSSE(n) (((n)&7)<<8) +#define CSI_DATA_CLK_LP_POSEEDGE_CHOSSE(n) (((n)&7)<<11) +#define CSI_CLK_LP_CK_INV (1<<14) +#define CSI_RCLR_MASK_EN (1<<15) +#define CSI_RINC_MASK_EN (1<<16) +#define CSI_HS_ENALBE_MASK_EN (1<<17) +#define CSI_DEN_INV_BIT (1<<18) +#define CSI_HSYNC_INV_BIT (1<<19) +#define CSI_VSYNC_INV_BIT (1<<20) +#define CSI_HS_DATA2_ENABLE_REG (1<<21) + +#define CSI_HS_TATA1_ENALBE_REG (1<<22) +#define CSI_HS_DATA1_ENABLE_CHOSSE (1<<23) +#define CSI_HS_DATA1_ENALBE_DRE (1<<24) +#define CSI_DATA2_TER_ENABLE_REG (1<<25) +#define CSI_DATAL_TER_ENABLE_REG (1<<26) +#define CSI_DATAL_TER_ENABLE_DR (1<<27) +#define CSI_LP_DATA_INTERRUPT_CLR (1<<28) +#define CSI_LP_CMD_INTERRUPT_CLR (1<<29) +#define CSI_LP_DATA_CLR (1<<30) +#define CSI_LP_CMD_CLR (1<<31) + +//-------------------------------- +// csi_config_reg02 +//-------------------------------- +#define CSI_NUM_C_TERM_EN(n) (((n)&0XFFFF)<<16) +#define CSI_NUM_HS_SETTLE_CLK(n) (((n)&0XFFFF)<<0) + +//-------------------------------- +// csi_config_reg03 +//-------------------------------- +#define CSI_DLY_SEL_REG(n) (((n)&3)<<0) +#define CSI_DLY_SEL_DATA2_REG(n) (((n)&3)<<2) +#define CSI_DLY_SEL_DATA1_REG(n) (((n)&3)<<4) +#define CSI_CLK_LP_IN_CHOOSE_BIT(n) (((n)&3)<<6) +#define CSI_PU_LPRX_REG (1<<8) +#define CSI_PU_HSRX_REG (1<<9) +#define CSI_PU_DR (1<<10) +#define CSI_AVDD1V8_2V8_SEL_REG (1<<11) +#define CSI_HS_CLK_ENABLE_REG (1<<12) +#define CSI_HS_CLK_ENABLE_CHOOSE_BIT (1<<13) +#define CSI_HS_CLK_ENALBE_DR (1<<14) +#define CSI_CLK_TERMINAL_ENABLE_REG (1<<15) +#define CSI_CLK_TERMINAL_ENABLE_DR (1<<16) +#define CSI_OBSERVE_REG_5_LOW8_CHOOSE (1 << 17) +#define CSI_ECC_ERROR_FLAG_REG (1 << 18) +#define CSI_ECC_ERROR_DR (1 << 19) +#define CSI_CHANNEL_SEL (1 << 20) +#define CSI_TWO_LANE_BYTE_REVERSE (1 << 21) +#define CSI_DATA2_LANE_BIT_REVERSE (1 << 22) +#define CSI_DATA1_LANE_BIT_REVERSE (1 << 23) +#define CSI_DATA2_HAS_NO_MASK (1 << 24) +#define CSI_DATA1_HAS_NO_MASK (1 << 25) +#define CSI_PU_LRX_D2_REG (1 << 26) +#define CSI_PU_LRX_D1_REG (1 << 27) +#define CSI_PU_LRX_CLK_REG (1 << 28) +#define CSI_CLK_EDGE_SEL (1 << 29) +#define CSI_CLK_X2_SEL (1 << 30) +#define CSI_SINGLE_DATALANE_EN (1 << 31) + +//-------------------------------- +// csi_config_reg04,modified in 8850e by xiankuiwei +//-------------------------------- +#define CSI_NUM_HS_CLK_USEFUL(n) (((n)&0X7FFFFFFF)<<0) +#define CSI_NUM_HS_CLK_USEFUL_EN (1<<31) + +//-------------------------------- +// csi_config_reg05 +//-------------------------------- +#define CSI_LP_CMD_OUT(n) (((n)&0XFF)<<0) +#define CSI_PHY_CLK_STATE(n) (((n)&0X1FF)<<10) +#define CSI_HS_DATA_ERROR_FLAG (1<<28) +#define CSI_ERR_ECC_CORRECTED_FLAG (1<<29) +#define CSI_ERR_DATA_CORRECTED_FLAG (1<<30) +#define CSI_ERR_DATA_ZERO_FLAG (1<<31) + +//-------------------------------- +// csi_observe_reg6 (read only) +//-------------------------------- + +//-------------------------------- +// csi_observe_reg6 (read only) +//-------------------------------- +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs.h new file mode 100644 index 0000000000..613c9cd659 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs.h @@ -0,0 +1,16 @@ +#ifdef CONFIG_MACH_RDA8810 +#include "reg_cfg_regs_rda8810.h" +#elif defined(CONFIG_MACH_RDA8810E) +#include "reg_cfg_regs_rda8810e.h" +#elif defined(CONFIG_MACH_RDA8820) +#include "reg_cfg_regs_rda8820.h" +#elif defined(CONFIG_MACH_RDA8850) +#include "reg_cfg_regs_rda8850.h" +#elif defined(CONFIG_MACH_RDA8850E) +#include "reg_cfg_regs_rda8850e.h" +#elif defined(CONFIG_MACH_RDA8810H) +#include "reg_cfg_regs_rda8810h.h" +#else +#error "unknown MACH" +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810.h new file mode 100644 index 0000000000..50f80fcf38 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810.h @@ -0,0 +1,1056 @@ +#ifndef _REG_IFC_H_ +#define _REG_IFC_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= +#define PROD_ID (0X8810) + +// ============================================================================ +// BB_GPIO_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// BB GPIO Map + BB_PIN_NONE_0 = 0x00000000, + BB_PIN_1 = 0x00000001, + BB_PIN_2 = 0x00000002, + BB_PIN_3 = 0x00000003, + BB_PIN_4 = 0x00000004, + BB_PIN_5 = 0x00000005, + BB_PIN_UART1_RXD = 0x00000006, + BB_PIN_UART2_RXD = 0x00000007, + BB_PIN_UART2_TXD = 0x00000008, + BB_PIN_SSD1_CLK = 0x00000009, + BB_PIN_SSD1_CMD = 0x0000000A, + BB_PIN_SDAT1_0 = 0x0000000B, + BB_PIN_SDAT1_1 = 0x0000000C, + BB_PIN_SDAT1_2 = 0x0000000D, + BB_PIN_SDAT1_3 = 0x0000000E, + BB_PIN_SSD2_CLK = 0x0000000F, + BB_PIN_SSD2_CMD = 0x00000010, + BB_PIN_SDAT2_0 = 0x00000011, + BB_PIN_SDAT2_1 = 0x00000012, + BB_PIN_SDAT2_2 = 0x00000013, + BB_PIN_SDAT2_3 = 0x00000014, + BB_PIN_SPI1_CLK = 0x00000015, + BB_PIN_SPI1_CS_0 = 0x00000016, + BB_PIN_SPI1_DIO = 0x00000017, + BB_PIN_SPI1_DI = 0x00000018, + BB_PIN_SIM2_RST = 0x00000019, + BB_PIN_SIM2_CLK = 0x0000001A, + BB_PIN_SIM2_DIO = 0x0000001B, + BB_PIN_SIM3_RST = 0x0000001C, + BB_PIN_SIM3_CLK = 0x0000001D, + BB_PIN_SIM3_DIO = 0x0000001E +} BB_GPIO_MAPPING_T; + +#define BB_GPIO_NB (31) + +// ============================================================================ +// AP_GPIO_A_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO A Map + AP_PIN_I2C2_SCL = 0x00000000, + AP_PIN_I2C2_SDA = 0x00000001, + AP_PIN_SPI2_CLK = 0x00000002, + AP_PIN_SPI2_DIO = 0x00000003, + AP_PIN_SPI2_DI = 0x00000004, + AP_PIN_SPI2_CS_0 = 0x00000005, + AP_PIN_SPI2_CS_1 = 0x00000006, + AP_PIN_KEYIN_4 = 0x00000007, + AP_PIN_CLK_OUT = 0x00000008, + AP_PIN_I2S_BCK = 0x00000009, + AP_PIN_I2S_LRCK = 0x0000000A, + AP_PIN_I2S_DI_0 = 0x0000000B, + AP_PIN_I2S_DI_1 = 0x0000000C, + AP_PIN_I2S_DO = 0x0000000D, + AP_PIN_UART1_TXD = 0x0000000E, + AP_PIN_UART1_CTS = 0x0000000F, + AP_PIN_UART1_RTS = 0x00000010, + AP_PIN_SPI1_CS_1 = 0x00000011, + AP_PIN_LCD_DATA_6 = 0x00000012, + AP_PIN_LCD_DATA_7 = 0x00000013, + AP_PIN_LCD_WR = 0x00000014, + AP_PIN_LCD_RS = 0x00000015, + AP_PIN_LCD_RD = 0x00000016, + AP_PIN_LCD_FMARK = 0x00000017, + AP_PIN_LCD_DATA_8 = 0x00000018, + AP_PIN_LCD_DATA_9 = 0x00000019, + AP_PIN_LCD_DATA_10 = 0x0000001A, + AP_PIN_LCD_DATA_11 = 0x0000001B, + AP_PIN_LCD_DATA_12 = 0x0000001C, + AP_PIN_LCD_DATA_13 = 0x0000001D, + AP_PIN_LCD_DATA_14 = 0x0000001E, + AP_PIN_LCD_DATA_15 = 0x0000001F +} AP_GPIO_A_MAPPING_T; + +#define AP_GPIO_A_NB (32) + +// ============================================================================ +// AP_GPIO_B_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO B Map + AP_PIN_KEYIN_0 = 0x00000000, + AP_PIN_KEYIN_1 = 0x00000001, + AP_PIN_KEYIN_2 = 0x00000002, + AP_PIN_KEYOUT_0 = 0x00000003, + AP_PIN_KEYOUT_1 = 0x00000004, + AP_PIN_KEYOUT_2 = 0x00000005, + AP_PIN_I2C3_SCL = 0x00000006, + AP_PIN_I2C3_SDA = 0x00000007, + AP_PIN_UART2_CTS = 0x00000008, + AP_PIN_UART2_RTS = 0x00000009, + AP_PIN_CAM_RST = 0x0000000A, + AP_PIN_CAM_PDN = 0x0000000B, + AP_PIN_CAM_CLK = 0x0000000C, + AP_PIN_CAM_VSYNC = 0x0000000D, + AP_PIN_CAM_HREF = 0x0000000E, + AP_PIN_CAM_PCLK = 0x0000000F, + AP_PIN_CAM_DATA_0 = 0x00000010, + AP_PIN_CAM_DATA_1 = 0x00000011, + AP_PIN_CAM_DATA_2 = 0x00000012, + AP_PIN_CAM_DATA_3 = 0x00000013, + AP_PIN_CAM_DATA_4 = 0x00000014, + AP_PIN_CAM_DATA_5 = 0x00000015, + AP_PIN_CAM_DATA_6 = 0x00000016, + AP_PIN_CAM_DATA_7 = 0x00000017, + AP_PIN_M_SPI_CS_0 = 0x00000018, + AP_PIN_NFCLE = 0x00000019, + AP_PIN_NFWEN = 0x0000001A, + AP_PIN_NFWPN = 0x0000001B, + AP_PIN_NFREN = 0x0000001C, + AP_PIN_NFRB = 0x0000001D, + AP_PIN_I2C1_SCL = 0x0000001E, + AP_PIN_I2C1_SDA = 0x0000001F +} AP_GPIO_B_MAPPING_T; + +#define AP_GPIO_B_NB (32) + +// ============================================================================ +// AP_GPIO_D_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO D Map + AP_PIN_UART3_RXD = 0x00000000, + AP_PIN_UART3_TXD = 0x00000001, + AP_PIN_UART3_CTS = 0x00000002, + AP_PIN_UART3_RTS = 0x00000003, + AP_PIN_NFDQS = 0x00000004 +} AP_GPIO_D_MAPPING_T; + +#define AP_GPIO_D_NB (5) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// CFG_REGS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +#define REG_CONFIG_REGS_BASE 0x01A09000 + +typedef volatile struct +{ + REG32 CHIP_ID; //0x00000000 + /// This register contain the synthesis date and version + REG32 Build_Version; //0x00000004 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 BB_GPIO_Mode; //0x00000008 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_A_Mode; //0x0000000C + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_B_Mode; //0x00000010 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_D_Mode; //0x00000014 + REG32 Alt_mux_select; //0x00000018 + REG32 IO_Drive1_Select; //0x0000001C + REG32 IO_Drive2_Select; //0x00000020 + REG32 RAM_DRIVE; //0x00000024 + REG32 H2X_AP_Offset; //0x00000028 + REG32 H2X_DDR_Offset; //0x0000002C + REG32 audio_pd_set; //0x00000030 + REG32 audio_pd_clr; //0x00000034 + REG32 audio_sel_cfg; //0x00000038 + REG32 audio_mic_cfg; //0x0000003C + REG32 audio_spk_cfg; //0x00000040 + REG32 audio_rcv_gain; //0x00000044 + REG32 audio_head_gain; //0x00000048 + REG32 TSC_DATA; //0x0000004C + REG32 GPADC_DATA_CH[8]; //0x00000050 +} HWP_CFG_REGS_T; + +#define hwp_configRegs ((HWP_CFG_REGS_T*)(RDA_CFG_REGS_BASE)) + + +//CHIP_ID +#define CFG_REGS_METAL_ID(n) (((n)&0xFFF)<<0) +#define CFG_REGS_METAL_ID_MASK (0xFFF<<0) +#define CFG_REGS_METAL_ID_SHIFT (0) +#define CFG_REGS_BOND_ID(n) (((n)&7)<<12) +#define CFG_REGS_BOND_ID_MASK (7<<12) +#define CFG_REGS_BOND_ID_SHIFT (12) +#define CFG_REGS_PROD_ID(n) (((n)&0xFFFF)<<16) +#define CFG_REGS_PROD_ID_MASK (0xFFFF<<16) +#define CFG_REGS_PROD_ID_SHIFT (16) + +//Build_Version +#define CFG_REGS_MAJOR(n) (((n)&15)<<28) +#define CFG_REGS_YEAR(n) (((n)&15)<<24) +#define CFG_REGS_MONTH(n) (((n)&0xFF)<<16) +#define CFG_REGS_DAY(n) (((n)&0xFF)<<8) +#define CFG_REGS_BUILD_STYLE_FPGA (0<<4) +#define CFG_REGS_BUILD_STYLE_CHIP (1<<4) +#define CFG_REGS_BUILD_STYLE_FPGA_USB (2<<4) +#define CFG_REGS_BUILD_STYLE_FPGA_GSM (3<<4) +#define CFG_REGS_BUILD_REVISION(n) (((n)&15)<<0) + +//BB_GPIO_Mode +#define CFG_REGS_MODE_BB_PIN_NONE_0 (1<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_MASK (1<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_SHIFT (0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_ALT (0<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_GPIO (1<<0) +#define CFG_REGS_MODE_BB_PIN_1 (1<<1) +#define CFG_REGS_MODE_BB_PIN_1_MASK (1<<1) +#define CFG_REGS_MODE_BB_PIN_1_SHIFT (1) +#define CFG_REGS_MODE_BB_PIN_1_ALT (0<<1) +#define CFG_REGS_MODE_BB_PIN_1_GPIO (1<<1) +#define CFG_REGS_MODE_BB_PIN_2 (1<<2) +#define CFG_REGS_MODE_BB_PIN_2_MASK (1<<2) +#define CFG_REGS_MODE_BB_PIN_2_SHIFT (2) +#define CFG_REGS_MODE_BB_PIN_2_ALT (0<<2) +#define CFG_REGS_MODE_BB_PIN_2_GPIO (1<<2) +#define CFG_REGS_MODE_BB_PIN_3 (1<<3) +#define CFG_REGS_MODE_BB_PIN_3_MASK (1<<3) +#define CFG_REGS_MODE_BB_PIN_3_SHIFT (3) +#define CFG_REGS_MODE_BB_PIN_3_ALT (0<<3) +#define CFG_REGS_MODE_BB_PIN_3_GPIO (1<<3) +#define CFG_REGS_MODE_BB_PIN_4 (1<<4) +#define CFG_REGS_MODE_BB_PIN_4_MASK (1<<4) +#define CFG_REGS_MODE_BB_PIN_4_SHIFT (4) +#define CFG_REGS_MODE_BB_PIN_4_ALT (0<<4) +#define CFG_REGS_MODE_BB_PIN_4_GPIO (1<<4) +#define CFG_REGS_MODE_BB_PIN_5 (1<<5) +#define CFG_REGS_MODE_BB_PIN_5_MASK (1<<5) +#define CFG_REGS_MODE_BB_PIN_5_SHIFT (5) +#define CFG_REGS_MODE_BB_PIN_5_ALT (0<<5) +#define CFG_REGS_MODE_BB_PIN_5_GPIO (1<<5) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_MASK (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_SHIFT (6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_ALT (0<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_GPIO (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_MASK (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_SHIFT (7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_ALT (0<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_GPIO (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD (1<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_MASK (1<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_SHIFT (8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_ALT (0<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_GPIO (1<<8) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_MASK (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_SHIFT (9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_ALT (0<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_GPIO (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD (1<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_MASK (1<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_SHIFT (10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_ALT (0<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_GPIO (1<<10) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0 (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_MASK (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_SHIFT (11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_ALT (0<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_GPIO (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1 (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_MASK (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_SHIFT (12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_ALT (0<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_GPIO (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2 (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_MASK (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_SHIFT (13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_ALT (0<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_GPIO (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3 (1<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_MASK (1<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_SHIFT (14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_ALT (0<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_GPIO (1<<14) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_MASK (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_SHIFT (15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_ALT (0<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_GPIO (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD (1<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_MASK (1<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_SHIFT (16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_ALT (0<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_GPIO (1<<16) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0 (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_MASK (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_SHIFT (17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_ALT (0<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_GPIO (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1 (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_MASK (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_SHIFT (18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_ALT (0<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_GPIO (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2 (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_MASK (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_SHIFT (19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_ALT (0<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_GPIO (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3 (1<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_MASK (1<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_SHIFT (20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_ALT (0<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_GPIO (1<<20) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_MASK (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_SHIFT (21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_ALT (0<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_GPIO (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0 (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_MASK (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_SHIFT (22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_ALT (0<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_GPIO (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_MASK (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_SHIFT (23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_ALT (0<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_GPIO (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI (1<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_MASK (1<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_SHIFT (24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_ALT (0<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_GPIO (1<<24) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_MASK (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_SHIFT (25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_ALT (0<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_GPIO (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_MASK (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_SHIFT (26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_ALT (0<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_GPIO (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_MASK (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_SHIFT (27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_ALT (0<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_GPIO (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_MASK (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_SHIFT (28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_ALT (0<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_GPIO (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_MASK (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_SHIFT (29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_ALT (0<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_GPIO (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO (1<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_MASK (1<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_SHIFT (30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_ALT (0<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_GPIO (1<<30) +#define CFG_REGS_BB_GPIO_MODE(n) (((n)&0x7FFFFFFF)<<0) +#define CFG_REGS_BB_GPIO_MODE_MASK (0x7FFFFFFF<<0) +#define CFG_REGS_BB_GPIO_MODE_SHIFT (0) + +//AP_GPIO_A_Mode +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0 (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1 (1<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4 (1<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT (1<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0 (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1 (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DO (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_GPIO (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS (1<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_MASK (1<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_SHIFT (16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_ALT (0<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_GPIO (1<<16) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1 (1<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_MASK (1<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_SHIFT (17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_ALT (0<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_GPIO (1<<17) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6 (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_MASK (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_SHIFT (18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_ALT (0<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_GPIO (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7 (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_MASK (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_SHIFT (19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_ALT (0<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_GPIO (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_WR (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_MASK (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_SHIFT (20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_ALT (0<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_GPIO (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_RS (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_MASK (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_SHIFT (21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_ALT (0<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_GPIO (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RD (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_MASK (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_SHIFT (22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_ALT (0<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_GPIO (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_MASK (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_SHIFT (23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_ALT (0<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_GPIO (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8 (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_MASK (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_SHIFT (24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_ALT (0<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_GPIO (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9 (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_MASK (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_SHIFT (25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_ALT (0<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_GPIO (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10 (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_MASK (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_SHIFT (26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_ALT (0<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_GPIO (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11 (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_MASK (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_SHIFT (27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_ALT (0<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_GPIO (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12 (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_MASK (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_SHIFT (28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_ALT (0<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_GPIO (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13 (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_MASK (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_SHIFT (29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_ALT (0<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_GPIO (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14 (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_MASK (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_SHIFT (30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_ALT (0<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_GPIO (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15 (1<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_MASK (1<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_SHIFT (31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_ALT (0<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_GPIO (1<<31) +#define CFG_REGS_AP_GPIO_A_MODE(n) (((n)&0xFFFFFFFF)<<0) +#define CFG_REGS_AP_GPIO_A_MODE_MASK (0xFFFFFFFF<<0) +#define CFG_REGS_AP_GPIO_A_MODE_SHIFT (0) + +//AP_GPIO_B_Mode +#define CFG_REGS_MODE_AP_PIN_KEYIN_0 (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1 (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2 (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0 (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1 (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2 (1<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA (1<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS (1<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM_RST (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_GPIO (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0 (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_MASK (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_SHIFT (16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_ALT (0<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_GPIO (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1 (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_MASK (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_SHIFT (17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_ALT (0<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_GPIO (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2 (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_MASK (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_SHIFT (18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_ALT (0<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_GPIO (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3 (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_MASK (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_SHIFT (19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_ALT (0<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_GPIO (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4 (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_MASK (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_SHIFT (20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_ALT (0<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_GPIO (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5 (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_MASK (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_SHIFT (21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_ALT (0<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_GPIO (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6 (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_MASK (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_SHIFT (22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_ALT (0<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_GPIO (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7 (1<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_MASK (1<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_SHIFT (23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_ALT (0<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_GPIO (1<<23) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0 (1<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_MASK (1<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_SHIFT (24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_ALT (0<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_GPIO (1<<24) +#define CFG_REGS_MODE_AP_PIN_NFCLE (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_MASK (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_SHIFT (25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_ALT (0<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_GPIO (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFWEN (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_MASK (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_SHIFT (26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_ALT (0<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_GPIO (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWPN (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_MASK (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_SHIFT (27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_ALT (0<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_GPIO (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFREN (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_MASK (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_SHIFT (28) +#define CFG_REGS_MODE_AP_PIN_NFREN_ALT (0<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_GPIO (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFRB (1<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_MASK (1<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_SHIFT (29) +#define CFG_REGS_MODE_AP_PIN_NFRB_ALT (0<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_GPIO (1<<29) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_MASK (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_SHIFT (30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_ALT (0<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_GPIO (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA (1<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_MASK (1<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_SHIFT (31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_ALT (0<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_GPIO (1<<31) +#define CFG_REGS_AP_GPIO_B_MODE(n) (((n)&0xFFFFFFFF)<<0) +#define CFG_REGS_AP_GPIO_B_MODE_MASK (0xFFFFFFFF<<0) +#define CFG_REGS_AP_GPIO_B_MODE_SHIFT (0) + +//AP_GPIO_D_Mode +#define CFG_REGS_MODE_AP_PIN_UART3_RXD (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS (1<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_NFDQS (1<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_GPIO (1<<4) +#define CFG_REGS_AP_GPIO_D_MODE(n) (((n)&31)<<0) +#define CFG_REGS_AP_GPIO_D_MODE_MASK (31<<0) +#define CFG_REGS_AP_GPIO_D_MODE_SHIFT (0) + +//Alt_mux_select +#define CFG_REGS_LCD_MODE_MASK (3<<0) +#define CFG_REGS_LCD_MODE_PARALLEL_16BIT (0<<0) +#define CFG_REGS_LCD_MODE_DSI (1<<0) +#define CFG_REGS_LCD_MODE_RGB_24BIT (2<<0) +#define CFG_REGS_LCD_MODE_RGB_16BIT (3<<0) +#define CFG_REGS_SPI_LCD_MASK (1<<2) +#define CFG_REGS_SPI_LCD_NONE (0<<2) +#define CFG_REGS_SPI_LCD_SPI_LCD (1<<2) +#define CFG_REGS_CAM_I2C2_MASK (1<<3) +#define CFG_REGS_CAM_I2C2_CAM (0<<3) +#define CFG_REGS_CAM_I2C2_I2C2 (1<<3) +#define CFG_REGS_CSI2_MASK (3<<4) +#define CFG_REGS_CSI2_PARALLEL_CAM (0<<4) +#define CFG_REGS_CSI2_CSI2 (1<<4) +#define CFG_REGS_CSI2_SPI_CAM (2<<4) +#define CFG_REGS_UART2_MASK (1<<6) +#define CFG_REGS_UART2_HOST_UART (0<<6) +#define CFG_REGS_UART2_UART2 (1<<6) +#define CFG_REGS_UART1_8LINE_MASK (1<<7) +#define CFG_REGS_UART1_8LINE_UART2 (0<<7) +#define CFG_REGS_UART1_8LINE_UART1_8_LINE (1<<7) +#define CFG_REGS_DAI_MASK (3<<8) +#define CFG_REGS_DAI_I2S (0<<8) +#define CFG_REGS_DAI_DAI (1<<8) +#define CFG_REGS_DAI_DAI_SIMPLE (2<<8) +#define CFG_REGS_KEYIN_3_MASK (1<<10) +#define CFG_REGS_KEYIN_3_SPI2_CS_1 (0<<10) +#define CFG_REGS_KEYIN_3_KEYIN_3 (1<<10) +#define CFG_REGS_LPSCO_1_MASK (1<<11) +#define CFG_REGS_LPSCO_1_KEYIN_4 (0<<11) +#define CFG_REGS_LPSCO_1_LPSCO_1 (1<<11) +#define CFG_REGS_SPI1_CS_2_MASK (1<<12) +#define CFG_REGS_SPI1_CS_2_KEYIN_1 (0<<12) +#define CFG_REGS_SPI1_CS_2_SPI1_CS_2 (1<<12) +#define CFG_REGS_I2S_DI_2_MASK (1<<13) +#define CFG_REGS_I2S_DI_2_KEYIN_2 (0<<13) +#define CFG_REGS_I2S_DI_2_I2S_DI_2 (1<<13) +#define CFG_REGS_TCO_0_MASK (1<<14) +#define CFG_REGS_TCO_0_KEYOUT_0 (0<<14) +#define CFG_REGS_TCO_0_TCO_0 (1<<14) +#define CFG_REGS_TCO_1_MASK (1<<15) +#define CFG_REGS_TCO_1_KEYOUT_1 (0<<15) +#define CFG_REGS_TCO_1_TCO_1 (1<<15) +#define CFG_REGS_TCO_2_MASK (1<<16) +#define CFG_REGS_TCO_2_KEYOUT_2 (0<<16) +#define CFG_REGS_TCO_2_TCO_2 (1<<16) +#define CFG_REGS_KEYOUT_3_4_MASK (1<<17) +#define CFG_REGS_KEYOUT_3_4_I2C3 (0<<17) +#define CFG_REGS_KEYOUT_3_4_KEYOUT_3_4 (1<<17) +#define CFG_REGS_KEYOUT_6_MASK (1<<18) +#define CFG_REGS_KEYOUT_6_UART2_RTS (0<<18) +#define CFG_REGS_KEYOUT_6_KEYOUT_6 (1<<18) +#define CFG_REGS_KEYOUT_7_MASK (1<<19) +#define CFG_REGS_KEYOUT_7_UART1_RTS (0<<19) +#define CFG_REGS_KEYOUT_7_KEYOUT_7 (1<<19) +#define CFG_REGS_GPO_0_MASK (3<<20) +#define CFG_REGS_GPO_0_GPO_0 (0<<20) +#define CFG_REGS_GPO_0_PWT (1<<20) +#define CFG_REGS_GPO_0_KEYIN_5 (2<<20) +#define CFG_REGS_GPO_1_MASK (3<<22) +#define CFG_REGS_GPO_1_GPO_1 (0<<22) +#define CFG_REGS_GPO_1_LPG (1<<22) +#define CFG_REGS_GPO_1_KEYOUT_5 (2<<22) +#define CFG_REGS_GPO_2_MASK (3<<24) +#define CFG_REGS_GPO_2_GPO_2 (0<<24) +#define CFG_REGS_GPO_2_PWL_1 (1<<24) +#define CFG_REGS_GPO_2_CLK_32K (2<<24) +#define CFG_REGS_GPO_3_MASK (1<<26) +#define CFG_REGS_GPO_3_LCD_CS_1 (0<<26) +#define CFG_REGS_GPO_3_GPO_3 (1<<26) +#define CFG_REGS_GPO_4_MASK (1<<27) +#define CFG_REGS_GPO_4_LCD_CS_0 (0<<27) +#define CFG_REGS_GPO_4_GPO_4 (1<<27) +#define CFG_REGS_CLK_OUT_MASK (1<<28) +#define CFG_REGS_CLK_OUT_HST_CLK (0<<28) +#define CFG_REGS_CLK_OUT_CLK_OUT (1<<28) +#define CFG_REGS_DEBUG_MASK (1<<29) +#define CFG_REGS_DEBUG_NONE (0<<29) +#define CFG_REGS_DEBUG_DEBUG_MONITOR (1<<29) +#define CFG_REGS_AP_SPI1_MASK (1<<30) +#define CFG_REGS_AP_SPI1_BB_SPI1 (0<<30) +#define CFG_REGS_AP_SPI1_AP_SPI1 (1<<30) +#define CFG_REGS_LCD24_CAM_MASK (1<<31) +#define CFG_REGS_LCD24_CAM_NAND_IO (0<<31) +#define CFG_REGS_LCD24_CAM_CAM_IO (1<<31) + +//IO_Drive1_Select +#define CFG_REGS_DDR_DRIVE_MASK (7<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_WEAK (7<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_WEAK (6<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_STRONG (5<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_STRONG (4<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_WEAK (3<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_WEAK (2<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_STRONG (1<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_STRONG (0<<0) +#define CFG_REGS_PSRAM1_DRIVE_MASK (7<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_WEAK (7<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_WEAK (6<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_STRONG (5<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_STRONG (4<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_WEAK (3<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_WEAK (2<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_STRONG (1<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_STRONG (0<<3) +#define CFG_REGS_PSRAM2_DRIVE_MASK (7<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_WEAK (7<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_WEAK (6<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_STRONG (5<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_STRONG (4<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_WEAK (3<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_WEAK (2<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_STRONG (1<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_STRONG (0<<6) +#define CFG_REGS_NFLSH_DRIVE_MASK (7<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_WEAK (7<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_WEAK (6<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_STRONG (5<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_STRONG (4<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_WEAK (3<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK (2<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_STRONG (1<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_STRONG (0<<9) +#define CFG_REGS_LCD1_DRIVE_MASK (7<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_WEAK (7<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_WEAK (6<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_STRONG (5<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_STRONG (4<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_WEAK (3<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_WEAK (2<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_STRONG (1<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_STRONG (0<<12) +#define CFG_REGS_LCD2_DRIVE_MASK (7<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_WEAK (7<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_WEAK (6<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_STRONG (5<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_STRONG (4<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_WEAK (3<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_WEAK (2<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_STRONG (1<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_STRONG (0<<15) +#define CFG_REGS_SDAT1_DRIVE_MASK (7<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_WEAK (7<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_WEAK (6<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_STRONG (5<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_STRONG (4<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_WEAK (3<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_WEAK (2<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_STRONG (1<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_STRONG (0<<18) +#define CFG_REGS_SDAT2_DRIVE_MASK (7<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_WEAK (7<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_WEAK (6<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_STRONG (5<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_STRONG (4<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_WEAK (3<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_WEAK (2<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_STRONG (1<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_STRONG (0<<21) +#define CFG_REGS_CAM_DRIVE_MASK (3<<24) +#define CFG_REGS_CAM_DRIVE_MOST_STRONG (0<<24) +#define CFG_REGS_CAM_DRIVE_STRONG (1<<24) +#define CFG_REGS_CAM_DRIVE_WEAK (2<<24) +#define CFG_REGS_CAM_DRIVE_MOST_WEAK (3<<24) +#define CFG_REGS_SIM1_DRIVE_MASK (3<<26) +#define CFG_REGS_SIM1_DRIVE_MOST_STRONG (0<<26) +#define CFG_REGS_SIM1_DRIVE_STRONG (1<<26) +#define CFG_REGS_SIM1_DRIVE_WEAK (2<<26) +#define CFG_REGS_SIM1_DRIVE_MOST_WEAK (3<<26) +#define CFG_REGS_SIM2_DRIVE_MASK (3<<28) +#define CFG_REGS_SIM2_DRIVE_MOST_STRONG (0<<28) +#define CFG_REGS_SIM2_DRIVE_STRONG (1<<28) +#define CFG_REGS_SIM2_DRIVE_WEAK (2<<28) +#define CFG_REGS_SIM2_DRIVE_MOST_WEAK (3<<28) +#define CFG_REGS_SIM3_DRIVE_MASK (3<<30) +#define CFG_REGS_SIM3_DRIVE_MOST_STRONG (0<<30) +#define CFG_REGS_SIM3_DRIVE_STRONG (1<<30) +#define CFG_REGS_SIM3_DRIVE_WEAK (2<<30) +#define CFG_REGS_SIM3_DRIVE_MOST_WEAK (3<<30) + +//IO_Drive2_Select +#define CFG_REGS_GPIO_DRIVE_MASK (3<<0) +#define CFG_REGS_GPIO_DRIVE_MOST_STRONG (0<<0) +#define CFG_REGS_GPIO_DRIVE_STRONG (1<<0) +#define CFG_REGS_GPIO_DRIVE_WEAK (2<<0) +#define CFG_REGS_GPIO_DRIVE_MOST_WEAK (3<<0) + +//RAM_DRIVE +#define CFG_REGS_MBRAM_A(n) (((n)&7)<<0) +#define CFG_REGS_MBRAM_A_MASK (7<<0) +#define CFG_REGS_MBRAM_A_SHIFT (0) +#define CFG_REGS_MBRAM_W(n) (((n)&3)<<3) +#define CFG_REGS_MBRAM_W_MASK (3<<3) +#define CFG_REGS_MBRAM_W_SHIFT (3) +#define CFG_REGS_MBRAM_R (1<<5) +#define CFG_REGS_BBRAM_A(n) (((n)&7)<<6) +#define CFG_REGS_BBRAM_A_MASK (7<<6) +#define CFG_REGS_BBRAM_A_SHIFT (6) +#define CFG_REGS_BBRAM_W(n) (((n)&3)<<9) +#define CFG_REGS_BBRAM_W_MASK (3<<9) +#define CFG_REGS_BBRAM_W_SHIFT (9) +#define CFG_REGS_BBRAM_R (1<<11) +#define CFG_REGS_XP_A(n) (((n)&7)<<12) +#define CFG_REGS_XP_A_MASK (7<<12) +#define CFG_REGS_XP_A_SHIFT (12) +#define CFG_REGS_XP_W(n) (((n)&3)<<15) +#define CFG_REGS_XP_W_MASK (3<<15) +#define CFG_REGS_XP_W_SHIFT (15) +#define CFG_REGS_XP_R (1<<17) +#define CFG_REGS_BP_A(n) (((n)&7)<<18) +#define CFG_REGS_BP_A_MASK (7<<18) +#define CFG_REGS_BP_A_SHIFT (18) +#define CFG_REGS_BP_W(n) (((n)&3)<<21) +#define CFG_REGS_BP_W_MASK (3<<21) +#define CFG_REGS_BP_W_SHIFT (21) +#define CFG_REGS_BP_R (1<<23) +#define CFG_REGS_EV_A(n) (((n)&7)<<24) +#define CFG_REGS_EV_A_MASK (7<<24) +#define CFG_REGS_EV_A_SHIFT (24) +#define CFG_REGS_EV_W(n) (((n)&3)<<27) +#define CFG_REGS_EV_W_MASK (3<<27) +#define CFG_REGS_EV_W_SHIFT (27) +#define CFG_REGS_EV_R (1<<29) + +//H2X_AP_Offset +#define CFG_REGS_H2X_AP_OFFSET(n) (((n)&0xFF)<<0) +#define CFG_REGS_H2X_AP_OFFSET_MASK (0xFF<<0) +#define CFG_REGS_H2X_AP_OFFSET_SHIFT (0) + +//H2X_DDR_Offset +#define CFG_REGS_H2X_DDR_OFFSET(n) (((n)&0xFF)<<0) +#define CFG_REGS_H2X_DDR_OFFSET_MASK (0xFF<<0) +#define CFG_REGS_H2X_DDR_OFFSET_SHIFT (0) + +//audio_pd_set +#define CFG_REGS_AU_DEEP_PD_N (1<<0) +#define CFG_REGS_AU_REF_PD_N (1<<1) +#define CFG_REGS_AU_MIC_PD_N (1<<2) +#define CFG_REGS_AU_AUXMIC_PD_N (1<<3) +#define CFG_REGS_AU_AD_PD_N (1<<4) +#define CFG_REGS_AU_DAC_PD_N (1<<5) +#define CFG_REGS_AU_DAC_RESET_N (1<<8) +#define CFG_REGS_AU_PLL_PU (1<<16) + +//audio_pd_clr +//#define CFG_REGS_AU_DEEP_PD_N (1<<0) +//#define CFG_REGS_AU_REF_PD_N (1<<1) +//#define CFG_REGS_AU_MIC_PD_N (1<<2) +//#define CFG_REGS_AU_AUXMIC_PD_N (1<<3) +//#define CFG_REGS_AU_AD_PD_N (1<<4) +//#define CFG_REGS_AU_DAC_PD_N (1<<5) +//#define CFG_REGS_AU_DAC_RESET_N (1<<8) +//#define CFG_REGS_AU_PLL_PU (1<<16) + +//audio_sel_cfg +#define CFG_REGS_AU_AUXMIC_SEL (1<<0) +#define CFG_REGS_AU_SPK_SEL (1<<1) +#define CFG_REGS_AU_SPK_MONO_SEL (1<<2) +#define CFG_REGS_AU_RCV_SEL (1<<3) +#define CFG_REGS_AU_HEAD_SEL (1<<4) + +//audio_mic_cfg +#define CFG_REGS_AU_MIC_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_MIC_GAIN_MASK (15<<0) +#define CFG_REGS_AU_MIC_GAIN_SHIFT (0) +#define CFG_REGS_AU_MIC_MUTE_N (1<<4) + +//audio_spk_cfg +#define CFG_REGS_AU_SPK_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_SPK_GAIN_MASK (15<<0) +#define CFG_REGS_AU_SPK_GAIN_SHIFT (0) +#define CFG_REGS_AU_SPK_MUTE_N (1<<4) + +//audio_rcv_gain +#define CFG_REGS_AU_RCV_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_RCV_GAIN_MASK (15<<0) +#define CFG_REGS_AU_RCV_GAIN_SHIFT (0) + +//audio_head_gain +#define CFG_REGS_AU_HEAD_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_HEAD_GAIN_MASK (15<<0) +#define CFG_REGS_AU_HEAD_GAIN_SHIFT (0) + +//TSC_DATA +#define CFG_REGS_TSC_X_VALUE_BIT(n) (((n)&0x3FF)<<0) +#define CFG_REGS_TSC_X_VALUE_BIT_MASK (0x3FF<<0) +#define CFG_REGS_TSC_X_VALUE_BIT_SHIFT (0) +#define CFG_REGS_TSC_X_VALUE_VALID (1<<10) +#define CFG_REGS_TSC_Y_VALUE_BIT(n) (((n)&0x3FF)<<11) +#define CFG_REGS_TSC_Y_VALUE_BIT_MASK (0x3FF<<11) +#define CFG_REGS_TSC_Y_VALUE_BIT_SHIFT (11) +#define CFG_REGS_TSC_Y_VALUE_VALID (1<<21) + +//GPADC_DATA_CH +#define CFG_REGS_GPADC_DATA(n) (((n)&0x3FF)<<0) +#define CFG_REGS_GPADC_DATA_MASK (0x3FF<<0) +#define CFG_REGS_GPADC_DATA_SHIFT (0) +#define CFG_REGS_GPADC_VALID (1<<10) +#define CFG_REGS_GPADC_CH_EN (1<<31) + + + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810e.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810e.h new file mode 100644 index 0000000000..e659daf337 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810e.h @@ -0,0 +1,1302 @@ +//============================================================================== +// +// Copyright (C) 2012-2014, RDA Microelectronics. +// All Rights Reserved +// +// This source code is the property of RDA Microelectronics and is +// confidential. Any modification, distribution, reproduction or +// exploitation of any content of this file is totally forbidden, +// except with the written permission of RDA Microelectronics. +// +//============================================================================== +// +// THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML. +// +// !!! PLEASE DO NOT EDIT !!! +// +// $HeadURL$ +// $Author$ +// $Date$ +// $Revision$ +// +//============================================================================== +// +/// @file +// +//============================================================================== + +#ifndef _CFG_REGS_H_ +#define _CFG_REGS_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +#ifdef CT_ASM +#error "You are trying to use in an assembly code the normal H description of 'cfg_regs'." +#endif + + + +// ============================================================================= +// MACROS +// ============================================================================= +#define PROD_ID (0X810E) + +// ============================================================================ +// BB_GPIO_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// BB GPIO Map + BB_PIN_NONE_0 = 0x00000000, + BB_PIN_1 = 0x00000001, + BB_PIN_2 = 0x00000002, + BB_PIN_3 = 0x00000003, + BB_PIN_4 = 0x00000004, + BB_PIN_5 = 0x00000005, + BB_PIN_UART1_RXD = 0x00000006, + BB_PIN_UART2_RXD = 0x00000007, + BB_PIN_UART2_TXD = 0x00000008, + BB_PIN_SSD1_CLK = 0x00000009, + BB_PIN_SSD1_CMD = 0x0000000A, + BB_PIN_SDAT1_0 = 0x0000000B, + BB_PIN_SDAT1_1 = 0x0000000C, + BB_PIN_SDAT1_2 = 0x0000000D, + BB_PIN_SDAT1_3 = 0x0000000E, + BB_PIN_SSD2_CLK = 0x0000000F, + BB_PIN_SSD2_CMD = 0x00000010, + BB_PIN_SDAT2_0 = 0x00000011, + BB_PIN_SDAT2_1 = 0x00000012, + BB_PIN_SDAT2_2 = 0x00000013, + BB_PIN_SDAT2_3 = 0x00000014, + BB_PIN_SPI1_CLK = 0x00000015, + BB_PIN_SPI1_CS_0 = 0x00000016, + BB_PIN_SPI1_DIO = 0x00000017, + BB_PIN_SPI1_DI = 0x00000018, + BB_PIN_SIM2_RST = 0x00000019, + BB_PIN_SIM2_CLK = 0x0000001A, + BB_PIN_SIM2_DIO = 0x0000001B, + BB_PIN_SIM3_RST = 0x0000001C, + BB_PIN_SIM3_CLK = 0x0000001D, + BB_PIN_SIM3_DIO = 0x0000001E +} BB_GPIO_MAPPING_T; + +#define BB_GPIO_NB (31) + +// ============================================================================ +// AP_GPIO_A_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO A Map + AP_PIN_I2C2_SCL = 0x00000000, + AP_PIN_I2C2_SDA = 0x00000001, + AP_PIN_SPI2_CLK = 0x00000002, + AP_PIN_SPI2_DIO = 0x00000003, + AP_PIN_SPI2_DI = 0x00000004, + AP_PIN_SPI2_CS_0 = 0x00000005, + AP_PIN_SPI2_CS_1 = 0x00000006, + AP_PIN_KEYIN_4 = 0x00000007, + AP_PIN_CLK_OUT = 0x00000008, + AP_PIN_I2S_BCK = 0x00000009, + AP_PIN_I2S_LRCK = 0x0000000A, + AP_PIN_I2S_DI_0 = 0x0000000B, + AP_PIN_I2S_DI_1 = 0x0000000C, + AP_PIN_I2S_DO = 0x0000000D, + AP_PIN_UART1_TXD = 0x0000000E, + AP_PIN_UART1_CTS = 0x0000000F, + AP_PIN_UART1_RTS = 0x00000010, + AP_PIN_SPI1_CS_1 = 0x00000011, + AP_PIN_LCD_DATA_6 = 0x00000012, + AP_PIN_LCD_DATA_7 = 0x00000013, + AP_PIN_LCD_WR = 0x00000014, + AP_PIN_LCD_RS = 0x00000015, + AP_PIN_LCD_RD = 0x00000016, + AP_PIN_LCD_FMARK = 0x00000017, + AP_PIN_LCD_DATA_8 = 0x00000018, + AP_PIN_LCD_DATA_9 = 0x00000019, + AP_PIN_LCD_DATA_10 = 0x0000001A, + AP_PIN_LCD_DATA_11 = 0x0000001B, + AP_PIN_LCD_DATA_12 = 0x0000001C, + AP_PIN_LCD_DATA_13 = 0x0000001D, + AP_PIN_LCD_DATA_14 = 0x0000001E, + AP_PIN_LCD_DATA_15 = 0x0000001F +} AP_GPIO_A_MAPPING_T; + +#define AP_GPIO_A_NB (32) + +// ============================================================================ +// AP_GPIO_B_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO B Map + AP_PIN_KEYIN_0 = 0x00000000, + AP_PIN_KEYIN_1 = 0x00000001, + AP_PIN_KEYIN_2 = 0x00000002, + AP_PIN_KEYOUT_0 = 0x00000003, + AP_PIN_KEYOUT_1 = 0x00000004, + AP_PIN_KEYOUT_2 = 0x00000005, + AP_PIN_I2C3_SCL = 0x00000006, + AP_PIN_I2C3_SDA = 0x00000007, + AP_PIN_UART2_CTS = 0x00000008, + AP_PIN_UART2_RTS = 0x00000009, + AP_PIN_CAM_RST = 0x0000000A, + AP_PIN_CAM_PDN = 0x0000000B, + AP_PIN_CAM_CLK = 0x0000000C, + AP_PIN_CAM_VSYNC = 0x0000000D, + AP_PIN_CAM_HREF = 0x0000000E, + AP_PIN_CAM_PCLK = 0x0000000F, + AP_PIN_CAM_DATA_0 = 0x00000010, + AP_PIN_CAM_DATA_1 = 0x00000011, + AP_PIN_CAM_DATA_2 = 0x00000012, + AP_PIN_CAM_DATA_3 = 0x00000013, + AP_PIN_CAM_DATA_4 = 0x00000014, + AP_PIN_CAM_DATA_5 = 0x00000015, + AP_PIN_CAM_DATA_6 = 0x00000016, + AP_PIN_CAM_DATA_7 = 0x00000017, + AP_PIN_M_SPI_CS_0 = 0x00000018, + AP_PIN_NFCLE = 0x00000019, + AP_PIN_NFWEN = 0x0000001A, + AP_PIN_NFWPN = 0x0000001B, + AP_PIN_NFREN = 0x0000001C, + AP_PIN_NFRB = 0x0000001D, + AP_PIN_I2C1_SCL = 0x0000001E, + AP_PIN_I2C1_SDA = 0x0000001F +} AP_GPIO_B_MAPPING_T; + +#define AP_GPIO_B_NB (32) + +// ============================================================================ +// AP_GPIO_D_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO D Map + AP_PIN_UART3_RXD = 0x00000000, + AP_PIN_UART3_TXD = 0x00000001, + AP_PIN_UART3_CTS = 0x00000002, + AP_PIN_UART3_RTS = 0x00000003, + AP_PIN_NFDQS = 0x00000004, + AP_PIN_VOLUME_DN = 0x00000005, + AP_PIN_VOLUME_UP = 0x00000006, + AP_PIN_PLUGIN = 0x00000007, + AP_PIN_NFCEN_1 = 0x00000008, + AP_PIN_NFCEN_2 = 0x00000009, + AP_PIN_NFCEN_3 = 0x0000000A, + AP_PIN_I2S2_BCK = 0x0000000B, + AP_PIN_I2S2_LRCK = 0x0000000C, + AP_PIN_I2S2_DI_0 = 0x0000000D, + AP_PIN_I2S2_DI_1 = 0x0000000E, + AP_PIN_I2S2_DO = 0x0000000F +} AP_GPIO_D_MAPPING_T; + +#define AP_GPIO_D_NB (16) + +// ============================================================================ +// AP_GPIO_E_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO E Map + AP_PIN_I2CBB_SCL = 0x00000000, + AP_PIN_I2CBB_SDA = 0x00000001, + AP_PIN_CAM2_RST = 0x00000002, + AP_PIN_CAM2_PDN = 0x00000003, + AP_PIN_CAM2_CLK = 0x00000004, + AP_PIN_CAM2_VSYNC = 0x00000005, + AP_PIN_CAM2_HREF = 0x00000006, + AP_PIN_CAM2_PCLK = 0x00000007, + AP_PIN_CAM2_DATA_0 = 0x00000008, + AP_PIN_CAM2_DATA_1 = 0x00000009, + AP_PIN_CAM2_DATA_2 = 0x0000000A, + AP_PIN_CAM2_DATA_3 = 0x0000000B, + AP_PIN_CAM2_DATA_4 = 0x0000000C, + AP_PIN_CAM2_DATA_5 = 0x0000000D, + AP_PIN_CAM2_DATA_6 = 0x0000000E, + AP_PIN_CAM2_DATA_7 = 0x0000000F +} AP_GPIO_E_MAPPING_T; + +#define AP_GPIO_E_NB (16) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// CFG_REGS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +#define REG_CONFIG_REGS_BASE 0x01A09000 + +typedef volatile struct +{ + REG32 CHIP_ID; //0x00000000 + /// This register contain the synthesis date and version + REG32 Build_Version; //0x00000004 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 BB_GPIO_Mode; //0x00000008 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_A_Mode; //0x0000000C + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_B_Mode; //0x00000010 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_D_Mode; //0x00000014 + REG32 Alt_mux_select; //0x00000018 + REG32 IO_Drive1_Select; //0x0000001C + REG32 IO_Drive2_Select; //0x00000020 + REG32 RAM_DRIVE; //0x00000024 + REG32 H2X_AP_Offset; //0x00000028 + REG32 H2X_DDR_Offset; //0x0000002C + REG32 audio_pd_set; //0x00000030 + REG32 audio_pd_clr; //0x00000034 + REG32 audio_sel_cfg; //0x00000038 + REG32 audio_mic_cfg; //0x0000003C + REG32 audio_spk_cfg; //0x00000040 + REG32 audio_rcv_gain; //0x00000044 + REG32 audio_head_gain; //0x00000048 + REG32 TSC_DATA; //0x0000004C + REG32 GPADC_DATA_CH[8]; //0x00000050 + REG32 Alt_mux_select2; //0x00000070 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_E_Mode; //0x00000074 +} HWP_CFG_REGS_T; + +#define hwp_configRegs ((HWP_CFG_REGS_T*) (RDA_CFG_REGS_BASE)) + + +//CHIP_ID +#define CFG_REGS_METAL_ID(n) (((n)&0xFFF)<<0) +#define CFG_REGS_METAL_ID_MASK (0xFFF<<0) +#define CFG_REGS_METAL_ID_SHIFT (0) +#define CFG_REGS_BOND_ID(n) (((n)&7)<<12) +#define CFG_REGS_BOND_ID_MASK (7<<12) +#define CFG_REGS_BOND_ID_SHIFT (12) +#define CFG_REGS_PROD_ID(n) (((n)&0xFFFF)<<16) +#define CFG_REGS_PROD_ID_MASK (0xFFFF<<16) +#define CFG_REGS_PROD_ID_SHIFT (16) + +//Build_Version +#define CFG_REGS_MAJOR(n) (((n)&15)<<28) +#define CFG_REGS_YEAR(n) (((n)&15)<<24) +#define CFG_REGS_MONTH(n) (((n)&0xFF)<<16) +#define CFG_REGS_DAY(n) (((n)&0xFF)<<8) +#define CFG_REGS_BUILD_STYLE_FPGA (0<<4) +#define CFG_REGS_BUILD_STYLE_CHIP (1<<4) +#define CFG_REGS_BUILD_STYLE_FPGA_USB (2<<4) +#define CFG_REGS_BUILD_STYLE_FPGA_GSM (3<<4) +#define CFG_REGS_BUILD_REVISION(n) (((n)&15)<<0) + +//BB_GPIO_Mode +#define CFG_REGS_MODE_BB_PIN_NONE_0 (1<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_MASK (1<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_SHIFT (0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_ALT (0<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_GPIO (1<<0) +#define CFG_REGS_MODE_BB_PIN_1 (1<<1) +#define CFG_REGS_MODE_BB_PIN_1_MASK (1<<1) +#define CFG_REGS_MODE_BB_PIN_1_SHIFT (1) +#define CFG_REGS_MODE_BB_PIN_1_ALT (0<<1) +#define CFG_REGS_MODE_BB_PIN_1_GPIO (1<<1) +#define CFG_REGS_MODE_BB_PIN_2 (1<<2) +#define CFG_REGS_MODE_BB_PIN_2_MASK (1<<2) +#define CFG_REGS_MODE_BB_PIN_2_SHIFT (2) +#define CFG_REGS_MODE_BB_PIN_2_ALT (0<<2) +#define CFG_REGS_MODE_BB_PIN_2_GPIO (1<<2) +#define CFG_REGS_MODE_BB_PIN_3 (1<<3) +#define CFG_REGS_MODE_BB_PIN_3_MASK (1<<3) +#define CFG_REGS_MODE_BB_PIN_3_SHIFT (3) +#define CFG_REGS_MODE_BB_PIN_3_ALT (0<<3) +#define CFG_REGS_MODE_BB_PIN_3_GPIO (1<<3) +#define CFG_REGS_MODE_BB_PIN_4 (1<<4) +#define CFG_REGS_MODE_BB_PIN_4_MASK (1<<4) +#define CFG_REGS_MODE_BB_PIN_4_SHIFT (4) +#define CFG_REGS_MODE_BB_PIN_4_ALT (0<<4) +#define CFG_REGS_MODE_BB_PIN_4_GPIO (1<<4) +#define CFG_REGS_MODE_BB_PIN_5 (1<<5) +#define CFG_REGS_MODE_BB_PIN_5_MASK (1<<5) +#define CFG_REGS_MODE_BB_PIN_5_SHIFT (5) +#define CFG_REGS_MODE_BB_PIN_5_ALT (0<<5) +#define CFG_REGS_MODE_BB_PIN_5_GPIO (1<<5) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_MASK (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_SHIFT (6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_ALT (0<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_GPIO (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_MASK (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_SHIFT (7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_ALT (0<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_GPIO (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD (1<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_MASK (1<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_SHIFT (8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_ALT (0<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_GPIO (1<<8) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_MASK (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_SHIFT (9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_ALT (0<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_GPIO (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD (1<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_MASK (1<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_SHIFT (10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_ALT (0<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_GPIO (1<<10) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0 (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_MASK (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_SHIFT (11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_ALT (0<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_GPIO (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1 (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_MASK (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_SHIFT (12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_ALT (0<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_GPIO (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2 (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_MASK (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_SHIFT (13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_ALT (0<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_GPIO (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3 (1<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_MASK (1<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_SHIFT (14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_ALT (0<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_GPIO (1<<14) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_MASK (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_SHIFT (15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_ALT (0<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_GPIO (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD (1<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_MASK (1<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_SHIFT (16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_ALT (0<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_GPIO (1<<16) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0 (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_MASK (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_SHIFT (17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_ALT (0<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_GPIO (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1 (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_MASK (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_SHIFT (18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_ALT (0<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_GPIO (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2 (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_MASK (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_SHIFT (19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_ALT (0<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_GPIO (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3 (1<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_MASK (1<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_SHIFT (20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_ALT (0<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_GPIO (1<<20) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_MASK (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_SHIFT (21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_ALT (0<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_GPIO (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0 (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_MASK (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_SHIFT (22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_ALT (0<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_GPIO (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_MASK (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_SHIFT (23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_ALT (0<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_GPIO (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI (1<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_MASK (1<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_SHIFT (24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_ALT (0<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_GPIO (1<<24) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_MASK (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_SHIFT (25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_ALT (0<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_GPIO (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_MASK (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_SHIFT (26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_ALT (0<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_GPIO (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_MASK (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_SHIFT (27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_ALT (0<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_GPIO (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_MASK (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_SHIFT (28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_ALT (0<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_GPIO (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_MASK (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_SHIFT (29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_ALT (0<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_GPIO (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO (1<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_MASK (1<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_SHIFT (30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_ALT (0<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_GPIO (1<<30) +#define CFG_REGS_BB_GPIO_MODE(n) (((n)&0x7FFFFFFF)<<0) +#define CFG_REGS_BB_GPIO_MODE_MASK (0x7FFFFFFF<<0) +#define CFG_REGS_BB_GPIO_MODE_SHIFT (0) + +//AP_GPIO_A_Mode +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0 (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1 (1<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4 (1<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT (1<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0 (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1 (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DO (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_GPIO (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS (1<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_MASK (1<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_SHIFT (16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_ALT (0<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_GPIO (1<<16) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1 (1<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_MASK (1<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_SHIFT (17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_ALT (0<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_GPIO (1<<17) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6 (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_MASK (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_SHIFT (18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_ALT (0<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_GPIO (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7 (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_MASK (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_SHIFT (19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_ALT (0<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_GPIO (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_WR (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_MASK (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_SHIFT (20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_ALT (0<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_GPIO (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_RS (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_MASK (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_SHIFT (21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_ALT (0<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_GPIO (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RD (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_MASK (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_SHIFT (22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_ALT (0<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_GPIO (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_MASK (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_SHIFT (23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_ALT (0<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_GPIO (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8 (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_MASK (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_SHIFT (24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_ALT (0<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_GPIO (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9 (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_MASK (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_SHIFT (25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_ALT (0<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_GPIO (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10 (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_MASK (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_SHIFT (26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_ALT (0<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_GPIO (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11 (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_MASK (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_SHIFT (27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_ALT (0<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_GPIO (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12 (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_MASK (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_SHIFT (28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_ALT (0<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_GPIO (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13 (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_MASK (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_SHIFT (29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_ALT (0<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_GPIO (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14 (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_MASK (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_SHIFT (30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_ALT (0<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_GPIO (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15 (1<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_MASK (1<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_SHIFT (31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_ALT (0<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_GPIO (1<<31) +#define CFG_REGS_AP_GPIO_A_MODE(n) (((n)&0xFFFFFFFF)<<0) +#define CFG_REGS_AP_GPIO_A_MODE_MASK (0xFFFFFFFF<<0) +#define CFG_REGS_AP_GPIO_A_MODE_SHIFT (0) + +//AP_GPIO_B_Mode +#define CFG_REGS_MODE_AP_PIN_KEYIN_0 (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1 (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2 (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0 (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1 (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2 (1<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA (1<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS (1<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM_RST (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_GPIO (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0 (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_MASK (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_SHIFT (16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_ALT (0<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_GPIO (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1 (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_MASK (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_SHIFT (17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_ALT (0<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_GPIO (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2 (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_MASK (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_SHIFT (18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_ALT (0<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_GPIO (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3 (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_MASK (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_SHIFT (19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_ALT (0<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_GPIO (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4 (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_MASK (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_SHIFT (20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_ALT (0<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_GPIO (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5 (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_MASK (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_SHIFT (21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_ALT (0<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_GPIO (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6 (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_MASK (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_SHIFT (22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_ALT (0<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_GPIO (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7 (1<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_MASK (1<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_SHIFT (23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_ALT (0<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_GPIO (1<<23) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0 (1<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_MASK (1<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_SHIFT (24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_ALT (0<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_GPIO (1<<24) +#define CFG_REGS_MODE_AP_PIN_NFCLE (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_MASK (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_SHIFT (25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_ALT (0<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_GPIO (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFWEN (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_MASK (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_SHIFT (26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_ALT (0<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_GPIO (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWPN (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_MASK (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_SHIFT (27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_ALT (0<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_GPIO (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFREN (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_MASK (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_SHIFT (28) +#define CFG_REGS_MODE_AP_PIN_NFREN_ALT (0<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_GPIO (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFRB (1<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_MASK (1<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_SHIFT (29) +#define CFG_REGS_MODE_AP_PIN_NFRB_ALT (0<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_GPIO (1<<29) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_MASK (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_SHIFT (30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_ALT (0<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_GPIO (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA (1<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_MASK (1<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_SHIFT (31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_ALT (0<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_GPIO (1<<31) +#define CFG_REGS_AP_GPIO_B_MODE(n) (((n)&0xFFFFFFFF)<<0) +#define CFG_REGS_AP_GPIO_B_MODE_MASK (0xFFFFFFFF<<0) +#define CFG_REGS_AP_GPIO_B_MODE_SHIFT (0) + +//AP_GPIO_D_Mode +#define CFG_REGS_MODE_AP_PIN_UART3_RXD (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS (1<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_NFDQS (1<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN (1<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP (1<<6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_PLUGIN (1<<7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1 (1<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2 (1<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3 (1<<10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0 (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1 (1<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO (1<<15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_GPIO (1<<15) +#define CFG_REGS_AP_GPIO_D_MODE(n) (((n)&0xFFFF)<<0) +#define CFG_REGS_AP_GPIO_D_MODE_MASK (0xFFFF<<0) +#define CFG_REGS_AP_GPIO_D_MODE_SHIFT (0) + +//Alt_mux_select +#define CFG_REGS_LCD_MODE_MASK (3<<0) +#define CFG_REGS_LCD_MODE_PARALLEL_16BIT (0<<0) +#define CFG_REGS_LCD_MODE_DSI (1<<0) +#define CFG_REGS_LCD_MODE_RGB_24BIT (2<<0) +#define CFG_REGS_LCD_MODE_RGB_16BIT (3<<0) +#define CFG_REGS_SPI_LCD_MASK (1<<2) +#define CFG_REGS_SPI_LCD_NONE (0<<2) +#define CFG_REGS_SPI_LCD_SPI_LCD (1<<2) +#define CFG_REGS_CAM_I2C2_MASK (1<<3) +#define CFG_REGS_CAM_I2C2_CAM (0<<3) +#define CFG_REGS_CAM_I2C2_I2C2 (1<<3) +#define CFG_REGS_CSI2_MASK (3<<4) +#define CFG_REGS_CSI2_PARALLEL_CAM (0<<4) +#define CFG_REGS_CSI2_CSI2 (1<<4) +#define CFG_REGS_CSI2_SPI_CAM (2<<4) +#define CFG_REGS_UART2_MASK (1<<6) +#define CFG_REGS_UART2_HOST_UART (0<<6) +#define CFG_REGS_UART2_UART2 (1<<6) +#define CFG_REGS_UART1_8LINE_MASK (1<<7) +#define CFG_REGS_UART1_8LINE_UART2 (0<<7) +#define CFG_REGS_UART1_8LINE_UART1_8_LINE (1<<7) +#define CFG_REGS_DAI_MASK (3<<8) +#define CFG_REGS_DAI_I2S (0<<8) +#define CFG_REGS_DAI_DAI (1<<8) +#define CFG_REGS_DAI_DAI_SIMPLE (2<<8) +#define CFG_REGS_KEYIN_3_MASK (1<<10) +#define CFG_REGS_KEYIN_3_SPI2_CS_1 (0<<10) +#define CFG_REGS_KEYIN_3_KEYIN_3 (1<<10) +#define CFG_REGS_LPSCO_1_MASK (1<<11) +#define CFG_REGS_LPSCO_1_KEYIN_4 (0<<11) +#define CFG_REGS_LPSCO_1_LPSCO_1 (1<<11) +#define CFG_REGS_SPI1_CS_2_MASK (1<<12) +#define CFG_REGS_SPI1_CS_2_KEYIN_1 (0<<12) +#define CFG_REGS_SPI1_CS_2_SPI1_CS_2 (1<<12) +#define CFG_REGS_I2S_DI_2_MASK (1<<13) +#define CFG_REGS_I2S_DI_2_KEYIN_2 (0<<13) +#define CFG_REGS_I2S_DI_2_I2S_DI_2 (1<<13) +#define CFG_REGS_TCO_0_MASK (1<<14) +#define CFG_REGS_TCO_0_KEYOUT_0 (0<<14) +#define CFG_REGS_TCO_0_TCO_0 (1<<14) +#define CFG_REGS_TCO_1_MASK (1<<15) +#define CFG_REGS_TCO_1_KEYOUT_1 (0<<15) +#define CFG_REGS_TCO_1_TCO_1 (1<<15) +#define CFG_REGS_TCO_2_MASK (1<<16) +#define CFG_REGS_TCO_2_KEYOUT_2 (0<<16) +#define CFG_REGS_TCO_2_TCO_2 (1<<16) +#define CFG_REGS_KEYOUT_3_4_MASK (1<<17) +#define CFG_REGS_KEYOUT_3_4_I2C3 (0<<17) +#define CFG_REGS_KEYOUT_3_4_KEYOUT_3_4 (1<<17) +#define CFG_REGS_KEYOUT_6_MASK (1<<18) +#define CFG_REGS_KEYOUT_6_UART2_RTS (0<<18) +#define CFG_REGS_KEYOUT_6_KEYOUT_6 (1<<18) +#define CFG_REGS_KEYOUT_7_MASK (1<<19) +#define CFG_REGS_KEYOUT_7_UART1_RTS (0<<19) +#define CFG_REGS_KEYOUT_7_KEYOUT_7 (1<<19) +#define CFG_REGS_GPO_0_MASK (3<<20) +#define CFG_REGS_GPO_0_GPO_0 (0<<20) +#define CFG_REGS_GPO_0_PWT (1<<20) +#define CFG_REGS_GPO_0_KEYIN_5 (2<<20) +#define CFG_REGS_GPO_1_MASK (3<<22) +#define CFG_REGS_GPO_1_GPO_1 (0<<22) +#define CFG_REGS_GPO_1_LPG (1<<22) +#define CFG_REGS_GPO_1_KEYOUT_5 (2<<22) +#define CFG_REGS_GPO_2_MASK (3<<24) +#define CFG_REGS_GPO_2_GPO_2 (0<<24) +#define CFG_REGS_GPO_2_PWL_1 (1<<24) +#define CFG_REGS_GPO_2_CLK_32K (2<<24) +#define CFG_REGS_GPO_3_MASK (1<<26) +#define CFG_REGS_GPO_3_LCD_CS_1 (0<<26) +#define CFG_REGS_GPO_3_GPO_3 (1<<26) +#define CFG_REGS_GPO_4_MASK (1<<27) +#define CFG_REGS_GPO_4_LCD_CS_0 (0<<27) +#define CFG_REGS_GPO_4_GPO_4 (1<<27) +#define CFG_REGS_CLK_OUT_MASK (1<<28) +#define CFG_REGS_CLK_OUT_HST_CLK (0<<28) +#define CFG_REGS_CLK_OUT_CLK_OUT (1<<28) +#define CFG_REGS_DEBUG_MASK (1<<29) +#define CFG_REGS_DEBUG_NONE (0<<29) +#define CFG_REGS_DEBUG_DEBUG_MONITOR (1<<29) +#define CFG_REGS_AP_SPI1_MASK (1<<30) +#define CFG_REGS_AP_SPI1_BB_SPI1 (0<<30) +#define CFG_REGS_AP_SPI1_AP_SPI1 (1<<30) +#define CFG_REGS_RGB_CAM_MASK (1<<31) +#define CFG_REGS_RGB_CAM_DISABLE (0<<31) +#define CFG_REGS_RGB_CAM_ENABLE (1<<31) + +//IO_Drive1_Select +#define CFG_REGS_DDR_DRIVE_MASK (7<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_WEAK (7<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_WEAK (6<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_STRONG (5<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_STRONG (4<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_WEAK (3<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_WEAK (2<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_STRONG (1<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_STRONG (0<<0) +#define CFG_REGS_PSRAM1_DRIVE_MASK (7<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_WEAK (7<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_WEAK (6<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_STRONG (5<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_STRONG (4<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_WEAK (3<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_WEAK (2<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_STRONG (1<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_STRONG (0<<3) +#define CFG_REGS_PSRAM2_DRIVE_MASK (7<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_WEAK (7<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_WEAK (6<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_STRONG (5<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_STRONG (4<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_WEAK (3<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_WEAK (2<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_STRONG (1<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_STRONG (0<<6) +#define CFG_REGS_NFLSH_DRIVE_MASK (7<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_WEAK (7<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_WEAK (6<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_STRONG (5<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_STRONG (4<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_WEAK (3<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK (2<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_STRONG (1<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_STRONG (0<<9) +#define CFG_REGS_LCD1_DRIVE_MASK (7<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_WEAK (7<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_WEAK (6<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_STRONG (5<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_STRONG (4<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_WEAK (3<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_WEAK (2<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_STRONG (1<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_STRONG (0<<12) +#define CFG_REGS_LCD2_DRIVE_MASK (7<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_WEAK (7<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_WEAK (6<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_STRONG (5<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_STRONG (4<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_WEAK (3<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_WEAK (2<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_STRONG (1<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_STRONG (0<<15) +#define CFG_REGS_SDAT1_DRIVE_MASK (7<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_WEAK (7<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_WEAK (6<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_STRONG (5<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_STRONG (4<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_WEAK (3<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_WEAK (2<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_STRONG (1<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_STRONG (0<<18) +#define CFG_REGS_SDAT2_DRIVE_MASK (7<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_WEAK (7<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_WEAK (6<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_STRONG (5<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_STRONG (4<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_WEAK (3<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_WEAK (2<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_STRONG (1<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_STRONG (0<<21) +#define CFG_REGS_CAM_DRIVE_MASK (3<<24) +#define CFG_REGS_CAM_DRIVE_MOST_STRONG (0<<24) +#define CFG_REGS_CAM_DRIVE_STRONG (1<<24) +#define CFG_REGS_CAM_DRIVE_WEAK (2<<24) +#define CFG_REGS_CAM_DRIVE_MOST_WEAK (3<<24) +#define CFG_REGS_SIM1_DRIVE_MASK (3<<26) +#define CFG_REGS_SIM1_DRIVE_MOST_STRONG (0<<26) +#define CFG_REGS_SIM1_DRIVE_STRONG (1<<26) +#define CFG_REGS_SIM1_DRIVE_WEAK (2<<26) +#define CFG_REGS_SIM1_DRIVE_MOST_WEAK (3<<26) +#define CFG_REGS_SIM2_DRIVE_MASK (3<<28) +#define CFG_REGS_SIM2_DRIVE_MOST_STRONG (0<<28) +#define CFG_REGS_SIM2_DRIVE_STRONG (1<<28) +#define CFG_REGS_SIM2_DRIVE_WEAK (2<<28) +#define CFG_REGS_SIM2_DRIVE_MOST_WEAK (3<<28) +#define CFG_REGS_SIM3_DRIVE_MASK (3<<30) +#define CFG_REGS_SIM3_DRIVE_MOST_STRONG (0<<30) +#define CFG_REGS_SIM3_DRIVE_STRONG (1<<30) +#define CFG_REGS_SIM3_DRIVE_WEAK (2<<30) +#define CFG_REGS_SIM3_DRIVE_MOST_WEAK (3<<30) + +//IO_Drive2_Select +#define CFG_REGS_GPIO_DRIVE_MASK (3<<0) +#define CFG_REGS_GPIO_DRIVE_MOST_STRONG (0<<0) +#define CFG_REGS_GPIO_DRIVE_STRONG (1<<0) +#define CFG_REGS_GPIO_DRIVE_WEAK (2<<0) +#define CFG_REGS_GPIO_DRIVE_MOST_WEAK (3<<0) +#define CFG_REGS_CAM2_DRIVE_MASK (3<<2) +#define CFG_REGS_CAM2_DRIVE_MOST_STRONG (0<<2) +#define CFG_REGS_CAM2_DRIVE_STRONG (1<<2) +#define CFG_REGS_CAM2_DRIVE_WEAK (2<<2) +#define CFG_REGS_CAM2_DRIVE_MOST_WEAK (3<<2) + +//RAM_DRIVE +#define CFG_REGS_MBRAM_A(n) (((n)&7)<<0) +#define CFG_REGS_MBRAM_A_MASK (7<<0) +#define CFG_REGS_MBRAM_A_SHIFT (0) +#define CFG_REGS_MBRAM_W(n) (((n)&3)<<3) +#define CFG_REGS_MBRAM_W_MASK (3<<3) +#define CFG_REGS_MBRAM_W_SHIFT (3) +#define CFG_REGS_MBRAM_R (1<<5) +#define CFG_REGS_BBRAM_A(n) (((n)&7)<<6) +#define CFG_REGS_BBRAM_A_MASK (7<<6) +#define CFG_REGS_BBRAM_A_SHIFT (6) +#define CFG_REGS_BBRAM_W(n) (((n)&3)<<9) +#define CFG_REGS_BBRAM_W_MASK (3<<9) +#define CFG_REGS_BBRAM_W_SHIFT (9) +#define CFG_REGS_BBRAM_R (1<<11) +#define CFG_REGS_XP_A(n) (((n)&7)<<12) +#define CFG_REGS_XP_A_MASK (7<<12) +#define CFG_REGS_XP_A_SHIFT (12) +#define CFG_REGS_XP_W(n) (((n)&3)<<15) +#define CFG_REGS_XP_W_MASK (3<<15) +#define CFG_REGS_XP_W_SHIFT (15) +#define CFG_REGS_XP_R (1<<17) +#define CFG_REGS_BP_A(n) (((n)&7)<<18) +#define CFG_REGS_BP_A_MASK (7<<18) +#define CFG_REGS_BP_A_SHIFT (18) +#define CFG_REGS_BP_W(n) (((n)&3)<<21) +#define CFG_REGS_BP_W_MASK (3<<21) +#define CFG_REGS_BP_W_SHIFT (21) +#define CFG_REGS_BP_R (1<<23) +#define CFG_REGS_EV_A(n) (((n)&7)<<24) +#define CFG_REGS_EV_A_MASK (7<<24) +#define CFG_REGS_EV_A_SHIFT (24) +#define CFG_REGS_EV_W(n) (((n)&3)<<27) +#define CFG_REGS_EV_W_MASK (3<<27) +#define CFG_REGS_EV_W_SHIFT (27) +#define CFG_REGS_EV_R (1<<29) + +//H2X_AP_Offset +#define CFG_REGS_H2X_AP_OFFSET(n) (((n)&0xFF)<<0) +#define CFG_REGS_H2X_AP_OFFSET_MASK (0xFF<<0) +#define CFG_REGS_H2X_AP_OFFSET_SHIFT (0) + +//H2X_DDR_Offset +#define CFG_REGS_H2X_DDR_OFFSET(n) (((n)&0xFF)<<0) +#define CFG_REGS_H2X_DDR_OFFSET_MASK (0xFF<<0) +#define CFG_REGS_H2X_DDR_OFFSET_SHIFT (0) + +//audio_pd_set +#define CFG_REGS_AU_DEEP_PD_N (1<<0) +#define CFG_REGS_AU_REF_PD_N (1<<1) +#define CFG_REGS_AU_MIC_PD_N (1<<2) +#define CFG_REGS_AU_AUXMIC_PD_N (1<<3) +#define CFG_REGS_AU_AD_PD_N (1<<4) +#define CFG_REGS_AU_DAC_PD_N (1<<5) +#define CFG_REGS_AU_DAC_RESET_N (1<<8) +#define CFG_REGS_AU_PLL_PU (1<<16) + +//audio_pd_clr +//#define CFG_REGS_AU_DEEP_PD_N (1<<0) +//#define CFG_REGS_AU_REF_PD_N (1<<1) +//#define CFG_REGS_AU_MIC_PD_N (1<<2) +//#define CFG_REGS_AU_AUXMIC_PD_N (1<<3) +//#define CFG_REGS_AU_AD_PD_N (1<<4) +//#define CFG_REGS_AU_DAC_PD_N (1<<5) +//#define CFG_REGS_AU_DAC_RESET_N (1<<8) +//#define CFG_REGS_AU_PLL_PU (1<<16) + +//audio_sel_cfg +#define CFG_REGS_AU_AUXMIC_SEL (1<<0) +#define CFG_REGS_AU_SPK_SEL (1<<1) +#define CFG_REGS_AU_SPK_MONO_SEL (1<<2) +#define CFG_REGS_AU_RCV_SEL (1<<3) +#define CFG_REGS_AU_HEAD_SEL (1<<4) + +//audio_mic_cfg +#define CFG_REGS_AU_MIC_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_MIC_GAIN_MASK (15<<0) +#define CFG_REGS_AU_MIC_GAIN_SHIFT (0) +#define CFG_REGS_AU_MIC_MUTE_N (1<<4) + +//audio_spk_cfg +#define CFG_REGS_AU_SPK_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_SPK_GAIN_MASK (15<<0) +#define CFG_REGS_AU_SPK_GAIN_SHIFT (0) +#define CFG_REGS_AU_SPK_MUTE_N (1<<4) +#define CFG_REGS_AU_SPK_VOC_GAIN_EN (1<<8) + +//audio_rcv_gain +#define CFG_REGS_AU_RCV_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_RCV_GAIN_MASK (15<<0) +#define CFG_REGS_AU_RCV_GAIN_SHIFT (0) +#define CFG_REGS_AU_RCV_VOC_GAIN_EN (1<<8) + +//audio_head_gain +#define CFG_REGS_AU_HEAD_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_HEAD_GAIN_MASK (15<<0) +#define CFG_REGS_AU_HEAD_GAIN_SHIFT (0) +#define CFG_REGS_AU_HEAD_VOC_GAIN_EN (1<<8) + +//TSC_DATA +#define CFG_REGS_TSC_X_VALUE_BIT(n) (((n)&0x3FF)<<0) +#define CFG_REGS_TSC_X_VALUE_BIT_MASK (0x3FF<<0) +#define CFG_REGS_TSC_X_VALUE_BIT_SHIFT (0) +#define CFG_REGS_TSC_X_VALUE_VALID (1<<10) +#define CFG_REGS_TSC_Y_VALUE_BIT(n) (((n)&0x3FF)<<11) +#define CFG_REGS_TSC_Y_VALUE_BIT_MASK (0x3FF<<11) +#define CFG_REGS_TSC_Y_VALUE_BIT_SHIFT (11) +#define CFG_REGS_TSC_Y_VALUE_VALID (1<<21) + +//GPADC_DATA_CH +#define CFG_REGS_GPADC_DATA(n) (((n)&0x3FF)<<0) +#define CFG_REGS_GPADC_DATA_MASK (0x3FF<<0) +#define CFG_REGS_GPADC_DATA_SHIFT (0) +#define CFG_REGS_GPADC_VALID (1<<10) +#define CFG_REGS_GPADC_CH_EN (1<<31) + +//Alt_mux_select2 +#define CFG_REGS_UART1_SDIO2_MASK (1<<0) +#define CFG_REGS_UART1_SDIO2_SDIO2 (0<<0) +#define CFG_REGS_UART1_SDIO2_UART1 (1<<0) +#define CFG_REGS_JTAG_EN_MASK (1<<1) +#define CFG_REGS_JTAG_EN_DISABLE (0<<1) +#define CFG_REGS_JTAG_EN_ENABLE (1<<1) +#define CFG_REGS_LCD_RGB_17_16_MASK (1<<2) +#define CFG_REGS_LCD_RGB_17_16_LCD_CS (0<<2) +#define CFG_REGS_LCD_RGB_17_16_LCD_DATA (1<<2) +#define CFG_REGS_CSI2_2_MASK (3<<3) +#define CFG_REGS_CSI2_2_PARALLEL_CAM (0<<3) +#define CFG_REGS_CSI2_2_CSI2 (1<<3) +#define CFG_REGS_CSI2_2_SPI_CAM (2<<3) +#define CFG_REGS_RGB_CAM_2_MASK (1<<5) +#define CFG_REGS_RGB_CAM_2_DISABLE (0<<5) +#define CFG_REGS_RGB_CAM_2_ENABLE (1<<5) +#define CFG_REGS_MAC_EN_MASK (1<<6) +#define CFG_REGS_MAC_EN_DISABLE (0<<6) +#define CFG_REGS_MAC_EN_ENABLE (1<<6) +#define CFG_REGS_IOMUX_CFG_RESERVED(n) (((n)&0x1FFFFFF)<<7) + +//AP_GPIO_E_Mode +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST (1<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN (1<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK (1<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC (1<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF (1<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK (1<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0 (1<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1 (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2 (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3 (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4 (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5 (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6 (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7 (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_GPIO (1<<15) +#define CFG_REGS_AP_GPIO_E_MODE(n) (((n)&0xFFFF)<<0) +#define CFG_REGS_AP_GPIO_E_MODE_MASK (0xFFFF<<0) +#define CFG_REGS_AP_GPIO_E_MODE_SHIFT (0) + + + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810h.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810h.h new file mode 100644 index 0000000000..e659daf337 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810h.h @@ -0,0 +1,1302 @@ +//============================================================================== +// +// Copyright (C) 2012-2014, RDA Microelectronics. +// All Rights Reserved +// +// This source code is the property of RDA Microelectronics and is +// confidential. Any modification, distribution, reproduction or +// exploitation of any content of this file is totally forbidden, +// except with the written permission of RDA Microelectronics. +// +//============================================================================== +// +// THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML. +// +// !!! PLEASE DO NOT EDIT !!! +// +// $HeadURL$ +// $Author$ +// $Date$ +// $Revision$ +// +//============================================================================== +// +/// @file +// +//============================================================================== + +#ifndef _CFG_REGS_H_ +#define _CFG_REGS_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +#ifdef CT_ASM +#error "You are trying to use in an assembly code the normal H description of 'cfg_regs'." +#endif + + + +// ============================================================================= +// MACROS +// ============================================================================= +#define PROD_ID (0X810E) + +// ============================================================================ +// BB_GPIO_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// BB GPIO Map + BB_PIN_NONE_0 = 0x00000000, + BB_PIN_1 = 0x00000001, + BB_PIN_2 = 0x00000002, + BB_PIN_3 = 0x00000003, + BB_PIN_4 = 0x00000004, + BB_PIN_5 = 0x00000005, + BB_PIN_UART1_RXD = 0x00000006, + BB_PIN_UART2_RXD = 0x00000007, + BB_PIN_UART2_TXD = 0x00000008, + BB_PIN_SSD1_CLK = 0x00000009, + BB_PIN_SSD1_CMD = 0x0000000A, + BB_PIN_SDAT1_0 = 0x0000000B, + BB_PIN_SDAT1_1 = 0x0000000C, + BB_PIN_SDAT1_2 = 0x0000000D, + BB_PIN_SDAT1_3 = 0x0000000E, + BB_PIN_SSD2_CLK = 0x0000000F, + BB_PIN_SSD2_CMD = 0x00000010, + BB_PIN_SDAT2_0 = 0x00000011, + BB_PIN_SDAT2_1 = 0x00000012, + BB_PIN_SDAT2_2 = 0x00000013, + BB_PIN_SDAT2_3 = 0x00000014, + BB_PIN_SPI1_CLK = 0x00000015, + BB_PIN_SPI1_CS_0 = 0x00000016, + BB_PIN_SPI1_DIO = 0x00000017, + BB_PIN_SPI1_DI = 0x00000018, + BB_PIN_SIM2_RST = 0x00000019, + BB_PIN_SIM2_CLK = 0x0000001A, + BB_PIN_SIM2_DIO = 0x0000001B, + BB_PIN_SIM3_RST = 0x0000001C, + BB_PIN_SIM3_CLK = 0x0000001D, + BB_PIN_SIM3_DIO = 0x0000001E +} BB_GPIO_MAPPING_T; + +#define BB_GPIO_NB (31) + +// ============================================================================ +// AP_GPIO_A_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO A Map + AP_PIN_I2C2_SCL = 0x00000000, + AP_PIN_I2C2_SDA = 0x00000001, + AP_PIN_SPI2_CLK = 0x00000002, + AP_PIN_SPI2_DIO = 0x00000003, + AP_PIN_SPI2_DI = 0x00000004, + AP_PIN_SPI2_CS_0 = 0x00000005, + AP_PIN_SPI2_CS_1 = 0x00000006, + AP_PIN_KEYIN_4 = 0x00000007, + AP_PIN_CLK_OUT = 0x00000008, + AP_PIN_I2S_BCK = 0x00000009, + AP_PIN_I2S_LRCK = 0x0000000A, + AP_PIN_I2S_DI_0 = 0x0000000B, + AP_PIN_I2S_DI_1 = 0x0000000C, + AP_PIN_I2S_DO = 0x0000000D, + AP_PIN_UART1_TXD = 0x0000000E, + AP_PIN_UART1_CTS = 0x0000000F, + AP_PIN_UART1_RTS = 0x00000010, + AP_PIN_SPI1_CS_1 = 0x00000011, + AP_PIN_LCD_DATA_6 = 0x00000012, + AP_PIN_LCD_DATA_7 = 0x00000013, + AP_PIN_LCD_WR = 0x00000014, + AP_PIN_LCD_RS = 0x00000015, + AP_PIN_LCD_RD = 0x00000016, + AP_PIN_LCD_FMARK = 0x00000017, + AP_PIN_LCD_DATA_8 = 0x00000018, + AP_PIN_LCD_DATA_9 = 0x00000019, + AP_PIN_LCD_DATA_10 = 0x0000001A, + AP_PIN_LCD_DATA_11 = 0x0000001B, + AP_PIN_LCD_DATA_12 = 0x0000001C, + AP_PIN_LCD_DATA_13 = 0x0000001D, + AP_PIN_LCD_DATA_14 = 0x0000001E, + AP_PIN_LCD_DATA_15 = 0x0000001F +} AP_GPIO_A_MAPPING_T; + +#define AP_GPIO_A_NB (32) + +// ============================================================================ +// AP_GPIO_B_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO B Map + AP_PIN_KEYIN_0 = 0x00000000, + AP_PIN_KEYIN_1 = 0x00000001, + AP_PIN_KEYIN_2 = 0x00000002, + AP_PIN_KEYOUT_0 = 0x00000003, + AP_PIN_KEYOUT_1 = 0x00000004, + AP_PIN_KEYOUT_2 = 0x00000005, + AP_PIN_I2C3_SCL = 0x00000006, + AP_PIN_I2C3_SDA = 0x00000007, + AP_PIN_UART2_CTS = 0x00000008, + AP_PIN_UART2_RTS = 0x00000009, + AP_PIN_CAM_RST = 0x0000000A, + AP_PIN_CAM_PDN = 0x0000000B, + AP_PIN_CAM_CLK = 0x0000000C, + AP_PIN_CAM_VSYNC = 0x0000000D, + AP_PIN_CAM_HREF = 0x0000000E, + AP_PIN_CAM_PCLK = 0x0000000F, + AP_PIN_CAM_DATA_0 = 0x00000010, + AP_PIN_CAM_DATA_1 = 0x00000011, + AP_PIN_CAM_DATA_2 = 0x00000012, + AP_PIN_CAM_DATA_3 = 0x00000013, + AP_PIN_CAM_DATA_4 = 0x00000014, + AP_PIN_CAM_DATA_5 = 0x00000015, + AP_PIN_CAM_DATA_6 = 0x00000016, + AP_PIN_CAM_DATA_7 = 0x00000017, + AP_PIN_M_SPI_CS_0 = 0x00000018, + AP_PIN_NFCLE = 0x00000019, + AP_PIN_NFWEN = 0x0000001A, + AP_PIN_NFWPN = 0x0000001B, + AP_PIN_NFREN = 0x0000001C, + AP_PIN_NFRB = 0x0000001D, + AP_PIN_I2C1_SCL = 0x0000001E, + AP_PIN_I2C1_SDA = 0x0000001F +} AP_GPIO_B_MAPPING_T; + +#define AP_GPIO_B_NB (32) + +// ============================================================================ +// AP_GPIO_D_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO D Map + AP_PIN_UART3_RXD = 0x00000000, + AP_PIN_UART3_TXD = 0x00000001, + AP_PIN_UART3_CTS = 0x00000002, + AP_PIN_UART3_RTS = 0x00000003, + AP_PIN_NFDQS = 0x00000004, + AP_PIN_VOLUME_DN = 0x00000005, + AP_PIN_VOLUME_UP = 0x00000006, + AP_PIN_PLUGIN = 0x00000007, + AP_PIN_NFCEN_1 = 0x00000008, + AP_PIN_NFCEN_2 = 0x00000009, + AP_PIN_NFCEN_3 = 0x0000000A, + AP_PIN_I2S2_BCK = 0x0000000B, + AP_PIN_I2S2_LRCK = 0x0000000C, + AP_PIN_I2S2_DI_0 = 0x0000000D, + AP_PIN_I2S2_DI_1 = 0x0000000E, + AP_PIN_I2S2_DO = 0x0000000F +} AP_GPIO_D_MAPPING_T; + +#define AP_GPIO_D_NB (16) + +// ============================================================================ +// AP_GPIO_E_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO E Map + AP_PIN_I2CBB_SCL = 0x00000000, + AP_PIN_I2CBB_SDA = 0x00000001, + AP_PIN_CAM2_RST = 0x00000002, + AP_PIN_CAM2_PDN = 0x00000003, + AP_PIN_CAM2_CLK = 0x00000004, + AP_PIN_CAM2_VSYNC = 0x00000005, + AP_PIN_CAM2_HREF = 0x00000006, + AP_PIN_CAM2_PCLK = 0x00000007, + AP_PIN_CAM2_DATA_0 = 0x00000008, + AP_PIN_CAM2_DATA_1 = 0x00000009, + AP_PIN_CAM2_DATA_2 = 0x0000000A, + AP_PIN_CAM2_DATA_3 = 0x0000000B, + AP_PIN_CAM2_DATA_4 = 0x0000000C, + AP_PIN_CAM2_DATA_5 = 0x0000000D, + AP_PIN_CAM2_DATA_6 = 0x0000000E, + AP_PIN_CAM2_DATA_7 = 0x0000000F +} AP_GPIO_E_MAPPING_T; + +#define AP_GPIO_E_NB (16) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// CFG_REGS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +#define REG_CONFIG_REGS_BASE 0x01A09000 + +typedef volatile struct +{ + REG32 CHIP_ID; //0x00000000 + /// This register contain the synthesis date and version + REG32 Build_Version; //0x00000004 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 BB_GPIO_Mode; //0x00000008 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_A_Mode; //0x0000000C + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_B_Mode; //0x00000010 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_D_Mode; //0x00000014 + REG32 Alt_mux_select; //0x00000018 + REG32 IO_Drive1_Select; //0x0000001C + REG32 IO_Drive2_Select; //0x00000020 + REG32 RAM_DRIVE; //0x00000024 + REG32 H2X_AP_Offset; //0x00000028 + REG32 H2X_DDR_Offset; //0x0000002C + REG32 audio_pd_set; //0x00000030 + REG32 audio_pd_clr; //0x00000034 + REG32 audio_sel_cfg; //0x00000038 + REG32 audio_mic_cfg; //0x0000003C + REG32 audio_spk_cfg; //0x00000040 + REG32 audio_rcv_gain; //0x00000044 + REG32 audio_head_gain; //0x00000048 + REG32 TSC_DATA; //0x0000004C + REG32 GPADC_DATA_CH[8]; //0x00000050 + REG32 Alt_mux_select2; //0x00000070 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_E_Mode; //0x00000074 +} HWP_CFG_REGS_T; + +#define hwp_configRegs ((HWP_CFG_REGS_T*) (RDA_CFG_REGS_BASE)) + + +//CHIP_ID +#define CFG_REGS_METAL_ID(n) (((n)&0xFFF)<<0) +#define CFG_REGS_METAL_ID_MASK (0xFFF<<0) +#define CFG_REGS_METAL_ID_SHIFT (0) +#define CFG_REGS_BOND_ID(n) (((n)&7)<<12) +#define CFG_REGS_BOND_ID_MASK (7<<12) +#define CFG_REGS_BOND_ID_SHIFT (12) +#define CFG_REGS_PROD_ID(n) (((n)&0xFFFF)<<16) +#define CFG_REGS_PROD_ID_MASK (0xFFFF<<16) +#define CFG_REGS_PROD_ID_SHIFT (16) + +//Build_Version +#define CFG_REGS_MAJOR(n) (((n)&15)<<28) +#define CFG_REGS_YEAR(n) (((n)&15)<<24) +#define CFG_REGS_MONTH(n) (((n)&0xFF)<<16) +#define CFG_REGS_DAY(n) (((n)&0xFF)<<8) +#define CFG_REGS_BUILD_STYLE_FPGA (0<<4) +#define CFG_REGS_BUILD_STYLE_CHIP (1<<4) +#define CFG_REGS_BUILD_STYLE_FPGA_USB (2<<4) +#define CFG_REGS_BUILD_STYLE_FPGA_GSM (3<<4) +#define CFG_REGS_BUILD_REVISION(n) (((n)&15)<<0) + +//BB_GPIO_Mode +#define CFG_REGS_MODE_BB_PIN_NONE_0 (1<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_MASK (1<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_SHIFT (0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_ALT (0<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_GPIO (1<<0) +#define CFG_REGS_MODE_BB_PIN_1 (1<<1) +#define CFG_REGS_MODE_BB_PIN_1_MASK (1<<1) +#define CFG_REGS_MODE_BB_PIN_1_SHIFT (1) +#define CFG_REGS_MODE_BB_PIN_1_ALT (0<<1) +#define CFG_REGS_MODE_BB_PIN_1_GPIO (1<<1) +#define CFG_REGS_MODE_BB_PIN_2 (1<<2) +#define CFG_REGS_MODE_BB_PIN_2_MASK (1<<2) +#define CFG_REGS_MODE_BB_PIN_2_SHIFT (2) +#define CFG_REGS_MODE_BB_PIN_2_ALT (0<<2) +#define CFG_REGS_MODE_BB_PIN_2_GPIO (1<<2) +#define CFG_REGS_MODE_BB_PIN_3 (1<<3) +#define CFG_REGS_MODE_BB_PIN_3_MASK (1<<3) +#define CFG_REGS_MODE_BB_PIN_3_SHIFT (3) +#define CFG_REGS_MODE_BB_PIN_3_ALT (0<<3) +#define CFG_REGS_MODE_BB_PIN_3_GPIO (1<<3) +#define CFG_REGS_MODE_BB_PIN_4 (1<<4) +#define CFG_REGS_MODE_BB_PIN_4_MASK (1<<4) +#define CFG_REGS_MODE_BB_PIN_4_SHIFT (4) +#define CFG_REGS_MODE_BB_PIN_4_ALT (0<<4) +#define CFG_REGS_MODE_BB_PIN_4_GPIO (1<<4) +#define CFG_REGS_MODE_BB_PIN_5 (1<<5) +#define CFG_REGS_MODE_BB_PIN_5_MASK (1<<5) +#define CFG_REGS_MODE_BB_PIN_5_SHIFT (5) +#define CFG_REGS_MODE_BB_PIN_5_ALT (0<<5) +#define CFG_REGS_MODE_BB_PIN_5_GPIO (1<<5) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_MASK (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_SHIFT (6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_ALT (0<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_GPIO (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_MASK (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_SHIFT (7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_ALT (0<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_GPIO (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD (1<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_MASK (1<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_SHIFT (8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_ALT (0<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_GPIO (1<<8) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_MASK (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_SHIFT (9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_ALT (0<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_GPIO (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD (1<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_MASK (1<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_SHIFT (10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_ALT (0<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_GPIO (1<<10) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0 (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_MASK (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_SHIFT (11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_ALT (0<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_GPIO (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1 (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_MASK (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_SHIFT (12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_ALT (0<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_GPIO (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2 (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_MASK (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_SHIFT (13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_ALT (0<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_GPIO (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3 (1<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_MASK (1<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_SHIFT (14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_ALT (0<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_GPIO (1<<14) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_MASK (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_SHIFT (15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_ALT (0<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_GPIO (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD (1<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_MASK (1<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_SHIFT (16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_ALT (0<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_GPIO (1<<16) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0 (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_MASK (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_SHIFT (17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_ALT (0<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_GPIO (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1 (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_MASK (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_SHIFT (18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_ALT (0<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_GPIO (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2 (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_MASK (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_SHIFT (19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_ALT (0<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_GPIO (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3 (1<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_MASK (1<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_SHIFT (20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_ALT (0<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_GPIO (1<<20) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_MASK (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_SHIFT (21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_ALT (0<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_GPIO (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0 (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_MASK (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_SHIFT (22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_ALT (0<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_GPIO (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_MASK (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_SHIFT (23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_ALT (0<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_GPIO (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI (1<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_MASK (1<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_SHIFT (24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_ALT (0<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_GPIO (1<<24) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_MASK (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_SHIFT (25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_ALT (0<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_GPIO (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_MASK (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_SHIFT (26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_ALT (0<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_GPIO (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_MASK (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_SHIFT (27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_ALT (0<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_GPIO (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_MASK (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_SHIFT (28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_ALT (0<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_GPIO (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_MASK (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_SHIFT (29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_ALT (0<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_GPIO (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO (1<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_MASK (1<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_SHIFT (30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_ALT (0<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_GPIO (1<<30) +#define CFG_REGS_BB_GPIO_MODE(n) (((n)&0x7FFFFFFF)<<0) +#define CFG_REGS_BB_GPIO_MODE_MASK (0x7FFFFFFF<<0) +#define CFG_REGS_BB_GPIO_MODE_SHIFT (0) + +//AP_GPIO_A_Mode +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0 (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1 (1<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4 (1<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT (1<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0 (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1 (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DO (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_GPIO (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS (1<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_MASK (1<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_SHIFT (16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_ALT (0<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_GPIO (1<<16) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1 (1<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_MASK (1<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_SHIFT (17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_ALT (0<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_GPIO (1<<17) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6 (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_MASK (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_SHIFT (18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_ALT (0<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_GPIO (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7 (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_MASK (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_SHIFT (19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_ALT (0<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_GPIO (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_WR (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_MASK (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_SHIFT (20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_ALT (0<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_GPIO (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_RS (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_MASK (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_SHIFT (21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_ALT (0<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_GPIO (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RD (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_MASK (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_SHIFT (22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_ALT (0<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_GPIO (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_MASK (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_SHIFT (23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_ALT (0<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_GPIO (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8 (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_MASK (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_SHIFT (24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_ALT (0<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_GPIO (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9 (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_MASK (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_SHIFT (25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_ALT (0<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_GPIO (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10 (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_MASK (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_SHIFT (26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_ALT (0<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_GPIO (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11 (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_MASK (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_SHIFT (27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_ALT (0<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_GPIO (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12 (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_MASK (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_SHIFT (28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_ALT (0<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_GPIO (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13 (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_MASK (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_SHIFT (29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_ALT (0<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_GPIO (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14 (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_MASK (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_SHIFT (30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_ALT (0<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_GPIO (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15 (1<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_MASK (1<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_SHIFT (31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_ALT (0<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_GPIO (1<<31) +#define CFG_REGS_AP_GPIO_A_MODE(n) (((n)&0xFFFFFFFF)<<0) +#define CFG_REGS_AP_GPIO_A_MODE_MASK (0xFFFFFFFF<<0) +#define CFG_REGS_AP_GPIO_A_MODE_SHIFT (0) + +//AP_GPIO_B_Mode +#define CFG_REGS_MODE_AP_PIN_KEYIN_0 (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1 (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2 (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0 (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1 (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2 (1<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA (1<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS (1<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM_RST (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_GPIO (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0 (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_MASK (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_SHIFT (16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_ALT (0<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_GPIO (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1 (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_MASK (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_SHIFT (17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_ALT (0<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_GPIO (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2 (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_MASK (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_SHIFT (18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_ALT (0<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_GPIO (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3 (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_MASK (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_SHIFT (19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_ALT (0<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_GPIO (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4 (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_MASK (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_SHIFT (20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_ALT (0<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_GPIO (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5 (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_MASK (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_SHIFT (21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_ALT (0<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_GPIO (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6 (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_MASK (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_SHIFT (22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_ALT (0<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_GPIO (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7 (1<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_MASK (1<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_SHIFT (23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_ALT (0<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_GPIO (1<<23) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0 (1<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_MASK (1<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_SHIFT (24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_ALT (0<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_GPIO (1<<24) +#define CFG_REGS_MODE_AP_PIN_NFCLE (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_MASK (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_SHIFT (25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_ALT (0<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_GPIO (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFWEN (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_MASK (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_SHIFT (26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_ALT (0<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_GPIO (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWPN (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_MASK (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_SHIFT (27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_ALT (0<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_GPIO (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFREN (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_MASK (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_SHIFT (28) +#define CFG_REGS_MODE_AP_PIN_NFREN_ALT (0<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_GPIO (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFRB (1<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_MASK (1<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_SHIFT (29) +#define CFG_REGS_MODE_AP_PIN_NFRB_ALT (0<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_GPIO (1<<29) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_MASK (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_SHIFT (30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_ALT (0<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_GPIO (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA (1<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_MASK (1<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_SHIFT (31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_ALT (0<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_GPIO (1<<31) +#define CFG_REGS_AP_GPIO_B_MODE(n) (((n)&0xFFFFFFFF)<<0) +#define CFG_REGS_AP_GPIO_B_MODE_MASK (0xFFFFFFFF<<0) +#define CFG_REGS_AP_GPIO_B_MODE_SHIFT (0) + +//AP_GPIO_D_Mode +#define CFG_REGS_MODE_AP_PIN_UART3_RXD (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS (1<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_NFDQS (1<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN (1<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP (1<<6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_PLUGIN (1<<7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1 (1<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2 (1<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3 (1<<10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0 (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1 (1<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO (1<<15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_GPIO (1<<15) +#define CFG_REGS_AP_GPIO_D_MODE(n) (((n)&0xFFFF)<<0) +#define CFG_REGS_AP_GPIO_D_MODE_MASK (0xFFFF<<0) +#define CFG_REGS_AP_GPIO_D_MODE_SHIFT (0) + +//Alt_mux_select +#define CFG_REGS_LCD_MODE_MASK (3<<0) +#define CFG_REGS_LCD_MODE_PARALLEL_16BIT (0<<0) +#define CFG_REGS_LCD_MODE_DSI (1<<0) +#define CFG_REGS_LCD_MODE_RGB_24BIT (2<<0) +#define CFG_REGS_LCD_MODE_RGB_16BIT (3<<0) +#define CFG_REGS_SPI_LCD_MASK (1<<2) +#define CFG_REGS_SPI_LCD_NONE (0<<2) +#define CFG_REGS_SPI_LCD_SPI_LCD (1<<2) +#define CFG_REGS_CAM_I2C2_MASK (1<<3) +#define CFG_REGS_CAM_I2C2_CAM (0<<3) +#define CFG_REGS_CAM_I2C2_I2C2 (1<<3) +#define CFG_REGS_CSI2_MASK (3<<4) +#define CFG_REGS_CSI2_PARALLEL_CAM (0<<4) +#define CFG_REGS_CSI2_CSI2 (1<<4) +#define CFG_REGS_CSI2_SPI_CAM (2<<4) +#define CFG_REGS_UART2_MASK (1<<6) +#define CFG_REGS_UART2_HOST_UART (0<<6) +#define CFG_REGS_UART2_UART2 (1<<6) +#define CFG_REGS_UART1_8LINE_MASK (1<<7) +#define CFG_REGS_UART1_8LINE_UART2 (0<<7) +#define CFG_REGS_UART1_8LINE_UART1_8_LINE (1<<7) +#define CFG_REGS_DAI_MASK (3<<8) +#define CFG_REGS_DAI_I2S (0<<8) +#define CFG_REGS_DAI_DAI (1<<8) +#define CFG_REGS_DAI_DAI_SIMPLE (2<<8) +#define CFG_REGS_KEYIN_3_MASK (1<<10) +#define CFG_REGS_KEYIN_3_SPI2_CS_1 (0<<10) +#define CFG_REGS_KEYIN_3_KEYIN_3 (1<<10) +#define CFG_REGS_LPSCO_1_MASK (1<<11) +#define CFG_REGS_LPSCO_1_KEYIN_4 (0<<11) +#define CFG_REGS_LPSCO_1_LPSCO_1 (1<<11) +#define CFG_REGS_SPI1_CS_2_MASK (1<<12) +#define CFG_REGS_SPI1_CS_2_KEYIN_1 (0<<12) +#define CFG_REGS_SPI1_CS_2_SPI1_CS_2 (1<<12) +#define CFG_REGS_I2S_DI_2_MASK (1<<13) +#define CFG_REGS_I2S_DI_2_KEYIN_2 (0<<13) +#define CFG_REGS_I2S_DI_2_I2S_DI_2 (1<<13) +#define CFG_REGS_TCO_0_MASK (1<<14) +#define CFG_REGS_TCO_0_KEYOUT_0 (0<<14) +#define CFG_REGS_TCO_0_TCO_0 (1<<14) +#define CFG_REGS_TCO_1_MASK (1<<15) +#define CFG_REGS_TCO_1_KEYOUT_1 (0<<15) +#define CFG_REGS_TCO_1_TCO_1 (1<<15) +#define CFG_REGS_TCO_2_MASK (1<<16) +#define CFG_REGS_TCO_2_KEYOUT_2 (0<<16) +#define CFG_REGS_TCO_2_TCO_2 (1<<16) +#define CFG_REGS_KEYOUT_3_4_MASK (1<<17) +#define CFG_REGS_KEYOUT_3_4_I2C3 (0<<17) +#define CFG_REGS_KEYOUT_3_4_KEYOUT_3_4 (1<<17) +#define CFG_REGS_KEYOUT_6_MASK (1<<18) +#define CFG_REGS_KEYOUT_6_UART2_RTS (0<<18) +#define CFG_REGS_KEYOUT_6_KEYOUT_6 (1<<18) +#define CFG_REGS_KEYOUT_7_MASK (1<<19) +#define CFG_REGS_KEYOUT_7_UART1_RTS (0<<19) +#define CFG_REGS_KEYOUT_7_KEYOUT_7 (1<<19) +#define CFG_REGS_GPO_0_MASK (3<<20) +#define CFG_REGS_GPO_0_GPO_0 (0<<20) +#define CFG_REGS_GPO_0_PWT (1<<20) +#define CFG_REGS_GPO_0_KEYIN_5 (2<<20) +#define CFG_REGS_GPO_1_MASK (3<<22) +#define CFG_REGS_GPO_1_GPO_1 (0<<22) +#define CFG_REGS_GPO_1_LPG (1<<22) +#define CFG_REGS_GPO_1_KEYOUT_5 (2<<22) +#define CFG_REGS_GPO_2_MASK (3<<24) +#define CFG_REGS_GPO_2_GPO_2 (0<<24) +#define CFG_REGS_GPO_2_PWL_1 (1<<24) +#define CFG_REGS_GPO_2_CLK_32K (2<<24) +#define CFG_REGS_GPO_3_MASK (1<<26) +#define CFG_REGS_GPO_3_LCD_CS_1 (0<<26) +#define CFG_REGS_GPO_3_GPO_3 (1<<26) +#define CFG_REGS_GPO_4_MASK (1<<27) +#define CFG_REGS_GPO_4_LCD_CS_0 (0<<27) +#define CFG_REGS_GPO_4_GPO_4 (1<<27) +#define CFG_REGS_CLK_OUT_MASK (1<<28) +#define CFG_REGS_CLK_OUT_HST_CLK (0<<28) +#define CFG_REGS_CLK_OUT_CLK_OUT (1<<28) +#define CFG_REGS_DEBUG_MASK (1<<29) +#define CFG_REGS_DEBUG_NONE (0<<29) +#define CFG_REGS_DEBUG_DEBUG_MONITOR (1<<29) +#define CFG_REGS_AP_SPI1_MASK (1<<30) +#define CFG_REGS_AP_SPI1_BB_SPI1 (0<<30) +#define CFG_REGS_AP_SPI1_AP_SPI1 (1<<30) +#define CFG_REGS_RGB_CAM_MASK (1<<31) +#define CFG_REGS_RGB_CAM_DISABLE (0<<31) +#define CFG_REGS_RGB_CAM_ENABLE (1<<31) + +//IO_Drive1_Select +#define CFG_REGS_DDR_DRIVE_MASK (7<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_WEAK (7<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_WEAK (6<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_STRONG (5<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_STRONG (4<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_WEAK (3<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_WEAK (2<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_STRONG (1<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_STRONG (0<<0) +#define CFG_REGS_PSRAM1_DRIVE_MASK (7<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_WEAK (7<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_WEAK (6<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_STRONG (5<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_STRONG (4<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_WEAK (3<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_WEAK (2<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_STRONG (1<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_STRONG (0<<3) +#define CFG_REGS_PSRAM2_DRIVE_MASK (7<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_WEAK (7<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_WEAK (6<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_STRONG (5<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_STRONG (4<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_WEAK (3<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_WEAK (2<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_STRONG (1<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_STRONG (0<<6) +#define CFG_REGS_NFLSH_DRIVE_MASK (7<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_WEAK (7<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_WEAK (6<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_STRONG (5<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_STRONG (4<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_WEAK (3<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK (2<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_STRONG (1<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_STRONG (0<<9) +#define CFG_REGS_LCD1_DRIVE_MASK (7<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_WEAK (7<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_WEAK (6<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_STRONG (5<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_STRONG (4<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_WEAK (3<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_WEAK (2<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_STRONG (1<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_STRONG (0<<12) +#define CFG_REGS_LCD2_DRIVE_MASK (7<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_WEAK (7<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_WEAK (6<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_STRONG (5<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_STRONG (4<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_WEAK (3<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_WEAK (2<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_STRONG (1<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_STRONG (0<<15) +#define CFG_REGS_SDAT1_DRIVE_MASK (7<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_WEAK (7<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_WEAK (6<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_STRONG (5<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_STRONG (4<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_WEAK (3<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_WEAK (2<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_STRONG (1<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_STRONG (0<<18) +#define CFG_REGS_SDAT2_DRIVE_MASK (7<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_WEAK (7<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_WEAK (6<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_STRONG (5<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_STRONG (4<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_WEAK (3<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_WEAK (2<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_STRONG (1<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_STRONG (0<<21) +#define CFG_REGS_CAM_DRIVE_MASK (3<<24) +#define CFG_REGS_CAM_DRIVE_MOST_STRONG (0<<24) +#define CFG_REGS_CAM_DRIVE_STRONG (1<<24) +#define CFG_REGS_CAM_DRIVE_WEAK (2<<24) +#define CFG_REGS_CAM_DRIVE_MOST_WEAK (3<<24) +#define CFG_REGS_SIM1_DRIVE_MASK (3<<26) +#define CFG_REGS_SIM1_DRIVE_MOST_STRONG (0<<26) +#define CFG_REGS_SIM1_DRIVE_STRONG (1<<26) +#define CFG_REGS_SIM1_DRIVE_WEAK (2<<26) +#define CFG_REGS_SIM1_DRIVE_MOST_WEAK (3<<26) +#define CFG_REGS_SIM2_DRIVE_MASK (3<<28) +#define CFG_REGS_SIM2_DRIVE_MOST_STRONG (0<<28) +#define CFG_REGS_SIM2_DRIVE_STRONG (1<<28) +#define CFG_REGS_SIM2_DRIVE_WEAK (2<<28) +#define CFG_REGS_SIM2_DRIVE_MOST_WEAK (3<<28) +#define CFG_REGS_SIM3_DRIVE_MASK (3<<30) +#define CFG_REGS_SIM3_DRIVE_MOST_STRONG (0<<30) +#define CFG_REGS_SIM3_DRIVE_STRONG (1<<30) +#define CFG_REGS_SIM3_DRIVE_WEAK (2<<30) +#define CFG_REGS_SIM3_DRIVE_MOST_WEAK (3<<30) + +//IO_Drive2_Select +#define CFG_REGS_GPIO_DRIVE_MASK (3<<0) +#define CFG_REGS_GPIO_DRIVE_MOST_STRONG (0<<0) +#define CFG_REGS_GPIO_DRIVE_STRONG (1<<0) +#define CFG_REGS_GPIO_DRIVE_WEAK (2<<0) +#define CFG_REGS_GPIO_DRIVE_MOST_WEAK (3<<0) +#define CFG_REGS_CAM2_DRIVE_MASK (3<<2) +#define CFG_REGS_CAM2_DRIVE_MOST_STRONG (0<<2) +#define CFG_REGS_CAM2_DRIVE_STRONG (1<<2) +#define CFG_REGS_CAM2_DRIVE_WEAK (2<<2) +#define CFG_REGS_CAM2_DRIVE_MOST_WEAK (3<<2) + +//RAM_DRIVE +#define CFG_REGS_MBRAM_A(n) (((n)&7)<<0) +#define CFG_REGS_MBRAM_A_MASK (7<<0) +#define CFG_REGS_MBRAM_A_SHIFT (0) +#define CFG_REGS_MBRAM_W(n) (((n)&3)<<3) +#define CFG_REGS_MBRAM_W_MASK (3<<3) +#define CFG_REGS_MBRAM_W_SHIFT (3) +#define CFG_REGS_MBRAM_R (1<<5) +#define CFG_REGS_BBRAM_A(n) (((n)&7)<<6) +#define CFG_REGS_BBRAM_A_MASK (7<<6) +#define CFG_REGS_BBRAM_A_SHIFT (6) +#define CFG_REGS_BBRAM_W(n) (((n)&3)<<9) +#define CFG_REGS_BBRAM_W_MASK (3<<9) +#define CFG_REGS_BBRAM_W_SHIFT (9) +#define CFG_REGS_BBRAM_R (1<<11) +#define CFG_REGS_XP_A(n) (((n)&7)<<12) +#define CFG_REGS_XP_A_MASK (7<<12) +#define CFG_REGS_XP_A_SHIFT (12) +#define CFG_REGS_XP_W(n) (((n)&3)<<15) +#define CFG_REGS_XP_W_MASK (3<<15) +#define CFG_REGS_XP_W_SHIFT (15) +#define CFG_REGS_XP_R (1<<17) +#define CFG_REGS_BP_A(n) (((n)&7)<<18) +#define CFG_REGS_BP_A_MASK (7<<18) +#define CFG_REGS_BP_A_SHIFT (18) +#define CFG_REGS_BP_W(n) (((n)&3)<<21) +#define CFG_REGS_BP_W_MASK (3<<21) +#define CFG_REGS_BP_W_SHIFT (21) +#define CFG_REGS_BP_R (1<<23) +#define CFG_REGS_EV_A(n) (((n)&7)<<24) +#define CFG_REGS_EV_A_MASK (7<<24) +#define CFG_REGS_EV_A_SHIFT (24) +#define CFG_REGS_EV_W(n) (((n)&3)<<27) +#define CFG_REGS_EV_W_MASK (3<<27) +#define CFG_REGS_EV_W_SHIFT (27) +#define CFG_REGS_EV_R (1<<29) + +//H2X_AP_Offset +#define CFG_REGS_H2X_AP_OFFSET(n) (((n)&0xFF)<<0) +#define CFG_REGS_H2X_AP_OFFSET_MASK (0xFF<<0) +#define CFG_REGS_H2X_AP_OFFSET_SHIFT (0) + +//H2X_DDR_Offset +#define CFG_REGS_H2X_DDR_OFFSET(n) (((n)&0xFF)<<0) +#define CFG_REGS_H2X_DDR_OFFSET_MASK (0xFF<<0) +#define CFG_REGS_H2X_DDR_OFFSET_SHIFT (0) + +//audio_pd_set +#define CFG_REGS_AU_DEEP_PD_N (1<<0) +#define CFG_REGS_AU_REF_PD_N (1<<1) +#define CFG_REGS_AU_MIC_PD_N (1<<2) +#define CFG_REGS_AU_AUXMIC_PD_N (1<<3) +#define CFG_REGS_AU_AD_PD_N (1<<4) +#define CFG_REGS_AU_DAC_PD_N (1<<5) +#define CFG_REGS_AU_DAC_RESET_N (1<<8) +#define CFG_REGS_AU_PLL_PU (1<<16) + +//audio_pd_clr +//#define CFG_REGS_AU_DEEP_PD_N (1<<0) +//#define CFG_REGS_AU_REF_PD_N (1<<1) +//#define CFG_REGS_AU_MIC_PD_N (1<<2) +//#define CFG_REGS_AU_AUXMIC_PD_N (1<<3) +//#define CFG_REGS_AU_AD_PD_N (1<<4) +//#define CFG_REGS_AU_DAC_PD_N (1<<5) +//#define CFG_REGS_AU_DAC_RESET_N (1<<8) +//#define CFG_REGS_AU_PLL_PU (1<<16) + +//audio_sel_cfg +#define CFG_REGS_AU_AUXMIC_SEL (1<<0) +#define CFG_REGS_AU_SPK_SEL (1<<1) +#define CFG_REGS_AU_SPK_MONO_SEL (1<<2) +#define CFG_REGS_AU_RCV_SEL (1<<3) +#define CFG_REGS_AU_HEAD_SEL (1<<4) + +//audio_mic_cfg +#define CFG_REGS_AU_MIC_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_MIC_GAIN_MASK (15<<0) +#define CFG_REGS_AU_MIC_GAIN_SHIFT (0) +#define CFG_REGS_AU_MIC_MUTE_N (1<<4) + +//audio_spk_cfg +#define CFG_REGS_AU_SPK_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_SPK_GAIN_MASK (15<<0) +#define CFG_REGS_AU_SPK_GAIN_SHIFT (0) +#define CFG_REGS_AU_SPK_MUTE_N (1<<4) +#define CFG_REGS_AU_SPK_VOC_GAIN_EN (1<<8) + +//audio_rcv_gain +#define CFG_REGS_AU_RCV_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_RCV_GAIN_MASK (15<<0) +#define CFG_REGS_AU_RCV_GAIN_SHIFT (0) +#define CFG_REGS_AU_RCV_VOC_GAIN_EN (1<<8) + +//audio_head_gain +#define CFG_REGS_AU_HEAD_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_HEAD_GAIN_MASK (15<<0) +#define CFG_REGS_AU_HEAD_GAIN_SHIFT (0) +#define CFG_REGS_AU_HEAD_VOC_GAIN_EN (1<<8) + +//TSC_DATA +#define CFG_REGS_TSC_X_VALUE_BIT(n) (((n)&0x3FF)<<0) +#define CFG_REGS_TSC_X_VALUE_BIT_MASK (0x3FF<<0) +#define CFG_REGS_TSC_X_VALUE_BIT_SHIFT (0) +#define CFG_REGS_TSC_X_VALUE_VALID (1<<10) +#define CFG_REGS_TSC_Y_VALUE_BIT(n) (((n)&0x3FF)<<11) +#define CFG_REGS_TSC_Y_VALUE_BIT_MASK (0x3FF<<11) +#define CFG_REGS_TSC_Y_VALUE_BIT_SHIFT (11) +#define CFG_REGS_TSC_Y_VALUE_VALID (1<<21) + +//GPADC_DATA_CH +#define CFG_REGS_GPADC_DATA(n) (((n)&0x3FF)<<0) +#define CFG_REGS_GPADC_DATA_MASK (0x3FF<<0) +#define CFG_REGS_GPADC_DATA_SHIFT (0) +#define CFG_REGS_GPADC_VALID (1<<10) +#define CFG_REGS_GPADC_CH_EN (1<<31) + +//Alt_mux_select2 +#define CFG_REGS_UART1_SDIO2_MASK (1<<0) +#define CFG_REGS_UART1_SDIO2_SDIO2 (0<<0) +#define CFG_REGS_UART1_SDIO2_UART1 (1<<0) +#define CFG_REGS_JTAG_EN_MASK (1<<1) +#define CFG_REGS_JTAG_EN_DISABLE (0<<1) +#define CFG_REGS_JTAG_EN_ENABLE (1<<1) +#define CFG_REGS_LCD_RGB_17_16_MASK (1<<2) +#define CFG_REGS_LCD_RGB_17_16_LCD_CS (0<<2) +#define CFG_REGS_LCD_RGB_17_16_LCD_DATA (1<<2) +#define CFG_REGS_CSI2_2_MASK (3<<3) +#define CFG_REGS_CSI2_2_PARALLEL_CAM (0<<3) +#define CFG_REGS_CSI2_2_CSI2 (1<<3) +#define CFG_REGS_CSI2_2_SPI_CAM (2<<3) +#define CFG_REGS_RGB_CAM_2_MASK (1<<5) +#define CFG_REGS_RGB_CAM_2_DISABLE (0<<5) +#define CFG_REGS_RGB_CAM_2_ENABLE (1<<5) +#define CFG_REGS_MAC_EN_MASK (1<<6) +#define CFG_REGS_MAC_EN_DISABLE (0<<6) +#define CFG_REGS_MAC_EN_ENABLE (1<<6) +#define CFG_REGS_IOMUX_CFG_RESERVED(n) (((n)&0x1FFFFFF)<<7) + +//AP_GPIO_E_Mode +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST (1<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN (1<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK (1<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC (1<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF (1<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK (1<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0 (1<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1 (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2 (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3 (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4 (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5 (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6 (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7 (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_GPIO (1<<15) +#define CFG_REGS_AP_GPIO_E_MODE(n) (((n)&0xFFFF)<<0) +#define CFG_REGS_AP_GPIO_E_MODE_MASK (0xFFFF<<0) +#define CFG_REGS_AP_GPIO_E_MODE_SHIFT (0) + + + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8820.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8820.h new file mode 100644 index 0000000000..3ff671b6fd --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8820.h @@ -0,0 +1,1300 @@ +//============================================================================== +// +// Copyright (C) 2012-2014, RDA Microelectronics. +// All Rights Reserved +// +// This source code is the property of RDA Microelectronics and is +// confidential. Any modification, distribution, reproduction or +// exploitation of any content of this file is totally forbidden, +// except with the written permission of RDA Microelectronics. +// +//============================================================================== +// +// THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML. +// +// !!! PLEASE DO NOT EDIT !!! +// +// $HeadURL$ +// $Author$ +// $Date$ +// $Revision$ +// +//============================================================================== +// +/// @file +// +//============================================================================== + +#ifndef _CFG_REGS_H_ +#define _CFG_REGS_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +#ifdef CT_ASM +#error "You are trying to use in an assembly code the normal H description of 'cfg_regs'." +#endif + + + +// ============================================================================= +// MACROS +// ============================================================================= +#define PROD_ID (0X810E) + +// ============================================================================ +// BB_GPIO_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// BB GPIO Map + BB_PIN_NONE_0 = 0x00000000, + BB_PIN_1 = 0x00000001, + BB_PIN_2 = 0x00000002, + BB_PIN_3 = 0x00000003, + BB_PIN_4 = 0x00000004, + BB_PIN_5 = 0x00000005, + BB_PIN_UART1_RXD = 0x00000006, + BB_PIN_UART2_RXD = 0x00000007, + BB_PIN_UART2_TXD = 0x00000008, + BB_PIN_SSD1_CLK = 0x00000009, + BB_PIN_SSD1_CMD = 0x0000000A, + BB_PIN_SDAT1_0 = 0x0000000B, + BB_PIN_SDAT1_1 = 0x0000000C, + BB_PIN_SDAT1_2 = 0x0000000D, + BB_PIN_SDAT1_3 = 0x0000000E, + BB_PIN_SSD2_CLK = 0x0000000F, + BB_PIN_SSD2_CMD = 0x00000010, + BB_PIN_SDAT2_0 = 0x00000011, + BB_PIN_SDAT2_1 = 0x00000012, + BB_PIN_SDAT2_2 = 0x00000013, + BB_PIN_SDAT2_3 = 0x00000014, + BB_PIN_SPI1_CLK = 0x00000015, + BB_PIN_SPI1_CS_0 = 0x00000016, + BB_PIN_SPI1_DIO = 0x00000017, + BB_PIN_SPI1_DI = 0x00000018, + BB_PIN_SIM2_RST = 0x00000019, + BB_PIN_SIM2_CLK = 0x0000001A, + BB_PIN_SIM2_DIO = 0x0000001B, + BB_PIN_SIM3_RST = 0x0000001C, + BB_PIN_SIM3_CLK = 0x0000001D, + BB_PIN_SIM3_DIO = 0x0000001E +} BB_GPIO_MAPPING_T; + +#define BB_GPIO_NB (31) + +// ============================================================================ +// AP_GPIO_A_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO A Map + AP_PIN_I2C2_SCL = 0x00000000, + AP_PIN_I2C2_SDA = 0x00000001, + AP_PIN_SPI2_CLK = 0x00000002, + AP_PIN_SPI2_DIO = 0x00000003, + AP_PIN_SPI2_DI = 0x00000004, + AP_PIN_SPI2_CS_0 = 0x00000005, + AP_PIN_SPI2_CS_1 = 0x00000006, + AP_PIN_KEYIN_4 = 0x00000007, + AP_PIN_CLK_OUT = 0x00000008, + AP_PIN_I2S_BCK = 0x00000009, + AP_PIN_I2S_LRCK = 0x0000000A, + AP_PIN_I2S_DI_0 = 0x0000000B, + AP_PIN_I2S_DI_1 = 0x0000000C, + AP_PIN_I2S_DO = 0x0000000D, + AP_PIN_UART1_TXD = 0x0000000E, + AP_PIN_UART1_CTS = 0x0000000F, + AP_PIN_UART1_RTS = 0x00000010, + AP_PIN_SPI1_CS_1 = 0x00000011, + AP_PIN_LCD_DATA_6 = 0x00000012, + AP_PIN_LCD_DATA_7 = 0x00000013, + AP_PIN_LCD_WR = 0x00000014, + AP_PIN_LCD_RS = 0x00000015, + AP_PIN_LCD_RD = 0x00000016, + AP_PIN_LCD_FMARK = 0x00000017, + AP_PIN_LCD_DATA_8 = 0x00000018, + AP_PIN_LCD_DATA_9 = 0x00000019, + AP_PIN_LCD_DATA_10 = 0x0000001A, + AP_PIN_LCD_DATA_11 = 0x0000001B, + AP_PIN_LCD_DATA_12 = 0x0000001C, + AP_PIN_LCD_DATA_13 = 0x0000001D, + AP_PIN_LCD_DATA_14 = 0x0000001E, + AP_PIN_LCD_DATA_15 = 0x0000001F +} AP_GPIO_A_MAPPING_T; + +#define AP_GPIO_A_NB (32) + +// ============================================================================ +// AP_GPIO_B_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO B Map + AP_PIN_KEYIN_0 = 0x00000000, + AP_PIN_KEYIN_1 = 0x00000001, + AP_PIN_KEYIN_2 = 0x00000002, + AP_PIN_KEYOUT_0 = 0x00000003, + AP_PIN_KEYOUT_1 = 0x00000004, + AP_PIN_KEYOUT_2 = 0x00000005, + AP_PIN_I2C3_SCL = 0x00000006, + AP_PIN_I2C3_SDA = 0x00000007, + AP_PIN_UART2_CTS = 0x00000008, + AP_PIN_UART2_RTS = 0x00000009, + AP_PIN_CAM_RST = 0x0000000A, + AP_PIN_CAM_PDN = 0x0000000B, + AP_PIN_CAM_CLK = 0x0000000C, + AP_PIN_CAM_VSYNC = 0x0000000D, + AP_PIN_CAM_HREF = 0x0000000E, + AP_PIN_CAM_PCLK = 0x0000000F, + AP_PIN_CAM_DATA_0 = 0x00000010, + AP_PIN_CAM_DATA_1 = 0x00000011, + AP_PIN_CAM_DATA_2 = 0x00000012, + AP_PIN_CAM_DATA_3 = 0x00000013, + AP_PIN_CAM_DATA_4 = 0x00000014, + AP_PIN_CAM_DATA_5 = 0x00000015, + AP_PIN_CAM_DATA_6 = 0x00000016, + AP_PIN_CAM_DATA_7 = 0x00000017, + AP_PIN_M_SPI_CS_0 = 0x00000018, + AP_PIN_NFCLE = 0x00000019, + AP_PIN_NFWEN = 0x0000001A, + AP_PIN_NFWPN = 0x0000001B, + AP_PIN_NFREN = 0x0000001C, + AP_PIN_NFRB = 0x0000001D, + AP_PIN_I2C1_SCL = 0x0000001E, + AP_PIN_I2C1_SDA = 0x0000001F +} AP_GPIO_B_MAPPING_T; + +#define AP_GPIO_B_NB (32) + +// ============================================================================ +// AP_GPIO_D_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO D Map + AP_PIN_UART3_RXD = 0x00000000, + AP_PIN_UART3_TXD = 0x00000001, + AP_PIN_UART3_CTS = 0x00000002, + AP_PIN_UART3_RTS = 0x00000003, + AP_PIN_NFDQS = 0x00000004, + AP_PIN_VOLUME_DN = 0x00000005, + AP_PIN_VOLUME_UP = 0x00000006, + AP_PIN_PLUGIN = 0x00000007, + AP_PIN_NFCEN_1 = 0x00000008, + AP_PIN_NFCEN_2 = 0x00000009, + AP_PIN_NFCEN_3 = 0x0000000A, + AP_PIN_I2S2_BCK = 0x0000000B, + AP_PIN_I2S2_LRCK = 0x0000000C, + AP_PIN_I2S2_DI_0 = 0x0000000D, + AP_PIN_I2S2_DI_1 = 0x0000000E, + AP_PIN_I2S2_DO = 0x0000000F +} AP_GPIO_D_MAPPING_T; + +#define AP_GPIO_D_NB (16) + +// ============================================================================ +// AP_GPIO_E_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO E Map + AP_PIN_I2CBB_SCL = 0x00000000, + AP_PIN_I2CBB_SDA = 0x00000001, + AP_PIN_CAM2_RST = 0x00000002, + AP_PIN_CAM2_PDN = 0x00000003, + AP_PIN_CAM2_CLK = 0x00000004, + AP_PIN_CAM2_VSYNC = 0x00000005, + AP_PIN_CAM2_HREF = 0x00000006, + AP_PIN_CAM2_PCLK = 0x00000007, + AP_PIN_CAM2_DATA_0 = 0x00000008, + AP_PIN_CAM2_DATA_1 = 0x00000009, + AP_PIN_CAM2_DATA_2 = 0x0000000A, + AP_PIN_CAM2_DATA_3 = 0x0000000B, + AP_PIN_CAM2_DATA_4 = 0x0000000C, + AP_PIN_CAM2_DATA_5 = 0x0000000D, + AP_PIN_CAM2_DATA_6 = 0x0000000E, + AP_PIN_CAM2_DATA_7 = 0x0000000F +} AP_GPIO_E_MAPPING_T; + +#define AP_GPIO_E_NB (16) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// CFG_REGS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + REG32 CHIP_ID; //0x00000000 + /// This register contain the synthesis date and version + REG32 Build_Version; //0x00000004 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 BB_GPIO_Mode; //0x00000008 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_A_Mode; //0x0000000C + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_B_Mode; //0x00000010 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_D_Mode; //0x00000014 + REG32 Alt_mux_select; //0x00000018 + REG32 IO_Drive1_Select; //0x0000001C + REG32 IO_Drive2_Select; //0x00000020 + REG32 RAM_DRIVE; //0x00000024 + REG32 H2X_AP_Offset; //0x00000028 + REG32 H2X_DDR_Offset; //0x0000002C + REG32 audio_pd_set; //0x00000030 + REG32 audio_pd_clr; //0x00000034 + REG32 audio_sel_cfg; //0x00000038 + REG32 audio_mic_cfg; //0x0000003C + REG32 audio_spk_cfg; //0x00000040 + REG32 audio_rcv_gain; //0x00000044 + REG32 audio_head_gain; //0x00000048 + REG32 TSC_DATA; //0x0000004C + REG32 GPADC_DATA_CH[8]; //0x00000050 + REG32 Alt_mux_select2; //0x00000070 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_E_Mode; //0x00000074 +} HWP_CFG_REGS_T; + +#define hwp_configRegs ((HWP_CFG_REGS_T*)(RDA_CFG_REGS_BASE)) + + +//CHIP_ID +#define CFG_REGS_METAL_ID(n) (((n)&0xFFF)<<0) +#define CFG_REGS_METAL_ID_MASK (0xFFF<<0) +#define CFG_REGS_METAL_ID_SHIFT (0) +#define CFG_REGS_BOND_ID(n) (((n)&7)<<12) +#define CFG_REGS_BOND_ID_MASK (7<<12) +#define CFG_REGS_BOND_ID_SHIFT (12) +#define CFG_REGS_PROD_ID(n) (((n)&0xFFFF)<<16) +#define CFG_REGS_PROD_ID_MASK (0xFFFF<<16) +#define CFG_REGS_PROD_ID_SHIFT (16) + +//Build_Version +#define CFG_REGS_MAJOR(n) (((n)&15)<<28) +#define CFG_REGS_YEAR(n) (((n)&15)<<24) +#define CFG_REGS_MONTH(n) (((n)&0xFF)<<16) +#define CFG_REGS_DAY(n) (((n)&0xFF)<<8) +#define CFG_REGS_BUILD_STYLE_FPGA (0<<4) +#define CFG_REGS_BUILD_STYLE_CHIP (1<<4) +#define CFG_REGS_BUILD_STYLE_FPGA_USB (2<<4) +#define CFG_REGS_BUILD_STYLE_FPGA_GSM (3<<4) +#define CFG_REGS_BUILD_REVISION(n) (((n)&15)<<0) + +//BB_GPIO_Mode +#define CFG_REGS_MODE_BB_PIN_NONE_0 (1<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_MASK (1<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_SHIFT (0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_ALT (0<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_GPIO (1<<0) +#define CFG_REGS_MODE_BB_PIN_1 (1<<1) +#define CFG_REGS_MODE_BB_PIN_1_MASK (1<<1) +#define CFG_REGS_MODE_BB_PIN_1_SHIFT (1) +#define CFG_REGS_MODE_BB_PIN_1_ALT (0<<1) +#define CFG_REGS_MODE_BB_PIN_1_GPIO (1<<1) +#define CFG_REGS_MODE_BB_PIN_2 (1<<2) +#define CFG_REGS_MODE_BB_PIN_2_MASK (1<<2) +#define CFG_REGS_MODE_BB_PIN_2_SHIFT (2) +#define CFG_REGS_MODE_BB_PIN_2_ALT (0<<2) +#define CFG_REGS_MODE_BB_PIN_2_GPIO (1<<2) +#define CFG_REGS_MODE_BB_PIN_3 (1<<3) +#define CFG_REGS_MODE_BB_PIN_3_MASK (1<<3) +#define CFG_REGS_MODE_BB_PIN_3_SHIFT (3) +#define CFG_REGS_MODE_BB_PIN_3_ALT (0<<3) +#define CFG_REGS_MODE_BB_PIN_3_GPIO (1<<3) +#define CFG_REGS_MODE_BB_PIN_4 (1<<4) +#define CFG_REGS_MODE_BB_PIN_4_MASK (1<<4) +#define CFG_REGS_MODE_BB_PIN_4_SHIFT (4) +#define CFG_REGS_MODE_BB_PIN_4_ALT (0<<4) +#define CFG_REGS_MODE_BB_PIN_4_GPIO (1<<4) +#define CFG_REGS_MODE_BB_PIN_5 (1<<5) +#define CFG_REGS_MODE_BB_PIN_5_MASK (1<<5) +#define CFG_REGS_MODE_BB_PIN_5_SHIFT (5) +#define CFG_REGS_MODE_BB_PIN_5_ALT (0<<5) +#define CFG_REGS_MODE_BB_PIN_5_GPIO (1<<5) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_MASK (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_SHIFT (6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_ALT (0<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_GPIO (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_MASK (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_SHIFT (7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_ALT (0<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_GPIO (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD (1<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_MASK (1<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_SHIFT (8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_ALT (0<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_GPIO (1<<8) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_MASK (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_SHIFT (9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_ALT (0<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_GPIO (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD (1<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_MASK (1<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_SHIFT (10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_ALT (0<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_GPIO (1<<10) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0 (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_MASK (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_SHIFT (11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_ALT (0<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_GPIO (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1 (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_MASK (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_SHIFT (12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_ALT (0<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_GPIO (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2 (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_MASK (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_SHIFT (13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_ALT (0<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_GPIO (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3 (1<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_MASK (1<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_SHIFT (14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_ALT (0<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_GPIO (1<<14) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_MASK (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_SHIFT (15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_ALT (0<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_GPIO (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD (1<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_MASK (1<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_SHIFT (16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_ALT (0<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_GPIO (1<<16) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0 (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_MASK (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_SHIFT (17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_ALT (0<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_GPIO (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1 (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_MASK (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_SHIFT (18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_ALT (0<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_GPIO (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2 (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_MASK (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_SHIFT (19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_ALT (0<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_GPIO (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3 (1<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_MASK (1<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_SHIFT (20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_ALT (0<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_GPIO (1<<20) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_MASK (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_SHIFT (21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_ALT (0<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_GPIO (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0 (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_MASK (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_SHIFT (22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_ALT (0<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_GPIO (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_MASK (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_SHIFT (23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_ALT (0<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_GPIO (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI (1<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_MASK (1<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_SHIFT (24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_ALT (0<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_GPIO (1<<24) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_MASK (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_SHIFT (25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_ALT (0<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_GPIO (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_MASK (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_SHIFT (26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_ALT (0<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_GPIO (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_MASK (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_SHIFT (27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_ALT (0<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_GPIO (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_MASK (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_SHIFT (28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_ALT (0<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_GPIO (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_MASK (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_SHIFT (29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_ALT (0<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_GPIO (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO (1<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_MASK (1<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_SHIFT (30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_ALT (0<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_GPIO (1<<30) +#define CFG_REGS_BB_GPIO_MODE(n) (((n)&0x7FFFFFFF)<<0) +#define CFG_REGS_BB_GPIO_MODE_MASK (0x7FFFFFFF<<0) +#define CFG_REGS_BB_GPIO_MODE_SHIFT (0) + +//AP_GPIO_A_Mode +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0 (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1 (1<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4 (1<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT (1<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0 (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1 (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DO (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_GPIO (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS (1<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_MASK (1<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_SHIFT (16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_ALT (0<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_GPIO (1<<16) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1 (1<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_MASK (1<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_SHIFT (17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_ALT (0<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_GPIO (1<<17) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6 (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_MASK (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_SHIFT (18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_ALT (0<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_GPIO (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7 (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_MASK (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_SHIFT (19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_ALT (0<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_GPIO (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_WR (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_MASK (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_SHIFT (20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_ALT (0<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_GPIO (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_RS (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_MASK (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_SHIFT (21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_ALT (0<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_GPIO (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RD (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_MASK (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_SHIFT (22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_ALT (0<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_GPIO (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_MASK (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_SHIFT (23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_ALT (0<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_GPIO (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8 (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_MASK (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_SHIFT (24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_ALT (0<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_GPIO (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9 (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_MASK (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_SHIFT (25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_ALT (0<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_GPIO (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10 (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_MASK (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_SHIFT (26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_ALT (0<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_GPIO (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11 (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_MASK (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_SHIFT (27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_ALT (0<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_GPIO (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12 (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_MASK (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_SHIFT (28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_ALT (0<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_GPIO (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13 (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_MASK (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_SHIFT (29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_ALT (0<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_GPIO (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14 (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_MASK (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_SHIFT (30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_ALT (0<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_GPIO (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15 (1<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_MASK (1<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_SHIFT (31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_ALT (0<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_GPIO (1<<31) +#define CFG_REGS_AP_GPIO_A_MODE(n) (((n)&0xFFFFFFFF)<<0) +#define CFG_REGS_AP_GPIO_A_MODE_MASK (0xFFFFFFFF<<0) +#define CFG_REGS_AP_GPIO_A_MODE_SHIFT (0) + +//AP_GPIO_B_Mode +#define CFG_REGS_MODE_AP_PIN_KEYIN_0 (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1 (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2 (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0 (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1 (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2 (1<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA (1<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS (1<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM_RST (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_GPIO (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0 (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_MASK (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_SHIFT (16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_ALT (0<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_GPIO (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1 (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_MASK (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_SHIFT (17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_ALT (0<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_GPIO (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2 (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_MASK (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_SHIFT (18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_ALT (0<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_GPIO (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3 (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_MASK (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_SHIFT (19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_ALT (0<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_GPIO (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4 (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_MASK (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_SHIFT (20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_ALT (0<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_GPIO (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5 (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_MASK (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_SHIFT (21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_ALT (0<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_GPIO (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6 (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_MASK (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_SHIFT (22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_ALT (0<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_GPIO (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7 (1<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_MASK (1<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_SHIFT (23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_ALT (0<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_GPIO (1<<23) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0 (1<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_MASK (1<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_SHIFT (24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_ALT (0<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_GPIO (1<<24) +#define CFG_REGS_MODE_AP_PIN_NFCLE (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_MASK (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_SHIFT (25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_ALT (0<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_GPIO (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFWEN (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_MASK (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_SHIFT (26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_ALT (0<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_GPIO (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWPN (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_MASK (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_SHIFT (27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_ALT (0<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_GPIO (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFREN (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_MASK (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_SHIFT (28) +#define CFG_REGS_MODE_AP_PIN_NFREN_ALT (0<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_GPIO (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFRB (1<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_MASK (1<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_SHIFT (29) +#define CFG_REGS_MODE_AP_PIN_NFRB_ALT (0<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_GPIO (1<<29) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_MASK (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_SHIFT (30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_ALT (0<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_GPIO (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA (1<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_MASK (1<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_SHIFT (31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_ALT (0<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_GPIO (1<<31) +#define CFG_REGS_AP_GPIO_B_MODE(n) (((n)&0xFFFFFFFF)<<0) +#define CFG_REGS_AP_GPIO_B_MODE_MASK (0xFFFFFFFF<<0) +#define CFG_REGS_AP_GPIO_B_MODE_SHIFT (0) + +//AP_GPIO_D_Mode +#define CFG_REGS_MODE_AP_PIN_UART3_RXD (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS (1<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_NFDQS (1<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN (1<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP (1<<6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_PLUGIN (1<<7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1 (1<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2 (1<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3 (1<<10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0 (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1 (1<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO (1<<15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_GPIO (1<<15) +#define CFG_REGS_AP_GPIO_D_MODE(n) (((n)&0xFFFF)<<0) +#define CFG_REGS_AP_GPIO_D_MODE_MASK (0xFFFF<<0) +#define CFG_REGS_AP_GPIO_D_MODE_SHIFT (0) + +//Alt_mux_select +#define CFG_REGS_LCD_MODE_MASK (3<<0) +#define CFG_REGS_LCD_MODE_PARALLEL_16BIT (0<<0) +#define CFG_REGS_LCD_MODE_DSI (1<<0) +#define CFG_REGS_LCD_MODE_RGB_24BIT (2<<0) +#define CFG_REGS_LCD_MODE_RGB_16BIT (3<<0) +#define CFG_REGS_SPI_LCD_MASK (1<<2) +#define CFG_REGS_SPI_LCD_NONE (0<<2) +#define CFG_REGS_SPI_LCD_SPI_LCD (1<<2) +#define CFG_REGS_CAM_I2C2_MASK (1<<3) +#define CFG_REGS_CAM_I2C2_CAM (0<<3) +#define CFG_REGS_CAM_I2C2_I2C2 (1<<3) +#define CFG_REGS_CSI2_MASK (3<<4) +#define CFG_REGS_CSI2_PARALLEL_CAM (0<<4) +#define CFG_REGS_CSI2_CSI2 (1<<4) +#define CFG_REGS_CSI2_SPI_CAM (2<<4) +#define CFG_REGS_UART2_MASK (1<<6) +#define CFG_REGS_UART2_HOST_UART (0<<6) +#define CFG_REGS_UART2_UART2 (1<<6) +#define CFG_REGS_UART1_8LINE_MASK (1<<7) +#define CFG_REGS_UART1_8LINE_UART2 (0<<7) +#define CFG_REGS_UART1_8LINE_UART1_8_LINE (1<<7) +#define CFG_REGS_DAI_MASK (3<<8) +#define CFG_REGS_DAI_I2S (0<<8) +#define CFG_REGS_DAI_DAI (1<<8) +#define CFG_REGS_DAI_DAI_SIMPLE (2<<8) +#define CFG_REGS_KEYIN_3_MASK (1<<10) +#define CFG_REGS_KEYIN_3_SPI2_CS_1 (0<<10) +#define CFG_REGS_KEYIN_3_KEYIN_3 (1<<10) +#define CFG_REGS_LPSCO_1_MASK (1<<11) +#define CFG_REGS_LPSCO_1_KEYIN_4 (0<<11) +#define CFG_REGS_LPSCO_1_LPSCO_1 (1<<11) +#define CFG_REGS_SPI1_CS_2_MASK (1<<12) +#define CFG_REGS_SPI1_CS_2_KEYIN_1 (0<<12) +#define CFG_REGS_SPI1_CS_2_SPI1_CS_2 (1<<12) +#define CFG_REGS_I2S_DI_2_MASK (1<<13) +#define CFG_REGS_I2S_DI_2_KEYIN_2 (0<<13) +#define CFG_REGS_I2S_DI_2_I2S_DI_2 (1<<13) +#define CFG_REGS_TCO_0_MASK (1<<14) +#define CFG_REGS_TCO_0_KEYOUT_0 (0<<14) +#define CFG_REGS_TCO_0_TCO_0 (1<<14) +#define CFG_REGS_TCO_1_MASK (1<<15) +#define CFG_REGS_TCO_1_KEYOUT_1 (0<<15) +#define CFG_REGS_TCO_1_TCO_1 (1<<15) +#define CFG_REGS_TCO_2_MASK (1<<16) +#define CFG_REGS_TCO_2_KEYOUT_2 (0<<16) +#define CFG_REGS_TCO_2_TCO_2 (1<<16) +#define CFG_REGS_KEYOUT_3_4_MASK (1<<17) +#define CFG_REGS_KEYOUT_3_4_I2C3 (0<<17) +#define CFG_REGS_KEYOUT_3_4_KEYOUT_3_4 (1<<17) +#define CFG_REGS_KEYOUT_6_MASK (1<<18) +#define CFG_REGS_KEYOUT_6_UART2_RTS (0<<18) +#define CFG_REGS_KEYOUT_6_KEYOUT_6 (1<<18) +#define CFG_REGS_KEYOUT_7_MASK (1<<19) +#define CFG_REGS_KEYOUT_7_UART1_RTS (0<<19) +#define CFG_REGS_KEYOUT_7_KEYOUT_7 (1<<19) +#define CFG_REGS_GPO_0_MASK (3<<20) +#define CFG_REGS_GPO_0_GPO_0 (0<<20) +#define CFG_REGS_GPO_0_PWT (1<<20) +#define CFG_REGS_GPO_0_KEYIN_5 (2<<20) +#define CFG_REGS_GPO_1_MASK (3<<22) +#define CFG_REGS_GPO_1_GPO_1 (0<<22) +#define CFG_REGS_GPO_1_LPG (1<<22) +#define CFG_REGS_GPO_1_KEYOUT_5 (2<<22) +#define CFG_REGS_GPO_2_MASK (3<<24) +#define CFG_REGS_GPO_2_GPO_2 (0<<24) +#define CFG_REGS_GPO_2_PWL_1 (1<<24) +#define CFG_REGS_GPO_2_CLK_32K (2<<24) +#define CFG_REGS_GPO_3_MASK (1<<26) +#define CFG_REGS_GPO_3_LCD_CS_1 (0<<26) +#define CFG_REGS_GPO_3_GPO_3 (1<<26) +#define CFG_REGS_GPO_4_MASK (1<<27) +#define CFG_REGS_GPO_4_LCD_CS_0 (0<<27) +#define CFG_REGS_GPO_4_GPO_4 (1<<27) +#define CFG_REGS_CLK_OUT_MASK (1<<28) +#define CFG_REGS_CLK_OUT_HST_CLK (0<<28) +#define CFG_REGS_CLK_OUT_CLK_OUT (1<<28) +#define CFG_REGS_DEBUG_MASK (1<<29) +#define CFG_REGS_DEBUG_NONE (0<<29) +#define CFG_REGS_DEBUG_DEBUG_MONITOR (1<<29) +#define CFG_REGS_AP_SPI1_MASK (1<<30) +#define CFG_REGS_AP_SPI1_BB_SPI1 (0<<30) +#define CFG_REGS_AP_SPI1_AP_SPI1 (1<<30) +#define CFG_REGS_RGB_CAM_MASK (1<<31) +#define CFG_REGS_RGB_CAM_DISABLE (0<<31) +#define CFG_REGS_RGB_CAM_ENABLE (1<<31) + +//IO_Drive1_Select +#define CFG_REGS_DDR_DRIVE_MASK (7<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_WEAK (7<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_WEAK (6<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_STRONG (5<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_STRONG (4<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_WEAK (3<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_WEAK (2<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_STRONG (1<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_STRONG (0<<0) +#define CFG_REGS_PSRAM1_DRIVE_MASK (7<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_WEAK (7<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_WEAK (6<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_STRONG (5<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_STRONG (4<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_WEAK (3<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_WEAK (2<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_STRONG (1<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_STRONG (0<<3) +#define CFG_REGS_PSRAM2_DRIVE_MASK (7<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_WEAK (7<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_WEAK (6<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_STRONG (5<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_STRONG (4<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_WEAK (3<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_WEAK (2<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_STRONG (1<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_STRONG (0<<6) +#define CFG_REGS_NFLSH_DRIVE_MASK (7<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_WEAK (7<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_WEAK (6<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_STRONG (5<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_STRONG (4<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_WEAK (3<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK (2<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_STRONG (1<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_STRONG (0<<9) +#define CFG_REGS_LCD1_DRIVE_MASK (7<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_WEAK (7<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_WEAK (6<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_STRONG (5<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_STRONG (4<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_WEAK (3<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_WEAK (2<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_STRONG (1<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_STRONG (0<<12) +#define CFG_REGS_LCD2_DRIVE_MASK (7<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_WEAK (7<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_WEAK (6<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_STRONG (5<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_STRONG (4<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_WEAK (3<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_WEAK (2<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_STRONG (1<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_STRONG (0<<15) +#define CFG_REGS_SDAT1_DRIVE_MASK (7<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_WEAK (7<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_WEAK (6<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_STRONG (5<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_STRONG (4<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_WEAK (3<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_WEAK (2<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_STRONG (1<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_STRONG (0<<18) +#define CFG_REGS_SDAT2_DRIVE_MASK (7<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_WEAK (7<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_WEAK (6<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_STRONG (5<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_STRONG (4<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_WEAK (3<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_WEAK (2<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_STRONG (1<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_STRONG (0<<21) +#define CFG_REGS_CAM_DRIVE_MASK (3<<24) +#define CFG_REGS_CAM_DRIVE_MOST_STRONG (0<<24) +#define CFG_REGS_CAM_DRIVE_STRONG (1<<24) +#define CFG_REGS_CAM_DRIVE_WEAK (2<<24) +#define CFG_REGS_CAM_DRIVE_MOST_WEAK (3<<24) +#define CFG_REGS_SIM1_DRIVE_MASK (3<<26) +#define CFG_REGS_SIM1_DRIVE_MOST_STRONG (0<<26) +#define CFG_REGS_SIM1_DRIVE_STRONG (1<<26) +#define CFG_REGS_SIM1_DRIVE_WEAK (2<<26) +#define CFG_REGS_SIM1_DRIVE_MOST_WEAK (3<<26) +#define CFG_REGS_SIM2_DRIVE_MASK (3<<28) +#define CFG_REGS_SIM2_DRIVE_MOST_STRONG (0<<28) +#define CFG_REGS_SIM2_DRIVE_STRONG (1<<28) +#define CFG_REGS_SIM2_DRIVE_WEAK (2<<28) +#define CFG_REGS_SIM2_DRIVE_MOST_WEAK (3<<28) +#define CFG_REGS_SIM3_DRIVE_MASK (3<<30) +#define CFG_REGS_SIM3_DRIVE_MOST_STRONG (0<<30) +#define CFG_REGS_SIM3_DRIVE_STRONG (1<<30) +#define CFG_REGS_SIM3_DRIVE_WEAK (2<<30) +#define CFG_REGS_SIM3_DRIVE_MOST_WEAK (3<<30) + +//IO_Drive2_Select +#define CFG_REGS_GPIO_DRIVE_MASK (3<<0) +#define CFG_REGS_GPIO_DRIVE_MOST_STRONG (0<<0) +#define CFG_REGS_GPIO_DRIVE_STRONG (1<<0) +#define CFG_REGS_GPIO_DRIVE_WEAK (2<<0) +#define CFG_REGS_GPIO_DRIVE_MOST_WEAK (3<<0) +#define CFG_REGS_CAM2_DRIVE_MASK (3<<2) +#define CFG_REGS_CAM2_DRIVE_MOST_STRONG (0<<2) +#define CFG_REGS_CAM2_DRIVE_STRONG (1<<2) +#define CFG_REGS_CAM2_DRIVE_WEAK (2<<2) +#define CFG_REGS_CAM2_DRIVE_MOST_WEAK (3<<2) + +//RAM_DRIVE +#define CFG_REGS_MBRAM_A(n) (((n)&7)<<0) +#define CFG_REGS_MBRAM_A_MASK (7<<0) +#define CFG_REGS_MBRAM_A_SHIFT (0) +#define CFG_REGS_MBRAM_W(n) (((n)&3)<<3) +#define CFG_REGS_MBRAM_W_MASK (3<<3) +#define CFG_REGS_MBRAM_W_SHIFT (3) +#define CFG_REGS_MBRAM_R (1<<5) +#define CFG_REGS_BBRAM_A(n) (((n)&7)<<6) +#define CFG_REGS_BBRAM_A_MASK (7<<6) +#define CFG_REGS_BBRAM_A_SHIFT (6) +#define CFG_REGS_BBRAM_W(n) (((n)&3)<<9) +#define CFG_REGS_BBRAM_W_MASK (3<<9) +#define CFG_REGS_BBRAM_W_SHIFT (9) +#define CFG_REGS_BBRAM_R (1<<11) +#define CFG_REGS_XP_A(n) (((n)&7)<<12) +#define CFG_REGS_XP_A_MASK (7<<12) +#define CFG_REGS_XP_A_SHIFT (12) +#define CFG_REGS_XP_W(n) (((n)&3)<<15) +#define CFG_REGS_XP_W_MASK (3<<15) +#define CFG_REGS_XP_W_SHIFT (15) +#define CFG_REGS_XP_R (1<<17) +#define CFG_REGS_BP_A(n) (((n)&7)<<18) +#define CFG_REGS_BP_A_MASK (7<<18) +#define CFG_REGS_BP_A_SHIFT (18) +#define CFG_REGS_BP_W(n) (((n)&3)<<21) +#define CFG_REGS_BP_W_MASK (3<<21) +#define CFG_REGS_BP_W_SHIFT (21) +#define CFG_REGS_BP_R (1<<23) +#define CFG_REGS_EV_A(n) (((n)&7)<<24) +#define CFG_REGS_EV_A_MASK (7<<24) +#define CFG_REGS_EV_A_SHIFT (24) +#define CFG_REGS_EV_W(n) (((n)&3)<<27) +#define CFG_REGS_EV_W_MASK (3<<27) +#define CFG_REGS_EV_W_SHIFT (27) +#define CFG_REGS_EV_R (1<<29) + +//H2X_AP_Offset +#define CFG_REGS_H2X_AP_OFFSET(n) (((n)&0xFF)<<0) +#define CFG_REGS_H2X_AP_OFFSET_MASK (0xFF<<0) +#define CFG_REGS_H2X_AP_OFFSET_SHIFT (0) + +//H2X_DDR_Offset +#define CFG_REGS_H2X_DDR_OFFSET(n) (((n)&0xFF)<<0) +#define CFG_REGS_H2X_DDR_OFFSET_MASK (0xFF<<0) +#define CFG_REGS_H2X_DDR_OFFSET_SHIFT (0) + +//audio_pd_set +#define CFG_REGS_AU_DEEP_PD_N (1<<0) +#define CFG_REGS_AU_REF_PD_N (1<<1) +#define CFG_REGS_AU_MIC_PD_N (1<<2) +#define CFG_REGS_AU_AUXMIC_PD_N (1<<3) +#define CFG_REGS_AU_AD_PD_N (1<<4) +#define CFG_REGS_AU_DAC_PD_N (1<<5) +#define CFG_REGS_AU_DAC_RESET_N (1<<8) +#define CFG_REGS_AU_PLL_PU (1<<16) + +//audio_pd_clr +//#define CFG_REGS_AU_DEEP_PD_N (1<<0) +//#define CFG_REGS_AU_REF_PD_N (1<<1) +//#define CFG_REGS_AU_MIC_PD_N (1<<2) +//#define CFG_REGS_AU_AUXMIC_PD_N (1<<3) +//#define CFG_REGS_AU_AD_PD_N (1<<4) +//#define CFG_REGS_AU_DAC_PD_N (1<<5) +//#define CFG_REGS_AU_DAC_RESET_N (1<<8) +//#define CFG_REGS_AU_PLL_PU (1<<16) + +//audio_sel_cfg +#define CFG_REGS_AU_AUXMIC_SEL (1<<0) +#define CFG_REGS_AU_SPK_SEL (1<<1) +#define CFG_REGS_AU_SPK_MONO_SEL (1<<2) +#define CFG_REGS_AU_RCV_SEL (1<<3) +#define CFG_REGS_AU_HEAD_SEL (1<<4) + +//audio_mic_cfg +#define CFG_REGS_AU_MIC_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_MIC_GAIN_MASK (15<<0) +#define CFG_REGS_AU_MIC_GAIN_SHIFT (0) +#define CFG_REGS_AU_MIC_MUTE_N (1<<4) + +//audio_spk_cfg +#define CFG_REGS_AU_SPK_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_SPK_GAIN_MASK (15<<0) +#define CFG_REGS_AU_SPK_GAIN_SHIFT (0) +#define CFG_REGS_AU_SPK_MUTE_N (1<<4) +#define CFG_REGS_AU_SPK_VOC_GAIN_EN (1<<8) + +//audio_rcv_gain +#define CFG_REGS_AU_RCV_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_RCV_GAIN_MASK (15<<0) +#define CFG_REGS_AU_RCV_GAIN_SHIFT (0) +#define CFG_REGS_AU_RCV_VOC_GAIN_EN (1<<8) + +//audio_head_gain +#define CFG_REGS_AU_HEAD_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_HEAD_GAIN_MASK (15<<0) +#define CFG_REGS_AU_HEAD_GAIN_SHIFT (0) +#define CFG_REGS_AU_HEAD_VOC_GAIN_EN (1<<8) + +//TSC_DATA +#define CFG_REGS_TSC_X_VALUE_BIT(n) (((n)&0x3FF)<<0) +#define CFG_REGS_TSC_X_VALUE_BIT_MASK (0x3FF<<0) +#define CFG_REGS_TSC_X_VALUE_BIT_SHIFT (0) +#define CFG_REGS_TSC_X_VALUE_VALID (1<<10) +#define CFG_REGS_TSC_Y_VALUE_BIT(n) (((n)&0x3FF)<<11) +#define CFG_REGS_TSC_Y_VALUE_BIT_MASK (0x3FF<<11) +#define CFG_REGS_TSC_Y_VALUE_BIT_SHIFT (11) +#define CFG_REGS_TSC_Y_VALUE_VALID (1<<21) + +//GPADC_DATA_CH +#define CFG_REGS_GPADC_DATA(n) (((n)&0x3FF)<<0) +#define CFG_REGS_GPADC_DATA_MASK (0x3FF<<0) +#define CFG_REGS_GPADC_DATA_SHIFT (0) +#define CFG_REGS_GPADC_VALID (1<<10) +#define CFG_REGS_GPADC_CH_EN (1<<31) + +//Alt_mux_select2 +#define CFG_REGS_UART1_SDIO2_MASK (1<<0) +#define CFG_REGS_UART1_SDIO2_SDIO2 (0<<0) +#define CFG_REGS_UART1_SDIO2_UART1 (1<<0) +#define CFG_REGS_JTAG_EN_MASK (1<<1) +#define CFG_REGS_JTAG_EN_DISABLE (0<<1) +#define CFG_REGS_JTAG_EN_ENABLE (1<<1) +#define CFG_REGS_LCD_RGB_17_16_MASK (1<<2) +#define CFG_REGS_LCD_RGB_17_16_LCD_CS (0<<2) +#define CFG_REGS_LCD_RGB_17_16_LCD_DATA (1<<2) +#define CFG_REGS_CSI2_2_MASK (3<<3) +#define CFG_REGS_CSI2_2_PARALLEL_CAM (0<<3) +#define CFG_REGS_CSI2_2_CSI2 (1<<3) +#define CFG_REGS_CSI2_2_SPI_CAM (2<<3) +#define CFG_REGS_RGB_CAM_2_MASK (1<<5) +#define CFG_REGS_RGB_CAM_2_DISABLE (0<<5) +#define CFG_REGS_RGB_CAM_2_ENABLE (1<<5) +#define CFG_REGS_MAC_EN_MASK (1<<6) +#define CFG_REGS_MAC_EN_DISABLE (0<<6) +#define CFG_REGS_MAC_EN_ENABLE (1<<6) +#define CFG_REGS_IOMUX_CFG_RESERVED(n) (((n)&0x1FFFFFF)<<7) + +//AP_GPIO_E_Mode +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST (1<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN (1<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK (1<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC (1<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF (1<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK (1<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0 (1<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1 (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2 (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3 (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4 (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5 (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6 (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7 (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_GPIO (1<<15) +#define CFG_REGS_AP_GPIO_E_MODE(n) (((n)&0xFFFF)<<0) +#define CFG_REGS_AP_GPIO_E_MODE_MASK (0xFFFF<<0) +#define CFG_REGS_AP_GPIO_E_MODE_SHIFT (0) + + + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8850.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8850.h new file mode 100644 index 0000000000..046c2e872b --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8850.h @@ -0,0 +1,1254 @@ +#ifndef _CFG_REGS_H_
+#define _CFG_REGS_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+#ifdef CT_ASM
+#error "You are trying to use in an assembly code the normal H description of 'cfg_regs'."
+#endif
+
+
+
+// =============================================================================
+// MACROS
+// =============================================================================
+#define PROD_ID (0X8850)
+
+// ============================================================================
+// BB_GPIO_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// BB GPIO Map
+ BB_PIN_NONE_0 = 0x00000000,
+ BB_PIN_1 = 0x00000001,
+ BB_PIN_2 = 0x00000002,
+ BB_PIN_3 = 0x00000003,
+ BB_PIN_4 = 0x00000004,
+ BB_PIN_5 = 0x00000005,
+ BB_PIN_UART1_RXD = 0x00000006,
+ BB_PIN_UART2_RXD = 0x00000007,
+ BB_PIN_UART2_TXD = 0x00000008,
+ BB_PIN_SSD1_CLK = 0x00000009,
+ BB_PIN_SSD1_CMD = 0x0000000A,
+ BB_PIN_SDAT1_0 = 0x0000000B,
+ BB_PIN_SDAT1_1 = 0x0000000C,
+ BB_PIN_SDAT1_2 = 0x0000000D,
+ BB_PIN_SDAT1_3 = 0x0000000E,
+ BB_PIN_SSD2_CLK = 0x0000000F,
+ BB_PIN_SSD2_CMD = 0x00000010,
+ BB_PIN_SDAT2_0 = 0x00000011,
+ BB_PIN_SDAT2_1 = 0x00000012,
+ BB_PIN_SDAT2_2 = 0x00000013,
+ BB_PIN_SDAT2_3 = 0x00000014,
+ BB_PIN_SPI1_CLK = 0x00000015,
+ BB_PIN_SPI1_CS_0 = 0x00000016,
+ BB_PIN_SPI1_DIO = 0x00000017,
+ BB_PIN_SPI1_DI = 0x00000018,
+ BB_PIN_SIM2_RST = 0x00000019,
+ BB_PIN_SIM2_CLK = 0x0000001A,
+ BB_PIN_SIM2_DIO = 0x0000001B,
+ BB_PIN_SIM3_RST = 0x0000001C,
+ BB_PIN_SIM3_CLK = 0x0000001D,
+ BB_PIN_SIM3_DIO = 0x0000001E
+} BB_GPIO_MAPPING_T;
+
+#define BB_GPIO_NB (31)
+
+// ============================================================================
+// AP_GPIO_A_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO A Map
+ AP_PIN_I2C2_SCL = 0x00000000,
+ AP_PIN_I2C2_SDA = 0x00000001,
+ AP_PIN_SPI2_CLK = 0x00000002,
+ AP_PIN_SPI2_DIO = 0x00000003,
+ AP_PIN_SPI2_DI = 0x00000004,
+ AP_PIN_SPI2_CS_0 = 0x00000005,
+ AP_PIN_SPI2_CS_1 = 0x00000006,
+ AP_PIN_KEYIN_4 = 0x00000007,
+ AP_PIN_CLK_OUT = 0x00000008,
+ AP_PIN_I2S_BCK = 0x00000009,
+ AP_PIN_I2S_LRCK = 0x0000000A,
+ AP_PIN_I2S_DI_0 = 0x0000000B,
+ AP_PIN_I2S_DI_1 = 0x0000000C,
+ AP_PIN_I2S_DO = 0x0000000D,
+ AP_PIN_UART1_TXD = 0x0000000E,
+ AP_PIN_UART1_CTS = 0x0000000F,
+ AP_PIN_UART1_RTS = 0x00000010,
+ AP_PIN_SPI1_CS_1 = 0x00000011,
+ AP_PIN_LCD_WR = 0x00000012,
+ AP_PIN_LCD_RS = 0x00000013,
+ AP_PIN_LCD_RD = 0x00000014,
+ AP_PIN_LCD_FMARK = 0x00000015,
+ AP_PIN_LCD_DATA_6 = 0x00000016,
+ AP_PIN_LCD_DATA_7 = 0x00000017,
+ AP_PIN_LCD_DATA_8 = 0x00000018,
+ AP_PIN_LCD_DATA_9 = 0x00000019,
+ AP_PIN_LCD_DATA_10 = 0x0000001A,
+ AP_PIN_LCD_DATA_11 = 0x0000001B,
+ AP_PIN_LCD_DATA_12 = 0x0000001C,
+ AP_PIN_LCD_DATA_13 = 0x0000001D,
+ AP_PIN_LCD_DATA_14 = 0x0000001E,
+ AP_PIN_LCD_DATA_15 = 0x0000001F
+} AP_GPIO_A_MAPPING_T;
+
+#define AP_GPIO_A_NB (32)
+
+// ============================================================================
+// AP_GPIO_B_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO B Map
+ AP_PIN_KEYIN_0 = 0x00000000,
+ AP_PIN_KEYIN_1 = 0x00000001,
+ AP_PIN_KEYIN_2 = 0x00000002,
+ AP_PIN_KEYOUT_0 = 0x00000003,
+ AP_PIN_KEYOUT_1 = 0x00000004,
+ AP_PIN_KEYOUT_2 = 0x00000005,
+ AP_PIN_I2C3_SCL = 0x00000006,
+ AP_PIN_I2C3_SDA = 0x00000007,
+ AP_PIN_UART2_CTS = 0x00000008,
+ AP_PIN_UART2_RTS = 0x00000009,
+ AP_PIN_CAM_RST = 0x0000000A,
+ AP_PIN_CAM_PDN = 0x0000000B,
+ AP_PIN_CAM_CLK = 0x0000000C,
+ AP_PIN_CAM_VSYNC = 0x0000000D,
+ AP_PIN_CAM_HREF = 0x0000000E,
+ AP_PIN_CAM_PCLK = 0x0000000F,
+ AP_PIN_CAM_DATA_0 = 0x00000010,
+ AP_PIN_CAM_DATA_1 = 0x00000011,
+ AP_PIN_CAM_DATA_2 = 0x00000012,
+ AP_PIN_CAM_DATA_3 = 0x00000013,
+ AP_PIN_CAM_DATA_4 = 0x00000014,
+ AP_PIN_CAM_DATA_5 = 0x00000015,
+ AP_PIN_CAM_DATA_6 = 0x00000016,
+ AP_PIN_CAM_DATA_7 = 0x00000017,
+ AP_PIN_M_SPI_CS_0 = 0x00000018,
+ AP_PIN_NFCLE = 0x00000019,
+ AP_PIN_NFWEN = 0x0000001A,
+ AP_PIN_NFWPN = 0x0000001B,
+ AP_PIN_NFREN = 0x0000001C,
+ AP_PIN_NFRB = 0x0000001D,
+ AP_PIN_I2C1_SCL = 0x0000001E,
+ AP_PIN_I2C1_SDA = 0x0000001F
+} AP_GPIO_B_MAPPING_T;
+
+#define AP_GPIO_B_NB (32)
+
+// ============================================================================
+// AP_GPIO_D_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO D Map
+ AP_PIN_UART3_RXD = 0x00000000,
+ AP_PIN_UART3_TXD = 0x00000001,
+ AP_PIN_UART3_CTS = 0x00000002,
+ AP_PIN_UART3_RTS = 0x00000003,
+ AP_PIN_NFDQS = 0x00000004,
+ AP_PIN_VOLUME_DN = 0x00000005,
+ AP_PIN_VOLUME_UP = 0x00000006,
+ AP_PIN_PLUGIN = 0x00000007,
+ AP_PIN_NFD_8 = 0x00000008,
+ AP_PIN_NFD_9 = 0x00000009,
+ AP_PIN_NFD_10 = 0x0000000A,
+ AP_PIN_NFD_11 = 0x0000000B,
+ AP_PIN_NFD_12 = 0x0000000C,
+ AP_PIN_NFD_13 = 0x0000000D,
+ AP_PIN_NFD_14 = 0x0000000E,
+ AP_PIN_NFD_15 = 0x0000000F,
+ AP_PIN_LCD_DATA_16 = 0x00000010,
+ AP_PIN_LCD_DATA_17 = 0x00000011,
+ AP_PIN_LCD_DATA_18 = 0x00000012,
+ AP_PIN_LCD_DATA_19 = 0x00000013,
+ AP_PIN_LCD_DATA_20 = 0x00000014,
+ AP_PIN_LCD_DATA_21 = 0x00000015,
+ AP_PIN_LCD_DATA_22 = 0x00000016,
+ AP_PIN_LCD_DATA_23 = 0x00000017,
+ AP_PIN_NFCEN_1 = 0x00000018,
+ AP_PIN_NFCEN_2 = 0x00000019,
+ AP_PIN_NFCEN_3 = 0x0000001A,
+ AP_PIN_I2S2_BCK = 0x0000001B,
+ AP_PIN_I2S2_LRCK = 0x0000001C,
+ AP_PIN_I2S2_DI_0 = 0x0000001D,
+ AP_PIN_I2S2_DI_1 = 0x0000001E,
+ AP_PIN_I2S2_DO = 0x0000001F
+} AP_GPIO_D_MAPPING_T;
+
+#define AP_GPIO_D_NB (32)
+
+// =============================================================================
+// TYPES
+// =============================================================================
+
+// ============================================================================
+// CFG_REGS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef volatile struct
+{
+ REG32 CHIP_ID; //0x00000000
+ /// This register contain the synthesis date and version
+ REG32 Build_Version; //0x00000004
+ /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+ /// bit n to '0' selects Alt.
+ REG32 BB_GPIO_Mode; //0x00000008
+ /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+ /// bit n to '0' selects Alt.
+ REG32 AP_GPIO_A_Mode; //0x0000000C
+ /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+ /// bit n to '0' selects Alt.
+ REG32 AP_GPIO_B_Mode; //0x00000010
+ /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+ /// bit n to '0' selects Alt.
+ REG32 AP_GPIO_D_Mode; //0x00000014
+ REG32 Alt_mux_select; //0x00000018
+ REG32 IO_Drive1_Select; //0x0000001C
+ REG32 IO_Drive2_Select; //0x00000020
+ REG32 RAM_DRIVE; //0x00000024
+ REG32 H2X_AP_Offset; //0x00000028
+ REG32 H2X_DDR_Offset; //0x0000002C
+ REG32 audio_pd_set; //0x00000030
+ REG32 audio_pd_clr; //0x00000034
+ REG32 audio_sel_cfg; //0x00000038
+ REG32 audio_mic_cfg; //0x0000003C
+ REG32 audio_spk_cfg; //0x00000040
+ REG32 audio_rcv_gain; //0x00000044
+ REG32 audio_head_gain; //0x00000048
+ REG32 TSC_DATA; //0x0000004C
+ REG32 GPADC_DATA_CH[8]; //0x00000050
+ REG32 Alt_mux_select2; //0x00000070
+ REG32 Mem_mode_Sel; //0x00000074
+} HWP_CFG_REGS_T;
+
+#define hwp_configRegs ((HWP_CFG_REGS_T*)(RDA_CFG_REGS_BASE))
+
+
+//CHIP_ID
+#define CFG_REGS_METAL_ID(n) (((n)&0xFFF)<<0)
+#define CFG_REGS_METAL_ID_MASK (0xFFF<<0)
+#define CFG_REGS_METAL_ID_SHIFT (0)
+#define CFG_REGS_BOND_ID(n) (((n)&7)<<12)
+#define CFG_REGS_BOND_ID_MASK (7<<12)
+#define CFG_REGS_BOND_ID_SHIFT (12)
+#define CFG_REGS_PROD_ID(n) (((n)&0xFFFF)<<16)
+#define CFG_REGS_PROD_ID_MASK (0xFFFF<<16)
+#define CFG_REGS_PROD_ID_SHIFT (16)
+
+//Build_Version
+#define CFG_REGS_MAJOR(n) (((n)&15)<<28)
+#define CFG_REGS_YEAR(n) (((n)&15)<<24)
+#define CFG_REGS_MONTH(n) (((n)&0xFF)<<16)
+#define CFG_REGS_DAY(n) (((n)&0xFF)<<8)
+#define CFG_REGS_BUILD_STYLE_FPGA (0<<4)
+#define CFG_REGS_BUILD_STYLE_CHIP (1<<4)
+#define CFG_REGS_BUILD_STYLE_FPGA_USB (2<<4)
+#define CFG_REGS_BUILD_STYLE_FPGA_GSM (3<<4)
+#define CFG_REGS_BUILD_REVISION(n) (((n)&15)<<0)
+
+//BB_GPIO_Mode
+#define CFG_REGS_MODE_BB_PIN_NONE_0 (1<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_MASK (1<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_SHIFT (0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_ALT (0<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_GPIO (1<<0)
+#define CFG_REGS_MODE_BB_PIN_1 (1<<1)
+#define CFG_REGS_MODE_BB_PIN_1_MASK (1<<1)
+#define CFG_REGS_MODE_BB_PIN_1_SHIFT (1)
+#define CFG_REGS_MODE_BB_PIN_1_ALT (0<<1)
+#define CFG_REGS_MODE_BB_PIN_1_GPIO (1<<1)
+#define CFG_REGS_MODE_BB_PIN_2 (1<<2)
+#define CFG_REGS_MODE_BB_PIN_2_MASK (1<<2)
+#define CFG_REGS_MODE_BB_PIN_2_SHIFT (2)
+#define CFG_REGS_MODE_BB_PIN_2_ALT (0<<2)
+#define CFG_REGS_MODE_BB_PIN_2_GPIO (1<<2)
+#define CFG_REGS_MODE_BB_PIN_3 (1<<3)
+#define CFG_REGS_MODE_BB_PIN_3_MASK (1<<3)
+#define CFG_REGS_MODE_BB_PIN_3_SHIFT (3)
+#define CFG_REGS_MODE_BB_PIN_3_ALT (0<<3)
+#define CFG_REGS_MODE_BB_PIN_3_GPIO (1<<3)
+#define CFG_REGS_MODE_BB_PIN_4 (1<<4)
+#define CFG_REGS_MODE_BB_PIN_4_MASK (1<<4)
+#define CFG_REGS_MODE_BB_PIN_4_SHIFT (4)
+#define CFG_REGS_MODE_BB_PIN_4_ALT (0<<4)
+#define CFG_REGS_MODE_BB_PIN_4_GPIO (1<<4)
+#define CFG_REGS_MODE_BB_PIN_5 (1<<5)
+#define CFG_REGS_MODE_BB_PIN_5_MASK (1<<5)
+#define CFG_REGS_MODE_BB_PIN_5_SHIFT (5)
+#define CFG_REGS_MODE_BB_PIN_5_ALT (0<<5)
+#define CFG_REGS_MODE_BB_PIN_5_GPIO (1<<5)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_MASK (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_SHIFT (6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_ALT (0<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_GPIO (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_MASK (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_SHIFT (7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_ALT (0<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_GPIO (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD (1<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_MASK (1<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_SHIFT (8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_ALT (0<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_GPIO (1<<8)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_MASK (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_SHIFT (9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_ALT (0<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_GPIO (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_MASK (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_SHIFT (10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_ALT (0<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_GPIO (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0 (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_MASK (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_SHIFT (11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_ALT (0<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_GPIO (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1 (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_MASK (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_SHIFT (12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_ALT (0<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_GPIO (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2 (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_MASK (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_SHIFT (13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_ALT (0<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_GPIO (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3 (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_MASK (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_SHIFT (14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_ALT (0<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_GPIO (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_MASK (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_SHIFT (15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_ALT (0<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_GPIO (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_MASK (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_SHIFT (16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_ALT (0<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_GPIO (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0 (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_MASK (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_SHIFT (17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_ALT (0<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_GPIO (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1 (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_MASK (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_SHIFT (18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_ALT (0<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_GPIO (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2 (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_MASK (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_SHIFT (19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_ALT (0<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_GPIO (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3 (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_MASK (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_SHIFT (20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_ALT (0<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_GPIO (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_MASK (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_SHIFT (21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_ALT (0<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_GPIO (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0 (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_MASK (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_SHIFT (22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_ALT (0<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_GPIO (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_MASK (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_SHIFT (23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_ALT (0<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_GPIO (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_MASK (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_SHIFT (24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_ALT (0<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_GPIO (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_MASK (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_SHIFT (25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_ALT (0<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_GPIO (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_MASK (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_SHIFT (26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_ALT (0<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_GPIO (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_MASK (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_SHIFT (27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_ALT (0<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_GPIO (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_MASK (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_SHIFT (28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_ALT (0<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_GPIO (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_MASK (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_SHIFT (29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_ALT (0<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_GPIO (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO (1<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_MASK (1<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_SHIFT (30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_ALT (0<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_GPIO (1<<30)
+#define CFG_REGS_BB_GPIO_MODE(n) (((n)&0x7FFFFFFF)<<0)
+#define CFG_REGS_BB_GPIO_MODE_MASK (0x7FFFFFFF<<0)
+#define CFG_REGS_BB_GPIO_MODE_SHIFT (0)
+
+//AP_GPIO_A_Mode
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0 (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1 (1<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4 (1<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0 (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1 (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_GPIO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS (1<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_MASK (1<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_SHIFT (16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_ALT (0<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_GPIO (1<<16)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1 (1<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_MASK (1<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_SHIFT (17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_ALT (0<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_GPIO (1<<17)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_MASK (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_SHIFT (18)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_ALT (0<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_GPIO (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_MASK (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_SHIFT (19)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_ALT (0<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_GPIO (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_MASK (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_SHIFT (20)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_ALT (0<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_GPIO (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_MASK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_SHIFT (21)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_ALT (0<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_GPIO (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6 (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_MASK (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_SHIFT (22)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_ALT (0<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_GPIO (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7 (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_MASK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_SHIFT (23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_ALT (0<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_GPIO (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8 (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_MASK (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_SHIFT (24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_ALT (0<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_GPIO (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9 (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_MASK (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_SHIFT (25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_ALT (0<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_GPIO (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10 (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_MASK (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_SHIFT (26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_ALT (0<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_GPIO (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11 (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_MASK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_SHIFT (27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_ALT (0<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_GPIO (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12 (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_MASK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_SHIFT (28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_ALT (0<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_GPIO (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13 (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_MASK (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_SHIFT (29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_ALT (0<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_GPIO (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14 (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_MASK (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_SHIFT (30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_ALT (0<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_GPIO (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15 (1<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_MASK (1<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_SHIFT (31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_ALT (0<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_GPIO (1<<31)
+#define CFG_REGS_AP_GPIO_A_MODE(n) (((n)&0xFFFFFFFF)<<0)
+#define CFG_REGS_AP_GPIO_A_MODE_MASK (0xFFFFFFFF<<0)
+#define CFG_REGS_AP_GPIO_A_MODE_SHIFT (0)
+
+//AP_GPIO_B_Mode
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0 (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1 (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2 (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0 (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1 (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2 (1<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA (1<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS (1<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_GPIO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0 (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_MASK (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_SHIFT (16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_ALT (0<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_GPIO (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1 (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_MASK (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_SHIFT (17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_ALT (0<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_GPIO (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2 (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_MASK (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_SHIFT (18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_ALT (0<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_GPIO (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3 (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_MASK (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_SHIFT (19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_ALT (0<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_GPIO (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4 (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_MASK (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_SHIFT (20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_ALT (0<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_GPIO (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5 (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_MASK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_SHIFT (21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_ALT (0<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_GPIO (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6 (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_MASK (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_SHIFT (22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_ALT (0<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_GPIO (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7 (1<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_MASK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_SHIFT (23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_ALT (0<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_GPIO (1<<23)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0 (1<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_MASK (1<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_SHIFT (24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_ALT (0<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_GPIO (1<<24)
+#define CFG_REGS_MODE_AP_PIN_NFCLE (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_MASK (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_SHIFT (25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_ALT (0<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_GPIO (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFWEN (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_MASK (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_SHIFT (26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_ALT (0<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_GPIO (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWPN (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_MASK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_SHIFT (27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_ALT (0<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_GPIO (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFREN (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_MASK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_SHIFT (28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_ALT (0<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_GPIO (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFRB (1<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_MASK (1<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_SHIFT (29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_ALT (0<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_GPIO (1<<29)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_MASK (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_SHIFT (30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_ALT (0<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_GPIO (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_MASK (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_SHIFT (31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_ALT (0<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_GPIO (1<<31)
+#define CFG_REGS_AP_GPIO_B_MODE(n) (((n)&0xFFFFFFFF)<<0)
+#define CFG_REGS_AP_GPIO_B_MODE_MASK (0xFFFFFFFF<<0)
+#define CFG_REGS_AP_GPIO_B_MODE_SHIFT (0)
+
+//AP_GPIO_D_Mode
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS (1<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_NFDQS (1<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP (1<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN (1<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_NFD_8 (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFD_8_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFD_8_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_NFD_8_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_NFD_8_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFD_9 (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFD_9_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFD_9_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_NFD_9_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_NFD_9_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFD_10 (1<<10)
+#define CFG_REGS_MODE_AP_PIN_NFD_10_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_NFD_10_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_NFD_10_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_NFD_10_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_NFD_11 (1<<11)
+#define CFG_REGS_MODE_AP_PIN_NFD_11_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_NFD_11_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_NFD_11_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_NFD_11_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_NFD_12 (1<<12)
+#define CFG_REGS_MODE_AP_PIN_NFD_12_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_NFD_12_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_NFD_12_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_NFD_12_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_NFD_13 (1<<13)
+#define CFG_REGS_MODE_AP_PIN_NFD_13_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_NFD_13_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_NFD_13_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_NFD_13_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_NFD_14 (1<<14)
+#define CFG_REGS_MODE_AP_PIN_NFD_14_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_NFD_14_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_NFD_14_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_NFD_14_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_NFD_15 (1<<15)
+#define CFG_REGS_MODE_AP_PIN_NFD_15_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_NFD_15_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_NFD_15_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_NFD_15_GPIO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_16 (1<<16)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_16_MASK (1<<16)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_16_SHIFT (16)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_16_ALT (0<<16)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_16_GPIO (1<<16)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_17 (1<<17)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_17_MASK (1<<17)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_17_SHIFT (17)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_17_ALT (0<<17)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_17_GPIO (1<<17)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_18 (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_18_MASK (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_18_SHIFT (18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_18_ALT (0<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_18_GPIO (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_19 (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_19_MASK (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_19_SHIFT (19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_19_ALT (0<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_19_GPIO (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_20 (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_20_MASK (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_20_SHIFT (20)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_20_ALT (0<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_20_GPIO (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_21 (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_21_MASK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_21_SHIFT (21)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_21_ALT (0<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_21_GPIO (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_22 (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_22_MASK (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_22_SHIFT (22)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_22_ALT (0<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_22_GPIO (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_23 (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_23_MASK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_23_SHIFT (23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_23_ALT (0<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_23_GPIO (1<<23)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1 (1<<24)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_MASK (1<<24)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_SHIFT (24)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_ALT (0<<24)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_GPIO (1<<24)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2 (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_MASK (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_SHIFT (25)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_ALT (0<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_GPIO (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3 (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_MASK (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_SHIFT (26)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_ALT (0<<26)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_GPIO (1<<26)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_MASK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_SHIFT (27)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_ALT (0<<27)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_GPIO (1<<27)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_MASK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_SHIFT (28)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_ALT (0<<28)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_GPIO (1<<28)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0 (1<<29)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_MASK (1<<29)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_SHIFT (29)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_ALT (0<<29)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_GPIO (1<<29)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1 (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_MASK (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_SHIFT (30)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_ALT (0<<30)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_GPIO (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_MASK (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_SHIFT (31)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_ALT (0<<31)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_GPIO (1<<31)
+#define CFG_REGS_AP_GPIO_D_MODE(n) (((n)&0xFFFFFFFF)<<0)
+#define CFG_REGS_AP_GPIO_D_MODE_MASK (0xFFFFFFFF<<0)
+#define CFG_REGS_AP_GPIO_D_MODE_SHIFT (0)
+
+//Alt_mux_select
+#define CFG_REGS_LCD_MODE_MASK (3<<0)
+#define CFG_REGS_LCD_MODE_PARALLEL_16BIT (0<<0)
+#define CFG_REGS_LCD_MODE_DSI (1<<0)
+#define CFG_REGS_LCD_MODE_RGB_24BIT (2<<0)
+#define CFG_REGS_LCD_MODE_RGB_16BIT (3<<0)
+#define CFG_REGS_SPI_LCD_MASK (1<<2)
+#define CFG_REGS_SPI_LCD_NONE (0<<2)
+#define CFG_REGS_SPI_LCD_SPI_LCD (1<<2)
+#define CFG_REGS_CAM_I2C2_MASK (1<<3)
+#define CFG_REGS_CAM_I2C2_CAM (0<<3)
+#define CFG_REGS_CAM_I2C2_I2C2 (1<<3)
+#define CFG_REGS_CSI2_MASK (3<<4)
+#define CFG_REGS_CSI2_PARALLEL_CAM (0<<4)
+#define CFG_REGS_CSI2_CSI2 (1<<4)
+#define CFG_REGS_CSI2_SPI_CAM (2<<4)
+#define CFG_REGS_UART2_MASK (1<<6)
+#define CFG_REGS_UART2_HOST_UART (0<<6)
+#define CFG_REGS_UART2_UART2 (1<<6)
+#define CFG_REGS_UART1_8LINE_MASK (1<<7)
+#define CFG_REGS_UART1_8LINE_UART2 (0<<7)
+#define CFG_REGS_UART1_8LINE_UART1_8_LINE (1<<7)
+#define CFG_REGS_DAI_MASK (3<<8)
+#define CFG_REGS_DAI_I2S (0<<8)
+#define CFG_REGS_DAI_DAI (1<<8)
+#define CFG_REGS_DAI_DAI_SIMPLE (2<<8)
+#define CFG_REGS_KEYIN_3_MASK (1<<10)
+#define CFG_REGS_KEYIN_3_SPI2_CS_1 (0<<10)
+#define CFG_REGS_KEYIN_3_KEYIN_3 (1<<10)
+#define CFG_REGS_LPSCO_1_MASK (1<<11)
+#define CFG_REGS_LPSCO_1_KEYIN_4 (0<<11)
+#define CFG_REGS_LPSCO_1_LPSCO_1 (1<<11)
+#define CFG_REGS_SPI1_CS_2_MASK (1<<12)
+#define CFG_REGS_SPI1_CS_2_KEYIN_1 (0<<12)
+#define CFG_REGS_SPI1_CS_2_SPI1_CS_2 (1<<12)
+#define CFG_REGS_I2S_DI_2_MASK (1<<13)
+#define CFG_REGS_I2S_DI_2_KEYIN_2 (0<<13)
+#define CFG_REGS_I2S_DI_2_I2S_DI_2 (1<<13)
+#define CFG_REGS_TCO_0_MASK (1<<14)
+#define CFG_REGS_TCO_0_KEYOUT_0 (0<<14)
+#define CFG_REGS_TCO_0_TCO_0 (1<<14)
+#define CFG_REGS_TCO_1_MASK (1<<15)
+#define CFG_REGS_TCO_1_KEYOUT_1 (0<<15)
+#define CFG_REGS_TCO_1_TCO_1 (1<<15)
+#define CFG_REGS_TCO_2_MASK (1<<16)
+#define CFG_REGS_TCO_2_KEYOUT_2 (0<<16)
+#define CFG_REGS_TCO_2_TCO_2 (1<<16)
+#define CFG_REGS_KEYOUT_3_4_MASK (1<<17)
+#define CFG_REGS_KEYOUT_3_4_I2C3 (0<<17)
+#define CFG_REGS_KEYOUT_3_4_KEYOUT_3_4 (1<<17)
+#define CFG_REGS_KEYOUT_6_MASK (1<<18)
+#define CFG_REGS_KEYOUT_6_UART2_RTS (0<<18)
+#define CFG_REGS_KEYOUT_6_KEYOUT_6 (1<<18)
+#define CFG_REGS_KEYOUT_7_MASK (1<<19)
+#define CFG_REGS_KEYOUT_7_UART1_RTS (0<<19)
+#define CFG_REGS_KEYOUT_7_KEYOUT_7 (1<<19)
+#define CFG_REGS_GPO_0_MASK (3<<20)
+#define CFG_REGS_GPO_0_GPO_0 (0<<20)
+#define CFG_REGS_GPO_0_PWT (1<<20)
+#define CFG_REGS_GPO_0_KEYIN_5 (2<<20)
+#define CFG_REGS_GPO_1_MASK (3<<22)
+#define CFG_REGS_GPO_1_GPO_1 (0<<22)
+#define CFG_REGS_GPO_1_LPG (1<<22)
+#define CFG_REGS_GPO_1_KEYOUT_5 (2<<22)
+#define CFG_REGS_GPO_2_MASK (3<<24)
+#define CFG_REGS_GPO_2_GPO_2 (0<<24)
+#define CFG_REGS_GPO_2_PWL_1 (1<<24)
+#define CFG_REGS_GPO_2_CLK_32K (2<<24)
+#define CFG_REGS_GPO_3_MASK (1<<26)
+#define CFG_REGS_GPO_3_LCD_CS_1 (0<<26)
+#define CFG_REGS_GPO_3_GPO_3 (1<<26)
+#define CFG_REGS_GPO_4_MASK (1<<27)
+#define CFG_REGS_GPO_4_LCD_CS_0 (0<<27)
+#define CFG_REGS_GPO_4_GPO_4 (1<<27)
+#define CFG_REGS_CLK_OUT_MASK (1<<28)
+#define CFG_REGS_CLK_OUT_HST_CLK (0<<28)
+#define CFG_REGS_CLK_OUT_CLK_OUT (1<<28)
+#define CFG_REGS_AP_SPI1_MASK (1<<29)
+#define CFG_REGS_AP_SPI1_BB_SPI1 (0<<29)
+#define CFG_REGS_AP_SPI1_AP_SPI1 (1<<29)
+#define CFG_REGS_DEBUG_MASK (3<<30)
+#define CFG_REGS_DEBUG_NONE (0<<30)
+#define CFG_REGS_DEBUG_AP_MONITOR (1<<30)
+#define CFG_REGS_DEBUG_WD_MONITOR (2<<30)
+
+//IO_Drive1_Select
+#define CFG_REGS_DDR_DRIVE_MASK (7<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_WEAK (7<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_WEAK (6<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_STRONG (5<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_STRONG (4<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_WEAK (3<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_WEAK (2<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_STRONG (1<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_STRONG (0<<0)
+#define CFG_REGS_PSRAM1_DRIVE_MASK (7<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_WEAK (7<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_WEAK (6<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_STRONG (5<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_STRONG (4<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_WEAK (3<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_WEAK (2<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_STRONG (1<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_STRONG (0<<3)
+#define CFG_REGS_PSRAM2_DRIVE_MASK (7<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_WEAK (7<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_WEAK (6<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_STRONG (5<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_STRONG (4<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_WEAK (3<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_WEAK (2<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_STRONG (1<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_STRONG (0<<6)
+#define CFG_REGS_NFLSH_DRIVE_MASK (7<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_WEAK (7<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_WEAK (6<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_STRONG (5<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_STRONG (4<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_WEAK (3<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK (2<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_STRONG (1<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_STRONG (0<<9)
+#define CFG_REGS_LCD1_DRIVE_MASK (7<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_WEAK (7<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_WEAK (6<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_STRONG (5<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_STRONG (4<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_WEAK (3<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_WEAK (2<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_STRONG (1<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_STRONG (0<<12)
+#define CFG_REGS_LCD2_DRIVE_MASK (7<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_WEAK (7<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_WEAK (6<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_STRONG (5<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_STRONG (4<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_WEAK (3<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_WEAK (2<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_STRONG (1<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_STRONG (0<<15)
+#define CFG_REGS_SDAT1_DRIVE_MASK (7<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_WEAK (7<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_WEAK (6<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_STRONG (5<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_STRONG (4<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_WEAK (3<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_WEAK (2<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_STRONG (1<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_STRONG (0<<18)
+#define CFG_REGS_SDAT2_DRIVE_MASK (7<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_WEAK (7<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_WEAK (6<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_STRONG (5<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_STRONG (4<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_WEAK (3<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_WEAK (2<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_STRONG (1<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_STRONG (0<<21)
+#define CFG_REGS_CAM_DRIVE_MASK (3<<24)
+#define CFG_REGS_CAM_DRIVE_MOST_STRONG (0<<24)
+#define CFG_REGS_CAM_DRIVE_STRONG (1<<24)
+#define CFG_REGS_CAM_DRIVE_WEAK (2<<24)
+#define CFG_REGS_CAM_DRIVE_MOST_WEAK (3<<24)
+#define CFG_REGS_SIM1_DRIVE_MASK (3<<26)
+#define CFG_REGS_SIM1_DRIVE_MOST_STRONG (0<<26)
+#define CFG_REGS_SIM1_DRIVE_STRONG (1<<26)
+#define CFG_REGS_SIM1_DRIVE_WEAK (2<<26)
+#define CFG_REGS_SIM1_DRIVE_MOST_WEAK (3<<26)
+#define CFG_REGS_SIM2_DRIVE_MASK (3<<28)
+#define CFG_REGS_SIM2_DRIVE_MOST_STRONG (0<<28)
+#define CFG_REGS_SIM2_DRIVE_STRONG (1<<28)
+#define CFG_REGS_SIM2_DRIVE_WEAK (2<<28)
+#define CFG_REGS_SIM2_DRIVE_MOST_WEAK (3<<28)
+#define CFG_REGS_SIM3_DRIVE_MASK (3<<30)
+#define CFG_REGS_SIM3_DRIVE_MOST_STRONG (0<<30)
+#define CFG_REGS_SIM3_DRIVE_STRONG (1<<30)
+#define CFG_REGS_SIM3_DRIVE_WEAK (2<<30)
+#define CFG_REGS_SIM3_DRIVE_MOST_WEAK (3<<30)
+
+//IO_Drive2_Select
+#define CFG_REGS_GPIO_DRIVE_MASK (3<<0)
+#define CFG_REGS_GPIO_DRIVE_MOST_STRONG (0<<0)
+#define CFG_REGS_GPIO_DRIVE_STRONG (1<<0)
+#define CFG_REGS_GPIO_DRIVE_WEAK (2<<0)
+#define CFG_REGS_GPIO_DRIVE_MOST_WEAK (3<<0)
+
+//RAM_DRIVE
+#define CFG_REGS_MBRAM_A(n) (((n)&7)<<0)
+#define CFG_REGS_MBRAM_A_MASK (7<<0)
+#define CFG_REGS_MBRAM_A_SHIFT (0)
+#define CFG_REGS_MBRAM_W(n) (((n)&3)<<3)
+#define CFG_REGS_MBRAM_W_MASK (3<<3)
+#define CFG_REGS_MBRAM_W_SHIFT (3)
+#define CFG_REGS_MBRAM_R (1<<5)
+#define CFG_REGS_BBRAM_A(n) (((n)&7)<<6)
+#define CFG_REGS_BBRAM_A_MASK (7<<6)
+#define CFG_REGS_BBRAM_A_SHIFT (6)
+#define CFG_REGS_BBRAM_W(n) (((n)&3)<<9)
+#define CFG_REGS_BBRAM_W_MASK (3<<9)
+#define CFG_REGS_BBRAM_W_SHIFT (9)
+#define CFG_REGS_BBRAM_R (1<<11)
+#define CFG_REGS_XP_A(n) (((n)&7)<<12)
+#define CFG_REGS_XP_A_MASK (7<<12)
+#define CFG_REGS_XP_A_SHIFT (12)
+#define CFG_REGS_XP_W(n) (((n)&3)<<15)
+#define CFG_REGS_XP_W_MASK (3<<15)
+#define CFG_REGS_XP_W_SHIFT (15)
+#define CFG_REGS_XP_R (1<<17)
+#define CFG_REGS_BP_A(n) (((n)&7)<<18)
+#define CFG_REGS_BP_A_MASK (7<<18)
+#define CFG_REGS_BP_A_SHIFT (18)
+#define CFG_REGS_BP_W(n) (((n)&3)<<21)
+#define CFG_REGS_BP_W_MASK (3<<21)
+#define CFG_REGS_BP_W_SHIFT (21)
+#define CFG_REGS_BP_R (1<<23)
+#define CFG_REGS_EV_A(n) (((n)&7)<<24)
+#define CFG_REGS_EV_A_MASK (7<<24)
+#define CFG_REGS_EV_A_SHIFT (24)
+#define CFG_REGS_EV_W(n) (((n)&3)<<27)
+#define CFG_REGS_EV_W_MASK (3<<27)
+#define CFG_REGS_EV_W_SHIFT (27)
+#define CFG_REGS_EV_R (1<<29)
+
+//H2X_AP_Offset
+#define CFG_REGS_H2X_AP_OFFSET(n) (((n)&0xFF)<<0)
+#define CFG_REGS_H2X_AP_OFFSET_MASK (0xFF<<0)
+#define CFG_REGS_H2X_AP_OFFSET_SHIFT (0)
+
+//H2X_DDR_Offset
+#define CFG_REGS_H2X_DDR_OFFSET(n) (((n)&0xFFFFFFF)<<4)
+#define CFG_REGS_H2X_DDR_OFFSET_MASK (0xFFFFFFF<<4)
+#define CFG_REGS_H2X_DDR_OFFSET_SHIFT (4)
+
+//audio_pd_set
+#define CFG_REGS_AU_DEEP_PD_N (1<<0)
+#define CFG_REGS_AU_REF_PD_N (1<<1)
+#define CFG_REGS_AU_MIC_PD_N (1<<2)
+#define CFG_REGS_AU_AUXMIC_PD_N (1<<3)
+#define CFG_REGS_AU_AD_PD_N (1<<4)
+#define CFG_REGS_AU_DAC_PD_N (1<<5)
+#define CFG_REGS_AU_DAC_RESET_N (1<<8)
+#define CFG_REGS_AU_PLL_PU (1<<16)
+
+//audio_pd_clr
+//#define CFG_REGS_AU_DEEP_PD_N (1<<0)
+//#define CFG_REGS_AU_REF_PD_N (1<<1)
+//#define CFG_REGS_AU_MIC_PD_N (1<<2)
+//#define CFG_REGS_AU_AUXMIC_PD_N (1<<3)
+//#define CFG_REGS_AU_AD_PD_N (1<<4)
+//#define CFG_REGS_AU_DAC_PD_N (1<<5)
+//#define CFG_REGS_AU_DAC_RESET_N (1<<8)
+//#define CFG_REGS_AU_PLL_PU (1<<16)
+
+//audio_sel_cfg
+#define CFG_REGS_AU_AUXMIC_SEL (1<<0)
+#define CFG_REGS_AU_SPK_SEL (1<<1)
+#define CFG_REGS_AU_SPK_MONO_SEL (1<<2)
+#define CFG_REGS_AU_RCV_SEL (1<<3)
+#define CFG_REGS_AU_HEAD_SEL (1<<4)
+
+//audio_mic_cfg
+#define CFG_REGS_AU_MIC_GAIN(n) (((n)&15)<<0)
+#define CFG_REGS_AU_MIC_GAIN_MASK (15<<0)
+#define CFG_REGS_AU_MIC_GAIN_SHIFT (0)
+#define CFG_REGS_AU_MIC_MUTE_N (1<<4)
+
+//audio_spk_cfg
+#define CFG_REGS_AU_SPK_GAIN(n) (((n)&15)<<0)
+#define CFG_REGS_AU_SPK_GAIN_MASK (15<<0)
+#define CFG_REGS_AU_SPK_GAIN_SHIFT (0)
+#define CFG_REGS_AU_SPK_MUTE_N (1<<4)
+#define CFG_REGS_AU_SPK_VOC_GAIN_EN (1<<8)
+
+//audio_rcv_gain
+#define CFG_REGS_AU_RCV_GAIN(n) (((n)&15)<<0)
+#define CFG_REGS_AU_RCV_GAIN_MASK (15<<0)
+#define CFG_REGS_AU_RCV_GAIN_SHIFT (0)
+#define CFG_REGS_AU_RCV_VOC_GAIN_EN (1<<8)
+
+//audio_head_gain
+#define CFG_REGS_AU_HEAD_GAIN(n) (((n)&15)<<0)
+#define CFG_REGS_AU_HEAD_GAIN_MASK (15<<0)
+#define CFG_REGS_AU_HEAD_GAIN_SHIFT (0)
+#define CFG_REGS_AU_HEAD_VOC_GAIN_EN (1<<8)
+
+//TSC_DATA
+#define CFG_REGS_TSC_X_VALUE_BIT(n) (((n)&0x3FF)<<0)
+#define CFG_REGS_TSC_X_VALUE_BIT_MASK (0x3FF<<0)
+#define CFG_REGS_TSC_X_VALUE_BIT_SHIFT (0)
+#define CFG_REGS_TSC_X_VALUE_VALID (1<<10)
+#define CFG_REGS_TSC_Y_VALUE_BIT(n) (((n)&0x3FF)<<11)
+#define CFG_REGS_TSC_Y_VALUE_BIT_MASK (0x3FF<<11)
+#define CFG_REGS_TSC_Y_VALUE_BIT_SHIFT (11)
+#define CFG_REGS_TSC_Y_VALUE_VALID (1<<21)
+
+//GPADC_DATA_CH
+#define CFG_REGS_GPADC_DATA(n) (((n)&0x3FF)<<0)
+#define CFG_REGS_GPADC_DATA_MASK (0x3FF<<0)
+#define CFG_REGS_GPADC_DATA_SHIFT (0)
+#define CFG_REGS_GPADC_VALID (1<<10)
+#define CFG_REGS_GPADC_CH_EN (1<<31)
+
+//Alt_mux_select2
+#define CFG_REGS_UART1_SDIO2_MASK (1<<0)
+#define CFG_REGS_UART1_SDIO2_SDIO2 (0<<0)
+#define CFG_REGS_UART1_SDIO2_UART1 (1<<0)
+#define CFG_REGS_RFSPI_WD_MODE_MASK (1<<1)
+#define CFG_REGS_RFSPI_WD_MODE_SPLIT (0<<1)
+#define CFG_REGS_RFSPI_WD_MODE_AUTO (1<<1)
+#define CFG_REGS_LCD_RGB_17_16_MASK (1<<2)
+#define CFG_REGS_LCD_RGB_17_16_LCD_CS (0<<2)
+#define CFG_REGS_LCD_RGB_17_16_LCD_DATA (1<<2)
+#define CFG_REGS_JTAG_EN_MASK (1<<3)
+#define CFG_REGS_JTAG_EN_DISABLE (0<<3)
+#define CFG_REGS_JTAG_EN_ENABLE (1<<3)
+#define CFG_REGS_RFIF_TEST_MASK (1<<4)
+#define CFG_REGS_RFIF_TEST_DISABLE (0<<4)
+#define CFG_REGS_RFIF_TEST_ENABLE (1<<4)
+#define CFG_REGS_IOMUX_CFG_RESERVED(n) (((n)&0x7FFFFFF)<<5)
+
+//Mem_mode_Sel
+#define CFG_REGS_MPMC_EN_MASK (1<<0)
+#define CFG_REGS_MPMC_EN_DISABLE (0<<0)
+#define CFG_REGS_MPMC_EN_ENABLE (1<<0)
+#define CFG_REGS_PSRAM_EN_MASK (1<<4)
+#define CFG_REGS_PSRAM_EN_DISABLE (0<<4)
+#define CFG_REGS_PSRAM_EN_ENABLE (1<<4)
+#define CFG_REGS_PSRAM_128_MASK (1<<8)
+#define CFG_REGS_PSRAM_128_DISABLE (0<<8)
+#define CFG_REGS_PSRAM_128_ENABLE (1<<8)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8850e.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8850e.h new file mode 100644 index 0000000000..5ef2d1bd6b --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8850e.h @@ -0,0 +1,1297 @@ +//============================================================================== +// +// Copyright (C) 2012-2014, RDA Microelectronics. +// All Rights Reserved +// +// This source code is the property of RDA Microelectronics and is +// confidential. Any modification, distribution, reproduction or +// exploitation of any content of this file is totally forbidden, +// except with the written permission of RDA Microelectronics. +// +//============================================================================== +// +// THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML. +// +// !!! PLEASE DO NOT EDIT !!! +// +// $HeadURL$ +// $Author$ +// $Date$ +// $Revision$ +// +//============================================================================== +// +/// @file +// +//============================================================================== + +#ifndef _CFG_REGS_H_ +#define _CFG_REGS_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +#ifdef CT_ASM +#error "You are trying to use in an assembly code the normal H description of 'cfg_regs'." +#endif + + + +// ============================================================================= +// MACROS +// ============================================================================= +#define PROD_ID (0X810E) + +// ============================================================================ +// BB_GPIO_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// BB GPIO Map + BB_PIN_NONE_0 = 0x00000000, + BB_PIN_1 = 0x00000001, + BB_PIN_2 = 0x00000002, + BB_PIN_3 = 0x00000003, + BB_PIN_4 = 0x00000004, + BB_PIN_5 = 0x00000005, + BB_PIN_UART1_RXD = 0x00000006, + BB_PIN_UART2_RXD = 0x00000007, + BB_PIN_UART2_TXD = 0x00000008, + BB_PIN_SSD1_CLK = 0x00000009, + BB_PIN_SSD1_CMD = 0x0000000A, + BB_PIN_SDAT1_0 = 0x0000000B, + BB_PIN_SDAT1_1 = 0x0000000C, + BB_PIN_SDAT1_2 = 0x0000000D, + BB_PIN_SDAT1_3 = 0x0000000E, + BB_PIN_SSD2_CLK = 0x0000000F, + BB_PIN_SSD2_CMD = 0x00000010, + BB_PIN_SDAT2_0 = 0x00000011, + BB_PIN_SDAT2_1 = 0x00000012, + BB_PIN_SDAT2_2 = 0x00000013, + BB_PIN_SDAT2_3 = 0x00000014, + BB_PIN_SPI1_CLK = 0x00000015, + BB_PIN_SPI1_CS_0 = 0x00000016, + BB_PIN_SPI1_DIO = 0x00000017, + BB_PIN_SPI1_DI = 0x00000018, + BB_PIN_SIM2_RST = 0x00000019, + BB_PIN_SIM2_CLK = 0x0000001A, + BB_PIN_SIM2_DIO = 0x0000001B, + BB_PIN_SIM3_RST = 0x0000001C, + BB_PIN_SIM3_CLK = 0x0000001D, + BB_PIN_SIM3_DIO = 0x0000001E +} BB_GPIO_MAPPING_T; + +#define BB_GPIO_NB (31) + +// ============================================================================ +// AP_GPIO_A_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO A Map + AP_PIN_I2C2_SCL = 0x00000000, + AP_PIN_I2C2_SDA = 0x00000001, + AP_PIN_SPI2_CLK = 0x00000002, + AP_PIN_SPI2_DIO = 0x00000003, + AP_PIN_SPI2_DI = 0x00000004, + AP_PIN_SPI2_CS_0 = 0x00000005, + AP_PIN_SPI2_CS_1 = 0x00000006, + AP_PIN_KEYIN_4 = 0x00000007, + AP_PIN_CLK_OUT = 0x00000008, + AP_PIN_I2S_BCK = 0x00000009, + AP_PIN_I2S_LRCK = 0x0000000A, + AP_PIN_I2S_DI_0 = 0x0000000B, + AP_PIN_I2S_DI_1 = 0x0000000C, + AP_PIN_I2S_DO = 0x0000000D, + AP_PIN_UART1_TXD = 0x0000000E, + AP_PIN_UART1_CTS = 0x0000000F, + AP_PIN_UART1_RTS = 0x00000010, + AP_PIN_SPI1_CS_1 = 0x00000011, + AP_PIN_LCD_DATA_6 = 0x00000012, + AP_PIN_LCD_DATA_7 = 0x00000013, + AP_PIN_LCD_WR = 0x00000014, + AP_PIN_LCD_RS = 0x00000015, + AP_PIN_LCD_RD = 0x00000016, + AP_PIN_LCD_FMARK = 0x00000017, + AP_PIN_LCD_DATA_8 = 0x00000018, + AP_PIN_LCD_DATA_9 = 0x00000019, + AP_PIN_LCD_DATA_10 = 0x0000001A, + AP_PIN_LCD_DATA_11 = 0x0000001B, + AP_PIN_LCD_DATA_12 = 0x0000001C, + AP_PIN_LCD_DATA_13 = 0x0000001D, + AP_PIN_LCD_DATA_14 = 0x0000001E, + AP_PIN_LCD_DATA_15 = 0x0000001F +} AP_GPIO_A_MAPPING_T; + +#define AP_GPIO_A_NB (32) + +// ============================================================================ +// AP_GPIO_B_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO B Map + AP_PIN_KEYIN_0 = 0x00000000, + AP_PIN_KEYIN_1 = 0x00000001, + AP_PIN_KEYIN_2 = 0x00000002, + AP_PIN_KEYOUT_0 = 0x00000003, + AP_PIN_KEYOUT_1 = 0x00000004, + AP_PIN_KEYOUT_2 = 0x00000005, + AP_PIN_I2C3_SCL = 0x00000006, + AP_PIN_I2C3_SDA = 0x00000007, + AP_PIN_UART2_CTS = 0x00000008, + AP_PIN_UART2_RTS = 0x00000009, + AP_PIN_CAM_RST = 0x0000000A, + AP_PIN_CAM_PDN = 0x0000000B, + AP_PIN_CAM_CLK = 0x0000000C, + AP_PIN_CAM_VSYNC = 0x0000000D, + AP_PIN_CAM_HREF = 0x0000000E, + AP_PIN_CAM_PCLK = 0x0000000F, + AP_PIN_CAM_DATA_0 = 0x00000010, + AP_PIN_CAM_DATA_1 = 0x00000011, + AP_PIN_CAM_DATA_2 = 0x00000012, + AP_PIN_CAM_DATA_3 = 0x00000013, + AP_PIN_CAM_DATA_4 = 0x00000014, + AP_PIN_CAM_DATA_5 = 0x00000015, + AP_PIN_CAM_DATA_6 = 0x00000016, + AP_PIN_CAM_DATA_7 = 0x00000017, + AP_PIN_M_SPI_CS_0 = 0x00000018, + AP_PIN_NFCLE = 0x00000019, + AP_PIN_NFWEN = 0x0000001A, + AP_PIN_NFWPN = 0x0000001B, + AP_PIN_NFREN = 0x0000001C, + AP_PIN_NFRB = 0x0000001D, + AP_PIN_I2C1_SCL = 0x0000001E, + AP_PIN_I2C1_SDA = 0x0000001F +} AP_GPIO_B_MAPPING_T; + +#define AP_GPIO_B_NB (32) + +// ============================================================================ +// AP_GPIO_D_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO D Map + AP_PIN_UART3_RXD = 0x00000000, + AP_PIN_UART3_TXD = 0x00000001, + AP_PIN_UART3_CTS = 0x00000002, + AP_PIN_UART3_RTS = 0x00000003, + AP_PIN_NFDQS = 0x00000004, + AP_PIN_VOLUME_DN = 0x00000005, + AP_PIN_VOLUME_UP = 0x00000006, + AP_PIN_PLUGIN = 0x00000007, + AP_PIN_NFCEN_1 = 0x00000008, + AP_PIN_NFCEN_2 = 0x00000009, + AP_PIN_NFCEN_3 = 0x0000000A, + AP_PIN_I2S2_BCK = 0x0000000B, + AP_PIN_I2S2_LRCK = 0x0000000C, + AP_PIN_I2S2_DI_0 = 0x0000000D, + AP_PIN_I2S2_DI_1 = 0x0000000E, + AP_PIN_I2S2_DO = 0x0000000F +} AP_GPIO_D_MAPPING_T; + +#define AP_GPIO_D_NB (16) + +// ============================================================================ +// AP_GPIO_E_MAPPING_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GPIO E Map + AP_PIN_I2CBB_SCL = 0x00000000, + AP_PIN_I2CBB_SDA = 0x00000001, + AP_PIN_CAM2_RST = 0x00000002, + AP_PIN_CAM2_PDN = 0x00000003, + AP_PIN_CAM2_CLK = 0x00000004, + AP_PIN_CAM2_VSYNC = 0x00000005, + AP_PIN_CAM2_HREF = 0x00000006, + AP_PIN_CAM2_PCLK = 0x00000007, + AP_PIN_CAM2_DATA_0 = 0x00000008, + AP_PIN_CAM2_DATA_1 = 0x00000009, + AP_PIN_CAM2_DATA_2 = 0x0000000A, + AP_PIN_CAM2_DATA_3 = 0x0000000B, + AP_PIN_CAM2_DATA_4 = 0x0000000C, + AP_PIN_CAM2_DATA_5 = 0x0000000D, + AP_PIN_CAM2_DATA_6 = 0x0000000E, + AP_PIN_CAM2_DATA_7 = 0x0000000F +} AP_GPIO_E_MAPPING_T; + +#define AP_GPIO_E_NB (16) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// CFG_REGS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + REG32 CHIP_ID; //0x00000000 + /// This register contain the synthesis date and version + REG32 Build_Version; //0x00000004 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 BB_GPIO_Mode; //0x00000008 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_A_Mode; //0x0000000C + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_B_Mode; //0x00000010 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_D_Mode; //0x00000014 + REG32 Alt_mux_select; //0x00000018 + REG32 IO_Drive1_Select; //0x0000001C + REG32 IO_Drive2_Select; //0x00000020 + REG32 RAM_DRIVE; //0x00000024 + REG32 H2X_AP_Offset; //0x00000028 + REG32 H2X_DDR_Offset; //0x0000002C + REG32 H2X_WD_DDR_Offset; //0x00000030 + REG32 audio_pd_set; //0x00000034 + REG32 audio_pd_clr; //0x00000038 + REG32 audio_sel_cfg; //0x0000003C + REG32 audio_mic_cfg; //0x00000040 + REG32 audio_spk_cfg; //0x00000044 + REG32 audio_rcv_gain; //0x00000048 + REG32 audio_head_gain; //0x0000004C + REG32 TSC_DATA; //0x00000050 + REG32 GPADC_DATA_CH[8]; //0x00000054 + REG32 Alt_mux_select2; //0x00000074 + REG32 Mem_mode_Sel; //0x00000078 + /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting + /// bit n to '0' selects Alt. + REG32 AP_GPIO_E_Mode; //0x0000007C +} HWP_CFG_REGS_T; + +#define hwp_configRegs ((HWP_CFG_REGS_T*)(RDA_CFG_REGS_BASE)) + + +//CHIP_ID +#define CFG_REGS_METAL_ID(n) (((n)&0xFFF)<<0) +#define CFG_REGS_METAL_ID_MASK (0xFFF<<0) +#define CFG_REGS_METAL_ID_SHIFT (0) +#define CFG_REGS_BOND_ID(n) (((n)&7)<<12) +#define CFG_REGS_BOND_ID_MASK (7<<12) +#define CFG_REGS_BOND_ID_SHIFT (12) +#define CFG_REGS_PROD_ID(n) (((n)&0xFFFF)<<16) +#define CFG_REGS_PROD_ID_MASK (0xFFFF<<16) +#define CFG_REGS_PROD_ID_SHIFT (16) + +//Build_Version +#define CFG_REGS_MAJOR(n) (((n)&15)<<28) +#define CFG_REGS_YEAR(n) (((n)&15)<<24) +#define CFG_REGS_MONTH(n) (((n)&0xFF)<<16) +#define CFG_REGS_DAY(n) (((n)&0xFF)<<8) +#define CFG_REGS_BUILD_STYLE_FPGA (0<<4) +#define CFG_REGS_BUILD_STYLE_CHIP (1<<4) +#define CFG_REGS_BUILD_STYLE_FPGA_USB (2<<4) +#define CFG_REGS_BUILD_STYLE_FPGA_GSM (3<<4) +#define CFG_REGS_BUILD_REVISION(n) (((n)&15)<<0) + +//BB_GPIO_Mode +#define CFG_REGS_MODE_BB_PIN_NONE_0 (1<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_MASK (1<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_SHIFT (0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_ALT (0<<0) +#define CFG_REGS_MODE_BB_PIN_NONE_0_GPIO (1<<0) +#define CFG_REGS_MODE_BB_PIN_1 (1<<1) +#define CFG_REGS_MODE_BB_PIN_1_MASK (1<<1) +#define CFG_REGS_MODE_BB_PIN_1_SHIFT (1) +#define CFG_REGS_MODE_BB_PIN_1_ALT (0<<1) +#define CFG_REGS_MODE_BB_PIN_1_GPIO (1<<1) +#define CFG_REGS_MODE_BB_PIN_2 (1<<2) +#define CFG_REGS_MODE_BB_PIN_2_MASK (1<<2) +#define CFG_REGS_MODE_BB_PIN_2_SHIFT (2) +#define CFG_REGS_MODE_BB_PIN_2_ALT (0<<2) +#define CFG_REGS_MODE_BB_PIN_2_GPIO (1<<2) +#define CFG_REGS_MODE_BB_PIN_3 (1<<3) +#define CFG_REGS_MODE_BB_PIN_3_MASK (1<<3) +#define CFG_REGS_MODE_BB_PIN_3_SHIFT (3) +#define CFG_REGS_MODE_BB_PIN_3_ALT (0<<3) +#define CFG_REGS_MODE_BB_PIN_3_GPIO (1<<3) +#define CFG_REGS_MODE_BB_PIN_4 (1<<4) +#define CFG_REGS_MODE_BB_PIN_4_MASK (1<<4) +#define CFG_REGS_MODE_BB_PIN_4_SHIFT (4) +#define CFG_REGS_MODE_BB_PIN_4_ALT (0<<4) +#define CFG_REGS_MODE_BB_PIN_4_GPIO (1<<4) +#define CFG_REGS_MODE_BB_PIN_5 (1<<5) +#define CFG_REGS_MODE_BB_PIN_5_MASK (1<<5) +#define CFG_REGS_MODE_BB_PIN_5_SHIFT (5) +#define CFG_REGS_MODE_BB_PIN_5_ALT (0<<5) +#define CFG_REGS_MODE_BB_PIN_5_GPIO (1<<5) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_MASK (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_SHIFT (6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_ALT (0<<6) +#define CFG_REGS_MODE_BB_PIN_UART1_RXD_GPIO (1<<6) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_MASK (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_SHIFT (7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_ALT (0<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_RXD_GPIO (1<<7) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD (1<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_MASK (1<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_SHIFT (8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_ALT (0<<8) +#define CFG_REGS_MODE_BB_PIN_UART2_TXD_GPIO (1<<8) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_MASK (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_SHIFT (9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_ALT (0<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_GPIO (1<<9) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD (1<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_MASK (1<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_SHIFT (10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_ALT (0<<10) +#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_GPIO (1<<10) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0 (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_MASK (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_SHIFT (11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_ALT (0<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_0_GPIO (1<<11) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1 (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_MASK (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_SHIFT (12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_ALT (0<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_1_GPIO (1<<12) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2 (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_MASK (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_SHIFT (13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_ALT (0<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_2_GPIO (1<<13) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3 (1<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_MASK (1<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_SHIFT (14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_ALT (0<<14) +#define CFG_REGS_MODE_BB_PIN_SDAT1_3_GPIO (1<<14) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_MASK (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_SHIFT (15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_ALT (0<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_GPIO (1<<15) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD (1<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_MASK (1<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_SHIFT (16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_ALT (0<<16) +#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_GPIO (1<<16) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0 (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_MASK (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_SHIFT (17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_ALT (0<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_0_GPIO (1<<17) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1 (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_MASK (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_SHIFT (18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_ALT (0<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_1_GPIO (1<<18) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2 (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_MASK (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_SHIFT (19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_ALT (0<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_2_GPIO (1<<19) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3 (1<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_MASK (1<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_SHIFT (20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_ALT (0<<20) +#define CFG_REGS_MODE_BB_PIN_SDAT2_3_GPIO (1<<20) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_MASK (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_SHIFT (21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_ALT (0<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_GPIO (1<<21) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0 (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_MASK (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_SHIFT (22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_ALT (0<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_GPIO (1<<22) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_MASK (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_SHIFT (23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_ALT (0<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_GPIO (1<<23) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI (1<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_MASK (1<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_SHIFT (24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_ALT (0<<24) +#define CFG_REGS_MODE_BB_PIN_SPI1_DI_GPIO (1<<24) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_MASK (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_SHIFT (25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_ALT (0<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_RST_GPIO (1<<25) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_MASK (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_SHIFT (26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_ALT (0<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_GPIO (1<<26) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_MASK (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_SHIFT (27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_ALT (0<<27) +#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_GPIO (1<<27) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_MASK (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_SHIFT (28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_ALT (0<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_RST_GPIO (1<<28) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_MASK (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_SHIFT (29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_ALT (0<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_GPIO (1<<29) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO (1<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_MASK (1<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_SHIFT (30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_ALT (0<<30) +#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_GPIO (1<<30) +#define CFG_REGS_BB_GPIO_MODE(n) (((n)&0x7FFFFFFF)<<0) +#define CFG_REGS_BB_GPIO_MODE_MASK (0x7FFFFFFF<<0) +#define CFG_REGS_BB_GPIO_MODE_SHIFT (0) + +//AP_GPIO_A_Mode +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_DI_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0 (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1 (1<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4 (1<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_KEYIN_4_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT (1<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_CLK_OUT_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_BCK_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0 (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1 (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S_DO (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_I2S_DO_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_TXD_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_CTS_GPIO (1<<15) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS (1<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_MASK (1<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_SHIFT (16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_ALT (0<<16) +#define CFG_REGS_MODE_AP_PIN_UART1_RTS_GPIO (1<<16) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1 (1<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_MASK (1<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_SHIFT (17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_ALT (0<<17) +#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_GPIO (1<<17) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6 (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_MASK (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_SHIFT (18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_ALT (0<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_GPIO (1<<18) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7 (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_MASK (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_SHIFT (19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_ALT (0<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_GPIO (1<<19) +#define CFG_REGS_MODE_AP_PIN_LCD_WR (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_MASK (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_SHIFT (20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_ALT (0<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_WR_GPIO (1<<20) +#define CFG_REGS_MODE_AP_PIN_LCD_RS (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_MASK (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_SHIFT (21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_ALT (0<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RS_GPIO (1<<21) +#define CFG_REGS_MODE_AP_PIN_LCD_RD (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_MASK (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_SHIFT (22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_ALT (0<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_RD_GPIO (1<<22) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_MASK (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_SHIFT (23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_ALT (0<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_GPIO (1<<23) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8 (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_MASK (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_SHIFT (24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_ALT (0<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_GPIO (1<<24) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9 (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_MASK (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_SHIFT (25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_ALT (0<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_GPIO (1<<25) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10 (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_MASK (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_SHIFT (26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_ALT (0<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_GPIO (1<<26) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11 (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_MASK (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_SHIFT (27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_ALT (0<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_GPIO (1<<27) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12 (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_MASK (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_SHIFT (28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_ALT (0<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_GPIO (1<<28) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13 (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_MASK (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_SHIFT (29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_ALT (0<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_GPIO (1<<29) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14 (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_MASK (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_SHIFT (30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_ALT (0<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_GPIO (1<<30) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15 (1<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_MASK (1<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_SHIFT (31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_ALT (0<<31) +#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_GPIO (1<<31) +#define CFG_REGS_AP_GPIO_A_MODE(n) (((n)&0xFFFFFFFF)<<0) +#define CFG_REGS_AP_GPIO_A_MODE_MASK (0xFFFFFFFF<<0) +#define CFG_REGS_AP_GPIO_A_MODE_SHIFT (0) + +//AP_GPIO_B_Mode +#define CFG_REGS_MODE_AP_PIN_KEYIN_0 (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_0_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1 (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_1_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2 (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_KEYIN_2_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0 (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1 (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2 (1<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA (1<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_CTS_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS (1<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_UART2_RTS_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM_RST (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_RST_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_PDN_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_CLK_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_HREF_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_GPIO (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0 (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_MASK (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_SHIFT (16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_ALT (0<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_GPIO (1<<16) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1 (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_MASK (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_SHIFT (17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_ALT (0<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_GPIO (1<<17) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2 (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_MASK (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_SHIFT (18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_ALT (0<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_GPIO (1<<18) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3 (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_MASK (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_SHIFT (19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_ALT (0<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_GPIO (1<<19) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4 (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_MASK (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_SHIFT (20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_ALT (0<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_GPIO (1<<20) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5 (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_MASK (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_SHIFT (21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_ALT (0<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_GPIO (1<<21) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6 (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_MASK (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_SHIFT (22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_ALT (0<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_GPIO (1<<22) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7 (1<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_MASK (1<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_SHIFT (23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_ALT (0<<23) +#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_GPIO (1<<23) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0 (1<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_MASK (1<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_SHIFT (24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_ALT (0<<24) +#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_GPIO (1<<24) +#define CFG_REGS_MODE_AP_PIN_NFCLE (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_MASK (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_SHIFT (25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_ALT (0<<25) +#define CFG_REGS_MODE_AP_PIN_NFCLE_GPIO (1<<25) +#define CFG_REGS_MODE_AP_PIN_NFWEN (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_MASK (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_SHIFT (26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_ALT (0<<26) +#define CFG_REGS_MODE_AP_PIN_NFWEN_GPIO (1<<26) +#define CFG_REGS_MODE_AP_PIN_NFWPN (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_MASK (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_SHIFT (27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_ALT (0<<27) +#define CFG_REGS_MODE_AP_PIN_NFWPN_GPIO (1<<27) +#define CFG_REGS_MODE_AP_PIN_NFREN (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_MASK (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_SHIFT (28) +#define CFG_REGS_MODE_AP_PIN_NFREN_ALT (0<<28) +#define CFG_REGS_MODE_AP_PIN_NFREN_GPIO (1<<28) +#define CFG_REGS_MODE_AP_PIN_NFRB (1<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_MASK (1<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_SHIFT (29) +#define CFG_REGS_MODE_AP_PIN_NFRB_ALT (0<<29) +#define CFG_REGS_MODE_AP_PIN_NFRB_GPIO (1<<29) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_MASK (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_SHIFT (30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_ALT (0<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_GPIO (1<<30) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA (1<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_MASK (1<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_SHIFT (31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_ALT (0<<31) +#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_GPIO (1<<31) +#define CFG_REGS_AP_GPIO_B_MODE(n) (((n)&0xFFFFFFFF)<<0) +#define CFG_REGS_AP_GPIO_B_MODE_MASK (0xFFFFFFFF<<0) +#define CFG_REGS_AP_GPIO_B_MODE_SHIFT (0) + +//AP_GPIO_D_Mode +#define CFG_REGS_MODE_AP_PIN_UART3_RXD (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_RXD_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_TXD_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_CTS_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS (1<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_UART3_RTS_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_NFDQS (1<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_NFDQS_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN (1<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP (1<<6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_PLUGIN (1<<7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_PLUGIN_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1 (1<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_1_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2 (1<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_2_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3 (1<<10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_NFCEN_3_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0 (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1 (1<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO (1<<15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_I2S2_DO_GPIO (1<<15) +#define CFG_REGS_AP_GPIO_D_MODE(n) (((n)&0xFFFF)<<0) +#define CFG_REGS_AP_GPIO_D_MODE_MASK (0xFFFF<<0) +#define CFG_REGS_AP_GPIO_D_MODE_SHIFT (0) + +//Alt_mux_select +#define CFG_REGS_LCD_MODE_MASK (3<<0) +#define CFG_REGS_LCD_MODE_PARALLEL_16BIT (0<<0) +#define CFG_REGS_LCD_MODE_DSI (1<<0) +#define CFG_REGS_LCD_MODE_RGB_24BIT (2<<0) +#define CFG_REGS_LCD_MODE_RGB_16BIT (3<<0) +#define CFG_REGS_SPI_LCD_MASK (1<<2) +#define CFG_REGS_SPI_LCD_NONE (0<<2) +#define CFG_REGS_SPI_LCD_SPI_LCD (1<<2) +#define CFG_REGS_CAM_I2C2_MASK (1<<3) +#define CFG_REGS_CAM_I2C2_CAM (0<<3) +#define CFG_REGS_CAM_I2C2_I2C2 (1<<3) +#define CFG_REGS_CSI2_MASK (3<<4) +#define CFG_REGS_CSI2_PARALLEL_CAM (0<<4) +#define CFG_REGS_CSI2_CSI2 (1<<4) +#define CFG_REGS_CSI2_SPI_CAM (2<<4) +#define CFG_REGS_UART2_MASK (1<<6) +#define CFG_REGS_UART2_HOST_UART (0<<6) +#define CFG_REGS_UART2_UART2 (1<<6) +#define CFG_REGS_UART1_8LINE_MASK (1<<7) +#define CFG_REGS_UART1_8LINE_UART2 (0<<7) +#define CFG_REGS_UART1_8LINE_UART1_8_LINE (1<<7) +#define CFG_REGS_DAI_MASK (3<<8) +#define CFG_REGS_DAI_I2S (0<<8) +#define CFG_REGS_DAI_DAI (1<<8) +#define CFG_REGS_DAI_DAI_SIMPLE (2<<8) +#define CFG_REGS_KEYIN_3_MASK (1<<10) +#define CFG_REGS_KEYIN_3_SPI2_CS_1 (0<<10) +#define CFG_REGS_KEYIN_3_KEYIN_3 (1<<10) +#define CFG_REGS_LPSCO_1_MASK (1<<11) +#define CFG_REGS_LPSCO_1_KEYIN_4 (0<<11) +#define CFG_REGS_LPSCO_1_LPSCO_1 (1<<11) +#define CFG_REGS_SPI1_CS_2_MASK (1<<12) +#define CFG_REGS_SPI1_CS_2_KEYIN_1 (0<<12) +#define CFG_REGS_SPI1_CS_2_SPI1_CS_2 (1<<12) +#define CFG_REGS_I2S_DI_2_MASK (1<<13) +#define CFG_REGS_I2S_DI_2_KEYIN_2 (0<<13) +#define CFG_REGS_I2S_DI_2_I2S_DI_2 (1<<13) +#define CFG_REGS_TCO_0_MASK (1<<14) +#define CFG_REGS_TCO_0_KEYOUT_0 (0<<14) +#define CFG_REGS_TCO_0_TCO_0 (1<<14) +#define CFG_REGS_TCO_1_MASK (1<<15) +#define CFG_REGS_TCO_1_KEYOUT_1 (0<<15) +#define CFG_REGS_TCO_1_TCO_1 (1<<15) +#define CFG_REGS_TCO_2_MASK (1<<16) +#define CFG_REGS_TCO_2_KEYOUT_2 (0<<16) +#define CFG_REGS_TCO_2_TCO_2 (1<<16) +#define CFG_REGS_KEYOUT_3_4_MASK (1<<17) +#define CFG_REGS_KEYOUT_3_4_I2C3 (0<<17) +#define CFG_REGS_KEYOUT_3_4_KEYOUT_3_4 (1<<17) +#define CFG_REGS_KEYOUT_6_MASK (1<<18) +#define CFG_REGS_KEYOUT_6_UART2_RTS (0<<18) +#define CFG_REGS_KEYOUT_6_KEYOUT_6 (1<<18) +#define CFG_REGS_KEYOUT_7_MASK (1<<19) +#define CFG_REGS_KEYOUT_7_UART1_RTS (0<<19) +#define CFG_REGS_KEYOUT_7_KEYOUT_7 (1<<19) +#define CFG_REGS_GPO_0_MASK (3<<20) +#define CFG_REGS_GPO_0_GPO_0 (0<<20) +#define CFG_REGS_GPO_0_PWT (1<<20) +#define CFG_REGS_GPO_0_KEYIN_5 (2<<20) +#define CFG_REGS_GPO_1_MASK (3<<22) +#define CFG_REGS_GPO_1_GPO_1 (0<<22) +#define CFG_REGS_GPO_1_LPG (1<<22) +#define CFG_REGS_GPO_1_KEYOUT_5 (2<<22) +#define CFG_REGS_GPO_2_MASK (3<<24) +#define CFG_REGS_GPO_2_GPO_2 (0<<24) +#define CFG_REGS_GPO_2_PWL_1 (1<<24) +#define CFG_REGS_GPO_2_CLK_32K (2<<24) +#define CFG_REGS_GPO_3_MASK (1<<26) +#define CFG_REGS_GPO_3_LCD_CS_1 (0<<26) +#define CFG_REGS_GPO_3_GPO_3 (1<<26) +#define CFG_REGS_GPO_4_MASK (1<<27) +#define CFG_REGS_GPO_4_LCD_CS_0 (0<<27) +#define CFG_REGS_GPO_4_GPO_4 (1<<27) +#define CFG_REGS_CLK_OUT_MASK (1<<28) +#define CFG_REGS_CLK_OUT_HST_CLK (0<<28) +#define CFG_REGS_CLK_OUT_CLK_OUT (1<<28) +#define CFG_REGS_DEBUG_MASK (1<<29) +#define CFG_REGS_DEBUG_NONE (0<<29) +#define CFG_REGS_DEBUG_DEBUG_MONITOR (1<<29) +#define CFG_REGS_AP_SPI1_MASK (1<<30) +#define CFG_REGS_AP_SPI1_BB_SPI1 (0<<30) +#define CFG_REGS_AP_SPI1_AP_SPI1 (1<<30) +#define CFG_REGS_RGB_CAM_MASK (1<<31) +#define CFG_REGS_RGB_CAM_DISABLE (0<<31) +#define CFG_REGS_RGB_CAM_ENABLE (1<<31) + +//IO_Drive1_Select +#define CFG_REGS_DDR_DRIVE_MASK (7<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_WEAK (7<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_WEAK (6<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_STRONG (5<<0) +#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_STRONG (4<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_WEAK (3<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_WEAK (2<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_STRONG (1<<0) +#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_STRONG (0<<0) +#define CFG_REGS_PSRAM1_DRIVE_MASK (7<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_WEAK (7<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_WEAK (6<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_STRONG (5<<3) +#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_STRONG (4<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_WEAK (3<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_WEAK (2<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_STRONG (1<<3) +#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_STRONG (0<<3) +#define CFG_REGS_PSRAM2_DRIVE_MASK (7<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_WEAK (7<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_WEAK (6<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_STRONG (5<<6) +#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_STRONG (4<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_WEAK (3<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_WEAK (2<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_STRONG (1<<6) +#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_STRONG (0<<6) +#define CFG_REGS_NFLSH_DRIVE_MASK (7<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_WEAK (7<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_WEAK (6<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_STRONG (5<<9) +#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_STRONG (4<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_WEAK (3<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK (2<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_STRONG (1<<9) +#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_STRONG (0<<9) +#define CFG_REGS_LCD1_DRIVE_MASK (7<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_WEAK (7<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_WEAK (6<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_STRONG (5<<12) +#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_STRONG (4<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_WEAK (3<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_WEAK (2<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_STRONG (1<<12) +#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_STRONG (0<<12) +#define CFG_REGS_LCD2_DRIVE_MASK (7<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_WEAK (7<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_WEAK (6<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_STRONG (5<<15) +#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_STRONG (4<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_WEAK (3<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_WEAK (2<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_STRONG (1<<15) +#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_STRONG (0<<15) +#define CFG_REGS_SDAT1_DRIVE_MASK (7<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_WEAK (7<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_WEAK (6<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_STRONG (5<<18) +#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_STRONG (4<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_WEAK (3<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_WEAK (2<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_STRONG (1<<18) +#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_STRONG (0<<18) +#define CFG_REGS_SDAT2_DRIVE_MASK (7<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_WEAK (7<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_WEAK (6<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_STRONG (5<<21) +#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_STRONG (4<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_WEAK (3<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_WEAK (2<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_STRONG (1<<21) +#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_STRONG (0<<21) +#define CFG_REGS_CAM_DRIVE_MASK (3<<24) +#define CFG_REGS_CAM_DRIVE_MOST_STRONG (0<<24) +#define CFG_REGS_CAM_DRIVE_STRONG (1<<24) +#define CFG_REGS_CAM_DRIVE_WEAK (2<<24) +#define CFG_REGS_CAM_DRIVE_MOST_WEAK (3<<24) +#define CFG_REGS_SIM1_DRIVE_MASK (3<<26) +#define CFG_REGS_SIM1_DRIVE_MOST_STRONG (0<<26) +#define CFG_REGS_SIM1_DRIVE_STRONG (1<<26) +#define CFG_REGS_SIM1_DRIVE_WEAK (2<<26) +#define CFG_REGS_SIM1_DRIVE_MOST_WEAK (3<<26) +#define CFG_REGS_SIM2_DRIVE_MASK (3<<28) +#define CFG_REGS_SIM2_DRIVE_MOST_STRONG (0<<28) +#define CFG_REGS_SIM2_DRIVE_STRONG (1<<28) +#define CFG_REGS_SIM2_DRIVE_WEAK (2<<28) +#define CFG_REGS_SIM2_DRIVE_MOST_WEAK (3<<28) +#define CFG_REGS_SIM3_DRIVE_MASK (3<<30) +#define CFG_REGS_SIM3_DRIVE_MOST_STRONG (0<<30) +#define CFG_REGS_SIM3_DRIVE_STRONG (1<<30) +#define CFG_REGS_SIM3_DRIVE_WEAK (2<<30) +#define CFG_REGS_SIM3_DRIVE_MOST_WEAK (3<<30) + +//IO_Drive2_Select +#define CFG_REGS_GPIO_DRIVE_MASK (3<<0) +#define CFG_REGS_GPIO_DRIVE_MOST_STRONG (0<<0) +#define CFG_REGS_GPIO_DRIVE_STRONG (1<<0) +#define CFG_REGS_GPIO_DRIVE_WEAK (2<<0) +#define CFG_REGS_GPIO_DRIVE_MOST_WEAK (3<<0) +#define CFG_REGS_CAM2_DRIVE_MASK (3<<2) +#define CFG_REGS_CAM2_DRIVE_MOST_STRONG (0<<2) +#define CFG_REGS_CAM2_DRIVE_STRONG (1<<2) +#define CFG_REGS_CAM2_DRIVE_WEAK (2<<2) +#define CFG_REGS_CAM2_DRIVE_MOST_WEAK (3<<2) + +//RAM_DRIVE +#define CFG_REGS_MBRAM_A(n) (((n)&7)<<0) +#define CFG_REGS_MBRAM_A_MASK (7<<0) +#define CFG_REGS_MBRAM_A_SHIFT (0) +#define CFG_REGS_MBRAM_W(n) (((n)&3)<<3) +#define CFG_REGS_MBRAM_W_MASK (3<<3) +#define CFG_REGS_MBRAM_W_SHIFT (3) +#define CFG_REGS_MBRAM_R (1<<5) +#define CFG_REGS_BBRAM_A(n) (((n)&7)<<6) +#define CFG_REGS_BBRAM_A_MASK (7<<6) +#define CFG_REGS_BBRAM_A_SHIFT (6) +#define CFG_REGS_BBRAM_W(n) (((n)&3)<<9) +#define CFG_REGS_BBRAM_W_MASK (3<<9) +#define CFG_REGS_BBRAM_W_SHIFT (9) +#define CFG_REGS_BBRAM_R (1<<11) +#define CFG_REGS_XP_A(n) (((n)&7)<<12) +#define CFG_REGS_XP_A_MASK (7<<12) +#define CFG_REGS_XP_A_SHIFT (12) +#define CFG_REGS_XP_W(n) (((n)&3)<<15) +#define CFG_REGS_XP_W_MASK (3<<15) +#define CFG_REGS_XP_W_SHIFT (15) +#define CFG_REGS_XP_R (1<<17) +#define CFG_REGS_BP_A(n) (((n)&7)<<18) +#define CFG_REGS_BP_A_MASK (7<<18) +#define CFG_REGS_BP_A_SHIFT (18) +#define CFG_REGS_BP_W(n) (((n)&3)<<21) +#define CFG_REGS_BP_W_MASK (3<<21) +#define CFG_REGS_BP_W_SHIFT (21) +#define CFG_REGS_BP_R (1<<23) +#define CFG_REGS_EV_A(n) (((n)&7)<<24) +#define CFG_REGS_EV_A_MASK (7<<24) +#define CFG_REGS_EV_A_SHIFT (24) +#define CFG_REGS_EV_W(n) (((n)&3)<<27) +#define CFG_REGS_EV_W_MASK (3<<27) +#define CFG_REGS_EV_W_SHIFT (27) +#define CFG_REGS_EV_R (1<<29) + +//H2X_AP_Offset +#define CFG_REGS_H2X_AP_OFFSET(n) (((n)&0xFF)<<0) +#define CFG_REGS_H2X_AP_OFFSET_MASK (0xFF<<0) +#define CFG_REGS_H2X_AP_OFFSET_SHIFT (0) + +//audio_pd_set +#define CFG_REGS_AU_DEEP_PD_N (1<<0) +#define CFG_REGS_AU_REF_PD_N (1<<1) +#define CFG_REGS_AU_MIC_PD_N (1<<2) +#define CFG_REGS_AU_AUXMIC_PD_N (1<<3) +#define CFG_REGS_AU_AD_PD_N (1<<4) +#define CFG_REGS_AU_DAC_PD_N (1<<5) +#define CFG_REGS_AU_DAC_RESET_N (1<<8) +#define CFG_REGS_AU_PLL_PU (1<<16) + +//audio_pd_clr +//#define CFG_REGS_AU_DEEP_PD_N (1<<0) +//#define CFG_REGS_AU_REF_PD_N (1<<1) +//#define CFG_REGS_AU_MIC_PD_N (1<<2) +//#define CFG_REGS_AU_AUXMIC_PD_N (1<<3) +//#define CFG_REGS_AU_AD_PD_N (1<<4) +//#define CFG_REGS_AU_DAC_PD_N (1<<5) +//#define CFG_REGS_AU_DAC_RESET_N (1<<8) +//#define CFG_REGS_AU_PLL_PU (1<<16) + +//audio_sel_cfg +#define CFG_REGS_AU_AUXMIC_SEL (1<<0) +#define CFG_REGS_AU_SPK_SEL (1<<1) +#define CFG_REGS_AU_SPK_MONO_SEL (1<<2) +#define CFG_REGS_AU_RCV_SEL (1<<3) +#define CFG_REGS_AU_HEAD_SEL (1<<4) + +//audio_mic_cfg +#define CFG_REGS_AU_MIC_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_MIC_GAIN_MASK (15<<0) +#define CFG_REGS_AU_MIC_GAIN_SHIFT (0) +#define CFG_REGS_AU_MIC_MUTE_N (1<<4) + +//audio_spk_cfg +#define CFG_REGS_AU_SPK_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_SPK_GAIN_MASK (15<<0) +#define CFG_REGS_AU_SPK_GAIN_SHIFT (0) +#define CFG_REGS_AU_SPK_MUTE_N (1<<4) +#define CFG_REGS_AU_SPK_VOC_GAIN_EN (1<<8) + +//audio_rcv_gain +#define CFG_REGS_AU_RCV_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_RCV_GAIN_MASK (15<<0) +#define CFG_REGS_AU_RCV_GAIN_SHIFT (0) +#define CFG_REGS_AU_RCV_VOC_GAIN_EN (1<<8) + +//audio_head_gain +#define CFG_REGS_AU_HEAD_GAIN(n) (((n)&15)<<0) +#define CFG_REGS_AU_HEAD_GAIN_MASK (15<<0) +#define CFG_REGS_AU_HEAD_GAIN_SHIFT (0) +#define CFG_REGS_AU_HEAD_VOC_GAIN_EN (1<<8) + +//TSC_DATA +#define CFG_REGS_TSC_X_VALUE_BIT(n) (((n)&0x3FF)<<0) +#define CFG_REGS_TSC_X_VALUE_BIT_MASK (0x3FF<<0) +#define CFG_REGS_TSC_X_VALUE_BIT_SHIFT (0) +#define CFG_REGS_TSC_X_VALUE_VALID (1<<10) +#define CFG_REGS_TSC_Y_VALUE_BIT(n) (((n)&0x3FF)<<11) +#define CFG_REGS_TSC_Y_VALUE_BIT_MASK (0x3FF<<11) +#define CFG_REGS_TSC_Y_VALUE_BIT_SHIFT (11) +#define CFG_REGS_TSC_Y_VALUE_VALID (1<<21) + +//GPADC_DATA_CH +#define CFG_REGS_GPADC_DATA(n) (((n)&0x3FF)<<0) +#define CFG_REGS_GPADC_DATA_MASK (0x3FF<<0) +#define CFG_REGS_GPADC_DATA_SHIFT (0) +#define CFG_REGS_GPADC_VALID (1<<10) +#define CFG_REGS_GPADC_CH_EN (1<<31) + +//Alt_mux_select2 +#define CFG_REGS_UART1_SDIO2_MASK (1<<0) +#define CFG_REGS_UART1_SDIO2_SDIO2 (0<<0) +#define CFG_REGS_UART1_SDIO2_UART1 (1<<0) +#define CFG_REGS_JTAG_EN_MASK (1<<1) +#define CFG_REGS_JTAG_EN_DISABLE (0<<1) +#define CFG_REGS_JTAG_EN_ENABLE (1<<1) +#define CFG_REGS_LCD_RGB_17_16_MASK (1<<2) +#define CFG_REGS_LCD_RGB_17_16_LCD_CS (0<<2) +#define CFG_REGS_LCD_RGB_17_16_LCD_DATA (1<<2) +#define CFG_REGS_CSI2_2_MASK (3<<3) +#define CFG_REGS_CSI2_2_PARALLEL_CAM (0<<3) +#define CFG_REGS_CSI2_2_CSI2 (1<<3) +#define CFG_REGS_CSI2_2_SPI_CAM (2<<3) +#define CFG_REGS_RGB_CAM_2_MASK (1<<5) +#define CFG_REGS_RGB_CAM_2_DISABLE (0<<5) +#define CFG_REGS_RGB_CAM_2_ENABLE (1<<5) +#define CFG_REGS_MAC_EN_MASK (1<<6) +#define CFG_REGS_MAC_EN_DISABLE (0<<6) +#define CFG_REGS_MAC_EN_ENABLE (1<<6) +#define CFG_REGS_IOMUX_CFG_RESERVED(n) (((n)&0x1FFFFFF)<<7) + +//AP_GPIO_E_Mode +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_MASK (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_SHIFT (0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_ALT (0<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_GPIO (1<<0) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_MASK (1<<1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_SHIFT (1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_ALT (0<<1) +#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_GPIO (1<<1) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST (1<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_MASK (1<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_SHIFT (2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_ALT (0<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_RST_GPIO (1<<2) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN (1<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_MASK (1<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_SHIFT (3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_ALT (0<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_GPIO (1<<3) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK (1<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_MASK (1<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_SHIFT (4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_ALT (0<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_GPIO (1<<4) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC (1<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_MASK (1<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_SHIFT (5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_ALT (0<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_GPIO (1<<5) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF (1<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_MASK (1<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_SHIFT (6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_ALT (0<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_GPIO (1<<6) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK (1<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_MASK (1<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_SHIFT (7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_ALT (0<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_GPIO (1<<7) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0 (1<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_MASK (1<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_SHIFT (8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_ALT (0<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_GPIO (1<<8) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1 (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_MASK (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_SHIFT (9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_ALT (0<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_GPIO (1<<9) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2 (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_MASK (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_SHIFT (10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_ALT (0<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_GPIO (1<<10) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3 (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_MASK (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_SHIFT (11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_ALT (0<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_GPIO (1<<11) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4 (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_MASK (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_SHIFT (12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_ALT (0<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_GPIO (1<<12) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5 (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_MASK (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_SHIFT (13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_ALT (0<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_GPIO (1<<13) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6 (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_MASK (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_SHIFT (14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_ALT (0<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_GPIO (1<<14) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7 (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_MASK (1<<15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_SHIFT (15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_ALT (0<<15) +#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_GPIO (1<<15) +#define CFG_REGS_AP_GPIO_E_MODE(n) (((n)&0xFFFF)<<0) +#define CFG_REGS_AP_GPIO_E_MODE_MASK (0xFFFF<<0) +#define CFG_REGS_AP_GPIO_E_MODE_SHIFT (0) + + + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_gpio.h b/arch/arm/include/asm/arch-rda/reg_gpio.h new file mode 100644 index 0000000000..e26f099ec3 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_gpio.h @@ -0,0 +1,141 @@ +//============================================================================== +// +// Copyright (C) 2012-2013, RDA Microelectronics. +// All Rights Reserved +// +// This source code is the property of RDA Microelectronics and is +// confidential. Any modification, distribution, reproduction or +// exploitation of any content of this file is totally forbidden, +// except with the written permission of RDA Microelectronics. +// +//============================================================================== +// +// THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML. +// +// !!! PLEASE DO NOT EDIT !!! +// +// $HeadURL$ +// $Author$ +// $Date$ +// $Revision$ +// +//============================================================================== +// +/// @file +// +//============================================================================== + +#ifndef _REG_GPIO_H_ +#define _REG_GPIO_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= +#define IDX_GPIO_DCON (0) +#define IDX_GPO_CHG (0) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// GPIO_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + REG32 gpio_oen_val; //0x00000000 + REG32 gpio_oen_set_out; //0x00000004 + REG32 gpio_oen_set_in; //0x00000008 + REG32 gpio_val; //0x0000000C + REG32 gpio_set; //0x00000010 + REG32 gpio_clr; //0x00000014 + REG32 gpint_ctrl_set; //0x00000018 + REG32 gpint_ctrl_clr; //0x0000001C + REG32 int_clr; //0x00000020 + REG32 int_status; //0x00000024 + REG32 chg_ctrl; //0x00000028 + REG32 chg_cmd; //0x0000002C + REG32 gpo_set; //0x00000030 + REG32 gpo_clr; //0x00000034 +} HWP_GPIO_T; + +#define hwp_apGpioA ((HWP_GPIO_T*) (RDA_GPIO_A_BASE)) +#define hwp_apGpioB ((HWP_GPIO_T*) (RDA_GPIO_B_BASE)) +#define hwp_apGpioD ((HWP_GPIO_T*) (RDA_GPIO_D_BASE)) +#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H) +#define hwp_apGpioE ((HWP_GPIO_T*) (RDA_GPIO_E_BASE)) +#endif +#define hwp_gpio ((HWP_GPIO_T*) (RDA_GPIO_BASE)) + + +//gpio_oen_val +#define GPIO_OEN_VAL(n) (((n)&0xFFFFFFFF)<<0) +#define GPIO_OEN_VAL_INPUT (0x1<<0) +#define GPIO_OEN_VAL_OUTPUT (0x0<<0) + +//gpio_oen_set_out +#define GPIO_OEN_SET_OUT(n) (((n)&0xFFFFFFFF)<<0) + +//gpio_oen_set_in +#define GPIO_OEN_SET_IN(n) (((n)&0xFFFFFFFF)<<0) + +//gpio_val +#define GPIO_GPIO_VAL(n) (((n)&0xFFFFFFFF)<<0) + +//gpio_set +#define GPIO_GPIO_SET(n) (((n)&0xFFFFFFFF)<<0) + +//gpio_clr +#define GPIO_GPIO_CLR(n) (((n)&0xFFFFFFFF)<<0) + +//gpint_ctrl_set +#define GPIO_GPINT_R_SET(n) (((n)&0xFF)<<0) +#define GPIO_GPINT_F_SET(n) (((n)&0xFF)<<8) +#define GPIO_DBN_EN_SET(n) (((n)&0xFF)<<16) +#define GPIO_GPINT_MODE_SET(n) (((n)&0xFF)<<24) + +//gpint_ctrl_clr +#define GPIO_GPINT_R_CLR(n) (((n)&0xFF)<<0) +#define GPIO_GPINT_F_CLR(n) (((n)&0xFF)<<8) +#define GPIO_DBN_EN_CLR(n) (((n)&0xFF)<<16) +#define GPIO_GPINT_MODE_CLR(n) (((n)&0xFF)<<24) + +//int_clr +#define GPIO_GPINT_CLR(n) (((n)&0xFF)<<0) + +//int_status +#define GPIO_GPINT_STATUS(n) (((n)&0xFF)<<0) +#define GPIO_GPINT_STATUS_MASK (0xFF<<0) +#define GPIO_GPINT_STATUS_SHIFT (0) + +//chg_ctrl +#define GPIO_OUT_TIME(n) (((n)&15)<<0) +#define GPIO_WAIT_TIME(n) (((n)&0x3F)<<4) +#define GPIO_INT_MODE_L2H (0<<16) +#define GPIO_INT_MODE_H2L (1<<16) +#define GPIO_INT_MODE_RR (3<<16) + +//chg_cmd +#define GPIO_DCON_MODE_SET (1<<0) +#define GPIO_CHG_MODE_SET (1<<4) +#define GPIO_DCON_MODE_CLR (1<<8) +#define GPIO_CHG_MODE_CLR (1<<12) +#define GPIO_CHG_DOWN (1<<24) + +//gpo_set +#define GPIO_GPO_SET(n) (((n)&31)<<0) + +//gpo_clr +#define GPIO_GPO_CLR(n) (((n)&31)<<0) + + + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_i2c.h b/arch/arm/include/asm/arch-rda/reg_i2c.h new file mode 100644 index 0000000000..8b39b9f527 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_i2c.h @@ -0,0 +1,93 @@ +#ifndef _REG_I2C_H_ +#define _REG_I2C_H_ + +//#include "iomap.h" +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================ +// I2C_MASTER_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + REG32 CTRL; //0x00000000 + REG32 STATUS; //0x00000004 + REG32 TXRX_BUFFER; //0x00000008 + REG32 CMD; //0x0000000C + REG32 IRQ_CLR; //0x00000010 + REG32 CTRL1; //0x00000014 +} HWP_I2C_MASTER_T; + +#define hwp_i2cMaster ((HWP_I2C_MASTER_T*)(RDA_I2C1_BASE)) +#define hwp_i2cMaster2 ((HWP_I2C_MASTER_T*)(RDA_I2C2_BASE)) +#define hwp_i2cMaster3 ((HWP_I2C_MASTER_T*)(RDA_I2C3_BASE)) + +//CTRL +#define I2C_MASTER_EN (1<<0) +#define I2C_MASTER_CLEAR_FIFO (1<<7) +#define I2C_MASTER_IRQ_MASK (1<<8) +#define I2C_MASTER_TX_FIFO_THRESHOLD(n) (((n)&0x1F)<<1) +#define I2C_MASTER_TX_FIFO_THRESHOLD_MASK (0x1F<<1) +#define I2C_MASTER_RX_READ_NUM(n) (((n)&0x1F)<<9) +#define I2C_MASTER_RX_READ_NUM_MASK (0x1F <<9) +#define I2C_MASTER_TIMEOUT_THRESHOLD_MASK (0x3<<14) +#define I2C_MASTER_TIMEOUT_THRESHOLD_SHIFT 14 +#define I2C_MASTER_CLOCK_PRESCALE(n) (((n)&0xFFFF)<<16) +#define I2C_MASTER_CLOCK_PRESCALE_MASK (0xFFFF<<16) + +//CTRL1 +#define I2C_MASTER_DMA_MODE (1 << 0) +#define I2C_MASTER_TXFIFO_OVER_IRQ_MASK (1<<1) +#define I2C_MASTER_TXFIFO_UNDER_IRQ_MASK (1<<2) +#define I2C_MASTER_RXFIFO_OVER_IRQ_MASK (1<<3) +#define I2C_MASTER_RXFIFO_UNDER_IRQ_MASK (1<<4) +#define I2C_MASTER_TXFIFO_EMPTY_IRQ_MASK (1<<5) +#define I2C_MASTER_RXFIFO_NUM_IRQ_MASK (1<<6) +#define I2C_MASTER_TX_DMA_IRQ_MASK (1<<7) +#define I2C_MASTER_RX_DMA_IRQ_MASK (1<<8) +#define I2C_MASTER_TX_DMA_COUNTER(n) (((n)&0x7FF)<< 9) +#define I2C_MASTER_TX_DMA_COUNTER_MASK (0x7FF<<9) +#define I2C_MASTER_RX_DMA_COUNTER(n) (((n)&0x7FF)<< 20) +#define I2C_MASTER_RX_DMA_COUNTER_MASK (0x7FF<<20) + +//STATUS +#define I2C_MASTER_IRQ_CAUSE (1<<0) +#define I2C_MASTER_IRQ_TX_DMA (1<<1) +#define I2C_MASTER_IRQ_RX_DMA (1<<2) +#define I2C_MASTER_IRQ_STATUS (1<<4) +#define I2C_MASTER_IRQ_TX_DMA_DONE (1<<5) +#define I2C_MASTER_IRQ_RX_DMA_DONE (1<<6) +#define I2C_MASTER_TIP (1<<8) +#define I2C_MASTER_AL (1<<12) +#define I2C_MASTER_BUSY (1<<16) +#define I2C_MASTER_IRQ_RX_OVF (1<<17) +#define I2C_MASTER_IRQ_RX_UDF (1<<18) +#define I2C_MASTER_IRQ_TX_OVF (1<<19) +#define I2C_MASTER_IRQ_TX_UDF (1<<20) + +//#define I2C_MASTER_RXACK (1<<20) +#define I2C_MASTER_RX_FIFO_DATA_NUM(n) (((n)&0x1F)<<21) +#define I2C_MASTER_RX_FIFO_DATA_NUM_MASK (0x1F<<21) +#define I2C_MASTER_TX_FIFO_FREE_NUM(n) (((n)&0x1F)<<26) +#define I2C_MASTER_TX_FIFO_FREE_NUM_MASK (0x1F<<26) +#define I2C_MASTER_TIMEOUT (1<<31) + +//TXRX_BUFFER +#define I2C_MASTER_TX_DATA(n) (((n)&0xFF)<<0) +#define I2C_MASTER_RX_DATA(n) (((n)&0xFF)<<0) + +//CMD +#define I2C_MASTER_ACK (1<<0) +#define I2C_MASTER_RD (1<<4) +#define I2C_MASTER_STO (1<<8) +#define I2C_MASTER_FORCE_STO (1<<9) +#define I2C_MASTER_WR (1<<12) +#define I2C_MASTER_STA (1<<16) + +//IRQ_CLR +#define I2C_MASTER_IRQ_CLR (1<<0) + +#endif /* _REG_I2C_H_ */ + diff --git a/arch/arm/include/asm/arch-rda/reg_ifc.h b/arch/arm/include/asm/arch-rda/reg_ifc.h new file mode 100644 index 0000000000..f5b69ccf98 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_ifc.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_MACH_RDA8810 +#include "reg_ifc_v1.h" +#else +#include "reg_ifc_v3.h" +#endif diff --git a/arch/arm/include/asm/arch-rda/reg_ifc_v1.h b/arch/arm/include/asm/arch-rda/reg_ifc_v1.h new file mode 100644 index 0000000000..e37786fc5d --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_ifc_v1.h @@ -0,0 +1,106 @@ +#ifndef _REG_IFC_H_ +#define _REG_IFC_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= +#define SYS_IFC_ADDR_ALIGN (0) +#define SYS_IFC_TC_LEN (23) +#define SYS_IFC_STD_CHAN_NB 7 //(SYS_IFC_NB_STD_CHANNEL) +#define SYS_IFC_RFSPI_CHAN (1) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// SYS_IFC_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + REG32 get_ch; //0x00000000 + REG32 dma_status; //0x00000004 + REG32 debug_status; //0x00000008 + REG32 Reserved_0000000C; //0x0000000C + struct + { + REG32 control; //0x00000010 + REG32 status; //0x00000014 + REG32 start_addr; //0x00000018 + REG32 tc; //0x0000001C + } std_ch[SYS_IFC_STD_CHAN_NB]; + // REG32 Reserved_00000080; //0x00000080 + REG32 ch_rfspi_control; //0x00000080 + REG32 ch_rfspi_status; //0x00000084 + REG32 ch_rfspi_start_addr; //0x00000088 + REG32 ch_rfspi_end_addr; //0x0000008C + REG32 ch_rfspi_tc; //0x00000090 +} HWP_SYS_IFC_T; + +#define hwp_sysIfc ((HWP_SYS_IFC_T*)(RDA_IFC_BASE)) + + +//get_ch +#define SYS_IFC_CH_TO_USE(n) (((n)&15)<<0) +#define SYS_IFC_CH_TO_USE_MASK (15<<0) +#define SYS_IFC_CH_TO_USE_SHIFT (0) + +//dma_status +#define SYS_IFC_CH_ENABLE(n) (((n)&0xFF)<<0) +#define SYS_IFC_CH_BUSY(n) (((n)&0x7F)<<16) + +//debug_status +#define SYS_IFC_DBG_STATUS (1<<0) + +//control +#define SYS_IFC_ENABLE (1<<0) +#define SYS_IFC_DISABLE (1<<1) +#define SYS_IFC_CH_RD_HW_EXCH (1<<2) +#define SYS_IFC_CH_WR_HW_EXCH (1<<3) +#define SYS_IFC_AUTODISABLE (1<<4) +#define SYS_IFC_SIZE(n) (((n)&3)<<5) +#define SYS_IFC_SIZE_MASK (3<<5) +#define SYS_IFC_SIZE_SHIFT (5) +#define SYS_IFC_SIZE_BYTE (0<<5) +#define SYS_IFC_SIZE_HALF_WORD (1<<5) +#define SYS_IFC_SIZE_WORD (2<<5) +#define SYS_IFC_REQ_SRC(n) (((n)&31)<<8) +#define SYS_IFC_REQ_SRC_MASK (31<<8) +#define SYS_IFC_REQ_SRC_SHIFT (8) +#define SYS_IFC_FLUSH (1<<16) + +//status +//#define SYS_IFC_ENABLE (1<<0) +#define SYS_IFC_FIFO_EMPTY (1<<4) + +//start_addr +#define SYS_IFC_START_ADDR(n) (((n)&0x3FFFFFF)<<0) + +//tc +#define SYS_IFC_TC(n) (((n)&0x7FFFFF)<<0) + +//ch_rfspi_control +//#define SYS_IFC_ENABLE (1<<0) +//#define SYS_IFC_DISABLE (1<<1) + +//ch_rfspi_status +//#define SYS_IFC_ENABLE (1<<0) +//#define SYS_IFC_FIFO_EMPTY (1<<4) +#define SYS_IFC_FIFO_LEVEL(n) (((n)&31)<<8) + +//ch_rfspi_start_addr +#define SYS_IFC_START_AHB_ADDR(n) (((n)&0x3FFFFFF)<<0) + +//ch_rfspi_end_addr +#define SYS_IFC_END_AHB_ADDR(n) (((n)&0x3FFFFFF)<<0) + +//ch_rfspi_tc +//#define SYS_IFC_TC(n) (((n)&0x3FFF)<<0) + +#endif /* _REG_IFC_H_ */ + diff --git a/arch/arm/include/asm/arch-rda/reg_ifc_v3.h b/arch/arm/include/asm/arch-rda/reg_ifc_v3.h new file mode 100644 index 0000000000..ecbb137aba --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_ifc_v3.h @@ -0,0 +1,207 @@ +#ifndef _REG_IFC_H_ +#define _REG_IFC_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= +#define SYS_IFC_STD_CHAN_NB (8) //(SYS_IFC_NB_STD_CHANNEL) +#define SYS_IFC_STD_CHAN_NB_SCATTER (3) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// SYS_IFC_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + REG32 get_ch; //0x00000000 + REG32 dma_status; //0x00000004 + REG32 debug_status; //0x00000008 + REG32 Reserved_0000000C; //0x0000000C + union + { + struct + { + REG32 control; //0x00000010 + REG32 status; //0x00000014 + REG32 start_addr1; //0x00000018 + REG32 tc1; //0x0000001C + REG32 start_addr2; //0x00000020 + REG32 tc2; //0x00000024 + REG32 start_addr3; //0x00000028 + REG32 tc3; //0x0000002C + REG32 start_addr4; //0x00000030 + REG32 tc4; //0x00000034 + REG32 start_addr5; //0x00000038 + REG32 tc5; //0x0000003C + REG32 start_addr6; //0x00000040 + REG32 tc6; //0x00000044 + REG32 start_addr7; //0x00000048 + REG32 tc7; //0x0000004C + REG32 start_addr8; //0x00000050 + REG32 tc8; //0x00000054 + REG32 Reserved_00000048[14]; //0x00000048 + } std_ch_scatter[SYS_IFC_STD_CHAN_NB_SCATTER]; + struct + { + REG32 control; //0x00000190 + REG32 status; //0x00000194 + REG32 start_addr; //0x00000198 + REG32 tc; //0x0000019C + REG32 Reserved_00000010[28]; //0x00000010 + } std_ch[SYS_IFC_STD_CHAN_NB]; + }; +} HWP_SYS_IFC_T; + +#define hwp_sysIfc ((HWP_SYS_IFC_T*)(RDA_IFC_BASE)) + + +//get_ch +#define SYS_IFC_CH_TO_USE(n) (((n)&15)<<0) +#define SYS_IFC_CH_TO_USE_MASK (15<<0) +#define SYS_IFC_CH_TO_USE_SHIFT (0) + +//dma_status +#define SYS_IFC_CH_ENABLE(n) (((n)&0xFF)<<0) +#define SYS_IFC_CH_BUSY(n) (((n)&0x7F)<<16) + +//debug_status +#define SYS_IFC_DBG_STATUS (1<<0) + +//control +#define SYS_IFC_ENABLE (1<<0) +#define SYS_IFC_DISABLE (1<<1) +#define SYS_IFC_CH_RD_HW_EXCH (1<<2) +#define SYS_IFC_CH_WR_HW_EXCH (1<<3) +#define SYS_IFC_AUTODISABLE (1<<4) +#define SYS_IFC_SIZE(n) (((n)&3)<<5) +#define SYS_IFC_SIZE_MASK (3<<5) +#define SYS_IFC_SIZE_SHIFT (5) +#define SYS_IFC_SIZE_BYTE (0<<5) +#define SYS_IFC_SIZE_HALF_WORD (1<<5) +#define SYS_IFC_SIZE_WORD (2<<5) +#define SYS_IFC_REQ_SRC(n) (((n)&31)<<8) +#define SYS_IFC_REQ_SRC_MASK (31<<8) +#define SYS_IFC_REQ_SRC_SHIFT (8) +#define SYS_IFC_REQ_SRC_SYS_ID_TX_SCI1 (0<<8) +#define SYS_IFC_REQ_SRC_SYS_ID_RX_SCI1 (1<<8) +#define SYS_IFC_REQ_SRC_SYS_ID_TX_SCI2 (2<<8) +#define SYS_IFC_REQ_SRC_SYS_ID_RX_SCI2 (3<<8) +#define SYS_IFC_REQ_SRC_SYS_ID_TX_SCI3 (4<<8) +#define SYS_IFC_REQ_SRC_SYS_ID_RX_SCI3 (5<<8) +#define SYS_IFC_REQ_SRC_SYS_ID_TX_SPI1 (6<<8) +#define SYS_IFC_REQ_SRC_SYS_ID_RX_SPI1 (7<<8) +#define SYS_IFC_REQ_SRC_SYS_ID_TX_SPI2 (8<<8) +#define SYS_IFC_REQ_SRC_SYS_ID_RX_SPI2 (9<<8) +#define SYS_IFC_REQ_SRC_SYS_ID_TX_I2C (10<<8) +#define SYS_IFC_REQ_SRC_SYS_ID_RX_I2C (11<<8) +#define SYS_IFC_REQ_SRC_SYS_ID_TX_DEBUG_UART (12<<8) +#define SYS_IFC_REQ_SRC_SYS_ID_RX_DEBUG_UART (13<<8) +#define SYS_IFC_FLUSH (1<<16) +#define SYS_IFC_ADDR_CNT(n) (((n)&7)<<17) + +//status +//#define SYS_IFC_ENABLE (1<<0) +#define SYS_IFC_FIFO_EMPTY (1<<4) + +//start_addr1 +#define SYS_IFC_START_ADDR1(n) (((n)&0xFFFFFFFF)<<0) + +//tc1 +#define SYS_IFC_TC1(n) (((n)&0x7FFFFF)<<0) + +//start_addr2 +#define SYS_IFC_START_ADDR2(n) (((n)&0xFFFFFFFF)<<0) + +//tc2 +#define SYS_IFC_TC2(n) (((n)&0x7FFFFF)<<0) + +//start_addr3 +#define SYS_IFC_START_ADDR3(n) (((n)&0xFFFFFFFF)<<0) + +//tc3 +#define SYS_IFC_TC3(n) (((n)&0x7FFFFF)<<0) + +//start_addr4 +#define SYS_IFC_START_ADDR4(n) (((n)&0xFFFFFFFF)<<0) + +//tc4 +#define SYS_IFC_TC4(n) (((n)&0x7FFFFF)<<0) + +//start_addr5 +#define SYS_IFC_START_ADDR5(n) (((n)&0xFFFFFFFF)<<0) + +//tc5 +#define SYS_IFC_TC5(n) (((n)&0x7FFFFF)<<0) + +//start_addr6 +#define SYS_IFC_START_ADDR6(n) (((n)&0xFFFFFFFF)<<0) + +//tc6 +#define SYS_IFC_TC6(n) (((n)&0x7FFFFF)<<0) + +//start_addr7 +#define SYS_IFC_START_ADDR7(n) (((n)&0xFFFFFFFF)<<0) + +//tc7 +#define SYS_IFC_TC7(n) (((n)&0x7FFFFF)<<0) + +//start_addr8 +#define SYS_IFC_START_ADDR8(n) (((n)&0xFFFFFFFF)<<0) + +//tc8 +#define SYS_IFC_TC8(n) (((n)&0x7FFFFF)<<0) + +//control +//#define SYS_IFC_ENABLE (1<<0) +//#define SYS_IFC_DISABLE (1<<1) +//#define SYS_IFC_CH_RD_HW_EXCH (1<<2) +//#define SYS_IFC_CH_WR_HW_EXCH (1<<3) +//#define SYS_IFC_AUTODISABLE (1<<4) +//#define SYS_IFC_SIZE(n) (((n)&3)<<5) +//#define SYS_IFC_SIZE_MASK (3<<5) +//#define SYS_IFC_SIZE_SHIFT (5) +//#define SYS_IFC_SIZE_BYTE (0<<5) +//#define SYS_IFC_SIZE_HALF_WORD (1<<5) +//#define SYS_IFC_SIZE_WORD (2<<5) +//#define SYS_IFC_REQ_SRC(n) (((n)&31)<<8) +//#define SYS_IFC_REQ_SRC_MASK (31<<8) +//#define SYS_IFC_REQ_SRC_SHIFT (8) +//#define SYS_IFC_REQ_SRC_SYS_ID_TX_SCI1 (0<<8) +//#define SYS_IFC_REQ_SRC_SYS_ID_RX_SCI1 (1<<8) +//#define SYS_IFC_REQ_SRC_SYS_ID_TX_SCI2 (2<<8) +//#define SYS_IFC_REQ_SRC_SYS_ID_RX_SCI2 (3<<8) +//#define SYS_IFC_REQ_SRC_SYS_ID_TX_SCI3 (4<<8) +//#define SYS_IFC_REQ_SRC_SYS_ID_RX_SCI3 (5<<8) +//#define SYS_IFC_REQ_SRC_SYS_ID_TX_SPI1 (6<<8) +//#define SYS_IFC_REQ_SRC_SYS_ID_RX_SPI1 (7<<8) +//#define SYS_IFC_REQ_SRC_SYS_ID_TX_SPI2 (8<<8) +//#define SYS_IFC_REQ_SRC_SYS_ID_RX_SPI2 (9<<8) +//#define SYS_IFC_REQ_SRC_SYS_ID_TX_I2C (10<<8) +//#define SYS_IFC_REQ_SRC_SYS_ID_RX_I2C (11<<8) +//#define SYS_IFC_REQ_SRC_SYS_ID_TX_DEBUG_UART (12<<8) +//#define SYS_IFC_REQ_SRC_SYS_ID_RX_DEBUG_UART (13<<8) +//#define SYS_IFC_FLUSH (1<<16) + +//status +//#define SYS_IFC_ENABLE (1<<0) +//#define SYS_IFC_FIFO_EMPTY (1<<4) + +//start_addr +#define SYS_IFC_START_ADDR(n) (((n)&0xFFFFFFFF)<<0) + +//tc +#define SYS_IFC_TC(n) (((n)&0x7FFFFF)<<0) + + + + +#endif /* _REG_IFC_H_ */ + diff --git a/arch/arm/include/asm/arch-rda/reg_keypad.h b/arch/arm/include/asm/arch-rda/reg_keypad.h new file mode 100644 index 0000000000..24ccb1c53f --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_keypad.h @@ -0,0 +1,89 @@ +#ifndef _KEYPAD_H_ +#define _KEYPAD_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + + + +// ============================================================================= +// MACROS +// ============================================================================= +/// Number of key in the keypad +#define KEY_NB (64) +/// Number of key in the low data register +#define LOW_KEY_NB (32) +/// Number of key in the high data register +#define HIGH_KEY_NB (32) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// KEYPAD_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= + +typedef volatile struct +{ + REG32 KP_DATA_L; //0x00000000 + REG32 KP_DATA_H; //0x00000004 + REG32 KP_STATUS; //0x00000008 + REG32 KP_CTRL; //0x0000000C + REG32 KP_IRQ_MASK; //0x00000010 + REG32 KP_IRQ_CAUSE; //0x00000014 + REG32 KP_IRQ_CLR; //0x00000018 +} HWP_KEYPAD_T; + +#define hwp_apKeypad ((HWP_KEYPAD_T*) (RDA_KEYPAD_BASE)) + + +//KP_DATA_L +#define KEYPAD_KP_DATA_L(n) (((n)&0xFFFFFFFF)<<0) +#define KEYPAD_KP_DATA_L_MASK (0xFFFFFFFF<<0) +#define KEYPAD_KP_DATA_L_SHIFT (0) + +//KP_DATA_H +#define KEYPAD_KP_DATA_H(n) (((n)&0xFFFFFFFF)<<0) +#define KEYPAD_KP_DATA_H_MASK (0xFFFFFFFF<<0) +#define KEYPAD_KP_DATA_H_SHIFT (0) + +//KP_STATUS +#define KEYPAD_KEYIN_STATUS(n) (((n)&0xFF)<<0) +#define KEYPAD_KEYIN_STATUS_MASK (0xFF<<0) +#define KEYPAD_KEYIN_STATUS_SHIFT (0) +#define KEYPAD_KP_ON (1<<31) +#define KEYPAD_KP_ON_MASK (1<<31) +#define KEYPAD_KP_ON_SHIFT (31) + +//KP_CTRL +#define KEYPAD_KP_EN (1<<0) +#define KEYPAD_KP_DBN_TIME(n) (((n)&0xFF)<<2) +#define KEYPAD_KP_ITV_TIME(n) (((n)&0x3F)<<10) +#define KEYPAD_KP_IN_MASK(n) (((n)&0xFF)<<16) +#define KEYPAD_KP_OUT_MASK(n) (((n)&0xFF)<<24) + +//KP_IRQ_MASK +#define KEYPAD_KP_EVT0_IRQ_MASK (1<<0) +#define KEYPAD_KP_EVT1_IRQ_MASK (1<<1) +#define KEYPAD_KP_ITV_IRQ_MASK (1<<2) + +//KP_IRQ_CAUSE +#define KEYPAD_KP_EVT0_IRQ_CAUSE (1<<0) +#define KEYPAD_KP_EVT1_IRQ_CAUSE (1<<1) +#define KEYPAD_KP_ITV_IRQ_CAUSE (1<<2) +#define KEYPAD_KP_EVT0_IRQ_STATUS (1<<16) +#define KEYPAD_KP_EVT1_IRQ_STATUS (1<<17) +#define KEYPAD_KP_ITV_IRQ_STATUS (1<<18) + +//KP_IRQ_CLR +#define KEYPAD_KP_IRQ_CLR (1<<0) + + + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl.h new file mode 100644 index 0000000000..1512065c2e --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl.h @@ -0,0 +1,16 @@ +#ifdef CONFIG_MACH_RDA8810 +#include "reg_md_sysctrl_rda8810.h" +#elif defined(CONFIG_MACH_RDA8810E) +#include "reg_md_sysctrl_rda8810e.h" +#elif defined(CONFIG_MACH_RDA8820) +#include "reg_md_sysctrl_rda8820.h" +#elif defined(CONFIG_MACH_RDA8850) +#include "reg_md_sysctrl_rda8850.h" +#elif defined(CONFIG_MACH_RDA8850E) +#include "reg_md_sysctrl_rda8850e.h" +#elif defined(CONFIG_MACH_RDA8810H) +#include "reg_md_sysctrl_rda8810h.h" +#else +#error "unknown MACH" +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810.h new file mode 100644 index 0000000000..efae979e5f --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810.h @@ -0,0 +1,958 @@ +#ifndef _REG_MD_SYSCTRL_H_ +#define _REG_MD_SYSCTRL_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= + +// ============================================================================ +// CPU_ID_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// CPU IDs + XCPU = 0x00000000, + BCPU = 0x00000001 +} CPU_ID_T; + + +// ============================================================================ +// SYS_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// System side System clocks + SYS_XCPU = 0x00000000, + SYS_XCPU_INT = 0x00000001, + SYS_PCLK_CONF = 0x00000002, + SYS_PCLK_DATA = 0x00000003, + SYS_AMBA = 0x00000004, + SYS_DMA = 0x00000005, + SYS_EBC = 0x00000006, + SYS_IFC_CH0 = 0x00000007, + SYS_IFC_CH1 = 0x00000008, + SYS_IFC_CH2 = 0x00000009, + SYS_IFC_CH3 = 0x0000000A, + SYS_IFC_DBG = 0x0000000B, + SYS_A2A = 0x0000000C, + SYS_AXI2AHB = 0x0000000D, + SYS_AHB2AXI = 0x0000000E, + SYS_EXT_AHB = 0x0000000F, + SYS_DEBUG_UART = 0x00000010, + SYS_DBGHST = 0x00000011, +/// System side divided clock (either divided by module or by sys_ctrl) + SYSD_SCI1 = 0x00000012, + SYSD_SCI2 = 0x00000013, + SYSD_SCI3 = 0x00000014, + SYSD_RF_SPI = 0x00000015, + SYSD_OSC = 0x00000016, +/// the following don't have an auto enable + SYS_GPIO = 0x00000017, + SYS_IRQ = 0x00000018, + SYS_TCU = 0x00000019, + SYS_TIMER = 0x0000001A, + SYS_COM_REGS = 0x0000001B, + SYS_DP_AP = 0x0000001C, +/// the following are sharing their enable + SYS_SCI1 = 0x0000001D, + SYS_SCI2 = 0x0000001E, + SYS_SCI3 = 0x0000001F, +/// keep last + SYS_NOGATE = 0x00000020 +} SYS_CLKS_T; + +#define NB_SYS_CLK_XCPU (2) +#define NB_SYS_CLK_AEN (23) +#define NB_SYS_CLK_EN (29) +#define NB_SYS_CLK (33) + +// ============================================================================ +// PER_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// System side divided clock (either divided by module or by sys_ctrl) + PERD_SPI1 = 0x00000000, +/// System side divided clock (either divided by module or by sys_ctrl) + PERD_SPI2 = 0x00000001, + PER_SPY = 0x00000002, + PER_TEST = 0x00000003 +} PER_CLKS_T; + +#define NB_PER_CLK_AEN (2) +#define NB_PER_CLK_EN (4) +#define NB_PER_CLK (4) + +// ============================================================================ +// BB_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// Baseband side System clocks + BB_BCPU = 0x00000000, + BB_BCPU_INT = 0x00000001, + BB_AMBA = 0x00000002, + BB_PCLK_CONF = 0x00000003, + BB_PCLK_DATA = 0x00000004, + BB_EXCOR = 0x00000005, + BB_IFC_CH2 = 0x00000006, + BB_IFC_CH3 = 0x00000007, + BB_SRAM = 0x00000008, + BB_A2A = 0x00000009, + BB_ITLV = 0x0000000A, + BB_VITERBI = 0x0000000B, + BB_CIPHER = 0x0000000C, + BB_RF_IF = 0x0000000D, + BB_COPRO = 0x0000000E, + BB_CP2_REG = 0x0000000F, + BB_XCOR = 0x00000010, + BB_EVITAC = 0x00000011, +/// the following don't have an auto enable + BB_IRQ = 0x00000012, + BB_COM_REGS = 0x00000013, + BB_CORDIC = 0x00000014 +} BB_CLKS_T; + +#define NB_BB_CLK_AEN (18) +#define NB_BB_CLK_EN (21) +#define NB_BB_CLK (21) +/// Other clocks +/// clocks with auto enble +/// the debug host clock auto enable is not used in host mode, only in uart mode +#define OC_HOST_UART (0) + +// ============================================================================ +// OTHER_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ + OC_DEBUG_UART = 0x00000000, + OC_RF_RX = 0x00000001, + OC_RF_TX = 0x00000002, + OC_MEM_BRIDGE = 0x00000003, +/// the following don't have an auto enable + OC_LPS = 0x00000004, + OC_GPIO = 0x00000005, + OC_CLK_OUT = 0x00000006, + OC_MEM_CLK_OUT = 0x00000007, + OC_TCU = 0x00000008 +} OTHER_CLKS_T; + +#define NB_OTHER_CLK_AEN (4) +#define NB_OTHER_CLK_EN (9) +#define NB_OTHER_CLK (9) + +// ============================================================================ +// RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// System side resets + RST_XCPU = 0x00000000, + RST_SYS_IRQ = 0x00000001, + RST_SYS_A2A = 0x00000002, + RST_SYS_AHB2AXI = 0x00000003, + RST_SYS_AXI2AHB = 0x00000004, + RST_DMA = 0x00000005, + RST_TIMER = 0x00000006, + RST_TCU = 0x00000007, + RST_GPIO = 0x00000008, + RST_CFG = 0x00000009, + RST_SPI1 = 0x0000000A, + RST_SPI2 = 0x0000000B, + RST_RF_SPI = 0x0000000C, + RST_SCI1 = 0x0000000D, + RST_SCI2 = 0x0000000E, + RST_SCI3 = 0x0000000F, + RST_SPY = 0x00000010, + RST_MEM_BRIDGE = 0x00000011, + RST_EXT_AHB = 0x00000012, + RST_DP_AP = 0x00000013, + RST_COMREGS = 0x00000014, + RST_COMREGS_AP = 0x00000015, + RST_AP_CLKEN = 0x00000016, + RST_AP_RST = 0x00000017, + RST_MEM_CHK = 0x00000018, + RST_BCPU = 0x00000019, + RST_BB_IRQ = 0x0000001A, + RST_BB_A2A = 0x0000001B, + RST_BB_IFC = 0x0000001C, + RST_BB_SRAM = 0x0000001D, + RST_ITLV = 0x0000001E, + RST_VITERBI = 0x0000001F, + RST_CIPHER = 0x00000020, + RST_XCOR = 0x00000021, + RST_COPRO = 0x00000022, + RST_RF_IF = 0x00000023, + RST_EXCOR = 0x00000024, + RST_EVITAC = 0x00000025, + RST_CORDIC = 0x00000026, + RST_TCU_BB = 0x00000027, + RST_BB_FULL = 0x00000028, + RST_SYS_FULL = 0x00000029 +} RESETS_T; + +#define NB_SRST (25) +/// Baseband side resets +#define BOUND_BRST_FIRST (25) +#define BOUND_BRST_AFTER (40) +/// The following reset does not have register +#define NR_RST_REG (41) +#define NB_RST (42) +#define NB_BRST (BOUND_BRST_AFTER-BOUND_BRST_FIRST) + +// ============================================================================ +// RESET_OTHERS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// Reset Other : resync on corresponding clock other + RSTO_DBG_HOST = 0x00000000, + RSTO_RF_RX = 0x00000001, + RSTO_RF_TX = 0x00000002, + RSTO_MEM_BRIDGE = 0x00000003, + RSTO_LPS = 0x00000004, + RSTO_GPIO = 0x00000005, + RSTO_WDTIMER = 0x00000006, + RSTO_TCU = 0x00000007 +} RESET_OTHERS_T; + +#define BOUND_RSTO_RF_FIRST (1) +#define BOUND_RSTO_RF_AFTER (3) +#define NB_RSTO (8) +/// For REG_DBG protect lock/unlock value +#define SYS_CTRL_PROTECT_LOCK (0XA50000) +#define SYS_CTRL_PROTECT_UNLOCK (0XA50001) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// SYS_CTRL_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + /// <strong>This register is used to Lock and Unlock the protected registers.</strong> + REG32 REG_DBG; //0x00000000 + /// This register is protected. + REG32 Sys_Rst_Set; //0x00000004 + REG32 Sys_Rst_Clr; //0x00000008 + /// This register is protected. + REG32 BB_Rst_Set; //0x0000000C + REG32 BB_Rst_Clr; //0x00000010 + REG32 Clk_Sys_Mode; //0x00000014 + REG32 Clk_Sys_Enable; //0x00000018 + /// This register is protected. + REG32 Clk_Sys_Disable; //0x0000001C + REG32 Clk_Per_Mode; //0x00000020 + REG32 Clk_Per_Enable; //0x00000024 + /// This register is protected. + REG32 Clk_Per_Disable; //0x00000028 + REG32 Clk_BB_Mode; //0x0000002C + REG32 Clk_BB_Enable; //0x00000030 + /// This register is protected. + REG32 Clk_BB_Disable; //0x00000034 + REG32 Clk_Other_Mode; //0x00000038 + REG32 Clk_Other_Enable; //0x0000003C + /// This register is protected. + REG32 Clk_Other_Disable; //0x00000040 + /// Register protected by Write_Unlocked_H. + REG32 Pll_Ctrl; //0x00000044 + /// This register is protected. + REG32 Sel_Clock; //0x00000048 + REG32 Cfg_Clk_Sys; //0x0000004C + REG32 Cfg_Clk_Mem_Bridge; //0x00000050 + /// This register is protected. + REG32 Cfg_Clk_Out; //0x00000054 + REG32 Cfg_Clk_Host_Uart; //0x00000058 + REG32 Cfg_Clk_Auxclk; //0x0000005C + /// This register is protected. + REG32 Cfg_AHB; //0x00000060 + /// This register is protected. Used to unsplit masters manualy. + REG32 Ctrl_AHB; //0x00000064 + REG32 XCpu_Dbg_BKP; //0x00000068 + REG32 XCpu_Dbg_Addr; //0x0000006C + REG32 BCpu_Dbg_BKP; //0x00000070 + REG32 BCpu_Dbg_Addr; //0x00000074 + REG32 Cfg_Cpus_Cache_Ram_Disable; //0x00000078 + REG32 Reset_Cause; //0x0000007C + /// This register is protected. + REG32 WakeUp; //0x00000080 + REG32 AP_Ctrl; //0x00000084 + /// This register is protected. + REG32 Ignore_Charger; //0x00000088 + REG32 Reserved_0000008C[28]; //0x0000008C + /// This register is reserved. + REG32 Cfg_Reserve; //0x000000FC +} HWP_SYS_CTRL_T; + +#define hwp_sysCtrlMd ((HWP_SYS_CTRL_T*)(RDA_MD_SYSCTRL_BASE)) + + +//REG_DBG +#define SYS_CTRL_SCRATCH(n) (((n)&0xFFFF)<<0) +#define SYS_CTRL_WRITE_UNLOCK_STATUS (1<<30) +#define SYS_CTRL_WRITE_UNLOCK (1<<31) + +//Sys_Rst_Set +#define SYS_CTRL_SET_RST_XCPU (1<<0) +#define SYS_CTRL_SET_RST_SYS_IRQ (1<<1) +#define SYS_CTRL_SET_RST_SYS_A2A (1<<2) +#define SYS_CTRL_SET_RST_SYS_AHB2AXI (1<<3) +#define SYS_CTRL_SET_RST_SYS_AXI2AHB (1<<4) +#define SYS_CTRL_SET_RST_DMA (1<<5) +#define SYS_CTRL_SET_RST_TIMER (1<<6) +#define SYS_CTRL_SET_RST_TCU (1<<7) +#define SYS_CTRL_SET_RST_GPIO (1<<8) +#define SYS_CTRL_SET_RST_CFG (1<<9) +#define SYS_CTRL_SET_RST_SPI1 (1<<10) +#define SYS_CTRL_SET_RST_SPI2 (1<<11) +#define SYS_CTRL_SET_RST_RF_SPI (1<<12) +#define SYS_CTRL_SET_RST_SCI1 (1<<13) +#define SYS_CTRL_SET_RST_SCI2 (1<<14) +#define SYS_CTRL_SET_RST_SCI3 (1<<15) +#define SYS_CTRL_SET_RST_SPY (1<<16) +#define SYS_CTRL_SET_RST_MEM_BRIDGE (1<<17) +#define SYS_CTRL_SET_RST_EXT_AHB (1<<18) +#define SYS_CTRL_SET_RST_DP_AP (1<<19) +#define SYS_CTRL_SET_RST_COMREGS (1<<20) +#define SYS_CTRL_SET_RST_COMREGS_AP (1<<21) +#define SYS_CTRL_SET_RST_AP_CLKEN (1<<22) +#define SYS_CTRL_SET_RST_AP_RST (1<<23) +#define SYS_CTRL_SET_RST_MEM_CHK (1<<24) +#define SYS_CTRL_SET_RST_OUT (1<<30) +#define SYS_CTRL_SOFT_RST (1<<31) +#define SYS_CTRL_SET_SYS_RST(n) (((n)&0x1FFFFFF)<<0) +#define SYS_CTRL_SET_SYS_RST_MASK (0x1FFFFFF<<0) +#define SYS_CTRL_SET_SYS_RST_SHIFT (0) + +//Sys_Rst_Clr +#define SYS_CTRL_CLR_RST_XCPU (1<<0) +#define SYS_CTRL_CLR_RST_SYS_IRQ (1<<1) +#define SYS_CTRL_CLR_RST_SYS_A2A (1<<2) +#define SYS_CTRL_CLR_RST_SYS_AHB2AXI (1<<3) +#define SYS_CTRL_CLR_RST_SYS_AXI2AHB (1<<4) +#define SYS_CTRL_CLR_RST_DMA (1<<5) +#define SYS_CTRL_CLR_RST_TIMER (1<<6) +#define SYS_CTRL_CLR_RST_TCU (1<<7) +#define SYS_CTRL_CLR_RST_GPIO (1<<8) +#define SYS_CTRL_CLR_RST_CFG (1<<9) +#define SYS_CTRL_CLR_RST_SPI1 (1<<10) +#define SYS_CTRL_CLR_RST_SPI2 (1<<11) +#define SYS_CTRL_CLR_RST_RF_SPI (1<<12) +#define SYS_CTRL_CLR_RST_SCI1 (1<<13) +#define SYS_CTRL_CLR_RST_SCI2 (1<<14) +#define SYS_CTRL_CLR_RST_SCI3 (1<<15) +#define SYS_CTRL_CLR_RST_SPY (1<<16) +#define SYS_CTRL_CLR_RST_MEM_BRIDGE (1<<17) +#define SYS_CTRL_CLR_RST_EXT_AHB (1<<18) +#define SYS_CTRL_CLR_RST_DP_AP (1<<19) +#define SYS_CTRL_CLR_RST_COMREGS (1<<20) +#define SYS_CTRL_CLR_RST_COMREGS_AP (1<<21) +#define SYS_CTRL_CLR_RST_AP_CLKEN (1<<22) +#define SYS_CTRL_CLR_RST_AP_RST (1<<23) +#define SYS_CTRL_CLR_RST_MEM_CHK (1<<24) +#define SYS_CTRL_CLR_RST_OUT (1<<30) +#define SYS_CTRL_CLR_SYS_RST(n) (((n)&0x1FFFFFF)<<0) +#define SYS_CTRL_CLR_SYS_RST_MASK (0x1FFFFFF<<0) +#define SYS_CTRL_CLR_SYS_RST_SHIFT (0) + +//BB_Rst_Set +#define SYS_CTRL_SET_RST_BCPU (1<<0) +#define SYS_CTRL_SET_RST_BB_IRQ (1<<1) +#define SYS_CTRL_SET_RST_BB_A2A (1<<2) +#define SYS_CTRL_SET_RST_BB_IFC (1<<3) +#define SYS_CTRL_SET_RST_BB_SRAM (1<<4) +#define SYS_CTRL_SET_RST_ITLV (1<<5) +#define SYS_CTRL_SET_RST_VITERBI (1<<6) +#define SYS_CTRL_SET_RST_CIPHER (1<<7) +#define SYS_CTRL_SET_RST_XCOR (1<<8) +#define SYS_CTRL_SET_RST_COPRO (1<<9) +#define SYS_CTRL_SET_RST_RF_IF (1<<10) +#define SYS_CTRL_SET_RST_EXCOR (1<<11) +#define SYS_CTRL_SET_RST_EVITAC (1<<12) +#define SYS_CTRL_SET_RST_CORDIC (1<<13) +#define SYS_CTRL_SET_RST_TCU_BB (1<<14) +#define SYS_CTRL_SET_RST_BB_FULL (1<<31) +#define SYS_CTRL_SET_BB_RST(n) (((n)&0x7FFF)<<0) +#define SYS_CTRL_SET_BB_RST_MASK (0x7FFF<<0) +#define SYS_CTRL_SET_BB_RST_SHIFT (0) + +//BB_Rst_Clr +#define SYS_CTRL_CLR_RST_BCPU (1<<0) +#define SYS_CTRL_CLR_RST_BB_IRQ (1<<1) +#define SYS_CTRL_CLR_RST_BB_A2A (1<<2) +#define SYS_CTRL_CLR_RST_BB_IFC (1<<3) +#define SYS_CTRL_CLR_RST_BB_SRAM (1<<4) +#define SYS_CTRL_CLR_RST_ITLV (1<<5) +#define SYS_CTRL_CLR_RST_VITERBI (1<<6) +#define SYS_CTRL_CLR_RST_CIPHER (1<<7) +#define SYS_CTRL_CLR_RST_XCOR (1<<8) +#define SYS_CTRL_CLR_RST_COPRO (1<<9) +#define SYS_CTRL_CLR_RST_RF_IF (1<<10) +#define SYS_CTRL_CLR_RST_EXCOR (1<<11) +#define SYS_CTRL_CLR_RST_EVITAC (1<<12) +#define SYS_CTRL_CLR_RST_CORDIC (1<<13) +#define SYS_CTRL_CLR_RST_TCU_BB (1<<14) +#define SYS_CTRL_CLR_RST_BB_FULL (1<<31) +#define SYS_CTRL_CLR_BB_RST(n) (((n)&0x7FFF)<<0) +#define SYS_CTRL_CLR_BB_RST_MASK (0x7FFF<<0) +#define SYS_CTRL_CLR_BB_RST_SHIFT (0) + +//Clk_Sys_Mode +#define SYS_CTRL_MODE_SYS_XCPU (1<<0) +#define SYS_CTRL_MODE_SYS_XCPU_INT_AUTOMATIC (0<<1) +#define SYS_CTRL_MODE_SYS_XCPU_INT_MANUAL (1<<1) +#define SYS_CTRL_MODE_SYS_PCLK_CONF_AUTOMATIC (0<<2) +#define SYS_CTRL_MODE_SYS_PCLK_CONF_MANUAL (1<<2) +#define SYS_CTRL_MODE_SYS_PCLK_DATA_AUTOMATIC (0<<3) +#define SYS_CTRL_MODE_SYS_PCLK_DATA_MANUAL (1<<3) +#define SYS_CTRL_MODE_SYS_AMBA_AUTOMATIC (0<<4) +#define SYS_CTRL_MODE_SYS_AMBA_MANUAL (1<<4) +#define SYS_CTRL_MODE_SYS_DMA_AUTOMATIC (0<<5) +#define SYS_CTRL_MODE_SYS_DMA_MANUAL (1<<5) +#define SYS_CTRL_MODE_SYS_EBC_AUTOMATIC (0<<6) +#define SYS_CTRL_MODE_SYS_EBC_MANUAL (1<<6) +#define SYS_CTRL_MODE_SYS_IFC_CH0_AUTOMATIC (0<<7) +#define SYS_CTRL_MODE_SYS_IFC_CH0_MANUAL (1<<7) +#define SYS_CTRL_MODE_SYS_IFC_CH1_AUTOMATIC (0<<8) +#define SYS_CTRL_MODE_SYS_IFC_CH1_MANUAL (1<<8) +#define SYS_CTRL_MODE_SYS_IFC_CH2_AUTOMATIC (0<<9) +#define SYS_CTRL_MODE_SYS_IFC_CH2_MANUAL (1<<9) +#define SYS_CTRL_MODE_SYS_IFC_CH3_AUTOMATIC (0<<10) +#define SYS_CTRL_MODE_SYS_IFC_CH3_MANUAL (1<<10) +#define SYS_CTRL_MODE_SYS_IFC_DBG_AUTOMATIC (0<<11) +#define SYS_CTRL_MODE_SYS_IFC_DBG_MANUAL (1<<11) +#define SYS_CTRL_MODE_SYS_A2A_AUTOMATIC (0<<12) +#define SYS_CTRL_MODE_SYS_A2A_MANUAL (1<<12) +#define SYS_CTRL_MODE_SYS_AXI2AHB_AUTOMATIC (0<<13) +#define SYS_CTRL_MODE_SYS_AXI2AHB_MANUAL (1<<13) +#define SYS_CTRL_MODE_SYS_AHB2AXI_AUTOMATIC (0<<14) +#define SYS_CTRL_MODE_SYS_AHB2AXI_MANUAL (1<<14) +#define SYS_CTRL_MODE_SYS_EXT_AHB_AUTOMATIC (0<<15) +#define SYS_CTRL_MODE_SYS_EXT_AHB_MANUAL (1<<15) +#define SYS_CTRL_MODE_SYS_DEBUG_UART_AUTOMATIC (0<<16) +#define SYS_CTRL_MODE_SYS_DEBUG_UART_MANUAL (1<<16) +#define SYS_CTRL_MODE_SYS_DBGHST_AUTOMATIC (0<<17) +#define SYS_CTRL_MODE_SYS_DBGHST_MANUAL (1<<17) +#define SYS_CTRL_MODE_SYSD_SCI1_AUTOMATIC (0<<18) +#define SYS_CTRL_MODE_SYSD_SCI1_MANUAL (1<<18) +#define SYS_CTRL_MODE_SYSD_SCI2_AUTOMATIC (0<<19) +#define SYS_CTRL_MODE_SYSD_SCI2_MANUAL (1<<19) +#define SYS_CTRL_MODE_SYSD_SCI3_AUTOMATIC (0<<20) +#define SYS_CTRL_MODE_SYSD_SCI3_MANUAL (1<<20) +#define SYS_CTRL_MODE_SYSD_RF_SPI_AUTOMATIC (0<<21) +#define SYS_CTRL_MODE_SYSD_RF_SPI_MANUAL (1<<21) +#define SYS_CTRL_MODE_SYSD_OSC_AUTOMATIC (0<<22) +#define SYS_CTRL_MODE_SYSD_OSC_MANUAL (1<<22) +#define SYS_CTRL_MODE_CLK_SYS(n) (((n)&0x3FFFFF)<<1) +#define SYS_CTRL_MODE_CLK_SYS_MASK (0x3FFFFF<<1) +#define SYS_CTRL_MODE_CLK_SYS_SHIFT (1) + +//Clk_Sys_Enable +#define SYS_CTRL_ENABLE_SYS_XCPU (1<<0) +#define SYS_CTRL_ENABLE_SYS_XCPU_INT (1<<1) +#define SYS_CTRL_ENABLE_SYS_PCLK_CONF (1<<2) +#define SYS_CTRL_ENABLE_SYS_PCLK_DATA (1<<3) +#define SYS_CTRL_ENABLE_SYS_AMBA (1<<4) +#define SYS_CTRL_ENABLE_SYS_DMA (1<<5) +#define SYS_CTRL_ENABLE_SYS_EBC (1<<6) +#define SYS_CTRL_ENABLE_SYS_IFC_CH0 (1<<7) +#define SYS_CTRL_ENABLE_SYS_IFC_CH1 (1<<8) +#define SYS_CTRL_ENABLE_SYS_IFC_CH2 (1<<9) +#define SYS_CTRL_ENABLE_SYS_IFC_CH3 (1<<10) +#define SYS_CTRL_ENABLE_SYS_IFC_DBG (1<<11) +#define SYS_CTRL_ENABLE_SYS_A2A (1<<12) +#define SYS_CTRL_ENABLE_SYS_AXI2AHB (1<<13) +#define SYS_CTRL_ENABLE_SYS_AHB2AXI (1<<14) +#define SYS_CTRL_ENABLE_SYS_EXT_AHB (1<<15) +#define SYS_CTRL_ENABLE_SYS_DEBUG_UART (1<<16) +#define SYS_CTRL_ENABLE_SYS_DBGHST (1<<17) +#define SYS_CTRL_ENABLE_SYSD_SCI1 (1<<18) +#define SYS_CTRL_ENABLE_SYSD_SCI2 (1<<19) +#define SYS_CTRL_ENABLE_SYSD_SCI3 (1<<20) +#define SYS_CTRL_ENABLE_SYSD_RF_SPI (1<<21) +#define SYS_CTRL_ENABLE_SYSD_OSC (1<<22) +#define SYS_CTRL_ENABLE_SYS_GPIO (1<<23) +#define SYS_CTRL_ENABLE_SYS_IRQ (1<<24) +#define SYS_CTRL_ENABLE_SYS_TCU (1<<25) +#define SYS_CTRL_ENABLE_SYS_TIMER (1<<26) +#define SYS_CTRL_ENABLE_SYS_COM_REGS (1<<27) +#define SYS_CTRL_ENABLE_SYS_DP_AP (1<<28) +#define SYS_CTRL_ENABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0) +#define SYS_CTRL_ENABLE_CLK_SYS_MASK (0x1FFFFFFF<<0) +#define SYS_CTRL_ENABLE_CLK_SYS_SHIFT (0) + +//Clk_Sys_Disable +#define SYS_CTRL_DISABLE_SYS_XCPU (1<<0) +#define SYS_CTRL_DISABLE_SYS_XCPU_INT (1<<1) +#define SYS_CTRL_DISABLE_SYS_PCLK_CONF (1<<2) +#define SYS_CTRL_DISABLE_SYS_PCLK_DATA (1<<3) +#define SYS_CTRL_DISABLE_SYS_AMBA (1<<4) +#define SYS_CTRL_DISABLE_SYS_DMA (1<<5) +#define SYS_CTRL_DISABLE_SYS_EBC (1<<6) +#define SYS_CTRL_DISABLE_SYS_IFC_CH0 (1<<7) +#define SYS_CTRL_DISABLE_SYS_IFC_CH1 (1<<8) +#define SYS_CTRL_DISABLE_SYS_IFC_CH2 (1<<9) +#define SYS_CTRL_DISABLE_SYS_IFC_CH3 (1<<10) +#define SYS_CTRL_DISABLE_SYS_IFC_DBG (1<<11) +#define SYS_CTRL_DISABLE_SYS_A2A (1<<12) +#define SYS_CTRL_DISABLE_SYS_AXI2AHB (1<<13) +#define SYS_CTRL_DISABLE_SYS_AHB2AXI (1<<14) +#define SYS_CTRL_DISABLE_SYS_EXT_AHB (1<<15) +#define SYS_CTRL_DISABLE_SYS_DEBUG_UART (1<<16) +#define SYS_CTRL_DISABLE_SYS_DBGHST (1<<17) +#define SYS_CTRL_DISABLE_SYSD_SCI1 (1<<18) +#define SYS_CTRL_DISABLE_SYSD_SCI2 (1<<19) +#define SYS_CTRL_DISABLE_SYSD_SCI3 (1<<20) +#define SYS_CTRL_DISABLE_SYSD_RF_SPI (1<<21) +#define SYS_CTRL_DISABLE_SYSD_OSC (1<<22) +#define SYS_CTRL_DISABLE_SYS_GPIO (1<<23) +#define SYS_CTRL_DISABLE_SYS_IRQ (1<<24) +#define SYS_CTRL_DISABLE_SYS_TCU (1<<25) +#define SYS_CTRL_DISABLE_SYS_TIMER (1<<26) +#define SYS_CTRL_DISABLE_SYS_COM_REGS (1<<27) +#define SYS_CTRL_DISABLE_SYS_DP_AP (1<<28) +#define SYS_CTRL_DISABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0) +#define SYS_CTRL_DISABLE_CLK_SYS_MASK (0x1FFFFFFF<<0) +#define SYS_CTRL_DISABLE_CLK_SYS_SHIFT (0) + +//Clk_Per_Mode +#define SYS_CTRL_MODE_PERD_SPI1_AUTOMATIC (0<<0) +#define SYS_CTRL_MODE_PERD_SPI1_MANUAL (1<<0) +#define SYS_CTRL_MODE_PERD_SPI2_AUTOMATIC (0<<1) +#define SYS_CTRL_MODE_PERD_SPI2_MANUAL (1<<1) +#define SYS_CTRL_MODE_CLK_PER(n) (((n)&3)<<0) +#define SYS_CTRL_MODE_CLK_PER_MASK (3<<0) +#define SYS_CTRL_MODE_CLK_PER_SHIFT (0) + +//Clk_Per_Enable +#define SYS_CTRL_ENABLE_PERD_SPI1 (1<<0) +#define SYS_CTRL_ENABLE_PERD_SPI2 (1<<1) +#define SYS_CTRL_ENABLE_PER_SPY (1<<2) +#define SYS_CTRL_ENABLE_PER_TEST (1<<3) +#define SYS_CTRL_ENABLE_CLK_PER(n) (((n)&15)<<0) +#define SYS_CTRL_ENABLE_CLK_PER_MASK (15<<0) +#define SYS_CTRL_ENABLE_CLK_PER_SHIFT (0) + +//Clk_Per_Disable +#define SYS_CTRL_DISABLE_PERD_SPI1 (1<<0) +#define SYS_CTRL_DISABLE_PERD_SPI2 (1<<1) +#define SYS_CTRL_DISABLE_PER_SPY (1<<2) +#define SYS_CTRL_DISABLE_PER_TEST (1<<3) +#define SYS_CTRL_DISABLE_CLK_PER(n) (((n)&15)<<0) +#define SYS_CTRL_DISABLE_CLK_PER_MASK (15<<0) +#define SYS_CTRL_DISABLE_CLK_PER_SHIFT (0) + +//Clk_BB_Mode +#define SYS_CTRL_MODE_BB_BCPU (1<<0) +#define SYS_CTRL_MODE_BB_BCPU_INT_AUTOMATIC (0<<1) +#define SYS_CTRL_MODE_BB_BCPU_INT_MANUAL (1<<1) +#define SYS_CTRL_MODE_BB_AMBA_AUTOMATIC (0<<2) +#define SYS_CTRL_MODE_BB_AMBA_MANUAL (1<<2) +#define SYS_CTRL_MODE_BB_PCLK_CONF_AUTOMATIC (0<<3) +#define SYS_CTRL_MODE_BB_PCLK_CONF_MANUAL (1<<3) +#define SYS_CTRL_MODE_BB_PCLK_DATA_AUTOMATIC (0<<4) +#define SYS_CTRL_MODE_BB_PCLK_DATA_MANUAL (1<<4) +#define SYS_CTRL_MODE_BB_EXCOR_AUTOMATIC (0<<5) +#define SYS_CTRL_MODE_BB_EXCOR_MANUAL (1<<5) +#define SYS_CTRL_MODE_BB_IFC_CH2_AUTOMATIC (0<<6) +#define SYS_CTRL_MODE_BB_IFC_CH2_MANUAL (1<<6) +#define SYS_CTRL_MODE_BB_IFC_CH3_AUTOMATIC (0<<7) +#define SYS_CTRL_MODE_BB_IFC_CH3_MANUAL (1<<7) +#define SYS_CTRL_MODE_BB_SRAM_AUTOMATIC (0<<8) +#define SYS_CTRL_MODE_BB_SRAM_MANUAL (1<<8) +#define SYS_CTRL_MODE_BB_A2A_AUTOMATIC (0<<9) +#define SYS_CTRL_MODE_BB_A2A_MANUAL (1<<9) +#define SYS_CTRL_MODE_BB_ITLV_AUTOMATIC (0<<10) +#define SYS_CTRL_MODE_BB_ITLV_MANUAL (1<<10) +#define SYS_CTRL_MODE_BB_VITERBI_AUTOMATIC (0<<11) +#define SYS_CTRL_MODE_BB_VITERBI_MANUAL (1<<11) +#define SYS_CTRL_MODE_BB_CIPHER_AUTOMATIC (0<<12) +#define SYS_CTRL_MODE_BB_CIPHER_MANUAL (1<<12) +#define SYS_CTRL_MODE_BB_RF_IF_AUTOMATIC (0<<13) +#define SYS_CTRL_MODE_BB_RF_IF_MANUAL (1<<13) +#define SYS_CTRL_MODE_BB_COPRO_AUTOMATIC (0<<14) +#define SYS_CTRL_MODE_BB_COPRO_MANUAL (1<<14) +#define SYS_CTRL_MODE_BB_CP2_REG_AUTOMATIC (0<<15) +#define SYS_CTRL_MODE_BB_CP2_REG_MANUAL (1<<15) +#define SYS_CTRL_MODE_BB_XCOR_AUTOMATIC (0<<16) +#define SYS_CTRL_MODE_BB_XCOR_MANUAL (1<<16) +#define SYS_CTRL_MODE_BB_EVITAC_AUTOMATIC (0<<17) +#define SYS_CTRL_MODE_BB_EVITAC_MANUAL (1<<17) +#define SYS_CTRL_MODE_CLK_BB(n) (((n)&0x1FFFF)<<1) +#define SYS_CTRL_MODE_CLK_BB_MASK (0x1FFFF<<1) +#define SYS_CTRL_MODE_CLK_BB_SHIFT (1) + +//Clk_BB_Enable +#define SYS_CTRL_ENABLE_BB_BCPU (1<<0) +#define SYS_CTRL_ENABLE_BB_BCPU_INT (1<<1) +#define SYS_CTRL_ENABLE_BB_AMBA (1<<2) +#define SYS_CTRL_ENABLE_BB_PCLK_CONF (1<<3) +#define SYS_CTRL_ENABLE_BB_PCLK_DATA (1<<4) +#define SYS_CTRL_ENABLE_BB_EXCOR (1<<5) +#define SYS_CTRL_ENABLE_BB_IFC_CH2 (1<<6) +#define SYS_CTRL_ENABLE_BB_IFC_CH3 (1<<7) +#define SYS_CTRL_ENABLE_BB_SRAM (1<<8) +#define SYS_CTRL_ENABLE_BB_A2A (1<<9) +#define SYS_CTRL_ENABLE_BB_ITLV (1<<10) +#define SYS_CTRL_ENABLE_BB_VITERBI (1<<11) +#define SYS_CTRL_ENABLE_BB_CIPHER (1<<12) +#define SYS_CTRL_ENABLE_BB_RF_IF (1<<13) +#define SYS_CTRL_ENABLE_BB_COPRO (1<<14) +#define SYS_CTRL_ENABLE_BB_CP2_REG (1<<15) +#define SYS_CTRL_ENABLE_BB_XCOR (1<<16) +#define SYS_CTRL_ENABLE_BB_EVITAC (1<<17) +#define SYS_CTRL_ENABLE_BB_IRQ (1<<18) +#define SYS_CTRL_ENABLE_BB_COM_REGS (1<<19) +#define SYS_CTRL_ENABLE_BB_CORDIC (1<<20) +#define SYS_CTRL_ENABLE_CLK_BB(n) (((n)&0x1FFFFF)<<0) +#define SYS_CTRL_ENABLE_CLK_BB_MASK (0x1FFFFF<<0) +#define SYS_CTRL_ENABLE_CLK_BB_SHIFT (0) + +//Clk_BB_Disable +#define SYS_CTRL_DISABLE_BB_BCPU (1<<0) +#define SYS_CTRL_DISABLE_BB_BCPU_INT (1<<1) +#define SYS_CTRL_DISABLE_BB_AMBA (1<<2) +#define SYS_CTRL_DISABLE_BB_PCLK_CONF (1<<3) +#define SYS_CTRL_DISABLE_BB_PCLK_DATA (1<<4) +#define SYS_CTRL_DISABLE_BB_EXCOR (1<<5) +#define SYS_CTRL_DISABLE_BB_IFC_CH2 (1<<6) +#define SYS_CTRL_DISABLE_BB_IFC_CH3 (1<<7) +#define SYS_CTRL_DISABLE_BB_SRAM (1<<8) +#define SYS_CTRL_DISABLE_BB_A2A (1<<9) +#define SYS_CTRL_DISABLE_BB_ITLV (1<<10) +#define SYS_CTRL_DISABLE_BB_VITERBI (1<<11) +#define SYS_CTRL_DISABLE_BB_CIPHER (1<<12) +#define SYS_CTRL_DISABLE_BB_RF_IF (1<<13) +#define SYS_CTRL_DISABLE_BB_COPRO (1<<14) +#define SYS_CTRL_DISABLE_BB_CP2_REG (1<<15) +#define SYS_CTRL_DISABLE_BB_XCOR (1<<16) +#define SYS_CTRL_DISABLE_BB_EVITAC (1<<17) +#define SYS_CTRL_DISABLE_BB_IRQ (1<<18) +#define SYS_CTRL_DISABLE_BB_COM_REGS (1<<19) +#define SYS_CTRL_DISABLE_BB_CORDIC (1<<20) +#define SYS_CTRL_DISABLE_CLK_BB(n) (((n)&0x1FFFFF)<<0) +#define SYS_CTRL_DISABLE_CLK_BB_MASK (0x1FFFFF<<0) +#define SYS_CTRL_DISABLE_CLK_BB_SHIFT (0) + +//Clk_Other_Mode +#define SYS_CTRL_MODE_OC_DEBUG_UART_AUTOMATIC (0<<0) +#define SYS_CTRL_MODE_OC_DEBUG_UART_MANUAL (1<<0) +#define SYS_CTRL_MODE_OC_RF_RX_AUTOMATIC (0<<1) +#define SYS_CTRL_MODE_OC_RF_RX_MANUAL (1<<1) +#define SYS_CTRL_MODE_OC_RF_TX_AUTOMATIC (0<<2) +#define SYS_CTRL_MODE_OC_RF_TX_MANUAL (1<<2) +#define SYS_CTRL_MODE_OC_MEM_BRIDGE_AUTOMATIC (0<<3) +#define SYS_CTRL_MODE_OC_MEM_BRIDGE_MANUAL (1<<3) +#define SYS_CTRL_MODE_CLK_OTHER(n) (((n)&15)<<0) +#define SYS_CTRL_MODE_CLK_OTHER_MASK (15<<0) +#define SYS_CTRL_MODE_CLK_OTHER_SHIFT (0) + +//Clk_Other_Enable +#define SYS_CTRL_ENABLE_OC_DEBUG_UART (1<<0) +#define SYS_CTRL_ENABLE_OC_RF_RX (1<<1) +#define SYS_CTRL_ENABLE_OC_RF_TX (1<<2) +#define SYS_CTRL_ENABLE_OC_MEM_BRIDGE (1<<3) +#define SYS_CTRL_ENABLE_OC_LPS (1<<4) +#define SYS_CTRL_ENABLE_OC_GPIO (1<<5) +#define SYS_CTRL_ENABLE_OC_CLK_OUT (1<<6) +#define SYS_CTRL_ENABLE_OC_MEM_CLK_OUT (1<<7) +#define SYS_CTRL_ENABLE_OC_TCU (1<<8) +#define SYS_CTRL_ENABLE_CLK_OTHER(n) (((n)&0x1FF)<<0) +#define SYS_CTRL_ENABLE_CLK_OTHER_MASK (0x1FF<<0) +#define SYS_CTRL_ENABLE_CLK_OTHER_SHIFT (0) + +//Clk_Other_Disable +#define SYS_CTRL_DISABLE_OC_DEBUG_UART (1<<0) +#define SYS_CTRL_DISABLE_OC_RF_RX (1<<1) +#define SYS_CTRL_DISABLE_OC_RF_TX (1<<2) +#define SYS_CTRL_DISABLE_OC_MEM_BRIDGE (1<<3) +#define SYS_CTRL_DISABLE_OC_LPS (1<<4) +#define SYS_CTRL_DISABLE_OC_GPIO (1<<5) +#define SYS_CTRL_DISABLE_OC_CLK_OUT (1<<6) +#define SYS_CTRL_DISABLE_OC_MEM_CLK_OUT (1<<7) +#define SYS_CTRL_DISABLE_OC_TCU (1<<8) +#define SYS_CTRL_DISABLE_CLK_OTHER(n) (((n)&0x1FF)<<0) +#define SYS_CTRL_DISABLE_CLK_OTHER_MASK (0x1FF<<0) +#define SYS_CTRL_DISABLE_CLK_OTHER_SHIFT (0) + +//Pll_Ctrl +#define SYS_CTRL_PLL_ENABLE (1<<0) +#define SYS_CTRL_PLL_ENABLE_MASK (1<<0) +#define SYS_CTRL_PLL_ENABLE_SHIFT (0) +#define SYS_CTRL_PLL_ENABLE_POWER_DOWN (0<<0) +#define SYS_CTRL_PLL_ENABLE_ENABLE (1<<0) +#define SYS_CTRL_PLL_LOCK_RESET (1<<4) +#define SYS_CTRL_PLL_LOCK_RESET_MASK (1<<4) +#define SYS_CTRL_PLL_LOCK_RESET_SHIFT (4) +#define SYS_CTRL_PLL_LOCK_RESET_RESET (0<<4) +#define SYS_CTRL_PLL_LOCK_RESET_NO_RESET (1<<4) +#define SYS_CTRL_PLL_BYPASS (1<<8) +#define SYS_CTRL_PLL_BYPASS_MASK (1<<8) +#define SYS_CTRL_PLL_BYPASS_SHIFT (8) +#define SYS_CTRL_PLL_BYPASS_PASS (0<<8) +#define SYS_CTRL_PLL_BYPASS_BYPASS (1<<8) +#define SYS_CTRL_PLL_CLK_FAST_ENABLE (1<<12) +#define SYS_CTRL_PLL_CLK_FAST_ENABLE_MASK (1<<12) +#define SYS_CTRL_PLL_CLK_FAST_ENABLE_SHIFT (12) +#define SYS_CTRL_PLL_CLK_FAST_ENABLE_ENABLE (1<<12) +#define SYS_CTRL_PLL_CLK_FAST_ENABLE_DISABLE (0<<12) +#define SYS_CTRL_PLL_XP_CFG(n) (((n)&4369)<<0) +#define SYS_CTRL_PLL_XP_CFG_MASK (4369<<0) +#define SYS_CTRL_PLL_XP_CFG_SHIFT (0) + +//Sel_Clock +#define SYS_CTRL_SLOW_SEL_RF_OSCILLATOR (1<<0) +#define SYS_CTRL_SLOW_SEL_RF_RF (0<<0) +#define SYS_CTRL_SYS_SEL_FAST_SLOW (1<<4) +#define SYS_CTRL_SYS_SEL_FAST_FAST (0<<4) +#define SYS_CTRL_TCU_13M_L_26M (1<<5) +#define SYS_CTRL_TCU_13M_L_13M (0<<5) +#define SYS_CTRL_PLL_DISABLE_LPS_DISABLE (1<<6) +#define SYS_CTRL_PLL_DISABLE_LPS_ENABLE (0<<6) +#define SYS_CTRL_DIGEN_H_ENABLE (1<<7) +#define SYS_CTRL_DIGEN_H_DISABLE (0<<7) +#define SYS_CTRL_RF_DETECTED_OK (1<<20) +#define SYS_CTRL_RF_DETECTED_NO (0<<20) +#define SYS_CTRL_RF_DETECT_BYPASS (1<<21) +#define SYS_CTRL_RF_DETECT_RESET (1<<22) +#define SYS_CTRL_RF_SELECTED_L (1<<23) +#define SYS_CTRL_PLL_LOCKED (1<<24) +#define SYS_CTRL_PLL_LOCKED_MASK (1<<24) +#define SYS_CTRL_PLL_LOCKED_SHIFT (24) +#define SYS_CTRL_PLL_LOCKED_LOCKED (1<<24) +#define SYS_CTRL_PLL_LOCKED_NOT_LOCKED (0<<24) +#define SYS_CTRL_PLL_BYPASS_LOCK (1<<27) +#define SYS_CTRL_FAST_SELECTED_L (1<<31) +#define SYS_CTRL_FAST_SELECTED_L_MASK (1<<31) +#define SYS_CTRL_FAST_SELECTED_L_SHIFT (31) + +//Cfg_Clk_Sys +#define SYS_CTRL_FREQ(n) (((n)&15)<<0) +#define SYS_CTRL_FREQ_MASK (15<<0) +#define SYS_CTRL_FREQ_SHIFT (0) +#define SYS_CTRL_FREQ_312M (13<<0) +#define SYS_CTRL_FREQ_250M (12<<0) +#define SYS_CTRL_FREQ_208M (11<<0) +#define SYS_CTRL_FREQ_178M (10<<0) +#define SYS_CTRL_FREQ_156M (9<<0) +#define SYS_CTRL_FREQ_139M (8<<0) +#define SYS_CTRL_FREQ_125M (7<<0) +#define SYS_CTRL_FREQ_113M (6<<0) +#define SYS_CTRL_FREQ_104M (5<<0) +#define SYS_CTRL_FREQ_89M (4<<0) +#define SYS_CTRL_FREQ_78M (3<<0) +#define SYS_CTRL_FREQ_52M (2<<0) +#define SYS_CTRL_FREQ_39M (1<<0) +#define SYS_CTRL_FREQ_26M (0<<0) +#define SYS_CTRL_FORCE_DIV_UPDATE (1<<4) +#define SYS_CTRL_REQ_DIV_UPDATE (1<<8) + +//Cfg_Clk_Mem_Bridge +#define SYS_CTRL_MEM_FREQ(n) (((n)&15)<<0) +#define SYS_CTRL_MEM_FREQ_MASK (15<<0) +#define SYS_CTRL_MEM_FREQ_SHIFT (0) +#define SYS_CTRL_MEM_FREQ_312M (13<<0) +#define SYS_CTRL_MEM_FREQ_250M (12<<0) +#define SYS_CTRL_MEM_FREQ_208M (11<<0) +#define SYS_CTRL_MEM_FREQ_178M (10<<0) +#define SYS_CTRL_MEM_FREQ_156M (9<<0) +#define SYS_CTRL_MEM_FREQ_139M (8<<0) +#define SYS_CTRL_MEM_FREQ_125M (7<<0) +#define SYS_CTRL_MEM_FREQ_113M (6<<0) +#define SYS_CTRL_MEM_FREQ_104M (5<<0) +#define SYS_CTRL_MEM_FREQ_89M (4<<0) +#define SYS_CTRL_MEM_FREQ_78M (3<<0) +#define SYS_CTRL_MEM_FREQ_52M (2<<0) +#define SYS_CTRL_MEM_FREQ_39M (1<<0) +#define SYS_CTRL_MEM_FREQ_26M (0<<0) +#define SYS_CTRL_DDR_MODE_EN_NORMAL_MODE (0<<6) +#define SYS_CTRL_DDR_MODE_EN_DDR_MODE (1<<6) +#define SYS_CTRL_DDR_FAST_CLK_POL_INVERT (1<<7) +#define SYS_CTRL_DDR_FAST_CLK_POL_NORMAL (0<<7) +#define SYS_CTRL_DDR_DQSL_I(n) (((n)&3)<<8) +#define SYS_CTRL_DDR_DQSU_I(n) (((n)&3)<<10) +#define SYS_CTRL_DDR_DQSL_O(n) (((n)&3)<<12) +#define SYS_CTRL_DDR_DQSU_O(n) (((n)&3)<<14) +#define SYS_CTRL_DDR_PLL_OFF (1<<16) +#define SYS_CTRL_MEM_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_Out +#define SYS_CTRL_CLKOUT_DIVIDER(n) (((n)&31)<<0) +#define SYS_CTRL_CLKOUT_SEL_OSC (0<<8) +#define SYS_CTRL_CLKOUT_SEL_RF (1<<8) +#define SYS_CTRL_CLKOUT_SEL_DIVIDER (2<<8) + +//Cfg_Clk_Host_Uart +#define SYS_CTRL_HOST_UART_DIVIDER(n) (((n)&0x3FF)<<0) +#define SYS_CTRL_HOST_UART_DIVIDER_MASK (0x3FF<<0) +#define SYS_CTRL_HOST_UART_DIVIDER_SHIFT (0) +#define SYS_CTRL_HOST_UART_SEL_PLL_SLOW (0<<12) +#define SYS_CTRL_HOST_UART_SEL_PLL_PLL (1<<12) + +//Cfg_Clk_Auxclk +#define SYS_CTRL_AUXCLK_EN_DISABLE (0<<0) +#define SYS_CTRL_AUXCLK_EN_ENABLE (1<<0) + +//Cfg_AHB +#define SYS_CTRL_SYS_NEW_ARBITRATION_ENABLE (1<<0) +#define SYS_CTRL_SYS_NEW_ARBITRATION_DISABLE (0<<0) +#define SYS_CTRL_ENABLE_SYS_MID_BIST_ENABLE (1<<1) +#define SYS_CTRL_ENABLE_SYS_MID_BIST_DISABLE (0<<1) +#define SYS_CTRL_ENABLE_SYS_MID_DMA_ENABLE (1<<2) +#define SYS_CTRL_ENABLE_SYS_MID_DMA_DISABLE (0<<2) +#define SYS_CTRL_ENABLE_SYS_MID_XCPU_ENABLE (1<<3) +#define SYS_CTRL_ENABLE_SYS_MID_XCPU_DISABLE (0<<3) +#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_ENABLE (1<<4) +#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_DISABLE (0<<4) +#define SYS_CTRL_ENABLE_SYS_MID_IFC_ENABLE (1<<5) +#define SYS_CTRL_ENABLE_SYS_MID_IFC_DISABLE (0<<5) +#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_ENABLE (1<<6) +#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_DISABLE (0<<6) +#define SYS_CTRL_BB_NEW_ARBITRATION_ENABLE (1<<16) +#define SYS_CTRL_BB_NEW_ARBITRATION_DISABLE (0<<16) +#define SYS_CTRL_ENABLE_BB_MID_BIST_ENABLE (1<<17) +#define SYS_CTRL_ENABLE_BB_MID_BIST_DISABLE (0<<17) +#define SYS_CTRL_ENABLE_BB_MID_IFC_ENABLE (1<<18) +#define SYS_CTRL_ENABLE_BB_MID_IFC_DISABLE (0<<18) +#define SYS_CTRL_ENABLE_BB_MID_BCPU_ENABLE (1<<19) +#define SYS_CTRL_ENABLE_BB_MID_BCPU_DISABLE (0<<19) +#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_ENABLE (1<<20) +#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_DISABLE (0<<20) +#define SYS_CTRL_SYS_ENABLE(n) (((n)&0x3F)<<1) +#define SYS_CTRL_SYS_ENABLE_MASK (0x3F<<1) +#define SYS_CTRL_SYS_ENABLE_SHIFT (1) +#define SYS_CTRL_BB_ENABLE(n) (((n)&15)<<17) +#define SYS_CTRL_BB_ENABLE_MASK (15<<17) +#define SYS_CTRL_BB_ENABLE_SHIFT (17) + +//Ctrl_AHB +#define SYS_CTRL_SPLIT_SYS_MID_BIST_NORMAL (1<<0) +#define SYS_CTRL_SPLIT_SYS_MID_BIST_FORCE (0<<0) +#define SYS_CTRL_SPLIT_SYS_MID_DMA_NORMAL (1<<1) +#define SYS_CTRL_SPLIT_SYS_MID_DMA_FORCE (0<<1) +#define SYS_CTRL_SPLIT_SYS_MID_XCPU_NORMAL (1<<2) +#define SYS_CTRL_SPLIT_SYS_MID_XCPU_FORCE (0<<2) +#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_NORMAL (1<<3) +#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_FORCE (0<<3) +#define SYS_CTRL_SPLIT_SYS_MID_IFC_NORMAL (1<<4) +#define SYS_CTRL_SPLIT_SYS_MID_IFC_FORCE (0<<4) +#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_NORMAL (1<<5) +#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_FORCE (0<<5) +#define SYS_CTRL_SPLIT_BB_MID_BIST_NORMAL (1<<16) +#define SYS_CTRL_SPLIT_BB_MID_BIST_FORCE (0<<16) +#define SYS_CTRL_SPLIT_BB_MID_IFC_NORMAL (1<<17) +#define SYS_CTRL_SPLIT_BB_MID_IFC_FORCE (0<<17) +#define SYS_CTRL_SPLIT_BB_MID_BCPU_NORMAL (1<<18) +#define SYS_CTRL_SPLIT_BB_MID_BCPU_FORCE (0<<18) +#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_NORMAL (1<<19) +#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_FORCE (0<<19) +#define SYS_CTRL_SYS_FORCE_HSPLIT(n) (((n)&0x3F)<<0) +#define SYS_CTRL_SYS_FORCE_HSPLIT_MASK (0x3F<<0) +#define SYS_CTRL_SYS_FORCE_HSPLIT_SHIFT (0) +#define SYS_CTRL_BB_FORCE_HSPLIT(n) (((n)&15)<<16) +#define SYS_CTRL_BB_FORCE_HSPLIT_MASK (15<<16) +#define SYS_CTRL_BB_FORCE_HSPLIT_SHIFT (16) + +//XCpu_Dbg_BKP +#define SYS_CTRL_BKPT_EN (1<<0) +#define SYS_CTRL_BKPT_MODE(n) (((n)&3)<<4) +#define SYS_CTRL_BKPT_MODE_I (0<<4) +#define SYS_CTRL_BKPT_MODE_R (1<<4) +#define SYS_CTRL_BKPT_MODE_W (2<<4) +#define SYS_CTRL_BKPT_MODE_RW (3<<4) +#define SYS_CTRL_STALLED (1<<8) + +//XCpu_Dbg_Addr +#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0) + +//BCpu_Dbg_BKP +//#define SYS_CTRL_BKPT_EN (1<<0) +//#define SYS_CTRL_BKPT_MODE(n) (((n)&3)<<4) +//#define SYS_CTRL_BKPT_MODE_I (0<<4) +//#define SYS_CTRL_BKPT_MODE_R (1<<4) +//#define SYS_CTRL_BKPT_MODE_W (2<<4) +//#define SYS_CTRL_BKPT_MODE_RW (3<<4) +//#define SYS_CTRL_STALLED (1<<8) + +//BCpu_Dbg_Addr +//#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0) + +//Cfg_Cpus_Cache_Ram_Disable +#define SYS_CTRL_XCPU_USE_MODE (1<<0) +#define SYS_CTRL_XCPU_CLK_OFF_MODE (1<<1) +#define SYS_CTRL_BCPU_USE_MODE (1<<16) +#define SYS_CTRL_BCPU_CLK_OFF_MODE (1<<17) +#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<0) +#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_MASK (3<<0) +#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_SHIFT (0) +#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<16) +#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_MASK (3<<16) +#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_SHIFT (16) + +//Reset_Cause +#define SYS_CTRL_WATCHDOG_RESET_HAPPENED (1<<0) +#define SYS_CTRL_WATCHDOG_RESET_NO (0<<0) +#define SYS_CTRL_APSOFT_RESET_HAPPENED (1<<1) +#define SYS_CTRL_APSOFT_RESET_NO (0<<1) +#define SYS_CTRL_GLOBALSOFT_RESET_HAPPENED (1<<4) +#define SYS_CTRL_GLOBALSOFT_RESET_NO (0<<4) +#define SYS_CTRL_HOSTDEBUG_RESET_HAPPENED (1<<5) +#define SYS_CTRL_HOSTDEBUG_RESET_NO (0<<5) +#define SYS_CTRL_ALARMCAUSE_HAPPENED (1<<6) +#define SYS_CTRL_ALARMCAUSE_NO (0<<6) +#define SYS_CTRL_MEMCHECKDONE_MASK (1<<7) +#define SYS_CTRL_MEMCHECKDONE_SHIFT (7) +#define SYS_CTRL_MEMCHECKDONE_DONE (1<<7) +#define SYS_CTRL_MEMCHECKDONE_RUNNING (0<<7) +#define SYS_CTRL_BOOT_MODE(n) (((n)&0xFFFF)<<8) +#define SYS_CTRL_BOOT_MODE_MASK (0xFFFF<<8) +#define SYS_CTRL_BOOT_MODE_SHIFT (8) +#define SYS_CTRL_SW_BOOT_MODE(n) (((n)&0x7F)<<24) +#define SYS_CTRL_SW_BOOT_MODE_MASK (0x7F<<24) +#define SYS_CTRL_SW_BOOT_MODE_SHIFT (24) +#define SYS_CTRL_FONCTIONAL_TEST_MODE (1<<31) + +//WakeUp +#define SYS_CTRL_FORCE_WAKEUP (1<<0) + +//AP_Ctrl +#define SYS_CTRL_AP_INT_STATUS (1<<0) +#define SYS_CTRL_AP_INT_MASK (1<<16) +#define SYS_CTRL_AP_DEEPSLEEP_EN (1<<24) + +//Ignore_Charger +#define SYS_CTRL_IGNORE_CHARGER (1<<0) + +//Cfg_Reserve +#define SYS_CTRL_RESERVE(n) (((n)&0x3FFF)<<0) +#define SYS_CTRL_AUIFC_CH0_IRQ_MASK (1<<14) +#define SYS_CTRL_AUIFC_CH1_IRQ_MASK (1<<15) + + + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810e.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810e.h new file mode 100644 index 0000000000..0ecd75897f --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810e.h @@ -0,0 +1,979 @@ +#ifndef _REG_MD_SYSCTRL_H_
+#define _REG_MD_SYSCTRL_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+// MACROS
+// =============================================================================
+
+// ============================================================================
+// CPU_ID_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// CPU IDs
+ XCPU = 0x00000000,
+ BCPU = 0x00000001
+} CPU_ID_T;
+
+
+// ============================================================================
+// SYS_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// System side System clocks
+ SYS_XCPU = 0x00000000,
+ SYS_XCPU_INT = 0x00000001,
+ SYS_PCLK_CONF = 0x00000002,
+ SYS_PCLK_DATA = 0x00000003,
+ SYS_AMBA = 0x00000004,
+ SYS_DMA = 0x00000005,
+ SYS_EBC = 0x00000006,
+ SYS_IFC_CH0 = 0x00000007,
+ SYS_IFC_CH1 = 0x00000008,
+ SYS_IFC_CH2 = 0x00000009,
+ SYS_IFC_CH3 = 0x0000000A,
+ SYS_IFC_DBG = 0x0000000B,
+ SYS_A2A = 0x0000000C,
+ SYS_AXI2AHB = 0x0000000D,
+ SYS_AHB2AXI = 0x0000000E,
+ SYS_EXT_AHB = 0x0000000F,
+ SYS_DEBUG_UART = 0x00000010,
+ SYS_DBGHST = 0x00000011,
+/// System side divided clock (either divided by module or by sys_ctrl)
+ SYSD_SCI1 = 0x00000012,
+ SYSD_SCI2 = 0x00000013,
+ SYSD_SCI3 = 0x00000014,
+ SYSD_RF_SPI = 0x00000015,
+ SYSD_OSC = 0x00000016,
+/// the following don't have an auto enable
+ SYS_GPIO = 0x00000017,
+ SYS_IRQ = 0x00000018,
+ SYS_TCU = 0x00000019,
+ SYS_TIMER = 0x0000001A,
+ SYS_COM_REGS = 0x0000001B,
+ SYS_DP_AP = 0x0000001C,
+/// the following are sharing their enable
+ SYS_SCI1 = 0x0000001D,
+ SYS_SCI2 = 0x0000001E,
+ SYS_SCI3 = 0x0000001F,
+/// keep last
+ SYS_NOGATE = 0x00000020
+} SYS_CLKS_T;
+
+#define NB_SYS_CLK_XCPU (2)
+#define NB_SYS_CLK_AEN (23)
+#define NB_SYS_CLK_EN (29)
+#define NB_SYS_CLK (33)
+
+// ============================================================================
+// PER_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+ PER_I2C = 0x00000000,
+/// System side divided clock (either divided by module or by sys_ctrl)
+ PERD_SPI1 = 0x00000001,
+/// System side divided clock (either divided by module or by sys_ctrl)
+ PERD_SPI2 = 0x00000002,
+ PER_SPY = 0x00000003,
+ PER_TEST = 0x00000004
+} PER_CLKS_T;
+
+#define NB_PER_CLK_AEN (3)
+#define NB_PER_CLK_EN (5)
+#define NB_PER_CLK (5)
+
+// ============================================================================
+// BB_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// Baseband side System clocks
+ BB_BCPU = 0x00000000,
+ BB_BCPU_INT = 0x00000001,
+ BB_AMBA = 0x00000002,
+ BB_PCLK_CONF = 0x00000003,
+ BB_PCLK_DATA = 0x00000004,
+ BB_EXCOR = 0x00000005,
+ BB_IFC_CH2 = 0x00000006,
+ BB_IFC_CH3 = 0x00000007,
+ BB_SRAM = 0x00000008,
+ BB_A2A = 0x00000009,
+ BB_ITLV = 0x0000000A,
+ BB_VITERBI = 0x0000000B,
+ BB_CIPHER = 0x0000000C,
+ BB_RF_IF = 0x0000000D,
+ BB_COPRO = 0x0000000E,
+ BB_CP2_REG = 0x0000000F,
+ BB_XCOR = 0x00000010,
+ BB_EVITAC = 0x00000011,
+/// the following don't have an auto enable
+ BB_IRQ = 0x00000012,
+ BB_COM_REGS = 0x00000013,
+ BB_CORDIC = 0x00000014
+} BB_CLKS_T;
+
+#define NB_BB_CLK_AEN (18)
+#define NB_BB_CLK_EN (21)
+#define NB_BB_CLK (21)
+/// Other clocks
+/// clocks with auto enble
+/// the debug host clock auto enable is not used in host mode, only in uart mode
+#define OC_HOST_UART (0)
+
+// ============================================================================
+// OTHER_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+ OC_DEBUG_UART = 0x00000000,
+ OC_RF_RX = 0x00000001,
+ OC_RF_TX = 0x00000002,
+ OC_MEM_BRIDGE = 0x00000003,
+/// the following don't have an auto enable
+ OC_LPS = 0x00000004,
+ OC_GPIO = 0x00000005,
+ OC_CLK_OUT = 0x00000006,
+ OC_MEM_CLK_OUT = 0x00000007,
+ OC_TCU = 0x00000008
+} OTHER_CLKS_T;
+
+#define NB_OTHER_CLK_AEN (4)
+#define NB_OTHER_CLK_EN (9)
+#define NB_OTHER_CLK (9)
+
+// ============================================================================
+// RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// System side resets
+ RST_XCPU = 0x00000000,
+ RST_SYS_IRQ = 0x00000001,
+ RST_SYS_A2A = 0x00000002,
+ RST_SYS_AHB2AXI = 0x00000003,
+ RST_SYS_AXI2AHB = 0x00000004,
+ RST_DMA = 0x00000005,
+ RST_TIMER = 0x00000006,
+ RST_TCU = 0x00000007,
+ RST_GPIO = 0x00000008,
+ RST_I2C = 0x00000009,
+ RST_SPI1 = 0x0000000A,
+ RST_SPI2 = 0x0000000B,
+ RST_RF_SPI = 0x0000000C,
+ RST_SCI1 = 0x0000000D,
+ RST_SCI2 = 0x0000000E,
+ RST_SCI3 = 0x0000000F,
+ RST_SPY = 0x00000010,
+ RST_MEM_BRIDGE = 0x00000011,
+ RST_EXT_AHB = 0x00000012,
+ RST_DP_AP = 0x00000013,
+ RST_COMREGS = 0x00000014,
+ RST_COMREGS_AP = 0x00000015,
+ RST_AP_CLKEN = 0x00000016,
+ RST_AP_RST = 0x00000017,
+ RST_MEM_CHK = 0x00000018,
+ RST_AP_RST1 = 0x00000019,
+ RST_AP_RST2 = 0x0000001A,
+ RST_AP_RST3 = 0x0000001B,
+ RST_AP_RST4 = 0x0000001C,
+ RST_AP_RST5 = 0x0000001D,
+ RST_BCPU = 0x0000001E,
+ RST_BB_IRQ = 0x0000001F,
+ RST_BB_A2A = 0x00000020,
+ RST_BB_IFC = 0x00000021,
+ RST_BB_SRAM = 0x00000022,
+ RST_ITLV = 0x00000023,
+ RST_VITERBI = 0x00000024,
+ RST_CIPHER = 0x00000025,
+ RST_XCOR = 0x00000026,
+ RST_COPRO = 0x00000027,
+ RST_RF_IF = 0x00000028,
+ RST_EXCOR = 0x00000029,
+ RST_EVITAC = 0x0000002A,
+ RST_CORDIC = 0x0000002B,
+ RST_TCU_BB = 0x0000002C,
+ RST_BB_FULL = 0x0000002D,
+ RST_SYS_FULL = 0x0000002E
+} RESETS_T;
+
+#define NB_SRST (30)
+/// Baseband side resets
+#define BOUND_BRST_FIRST (30)
+#define BOUND_BRST_AFTER (45)
+/// The following reset does not have register
+#define NR_RST_REG (46)
+#define NB_RST (47)
+#define NB_BRST (BOUND_BRST_AFTER-BOUND_BRST_FIRST)
+
+// ============================================================================
+// RESET_OTHERS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// Reset Other : resync on corresponding clock other
+ RSTO_DBG_HOST = 0x00000000,
+ RSTO_RF_RX = 0x00000001,
+ RSTO_RF_TX = 0x00000002,
+ RSTO_MEM_BRIDGE = 0x00000003,
+ RSTO_LPS = 0x00000004,
+ RSTO_GPIO = 0x00000005,
+ RSTO_WDTIMER = 0x00000006,
+ RSTO_TCU = 0x00000007
+} RESET_OTHERS_T;
+
+#define BOUND_RSTO_RF_FIRST (1)
+#define BOUND_RSTO_RF_AFTER (3)
+#define NB_RSTO (8)
+/// For REG_DBG protect lock/unlock value
+#define SYS_CTRL_PROTECT_LOCK (0XA50000)
+#define SYS_CTRL_PROTECT_UNLOCK (0XA50001)
+
+// =============================================================================
+// TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_CTRL_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef volatile struct
+{
+ /// <strong>This register is used to Lock and Unlock the protected registers.</strong>
+ REG32 REG_DBG; //0x00000000
+ /// This register is protected.
+ REG32 Sys_Rst_Set; //0x00000004
+ REG32 Sys_Rst_Clr; //0x00000008
+ /// This register is protected.
+ REG32 BB_Rst_Set; //0x0000000C
+ REG32 BB_Rst_Clr; //0x00000010
+ REG32 Clk_Sys_Mode; //0x00000014
+ REG32 Clk_Sys_Enable; //0x00000018
+ /// This register is protected.
+ REG32 Clk_Sys_Disable; //0x0000001C
+ REG32 Clk_Per_Mode; //0x00000020
+ REG32 Clk_Per_Enable; //0x00000024
+ /// This register is protected.
+ REG32 Clk_Per_Disable; //0x00000028
+ REG32 Clk_BB_Mode; //0x0000002C
+ REG32 Clk_BB_Enable; //0x00000030
+ /// This register is protected.
+ REG32 Clk_BB_Disable; //0x00000034
+ REG32 Clk_Other_Mode; //0x00000038
+ REG32 Clk_Other_Enable; //0x0000003C
+ /// This register is protected.
+ REG32 Clk_Other_Disable; //0x00000040
+ /// Register protected by Write_Unlocked_H.
+ REG32 Pll_Ctrl; //0x00000044
+ /// This register is protected.
+ REG32 Sel_Clock; //0x00000048
+ REG32 Cfg_Clk_Sys; //0x0000004C
+ REG32 Cfg_Clk_Mem_Bridge; //0x00000050
+ /// This register is protected.
+ REG32 Cfg_Clk_Out; //0x00000054
+ REG32 Cfg_Clk_Host_Uart; //0x00000058
+ REG32 Cfg_Clk_Auxclk; //0x0000005C
+ /// This register is protected.
+ REG32 Cfg_AHB; //0x00000060
+ /// This register is protected. Used to unsplit masters manualy.
+ REG32 Ctrl_AHB; //0x00000064
+ REG32 XCpu_Dbg_BKP; //0x00000068
+ REG32 XCpu_Dbg_Addr; //0x0000006C
+ REG32 BCpu_Dbg_BKP; //0x00000070
+ REG32 BCpu_Dbg_Addr; //0x00000074
+ REG32 Cfg_Cpus_Cache_Ram_Disable; //0x00000078
+ REG32 Reset_Cause; //0x0000007C
+ /// This register is protected.
+ REG32 WakeUp; //0x00000080
+ REG32 AP_Ctrl; //0x00000084
+ /// This register is protected.
+ REG32 Ignore_Charger; //0x00000088
+ REG32 Reserved_0000008C[28]; //0x0000008C
+ /// This register is reserved.
+ REG32 Cfg_Reserve; //0x000000FC
+} HWP_SYS_CTRL_T;
+
+#define hwp_sysCtrlMd ((HWP_SYS_CTRL_T*)(RDA_MD_SYSCTRL_BASE))
+
+
+//REG_DBG
+#define SYS_CTRL_SCRATCH(n) (((n)&0xFFFF)<<0)
+#define SYS_CTRL_WRITE_UNLOCK_STATUS (1<<30)
+#define SYS_CTRL_WRITE_UNLOCK (1<<31)
+
+//Sys_Rst_Set
+#define SYS_CTRL_SET_RST_XCPU (1<<0)
+#define SYS_CTRL_SET_RST_SYS_IRQ (1<<1)
+#define SYS_CTRL_SET_RST_SYS_A2A (1<<2)
+#define SYS_CTRL_SET_RST_SYS_AHB2AXI (1<<3)
+#define SYS_CTRL_SET_RST_SYS_AXI2AHB (1<<4)
+#define SYS_CTRL_SET_RST_DMA (1<<5)
+#define SYS_CTRL_SET_RST_TIMER (1<<6)
+#define SYS_CTRL_SET_RST_TCU (1<<7)
+#define SYS_CTRL_SET_RST_GPIO (1<<8)
+#define SYS_CTRL_SET_RST_I2C (1<<9)
+#define SYS_CTRL_SET_RST_SPI1 (1<<10)
+#define SYS_CTRL_SET_RST_SPI2 (1<<11)
+#define SYS_CTRL_SET_RST_RF_SPI (1<<12)
+#define SYS_CTRL_SET_RST_SCI1 (1<<13)
+#define SYS_CTRL_SET_RST_SCI2 (1<<14)
+#define SYS_CTRL_SET_RST_SCI3 (1<<15)
+#define SYS_CTRL_SET_RST_SPY (1<<16)
+#define SYS_CTRL_SET_RST_MEM_BRIDGE (1<<17)
+#define SYS_CTRL_SET_RST_EXT_AHB (1<<18)
+#define SYS_CTRL_SET_RST_DP_AP (1<<19)
+#define SYS_CTRL_SET_RST_COMREGS (1<<20)
+#define SYS_CTRL_SET_RST_COMREGS_AP (1<<21)
+#define SYS_CTRL_SET_RST_AP_CLKEN (1<<22)
+#define SYS_CTRL_SET_RST_AP_RST (1<<23)
+#define SYS_CTRL_SET_RST_MEM_CHK (1<<24)
+#define SYS_CTRL_SET_RST_AP_RST1 (1<<25)
+#define SYS_CTRL_SET_RST_AP_RST2 (1<<26)
+#define SYS_CTRL_SET_RST_AP_RST3 (1<<27)
+#define SYS_CTRL_SET_RST_AP_RST4 (1<<28)
+#define SYS_CTRL_SET_RST_AP_RST5 (1<<29)
+#define SYS_CTRL_SET_RST_OUT (1<<30)
+#define SYS_CTRL_SOFT_RST (1<<31)
+#define SYS_CTRL_SET_SYS_RST(n) (((n)&0x3FFFFFFF)<<0)
+#define SYS_CTRL_SET_SYS_RST_MASK (0x3FFFFFFF<<0)
+#define SYS_CTRL_SET_SYS_RST_SHIFT (0)
+
+//Sys_Rst_Clr
+#define SYS_CTRL_CLR_RST_XCPU (1<<0)
+#define SYS_CTRL_CLR_RST_SYS_IRQ (1<<1)
+#define SYS_CTRL_CLR_RST_SYS_A2A (1<<2)
+#define SYS_CTRL_CLR_RST_SYS_AHB2AXI (1<<3)
+#define SYS_CTRL_CLR_RST_SYS_AXI2AHB (1<<4)
+#define SYS_CTRL_CLR_RST_DMA (1<<5)
+#define SYS_CTRL_CLR_RST_TIMER (1<<6)
+#define SYS_CTRL_CLR_RST_TCU (1<<7)
+#define SYS_CTRL_CLR_RST_GPIO (1<<8)
+#define SYS_CTRL_CLR_RST_I2C (1<<9)
+#define SYS_CTRL_CLR_RST_SPI1 (1<<10)
+#define SYS_CTRL_CLR_RST_SPI2 (1<<11)
+#define SYS_CTRL_CLR_RST_RF_SPI (1<<12)
+#define SYS_CTRL_CLR_RST_SCI1 (1<<13)
+#define SYS_CTRL_CLR_RST_SCI2 (1<<14)
+#define SYS_CTRL_CLR_RST_SCI3 (1<<15)
+#define SYS_CTRL_CLR_RST_SPY (1<<16)
+#define SYS_CTRL_CLR_RST_MEM_BRIDGE (1<<17)
+#define SYS_CTRL_CLR_RST_EXT_AHB (1<<18)
+#define SYS_CTRL_CLR_RST_DP_AP (1<<19)
+#define SYS_CTRL_CLR_RST_COMREGS (1<<20)
+#define SYS_CTRL_CLR_RST_COMREGS_AP (1<<21)
+#define SYS_CTRL_CLR_RST_AP_CLKEN (1<<22)
+#define SYS_CTRL_CLR_RST_AP_RST (1<<23)
+#define SYS_CTRL_CLR_RST_MEM_CHK (1<<24)
+#define SYS_CTRL_CLR_RST_AP_RST1 (1<<25)
+#define SYS_CTRL_CLR_RST_AP_RST2 (1<<26)
+#define SYS_CTRL_CLR_RST_AP_RST3 (1<<27)
+#define SYS_CTRL_CLR_RST_AP_RST4 (1<<28)
+#define SYS_CTRL_CLR_RST_AP_RST5 (1<<29)
+#define SYS_CTRL_CLR_RST_OUT (1<<30)
+#define SYS_CTRL_CLR_SYS_RST(n) (((n)&0x3FFFFFFF)<<0)
+#define SYS_CTRL_CLR_SYS_RST_MASK (0x3FFFFFFF<<0)
+#define SYS_CTRL_CLR_SYS_RST_SHIFT (0)
+
+//BB_Rst_Set
+#define SYS_CTRL_SET_RST_BCPU (1<<0)
+#define SYS_CTRL_SET_RST_BB_IRQ (1<<1)
+#define SYS_CTRL_SET_RST_BB_A2A (1<<2)
+#define SYS_CTRL_SET_RST_BB_IFC (1<<3)
+#define SYS_CTRL_SET_RST_BB_SRAM (1<<4)
+#define SYS_CTRL_SET_RST_ITLV (1<<5)
+#define SYS_CTRL_SET_RST_VITERBI (1<<6)
+#define SYS_CTRL_SET_RST_CIPHER (1<<7)
+#define SYS_CTRL_SET_RST_XCOR (1<<8)
+#define SYS_CTRL_SET_RST_COPRO (1<<9)
+#define SYS_CTRL_SET_RST_RF_IF (1<<10)
+#define SYS_CTRL_SET_RST_EXCOR (1<<11)
+#define SYS_CTRL_SET_RST_EVITAC (1<<12)
+#define SYS_CTRL_SET_RST_CORDIC (1<<13)
+#define SYS_CTRL_SET_RST_TCU_BB (1<<14)
+#define SYS_CTRL_SET_RST_BB_FULL (1<<31)
+#define SYS_CTRL_SET_BB_RST(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_SET_BB_RST_MASK (0x7FFF<<0)
+#define SYS_CTRL_SET_BB_RST_SHIFT (0)
+
+//BB_Rst_Clr
+#define SYS_CTRL_CLR_RST_BCPU (1<<0)
+#define SYS_CTRL_CLR_RST_BB_IRQ (1<<1)
+#define SYS_CTRL_CLR_RST_BB_A2A (1<<2)
+#define SYS_CTRL_CLR_RST_BB_IFC (1<<3)
+#define SYS_CTRL_CLR_RST_BB_SRAM (1<<4)
+#define SYS_CTRL_CLR_RST_ITLV (1<<5)
+#define SYS_CTRL_CLR_RST_VITERBI (1<<6)
+#define SYS_CTRL_CLR_RST_CIPHER (1<<7)
+#define SYS_CTRL_CLR_RST_XCOR (1<<8)
+#define SYS_CTRL_CLR_RST_COPRO (1<<9)
+#define SYS_CTRL_CLR_RST_RF_IF (1<<10)
+#define SYS_CTRL_CLR_RST_EXCOR (1<<11)
+#define SYS_CTRL_CLR_RST_EVITAC (1<<12)
+#define SYS_CTRL_CLR_RST_CORDIC (1<<13)
+#define SYS_CTRL_CLR_RST_TCU_BB (1<<14)
+#define SYS_CTRL_CLR_RST_BB_FULL (1<<31)
+#define SYS_CTRL_CLR_BB_RST(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_CLR_BB_RST_MASK (0x7FFF<<0)
+#define SYS_CTRL_CLR_BB_RST_SHIFT (0)
+
+//Clk_Sys_Mode
+#define SYS_CTRL_MODE_SYS_XCPU (1<<0)
+#define SYS_CTRL_MODE_SYS_XCPU_INT_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_SYS_XCPU_INT_MANUAL (1<<1)
+#define SYS_CTRL_MODE_SYS_PCLK_CONF_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_SYS_PCLK_CONF_MANUAL (1<<2)
+#define SYS_CTRL_MODE_SYS_PCLK_DATA_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_SYS_PCLK_DATA_MANUAL (1<<3)
+#define SYS_CTRL_MODE_SYS_AMBA_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_SYS_AMBA_MANUAL (1<<4)
+#define SYS_CTRL_MODE_SYS_DMA_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_SYS_DMA_MANUAL (1<<5)
+#define SYS_CTRL_MODE_SYS_EBC_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_SYS_EBC_MANUAL (1<<6)
+#define SYS_CTRL_MODE_SYS_IFC_CH0_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_SYS_IFC_CH0_MANUAL (1<<7)
+#define SYS_CTRL_MODE_SYS_IFC_CH1_AUTOMATIC (0<<8)
+#define SYS_CTRL_MODE_SYS_IFC_CH1_MANUAL (1<<8)
+#define SYS_CTRL_MODE_SYS_IFC_CH2_AUTOMATIC (0<<9)
+#define SYS_CTRL_MODE_SYS_IFC_CH2_MANUAL (1<<9)
+#define SYS_CTRL_MODE_SYS_IFC_CH3_AUTOMATIC (0<<10)
+#define SYS_CTRL_MODE_SYS_IFC_CH3_MANUAL (1<<10)
+#define SYS_CTRL_MODE_SYS_IFC_DBG_AUTOMATIC (0<<11)
+#define SYS_CTRL_MODE_SYS_IFC_DBG_MANUAL (1<<11)
+#define SYS_CTRL_MODE_SYS_A2A_AUTOMATIC (0<<12)
+#define SYS_CTRL_MODE_SYS_A2A_MANUAL (1<<12)
+#define SYS_CTRL_MODE_SYS_AXI2AHB_AUTOMATIC (0<<13)
+#define SYS_CTRL_MODE_SYS_AXI2AHB_MANUAL (1<<13)
+#define SYS_CTRL_MODE_SYS_AHB2AXI_AUTOMATIC (0<<14)
+#define SYS_CTRL_MODE_SYS_AHB2AXI_MANUAL (1<<14)
+#define SYS_CTRL_MODE_SYS_EXT_AHB_AUTOMATIC (0<<15)
+#define SYS_CTRL_MODE_SYS_EXT_AHB_MANUAL (1<<15)
+#define SYS_CTRL_MODE_SYS_DEBUG_UART_AUTOMATIC (0<<16)
+#define SYS_CTRL_MODE_SYS_DEBUG_UART_MANUAL (1<<16)
+#define SYS_CTRL_MODE_SYS_DBGHST_AUTOMATIC (0<<17)
+#define SYS_CTRL_MODE_SYS_DBGHST_MANUAL (1<<17)
+#define SYS_CTRL_MODE_SYSD_SCI1_AUTOMATIC (0<<18)
+#define SYS_CTRL_MODE_SYSD_SCI1_MANUAL (1<<18)
+#define SYS_CTRL_MODE_SYSD_SCI2_AUTOMATIC (0<<19)
+#define SYS_CTRL_MODE_SYSD_SCI2_MANUAL (1<<19)
+#define SYS_CTRL_MODE_SYSD_SCI3_AUTOMATIC (0<<20)
+#define SYS_CTRL_MODE_SYSD_SCI3_MANUAL (1<<20)
+#define SYS_CTRL_MODE_SYSD_RF_SPI_AUTOMATIC (0<<21)
+#define SYS_CTRL_MODE_SYSD_RF_SPI_MANUAL (1<<21)
+#define SYS_CTRL_MODE_SYSD_OSC_AUTOMATIC (0<<22)
+#define SYS_CTRL_MODE_SYSD_OSC_MANUAL (1<<22)
+#define SYS_CTRL_MODE_CLK_SYS(n) (((n)&0x3FFFFF)<<1)
+#define SYS_CTRL_MODE_CLK_SYS_MASK (0x3FFFFF<<1)
+#define SYS_CTRL_MODE_CLK_SYS_SHIFT (1)
+
+//Clk_Sys_Enable
+#define SYS_CTRL_ENABLE_SYS_XCPU (1<<0)
+#define SYS_CTRL_ENABLE_SYS_XCPU_INT (1<<1)
+#define SYS_CTRL_ENABLE_SYS_PCLK_CONF (1<<2)
+#define SYS_CTRL_ENABLE_SYS_PCLK_DATA (1<<3)
+#define SYS_CTRL_ENABLE_SYS_AMBA (1<<4)
+#define SYS_CTRL_ENABLE_SYS_DMA (1<<5)
+#define SYS_CTRL_ENABLE_SYS_EBC (1<<6)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH0 (1<<7)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH1 (1<<8)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH2 (1<<9)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH3 (1<<10)
+#define SYS_CTRL_ENABLE_SYS_IFC_DBG (1<<11)
+#define SYS_CTRL_ENABLE_SYS_A2A (1<<12)
+#define SYS_CTRL_ENABLE_SYS_AXI2AHB (1<<13)
+#define SYS_CTRL_ENABLE_SYS_AHB2AXI (1<<14)
+#define SYS_CTRL_ENABLE_SYS_EXT_AHB (1<<15)
+#define SYS_CTRL_ENABLE_SYS_DEBUG_UART (1<<16)
+#define SYS_CTRL_ENABLE_SYS_DBGHST (1<<17)
+#define SYS_CTRL_ENABLE_SYSD_SCI1 (1<<18)
+#define SYS_CTRL_ENABLE_SYSD_SCI2 (1<<19)
+#define SYS_CTRL_ENABLE_SYSD_SCI3 (1<<20)
+#define SYS_CTRL_ENABLE_SYSD_RF_SPI (1<<21)
+#define SYS_CTRL_ENABLE_SYSD_OSC (1<<22)
+#define SYS_CTRL_ENABLE_SYS_GPIO (1<<23)
+#define SYS_CTRL_ENABLE_SYS_IRQ (1<<24)
+#define SYS_CTRL_ENABLE_SYS_TCU (1<<25)
+#define SYS_CTRL_ENABLE_SYS_TIMER (1<<26)
+#define SYS_CTRL_ENABLE_SYS_COM_REGS (1<<27)
+#define SYS_CTRL_ENABLE_SYS_DP_AP (1<<28)
+#define SYS_CTRL_ENABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS_SHIFT (0)
+
+//Clk_Sys_Disable
+#define SYS_CTRL_DISABLE_SYS_XCPU (1<<0)
+#define SYS_CTRL_DISABLE_SYS_XCPU_INT (1<<1)
+#define SYS_CTRL_DISABLE_SYS_PCLK_CONF (1<<2)
+#define SYS_CTRL_DISABLE_SYS_PCLK_DATA (1<<3)
+#define SYS_CTRL_DISABLE_SYS_AMBA (1<<4)
+#define SYS_CTRL_DISABLE_SYS_DMA (1<<5)
+#define SYS_CTRL_DISABLE_SYS_EBC (1<<6)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH0 (1<<7)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH1 (1<<8)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH2 (1<<9)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH3 (1<<10)
+#define SYS_CTRL_DISABLE_SYS_IFC_DBG (1<<11)
+#define SYS_CTRL_DISABLE_SYS_A2A (1<<12)
+#define SYS_CTRL_DISABLE_SYS_AXI2AHB (1<<13)
+#define SYS_CTRL_DISABLE_SYS_AHB2AXI (1<<14)
+#define SYS_CTRL_DISABLE_SYS_EXT_AHB (1<<15)
+#define SYS_CTRL_DISABLE_SYS_DEBUG_UART (1<<16)
+#define SYS_CTRL_DISABLE_SYS_DBGHST (1<<17)
+#define SYS_CTRL_DISABLE_SYSD_SCI1 (1<<18)
+#define SYS_CTRL_DISABLE_SYSD_SCI2 (1<<19)
+#define SYS_CTRL_DISABLE_SYSD_SCI3 (1<<20)
+#define SYS_CTRL_DISABLE_SYSD_RF_SPI (1<<21)
+#define SYS_CTRL_DISABLE_SYSD_OSC (1<<22)
+#define SYS_CTRL_DISABLE_SYS_GPIO (1<<23)
+#define SYS_CTRL_DISABLE_SYS_IRQ (1<<24)
+#define SYS_CTRL_DISABLE_SYS_TCU (1<<25)
+#define SYS_CTRL_DISABLE_SYS_TIMER (1<<26)
+#define SYS_CTRL_DISABLE_SYS_COM_REGS (1<<27)
+#define SYS_CTRL_DISABLE_SYS_DP_AP (1<<28)
+#define SYS_CTRL_DISABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS_SHIFT (0)
+
+//Clk_Per_Mode
+#define SYS_CTRL_MODE_PER_I2C_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_PER_I2C_MANUAL (1<<0)
+#define SYS_CTRL_MODE_PERD_SPI1_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_PERD_SPI1_MANUAL (1<<1)
+#define SYS_CTRL_MODE_PERD_SPI2_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_PERD_SPI2_MANUAL (1<<2)
+#define SYS_CTRL_MODE_CLK_PER(n) (((n)&7)<<0)
+#define SYS_CTRL_MODE_CLK_PER_MASK (7<<0)
+#define SYS_CTRL_MODE_CLK_PER_SHIFT (0)
+
+//Clk_Per_Enable
+#define SYS_CTRL_ENABLE_PER_I2C (1<<0)
+#define SYS_CTRL_ENABLE_PERD_SPI1 (1<<1)
+#define SYS_CTRL_ENABLE_PERD_SPI2 (1<<2)
+#define SYS_CTRL_ENABLE_PER_SPY (1<<3)
+#define SYS_CTRL_ENABLE_PER_TEST (1<<4)
+#define SYS_CTRL_ENABLE_CLK_PER(n) (((n)&31)<<0)
+#define SYS_CTRL_ENABLE_CLK_PER_MASK (31<<0)
+#define SYS_CTRL_ENABLE_CLK_PER_SHIFT (0)
+
+//Clk_Per_Disable
+#define SYS_CTRL_DISABLE_PER_I2C (1<<0)
+#define SYS_CTRL_DISABLE_PERD_SPI1 (1<<1)
+#define SYS_CTRL_DISABLE_PERD_SPI2 (1<<2)
+#define SYS_CTRL_DISABLE_PER_SPY (1<<3)
+#define SYS_CTRL_DISABLE_PER_TEST (1<<4)
+#define SYS_CTRL_DISABLE_CLK_PER(n) (((n)&31)<<0)
+#define SYS_CTRL_DISABLE_CLK_PER_MASK (31<<0)
+#define SYS_CTRL_DISABLE_CLK_PER_SHIFT (0)
+
+//Clk_BB_Mode
+#define SYS_CTRL_MODE_BB_BCPU (1<<0)
+#define SYS_CTRL_MODE_BB_BCPU_INT_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_BB_BCPU_INT_MANUAL (1<<1)
+#define SYS_CTRL_MODE_BB_AMBA_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_BB_AMBA_MANUAL (1<<2)
+#define SYS_CTRL_MODE_BB_PCLK_CONF_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_BB_PCLK_CONF_MANUAL (1<<3)
+#define SYS_CTRL_MODE_BB_PCLK_DATA_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_BB_PCLK_DATA_MANUAL (1<<4)
+#define SYS_CTRL_MODE_BB_EXCOR_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_BB_EXCOR_MANUAL (1<<5)
+#define SYS_CTRL_MODE_BB_IFC_CH2_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_BB_IFC_CH2_MANUAL (1<<6)
+#define SYS_CTRL_MODE_BB_IFC_CH3_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_BB_IFC_CH3_MANUAL (1<<7)
+#define SYS_CTRL_MODE_BB_SRAM_AUTOMATIC (0<<8)
+#define SYS_CTRL_MODE_BB_SRAM_MANUAL (1<<8)
+#define SYS_CTRL_MODE_BB_A2A_AUTOMATIC (0<<9)
+#define SYS_CTRL_MODE_BB_A2A_MANUAL (1<<9)
+#define SYS_CTRL_MODE_BB_ITLV_AUTOMATIC (0<<10)
+#define SYS_CTRL_MODE_BB_ITLV_MANUAL (1<<10)
+#define SYS_CTRL_MODE_BB_VITERBI_AUTOMATIC (0<<11)
+#define SYS_CTRL_MODE_BB_VITERBI_MANUAL (1<<11)
+#define SYS_CTRL_MODE_BB_CIPHER_AUTOMATIC (0<<12)
+#define SYS_CTRL_MODE_BB_CIPHER_MANUAL (1<<12)
+#define SYS_CTRL_MODE_BB_RF_IF_AUTOMATIC (0<<13)
+#define SYS_CTRL_MODE_BB_RF_IF_MANUAL (1<<13)
+#define SYS_CTRL_MODE_BB_COPRO_AUTOMATIC (0<<14)
+#define SYS_CTRL_MODE_BB_COPRO_MANUAL (1<<14)
+#define SYS_CTRL_MODE_BB_CP2_REG_AUTOMATIC (0<<15)
+#define SYS_CTRL_MODE_BB_CP2_REG_MANUAL (1<<15)
+#define SYS_CTRL_MODE_BB_XCOR_AUTOMATIC (0<<16)
+#define SYS_CTRL_MODE_BB_XCOR_MANUAL (1<<16)
+#define SYS_CTRL_MODE_BB_EVITAC_AUTOMATIC (0<<17)
+#define SYS_CTRL_MODE_BB_EVITAC_MANUAL (1<<17)
+#define SYS_CTRL_MODE_CLK_BB(n) (((n)&0x1FFFF)<<1)
+#define SYS_CTRL_MODE_CLK_BB_MASK (0x1FFFF<<1)
+#define SYS_CTRL_MODE_CLK_BB_SHIFT (1)
+
+//Clk_BB_Enable
+#define SYS_CTRL_ENABLE_BB_BCPU (1<<0)
+#define SYS_CTRL_ENABLE_BB_BCPU_INT (1<<1)
+#define SYS_CTRL_ENABLE_BB_AMBA (1<<2)
+#define SYS_CTRL_ENABLE_BB_PCLK_CONF (1<<3)
+#define SYS_CTRL_ENABLE_BB_PCLK_DATA (1<<4)
+#define SYS_CTRL_ENABLE_BB_EXCOR (1<<5)
+#define SYS_CTRL_ENABLE_BB_IFC_CH2 (1<<6)
+#define SYS_CTRL_ENABLE_BB_IFC_CH3 (1<<7)
+#define SYS_CTRL_ENABLE_BB_SRAM (1<<8)
+#define SYS_CTRL_ENABLE_BB_A2A (1<<9)
+#define SYS_CTRL_ENABLE_BB_ITLV (1<<10)
+#define SYS_CTRL_ENABLE_BB_VITERBI (1<<11)
+#define SYS_CTRL_ENABLE_BB_CIPHER (1<<12)
+#define SYS_CTRL_ENABLE_BB_RF_IF (1<<13)
+#define SYS_CTRL_ENABLE_BB_COPRO (1<<14)
+#define SYS_CTRL_ENABLE_BB_CP2_REG (1<<15)
+#define SYS_CTRL_ENABLE_BB_XCOR (1<<16)
+#define SYS_CTRL_ENABLE_BB_EVITAC (1<<17)
+#define SYS_CTRL_ENABLE_BB_IRQ (1<<18)
+#define SYS_CTRL_ENABLE_BB_COM_REGS (1<<19)
+#define SYS_CTRL_ENABLE_BB_CORDIC (1<<20)
+#define SYS_CTRL_ENABLE_CLK_BB(n) (((n)&0x1FFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_BB_MASK (0x1FFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_BB_SHIFT (0)
+
+//Clk_BB_Disable
+#define SYS_CTRL_DISABLE_BB_BCPU (1<<0)
+#define SYS_CTRL_DISABLE_BB_BCPU_INT (1<<1)
+#define SYS_CTRL_DISABLE_BB_AMBA (1<<2)
+#define SYS_CTRL_DISABLE_BB_PCLK_CONF (1<<3)
+#define SYS_CTRL_DISABLE_BB_PCLK_DATA (1<<4)
+#define SYS_CTRL_DISABLE_BB_EXCOR (1<<5)
+#define SYS_CTRL_DISABLE_BB_IFC_CH2 (1<<6)
+#define SYS_CTRL_DISABLE_BB_IFC_CH3 (1<<7)
+#define SYS_CTRL_DISABLE_BB_SRAM (1<<8)
+#define SYS_CTRL_DISABLE_BB_A2A (1<<9)
+#define SYS_CTRL_DISABLE_BB_ITLV (1<<10)
+#define SYS_CTRL_DISABLE_BB_VITERBI (1<<11)
+#define SYS_CTRL_DISABLE_BB_CIPHER (1<<12)
+#define SYS_CTRL_DISABLE_BB_RF_IF (1<<13)
+#define SYS_CTRL_DISABLE_BB_COPRO (1<<14)
+#define SYS_CTRL_DISABLE_BB_CP2_REG (1<<15)
+#define SYS_CTRL_DISABLE_BB_XCOR (1<<16)
+#define SYS_CTRL_DISABLE_BB_EVITAC (1<<17)
+#define SYS_CTRL_DISABLE_BB_IRQ (1<<18)
+#define SYS_CTRL_DISABLE_BB_COM_REGS (1<<19)
+#define SYS_CTRL_DISABLE_BB_CORDIC (1<<20)
+#define SYS_CTRL_DISABLE_CLK_BB(n) (((n)&0x1FFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_BB_MASK (0x1FFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_BB_SHIFT (0)
+
+//Clk_Other_Mode
+#define SYS_CTRL_MODE_OC_DEBUG_UART_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_OC_DEBUG_UART_MANUAL (1<<0)
+#define SYS_CTRL_MODE_OC_RF_RX_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_OC_RF_RX_MANUAL (1<<1)
+#define SYS_CTRL_MODE_OC_RF_TX_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_OC_RF_TX_MANUAL (1<<2)
+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_MANUAL (1<<3)
+#define SYS_CTRL_MODE_CLK_OTHER(n) (((n)&15)<<0)
+#define SYS_CTRL_MODE_CLK_OTHER_MASK (15<<0)
+#define SYS_CTRL_MODE_CLK_OTHER_SHIFT (0)
+
+//Clk_Other_Enable
+#define SYS_CTRL_ENABLE_OC_DEBUG_UART (1<<0)
+#define SYS_CTRL_ENABLE_OC_RF_RX (1<<1)
+#define SYS_CTRL_ENABLE_OC_RF_TX (1<<2)
+#define SYS_CTRL_ENABLE_OC_MEM_BRIDGE (1<<3)
+#define SYS_CTRL_ENABLE_OC_LPS (1<<4)
+#define SYS_CTRL_ENABLE_OC_GPIO (1<<5)
+#define SYS_CTRL_ENABLE_OC_CLK_OUT (1<<6)
+#define SYS_CTRL_ENABLE_OC_MEM_CLK_OUT (1<<7)
+#define SYS_CTRL_ENABLE_OC_TCU (1<<8)
+#define SYS_CTRL_ENABLE_CLK_OTHER(n) (((n)&0x1FF)<<0)
+#define SYS_CTRL_ENABLE_CLK_OTHER_MASK (0x1FF<<0)
+#define SYS_CTRL_ENABLE_CLK_OTHER_SHIFT (0)
+
+//Clk_Other_Disable
+#define SYS_CTRL_DISABLE_OC_DEBUG_UART (1<<0)
+#define SYS_CTRL_DISABLE_OC_RF_RX (1<<1)
+#define SYS_CTRL_DISABLE_OC_RF_TX (1<<2)
+#define SYS_CTRL_DISABLE_OC_MEM_BRIDGE (1<<3)
+#define SYS_CTRL_DISABLE_OC_LPS (1<<4)
+#define SYS_CTRL_DISABLE_OC_GPIO (1<<5)
+#define SYS_CTRL_DISABLE_OC_CLK_OUT (1<<6)
+#define SYS_CTRL_DISABLE_OC_MEM_CLK_OUT (1<<7)
+#define SYS_CTRL_DISABLE_OC_TCU (1<<8)
+#define SYS_CTRL_DISABLE_CLK_OTHER(n) (((n)&0x1FF)<<0)
+#define SYS_CTRL_DISABLE_CLK_OTHER_MASK (0x1FF<<0)
+#define SYS_CTRL_DISABLE_CLK_OTHER_SHIFT (0)
+
+//Pll_Ctrl
+#define SYS_CTRL_PLL_ENABLE (1<<0)
+#define SYS_CTRL_PLL_ENABLE_MASK (1<<0)
+#define SYS_CTRL_PLL_ENABLE_SHIFT (0)
+#define SYS_CTRL_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_PLL_LOCK_RESET (1<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_PLL_BYPASS (1<<8)
+#define SYS_CTRL_PLL_BYPASS_MASK (1<<8)
+#define SYS_CTRL_PLL_BYPASS_SHIFT (8)
+#define SYS_CTRL_PLL_BYPASS_PASS (0<<8)
+#define SYS_CTRL_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_PLL_XP_CFG(n) (((n)&4369)<<0)
+#define SYS_CTRL_PLL_XP_CFG_MASK (4369<<0)
+#define SYS_CTRL_PLL_XP_CFG_SHIFT (0)
+
+//Sel_Clock
+#define SYS_CTRL_SLOW_SEL_RF_OSCILLATOR (1<<0)
+#define SYS_CTRL_SLOW_SEL_RF_RF (0<<0)
+#define SYS_CTRL_SYS_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_SYS_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_TCU_13M_L_26M (1<<5)
+#define SYS_CTRL_TCU_13M_L_13M (0<<5)
+#define SYS_CTRL_PLL_DISABLE_LPS_DISABLE (1<<6)
+#define SYS_CTRL_PLL_DISABLE_LPS_ENABLE (0<<6)
+#define SYS_CTRL_DIGEN_H_ENABLE (1<<7)
+#define SYS_CTRL_DIGEN_H_DISABLE (0<<7)
+#define SYS_CTRL_RF_DETECTED_OK (1<<20)
+#define SYS_CTRL_RF_DETECTED_NO (0<<20)
+#define SYS_CTRL_RF_DETECT_BYPASS (1<<21)
+#define SYS_CTRL_RF_DETECT_RESET (1<<22)
+#define SYS_CTRL_RF_SELECTED_L (1<<23)
+#define SYS_CTRL_PLL_LOCKED (1<<24)
+#define SYS_CTRL_PLL_LOCKED_MASK (1<<24)
+#define SYS_CTRL_PLL_LOCKED_SHIFT (24)
+#define SYS_CTRL_PLL_LOCKED_LOCKED (1<<24)
+#define SYS_CTRL_PLL_LOCKED_NOT_LOCKED (0<<24)
+#define SYS_CTRL_PLL_BYPASS_LOCK (1<<27)
+#define SYS_CTRL_FAST_SELECTED_L (1<<31)
+#define SYS_CTRL_FAST_SELECTED_L_MASK (1<<31)
+#define SYS_CTRL_FAST_SELECTED_L_SHIFT (31)
+
+//Cfg_Clk_Sys
+#define SYS_CTRL_FREQ(n) (((n)&15)<<0)
+#define SYS_CTRL_FREQ_MASK (15<<0)
+#define SYS_CTRL_FREQ_SHIFT (0)
+#define SYS_CTRL_FREQ_312M (13<<0)
+#define SYS_CTRL_FREQ_250M (12<<0)
+#define SYS_CTRL_FREQ_208M (11<<0)
+#define SYS_CTRL_FREQ_178M (10<<0)
+#define SYS_CTRL_FREQ_156M (9<<0)
+#define SYS_CTRL_FREQ_139M (8<<0)
+#define SYS_CTRL_FREQ_125M (7<<0)
+#define SYS_CTRL_FREQ_113M (6<<0)
+#define SYS_CTRL_FREQ_104M (5<<0)
+#define SYS_CTRL_FREQ_89M (4<<0)
+#define SYS_CTRL_FREQ_78M (3<<0)
+#define SYS_CTRL_FREQ_52M (2<<0)
+#define SYS_CTRL_FREQ_39M (1<<0)
+#define SYS_CTRL_FREQ_26M (0<<0)
+#define SYS_CTRL_FORCE_DIV_UPDATE (1<<4)
+#define SYS_CTRL_REQ_DIV_UPDATE (1<<8)
+
+//Cfg_Clk_Mem_Bridge
+#define SYS_CTRL_MEM_FREQ(n) (((n)&15)<<0)
+#define SYS_CTRL_MEM_FREQ_MASK (15<<0)
+#define SYS_CTRL_MEM_FREQ_SHIFT (0)
+#define SYS_CTRL_MEM_FREQ_312M (13<<0)
+#define SYS_CTRL_MEM_FREQ_250M (12<<0)
+#define SYS_CTRL_MEM_FREQ_208M (11<<0)
+#define SYS_CTRL_MEM_FREQ_178M (10<<0)
+#define SYS_CTRL_MEM_FREQ_156M (9<<0)
+#define SYS_CTRL_MEM_FREQ_139M (8<<0)
+#define SYS_CTRL_MEM_FREQ_125M (7<<0)
+#define SYS_CTRL_MEM_FREQ_113M (6<<0)
+#define SYS_CTRL_MEM_FREQ_104M (5<<0)
+#define SYS_CTRL_MEM_FREQ_89M (4<<0)
+#define SYS_CTRL_MEM_FREQ_78M (3<<0)
+#define SYS_CTRL_MEM_FREQ_52M (2<<0)
+#define SYS_CTRL_MEM_FREQ_39M (1<<0)
+#define SYS_CTRL_MEM_FREQ_26M (0<<0)
+#define SYS_CTRL_DDR_MODE_EN_NORMAL_MODE (0<<4)
+#define SYS_CTRL_DDR_MODE_EN_DDR_MODE (1<<4)
+#define SYS_CTRL_DDR_FAST_CLK_POL_INVERT (1<<5)
+#define SYS_CTRL_DDR_FAST_CLK_POL_NORMAL (0<<5)
+#define SYS_CTRL_DDR_DQSL_O(n) (((n)&31)<<6)
+#define SYS_CTRL_DDR_DQSU_O(n) (((n)&31)<<11)
+#define SYS_CTRL_DDR_DQS_OEN(n) (((n)&31)<<16)
+#define SYS_CTRL_DDR_DQSL_I(n) (((n)&31)<<21)
+#define SYS_CTRL_DDR_DQSU_I(n) (((n)&31)<<26)
+#define SYS_CTRL_MEM_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_Out
+#define SYS_CTRL_CLKOUT_DIVIDER(n) (((n)&31)<<0)
+#define SYS_CTRL_CLKOUT_SEL_OSC (0<<8)
+#define SYS_CTRL_CLKOUT_SEL_RF (1<<8)
+#define SYS_CTRL_CLKOUT_SEL_DIVIDER (2<<8)
+
+//Cfg_Clk_Host_Uart
+#define SYS_CTRL_HOST_UART_DIVIDER(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_HOST_UART_DIVIDER_MASK (0x3FF<<0)
+#define SYS_CTRL_HOST_UART_DIVIDER_SHIFT (0)
+#define SYS_CTRL_HOST_UART_SEL_PLL_SLOW (0<<12)
+#define SYS_CTRL_HOST_UART_SEL_PLL_PLL (1<<12)
+
+//Cfg_Clk_Auxclk
+#define SYS_CTRL_AUXCLK_EN_DISABLE (0<<0)
+#define SYS_CTRL_AUXCLK_EN_ENABLE (1<<0)
+
+//Cfg_AHB
+#define SYS_CTRL_SYS_NEW_ARBITRATION_ENABLE (1<<0)
+#define SYS_CTRL_SYS_NEW_ARBITRATION_DISABLE (0<<0)
+#define SYS_CTRL_ENABLE_SYS_MID_BIST_ENABLE (1<<1)
+#define SYS_CTRL_ENABLE_SYS_MID_BIST_DISABLE (0<<1)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA_ENABLE (1<<2)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA_DISABLE (0<<2)
+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_ENABLE (1<<3)
+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_DISABLE (0<<3)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_ENABLE (1<<4)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_DISABLE (0<<4)
+#define SYS_CTRL_ENABLE_SYS_MID_IFC_ENABLE (1<<5)
+#define SYS_CTRL_ENABLE_SYS_MID_IFC_DISABLE (0<<5)
+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_ENABLE (1<<6)
+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_DISABLE (0<<6)
+#define SYS_CTRL_BB_NEW_ARBITRATION_ENABLE (1<<16)
+#define SYS_CTRL_BB_NEW_ARBITRATION_DISABLE (0<<16)
+#define SYS_CTRL_ENABLE_BB_MID_BIST_ENABLE (1<<17)
+#define SYS_CTRL_ENABLE_BB_MID_BIST_DISABLE (0<<17)
+#define SYS_CTRL_ENABLE_BB_MID_IFC_ENABLE (1<<18)
+#define SYS_CTRL_ENABLE_BB_MID_IFC_DISABLE (0<<18)
+#define SYS_CTRL_ENABLE_BB_MID_BCPU_ENABLE (1<<19)
+#define SYS_CTRL_ENABLE_BB_MID_BCPU_DISABLE (0<<19)
+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_ENABLE (1<<20)
+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_DISABLE (0<<20)
+#define SYS_CTRL_SYS_ENABLE(n) (((n)&0x3F)<<1)
+#define SYS_CTRL_SYS_ENABLE_MASK (0x3F<<1)
+#define SYS_CTRL_SYS_ENABLE_SHIFT (1)
+#define SYS_CTRL_BB_ENABLE(n) (((n)&15)<<17)
+#define SYS_CTRL_BB_ENABLE_MASK (15<<17)
+#define SYS_CTRL_BB_ENABLE_SHIFT (17)
+
+//Ctrl_AHB
+#define SYS_CTRL_SPLIT_SYS_MID_BIST_NORMAL (1<<0)
+#define SYS_CTRL_SPLIT_SYS_MID_BIST_FORCE (0<<0)
+#define SYS_CTRL_SPLIT_SYS_MID_DMA_NORMAL (1<<1)
+#define SYS_CTRL_SPLIT_SYS_MID_DMA_FORCE (0<<1)
+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_NORMAL (1<<2)
+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_FORCE (0<<2)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_NORMAL (1<<3)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_FORCE (0<<3)
+#define SYS_CTRL_SPLIT_SYS_MID_IFC_NORMAL (1<<4)
+#define SYS_CTRL_SPLIT_SYS_MID_IFC_FORCE (0<<4)
+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_NORMAL (1<<5)
+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_FORCE (0<<5)
+#define SYS_CTRL_SPLIT_BB_MID_BIST_NORMAL (1<<16)
+#define SYS_CTRL_SPLIT_BB_MID_BIST_FORCE (0<<16)
+#define SYS_CTRL_SPLIT_BB_MID_IFC_NORMAL (1<<17)
+#define SYS_CTRL_SPLIT_BB_MID_IFC_FORCE (0<<17)
+#define SYS_CTRL_SPLIT_BB_MID_BCPU_NORMAL (1<<18)
+#define SYS_CTRL_SPLIT_BB_MID_BCPU_FORCE (0<<18)
+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_NORMAL (1<<19)
+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_FORCE (0<<19)
+#define SYS_CTRL_SYS_FORCE_HSPLIT(n) (((n)&0x3F)<<0)
+#define SYS_CTRL_SYS_FORCE_HSPLIT_MASK (0x3F<<0)
+#define SYS_CTRL_SYS_FORCE_HSPLIT_SHIFT (0)
+#define SYS_CTRL_BB_FORCE_HSPLIT(n) (((n)&15)<<16)
+#define SYS_CTRL_BB_FORCE_HSPLIT_MASK (15<<16)
+#define SYS_CTRL_BB_FORCE_HSPLIT_SHIFT (16)
+
+//XCpu_Dbg_BKP
+#define SYS_CTRL_BKPT_EN (1<<0)
+#define SYS_CTRL_BKPT_MODE(n) (((n)&3)<<4)
+#define SYS_CTRL_BKPT_MODE_I (0<<4)
+#define SYS_CTRL_BKPT_MODE_R (1<<4)
+#define SYS_CTRL_BKPT_MODE_W (2<<4)
+#define SYS_CTRL_BKPT_MODE_RW (3<<4)
+#define SYS_CTRL_STALLED (1<<8)
+
+//XCpu_Dbg_Addr
+#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)
+
+//BCpu_Dbg_BKP
+//#define SYS_CTRL_BKPT_EN (1<<0)
+//#define SYS_CTRL_BKPT_MODE(n) (((n)&3)<<4)
+//#define SYS_CTRL_BKPT_MODE_I (0<<4)
+//#define SYS_CTRL_BKPT_MODE_R (1<<4)
+//#define SYS_CTRL_BKPT_MODE_W (2<<4)
+//#define SYS_CTRL_BKPT_MODE_RW (3<<4)
+//#define SYS_CTRL_STALLED (1<<8)
+
+//BCpu_Dbg_Addr
+//#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)
+
+//Cfg_Cpus_Cache_Ram_Disable
+#define SYS_CTRL_XCPU_USE_MODE (1<<0)
+#define SYS_CTRL_XCPU_CLK_OFF_MODE (1<<1)
+#define SYS_CTRL_BCPU_USE_MODE (1<<16)
+#define SYS_CTRL_BCPU_CLK_OFF_MODE (1<<17)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<0)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_MASK (3<<0)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_SHIFT (0)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<16)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_MASK (3<<16)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_SHIFT (16)
+
+//Reset_Cause
+#define SYS_CTRL_WATCHDOG_RESET_HAPPENED (1<<0)
+#define SYS_CTRL_WATCHDOG_RESET_NO (0<<0)
+#define SYS_CTRL_APSOFT_RESET_HAPPENED (1<<1)
+#define SYS_CTRL_APSOFT_RESET_NO (0<<1)
+#define SYS_CTRL_GLOBALSOFT_RESET_HAPPENED (1<<4)
+#define SYS_CTRL_GLOBALSOFT_RESET_NO (0<<4)
+#define SYS_CTRL_HOSTDEBUG_RESET_HAPPENED (1<<5)
+#define SYS_CTRL_HOSTDEBUG_RESET_NO (0<<5)
+#define SYS_CTRL_ALARMCAUSE_HAPPENED (1<<6)
+#define SYS_CTRL_ALARMCAUSE_NO (0<<6)
+#define SYS_CTRL_MEMCHECKDONE_MASK (1<<7)
+#define SYS_CTRL_MEMCHECKDONE_SHIFT (7)
+#define SYS_CTRL_MEMCHECKDONE_DONE (1<<7)
+#define SYS_CTRL_MEMCHECKDONE_RUNNING (0<<7)
+#define SYS_CTRL_BOOT_MODE(n) (((n)&0xFFFF)<<8)
+#define SYS_CTRL_BOOT_MODE_MASK (0xFFFF<<8)
+#define SYS_CTRL_BOOT_MODE_SHIFT (8)
+#define SYS_CTRL_SW_BOOT_MODE(n) (((n)&0x7F)<<24)
+#define SYS_CTRL_SW_BOOT_MODE_MASK (0x7F<<24)
+#define SYS_CTRL_SW_BOOT_MODE_SHIFT (24)
+#define SYS_CTRL_FONCTIONAL_TEST_MODE (1<<31)
+
+//WakeUp
+#define SYS_CTRL_FORCE_WAKEUP (1<<0)
+
+//AP_Ctrl
+#define SYS_CTRL_AP_INT_STATUS (1<<0)
+#define SYS_CTRL_AP_INT_MASK (1<<16)
+#define SYS_CTRL_AP_DEEPSLEEP_EN (1<<24)
+
+//Ignore_Charger
+#define SYS_CTRL_IGNORE_CHARGER (1<<0)
+
+//Cfg_Reserve
+#define SYS_CTRL_RESERVE_L(n) (((n)&0x3FFF)<<0)
+#define SYS_CTRL_AUIFC_CH0_IRQ_MASK (1<<14)
+#define SYS_CTRL_AUIFC_CH1_IRQ_MASK (1<<15)
+#define SYS_CTRL_RESERVE_H(n) (((n)&0xFFFF)<<16)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810h.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810h.h new file mode 100644 index 0000000000..0ecd75897f --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810h.h @@ -0,0 +1,979 @@ +#ifndef _REG_MD_SYSCTRL_H_
+#define _REG_MD_SYSCTRL_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+// MACROS
+// =============================================================================
+
+// ============================================================================
+// CPU_ID_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// CPU IDs
+ XCPU = 0x00000000,
+ BCPU = 0x00000001
+} CPU_ID_T;
+
+
+// ============================================================================
+// SYS_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// System side System clocks
+ SYS_XCPU = 0x00000000,
+ SYS_XCPU_INT = 0x00000001,
+ SYS_PCLK_CONF = 0x00000002,
+ SYS_PCLK_DATA = 0x00000003,
+ SYS_AMBA = 0x00000004,
+ SYS_DMA = 0x00000005,
+ SYS_EBC = 0x00000006,
+ SYS_IFC_CH0 = 0x00000007,
+ SYS_IFC_CH1 = 0x00000008,
+ SYS_IFC_CH2 = 0x00000009,
+ SYS_IFC_CH3 = 0x0000000A,
+ SYS_IFC_DBG = 0x0000000B,
+ SYS_A2A = 0x0000000C,
+ SYS_AXI2AHB = 0x0000000D,
+ SYS_AHB2AXI = 0x0000000E,
+ SYS_EXT_AHB = 0x0000000F,
+ SYS_DEBUG_UART = 0x00000010,
+ SYS_DBGHST = 0x00000011,
+/// System side divided clock (either divided by module or by sys_ctrl)
+ SYSD_SCI1 = 0x00000012,
+ SYSD_SCI2 = 0x00000013,
+ SYSD_SCI3 = 0x00000014,
+ SYSD_RF_SPI = 0x00000015,
+ SYSD_OSC = 0x00000016,
+/// the following don't have an auto enable
+ SYS_GPIO = 0x00000017,
+ SYS_IRQ = 0x00000018,
+ SYS_TCU = 0x00000019,
+ SYS_TIMER = 0x0000001A,
+ SYS_COM_REGS = 0x0000001B,
+ SYS_DP_AP = 0x0000001C,
+/// the following are sharing their enable
+ SYS_SCI1 = 0x0000001D,
+ SYS_SCI2 = 0x0000001E,
+ SYS_SCI3 = 0x0000001F,
+/// keep last
+ SYS_NOGATE = 0x00000020
+} SYS_CLKS_T;
+
+#define NB_SYS_CLK_XCPU (2)
+#define NB_SYS_CLK_AEN (23)
+#define NB_SYS_CLK_EN (29)
+#define NB_SYS_CLK (33)
+
+// ============================================================================
+// PER_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+ PER_I2C = 0x00000000,
+/// System side divided clock (either divided by module or by sys_ctrl)
+ PERD_SPI1 = 0x00000001,
+/// System side divided clock (either divided by module or by sys_ctrl)
+ PERD_SPI2 = 0x00000002,
+ PER_SPY = 0x00000003,
+ PER_TEST = 0x00000004
+} PER_CLKS_T;
+
+#define NB_PER_CLK_AEN (3)
+#define NB_PER_CLK_EN (5)
+#define NB_PER_CLK (5)
+
+// ============================================================================
+// BB_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// Baseband side System clocks
+ BB_BCPU = 0x00000000,
+ BB_BCPU_INT = 0x00000001,
+ BB_AMBA = 0x00000002,
+ BB_PCLK_CONF = 0x00000003,
+ BB_PCLK_DATA = 0x00000004,
+ BB_EXCOR = 0x00000005,
+ BB_IFC_CH2 = 0x00000006,
+ BB_IFC_CH3 = 0x00000007,
+ BB_SRAM = 0x00000008,
+ BB_A2A = 0x00000009,
+ BB_ITLV = 0x0000000A,
+ BB_VITERBI = 0x0000000B,
+ BB_CIPHER = 0x0000000C,
+ BB_RF_IF = 0x0000000D,
+ BB_COPRO = 0x0000000E,
+ BB_CP2_REG = 0x0000000F,
+ BB_XCOR = 0x00000010,
+ BB_EVITAC = 0x00000011,
+/// the following don't have an auto enable
+ BB_IRQ = 0x00000012,
+ BB_COM_REGS = 0x00000013,
+ BB_CORDIC = 0x00000014
+} BB_CLKS_T;
+
+#define NB_BB_CLK_AEN (18)
+#define NB_BB_CLK_EN (21)
+#define NB_BB_CLK (21)
+/// Other clocks
+/// clocks with auto enble
+/// the debug host clock auto enable is not used in host mode, only in uart mode
+#define OC_HOST_UART (0)
+
+// ============================================================================
+// OTHER_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+ OC_DEBUG_UART = 0x00000000,
+ OC_RF_RX = 0x00000001,
+ OC_RF_TX = 0x00000002,
+ OC_MEM_BRIDGE = 0x00000003,
+/// the following don't have an auto enable
+ OC_LPS = 0x00000004,
+ OC_GPIO = 0x00000005,
+ OC_CLK_OUT = 0x00000006,
+ OC_MEM_CLK_OUT = 0x00000007,
+ OC_TCU = 0x00000008
+} OTHER_CLKS_T;
+
+#define NB_OTHER_CLK_AEN (4)
+#define NB_OTHER_CLK_EN (9)
+#define NB_OTHER_CLK (9)
+
+// ============================================================================
+// RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// System side resets
+ RST_XCPU = 0x00000000,
+ RST_SYS_IRQ = 0x00000001,
+ RST_SYS_A2A = 0x00000002,
+ RST_SYS_AHB2AXI = 0x00000003,
+ RST_SYS_AXI2AHB = 0x00000004,
+ RST_DMA = 0x00000005,
+ RST_TIMER = 0x00000006,
+ RST_TCU = 0x00000007,
+ RST_GPIO = 0x00000008,
+ RST_I2C = 0x00000009,
+ RST_SPI1 = 0x0000000A,
+ RST_SPI2 = 0x0000000B,
+ RST_RF_SPI = 0x0000000C,
+ RST_SCI1 = 0x0000000D,
+ RST_SCI2 = 0x0000000E,
+ RST_SCI3 = 0x0000000F,
+ RST_SPY = 0x00000010,
+ RST_MEM_BRIDGE = 0x00000011,
+ RST_EXT_AHB = 0x00000012,
+ RST_DP_AP = 0x00000013,
+ RST_COMREGS = 0x00000014,
+ RST_COMREGS_AP = 0x00000015,
+ RST_AP_CLKEN = 0x00000016,
+ RST_AP_RST = 0x00000017,
+ RST_MEM_CHK = 0x00000018,
+ RST_AP_RST1 = 0x00000019,
+ RST_AP_RST2 = 0x0000001A,
+ RST_AP_RST3 = 0x0000001B,
+ RST_AP_RST4 = 0x0000001C,
+ RST_AP_RST5 = 0x0000001D,
+ RST_BCPU = 0x0000001E,
+ RST_BB_IRQ = 0x0000001F,
+ RST_BB_A2A = 0x00000020,
+ RST_BB_IFC = 0x00000021,
+ RST_BB_SRAM = 0x00000022,
+ RST_ITLV = 0x00000023,
+ RST_VITERBI = 0x00000024,
+ RST_CIPHER = 0x00000025,
+ RST_XCOR = 0x00000026,
+ RST_COPRO = 0x00000027,
+ RST_RF_IF = 0x00000028,
+ RST_EXCOR = 0x00000029,
+ RST_EVITAC = 0x0000002A,
+ RST_CORDIC = 0x0000002B,
+ RST_TCU_BB = 0x0000002C,
+ RST_BB_FULL = 0x0000002D,
+ RST_SYS_FULL = 0x0000002E
+} RESETS_T;
+
+#define NB_SRST (30)
+/// Baseband side resets
+#define BOUND_BRST_FIRST (30)
+#define BOUND_BRST_AFTER (45)
+/// The following reset does not have register
+#define NR_RST_REG (46)
+#define NB_RST (47)
+#define NB_BRST (BOUND_BRST_AFTER-BOUND_BRST_FIRST)
+
+// ============================================================================
+// RESET_OTHERS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// Reset Other : resync on corresponding clock other
+ RSTO_DBG_HOST = 0x00000000,
+ RSTO_RF_RX = 0x00000001,
+ RSTO_RF_TX = 0x00000002,
+ RSTO_MEM_BRIDGE = 0x00000003,
+ RSTO_LPS = 0x00000004,
+ RSTO_GPIO = 0x00000005,
+ RSTO_WDTIMER = 0x00000006,
+ RSTO_TCU = 0x00000007
+} RESET_OTHERS_T;
+
+#define BOUND_RSTO_RF_FIRST (1)
+#define BOUND_RSTO_RF_AFTER (3)
+#define NB_RSTO (8)
+/// For REG_DBG protect lock/unlock value
+#define SYS_CTRL_PROTECT_LOCK (0XA50000)
+#define SYS_CTRL_PROTECT_UNLOCK (0XA50001)
+
+// =============================================================================
+// TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_CTRL_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef volatile struct
+{
+ /// <strong>This register is used to Lock and Unlock the protected registers.</strong>
+ REG32 REG_DBG; //0x00000000
+ /// This register is protected.
+ REG32 Sys_Rst_Set; //0x00000004
+ REG32 Sys_Rst_Clr; //0x00000008
+ /// This register is protected.
+ REG32 BB_Rst_Set; //0x0000000C
+ REG32 BB_Rst_Clr; //0x00000010
+ REG32 Clk_Sys_Mode; //0x00000014
+ REG32 Clk_Sys_Enable; //0x00000018
+ /// This register is protected.
+ REG32 Clk_Sys_Disable; //0x0000001C
+ REG32 Clk_Per_Mode; //0x00000020
+ REG32 Clk_Per_Enable; //0x00000024
+ /// This register is protected.
+ REG32 Clk_Per_Disable; //0x00000028
+ REG32 Clk_BB_Mode; //0x0000002C
+ REG32 Clk_BB_Enable; //0x00000030
+ /// This register is protected.
+ REG32 Clk_BB_Disable; //0x00000034
+ REG32 Clk_Other_Mode; //0x00000038
+ REG32 Clk_Other_Enable; //0x0000003C
+ /// This register is protected.
+ REG32 Clk_Other_Disable; //0x00000040
+ /// Register protected by Write_Unlocked_H.
+ REG32 Pll_Ctrl; //0x00000044
+ /// This register is protected.
+ REG32 Sel_Clock; //0x00000048
+ REG32 Cfg_Clk_Sys; //0x0000004C
+ REG32 Cfg_Clk_Mem_Bridge; //0x00000050
+ /// This register is protected.
+ REG32 Cfg_Clk_Out; //0x00000054
+ REG32 Cfg_Clk_Host_Uart; //0x00000058
+ REG32 Cfg_Clk_Auxclk; //0x0000005C
+ /// This register is protected.
+ REG32 Cfg_AHB; //0x00000060
+ /// This register is protected. Used to unsplit masters manualy.
+ REG32 Ctrl_AHB; //0x00000064
+ REG32 XCpu_Dbg_BKP; //0x00000068
+ REG32 XCpu_Dbg_Addr; //0x0000006C
+ REG32 BCpu_Dbg_BKP; //0x00000070
+ REG32 BCpu_Dbg_Addr; //0x00000074
+ REG32 Cfg_Cpus_Cache_Ram_Disable; //0x00000078
+ REG32 Reset_Cause; //0x0000007C
+ /// This register is protected.
+ REG32 WakeUp; //0x00000080
+ REG32 AP_Ctrl; //0x00000084
+ /// This register is protected.
+ REG32 Ignore_Charger; //0x00000088
+ REG32 Reserved_0000008C[28]; //0x0000008C
+ /// This register is reserved.
+ REG32 Cfg_Reserve; //0x000000FC
+} HWP_SYS_CTRL_T;
+
+#define hwp_sysCtrlMd ((HWP_SYS_CTRL_T*)(RDA_MD_SYSCTRL_BASE))
+
+
+//REG_DBG
+#define SYS_CTRL_SCRATCH(n) (((n)&0xFFFF)<<0)
+#define SYS_CTRL_WRITE_UNLOCK_STATUS (1<<30)
+#define SYS_CTRL_WRITE_UNLOCK (1<<31)
+
+//Sys_Rst_Set
+#define SYS_CTRL_SET_RST_XCPU (1<<0)
+#define SYS_CTRL_SET_RST_SYS_IRQ (1<<1)
+#define SYS_CTRL_SET_RST_SYS_A2A (1<<2)
+#define SYS_CTRL_SET_RST_SYS_AHB2AXI (1<<3)
+#define SYS_CTRL_SET_RST_SYS_AXI2AHB (1<<4)
+#define SYS_CTRL_SET_RST_DMA (1<<5)
+#define SYS_CTRL_SET_RST_TIMER (1<<6)
+#define SYS_CTRL_SET_RST_TCU (1<<7)
+#define SYS_CTRL_SET_RST_GPIO (1<<8)
+#define SYS_CTRL_SET_RST_I2C (1<<9)
+#define SYS_CTRL_SET_RST_SPI1 (1<<10)
+#define SYS_CTRL_SET_RST_SPI2 (1<<11)
+#define SYS_CTRL_SET_RST_RF_SPI (1<<12)
+#define SYS_CTRL_SET_RST_SCI1 (1<<13)
+#define SYS_CTRL_SET_RST_SCI2 (1<<14)
+#define SYS_CTRL_SET_RST_SCI3 (1<<15)
+#define SYS_CTRL_SET_RST_SPY (1<<16)
+#define SYS_CTRL_SET_RST_MEM_BRIDGE (1<<17)
+#define SYS_CTRL_SET_RST_EXT_AHB (1<<18)
+#define SYS_CTRL_SET_RST_DP_AP (1<<19)
+#define SYS_CTRL_SET_RST_COMREGS (1<<20)
+#define SYS_CTRL_SET_RST_COMREGS_AP (1<<21)
+#define SYS_CTRL_SET_RST_AP_CLKEN (1<<22)
+#define SYS_CTRL_SET_RST_AP_RST (1<<23)
+#define SYS_CTRL_SET_RST_MEM_CHK (1<<24)
+#define SYS_CTRL_SET_RST_AP_RST1 (1<<25)
+#define SYS_CTRL_SET_RST_AP_RST2 (1<<26)
+#define SYS_CTRL_SET_RST_AP_RST3 (1<<27)
+#define SYS_CTRL_SET_RST_AP_RST4 (1<<28)
+#define SYS_CTRL_SET_RST_AP_RST5 (1<<29)
+#define SYS_CTRL_SET_RST_OUT (1<<30)
+#define SYS_CTRL_SOFT_RST (1<<31)
+#define SYS_CTRL_SET_SYS_RST(n) (((n)&0x3FFFFFFF)<<0)
+#define SYS_CTRL_SET_SYS_RST_MASK (0x3FFFFFFF<<0)
+#define SYS_CTRL_SET_SYS_RST_SHIFT (0)
+
+//Sys_Rst_Clr
+#define SYS_CTRL_CLR_RST_XCPU (1<<0)
+#define SYS_CTRL_CLR_RST_SYS_IRQ (1<<1)
+#define SYS_CTRL_CLR_RST_SYS_A2A (1<<2)
+#define SYS_CTRL_CLR_RST_SYS_AHB2AXI (1<<3)
+#define SYS_CTRL_CLR_RST_SYS_AXI2AHB (1<<4)
+#define SYS_CTRL_CLR_RST_DMA (1<<5)
+#define SYS_CTRL_CLR_RST_TIMER (1<<6)
+#define SYS_CTRL_CLR_RST_TCU (1<<7)
+#define SYS_CTRL_CLR_RST_GPIO (1<<8)
+#define SYS_CTRL_CLR_RST_I2C (1<<9)
+#define SYS_CTRL_CLR_RST_SPI1 (1<<10)
+#define SYS_CTRL_CLR_RST_SPI2 (1<<11)
+#define SYS_CTRL_CLR_RST_RF_SPI (1<<12)
+#define SYS_CTRL_CLR_RST_SCI1 (1<<13)
+#define SYS_CTRL_CLR_RST_SCI2 (1<<14)
+#define SYS_CTRL_CLR_RST_SCI3 (1<<15)
+#define SYS_CTRL_CLR_RST_SPY (1<<16)
+#define SYS_CTRL_CLR_RST_MEM_BRIDGE (1<<17)
+#define SYS_CTRL_CLR_RST_EXT_AHB (1<<18)
+#define SYS_CTRL_CLR_RST_DP_AP (1<<19)
+#define SYS_CTRL_CLR_RST_COMREGS (1<<20)
+#define SYS_CTRL_CLR_RST_COMREGS_AP (1<<21)
+#define SYS_CTRL_CLR_RST_AP_CLKEN (1<<22)
+#define SYS_CTRL_CLR_RST_AP_RST (1<<23)
+#define SYS_CTRL_CLR_RST_MEM_CHK (1<<24)
+#define SYS_CTRL_CLR_RST_AP_RST1 (1<<25)
+#define SYS_CTRL_CLR_RST_AP_RST2 (1<<26)
+#define SYS_CTRL_CLR_RST_AP_RST3 (1<<27)
+#define SYS_CTRL_CLR_RST_AP_RST4 (1<<28)
+#define SYS_CTRL_CLR_RST_AP_RST5 (1<<29)
+#define SYS_CTRL_CLR_RST_OUT (1<<30)
+#define SYS_CTRL_CLR_SYS_RST(n) (((n)&0x3FFFFFFF)<<0)
+#define SYS_CTRL_CLR_SYS_RST_MASK (0x3FFFFFFF<<0)
+#define SYS_CTRL_CLR_SYS_RST_SHIFT (0)
+
+//BB_Rst_Set
+#define SYS_CTRL_SET_RST_BCPU (1<<0)
+#define SYS_CTRL_SET_RST_BB_IRQ (1<<1)
+#define SYS_CTRL_SET_RST_BB_A2A (1<<2)
+#define SYS_CTRL_SET_RST_BB_IFC (1<<3)
+#define SYS_CTRL_SET_RST_BB_SRAM (1<<4)
+#define SYS_CTRL_SET_RST_ITLV (1<<5)
+#define SYS_CTRL_SET_RST_VITERBI (1<<6)
+#define SYS_CTRL_SET_RST_CIPHER (1<<7)
+#define SYS_CTRL_SET_RST_XCOR (1<<8)
+#define SYS_CTRL_SET_RST_COPRO (1<<9)
+#define SYS_CTRL_SET_RST_RF_IF (1<<10)
+#define SYS_CTRL_SET_RST_EXCOR (1<<11)
+#define SYS_CTRL_SET_RST_EVITAC (1<<12)
+#define SYS_CTRL_SET_RST_CORDIC (1<<13)
+#define SYS_CTRL_SET_RST_TCU_BB (1<<14)
+#define SYS_CTRL_SET_RST_BB_FULL (1<<31)
+#define SYS_CTRL_SET_BB_RST(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_SET_BB_RST_MASK (0x7FFF<<0)
+#define SYS_CTRL_SET_BB_RST_SHIFT (0)
+
+//BB_Rst_Clr
+#define SYS_CTRL_CLR_RST_BCPU (1<<0)
+#define SYS_CTRL_CLR_RST_BB_IRQ (1<<1)
+#define SYS_CTRL_CLR_RST_BB_A2A (1<<2)
+#define SYS_CTRL_CLR_RST_BB_IFC (1<<3)
+#define SYS_CTRL_CLR_RST_BB_SRAM (1<<4)
+#define SYS_CTRL_CLR_RST_ITLV (1<<5)
+#define SYS_CTRL_CLR_RST_VITERBI (1<<6)
+#define SYS_CTRL_CLR_RST_CIPHER (1<<7)
+#define SYS_CTRL_CLR_RST_XCOR (1<<8)
+#define SYS_CTRL_CLR_RST_COPRO (1<<9)
+#define SYS_CTRL_CLR_RST_RF_IF (1<<10)
+#define SYS_CTRL_CLR_RST_EXCOR (1<<11)
+#define SYS_CTRL_CLR_RST_EVITAC (1<<12)
+#define SYS_CTRL_CLR_RST_CORDIC (1<<13)
+#define SYS_CTRL_CLR_RST_TCU_BB (1<<14)
+#define SYS_CTRL_CLR_RST_BB_FULL (1<<31)
+#define SYS_CTRL_CLR_BB_RST(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_CLR_BB_RST_MASK (0x7FFF<<0)
+#define SYS_CTRL_CLR_BB_RST_SHIFT (0)
+
+//Clk_Sys_Mode
+#define SYS_CTRL_MODE_SYS_XCPU (1<<0)
+#define SYS_CTRL_MODE_SYS_XCPU_INT_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_SYS_XCPU_INT_MANUAL (1<<1)
+#define SYS_CTRL_MODE_SYS_PCLK_CONF_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_SYS_PCLK_CONF_MANUAL (1<<2)
+#define SYS_CTRL_MODE_SYS_PCLK_DATA_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_SYS_PCLK_DATA_MANUAL (1<<3)
+#define SYS_CTRL_MODE_SYS_AMBA_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_SYS_AMBA_MANUAL (1<<4)
+#define SYS_CTRL_MODE_SYS_DMA_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_SYS_DMA_MANUAL (1<<5)
+#define SYS_CTRL_MODE_SYS_EBC_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_SYS_EBC_MANUAL (1<<6)
+#define SYS_CTRL_MODE_SYS_IFC_CH0_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_SYS_IFC_CH0_MANUAL (1<<7)
+#define SYS_CTRL_MODE_SYS_IFC_CH1_AUTOMATIC (0<<8)
+#define SYS_CTRL_MODE_SYS_IFC_CH1_MANUAL (1<<8)
+#define SYS_CTRL_MODE_SYS_IFC_CH2_AUTOMATIC (0<<9)
+#define SYS_CTRL_MODE_SYS_IFC_CH2_MANUAL (1<<9)
+#define SYS_CTRL_MODE_SYS_IFC_CH3_AUTOMATIC (0<<10)
+#define SYS_CTRL_MODE_SYS_IFC_CH3_MANUAL (1<<10)
+#define SYS_CTRL_MODE_SYS_IFC_DBG_AUTOMATIC (0<<11)
+#define SYS_CTRL_MODE_SYS_IFC_DBG_MANUAL (1<<11)
+#define SYS_CTRL_MODE_SYS_A2A_AUTOMATIC (0<<12)
+#define SYS_CTRL_MODE_SYS_A2A_MANUAL (1<<12)
+#define SYS_CTRL_MODE_SYS_AXI2AHB_AUTOMATIC (0<<13)
+#define SYS_CTRL_MODE_SYS_AXI2AHB_MANUAL (1<<13)
+#define SYS_CTRL_MODE_SYS_AHB2AXI_AUTOMATIC (0<<14)
+#define SYS_CTRL_MODE_SYS_AHB2AXI_MANUAL (1<<14)
+#define SYS_CTRL_MODE_SYS_EXT_AHB_AUTOMATIC (0<<15)
+#define SYS_CTRL_MODE_SYS_EXT_AHB_MANUAL (1<<15)
+#define SYS_CTRL_MODE_SYS_DEBUG_UART_AUTOMATIC (0<<16)
+#define SYS_CTRL_MODE_SYS_DEBUG_UART_MANUAL (1<<16)
+#define SYS_CTRL_MODE_SYS_DBGHST_AUTOMATIC (0<<17)
+#define SYS_CTRL_MODE_SYS_DBGHST_MANUAL (1<<17)
+#define SYS_CTRL_MODE_SYSD_SCI1_AUTOMATIC (0<<18)
+#define SYS_CTRL_MODE_SYSD_SCI1_MANUAL (1<<18)
+#define SYS_CTRL_MODE_SYSD_SCI2_AUTOMATIC (0<<19)
+#define SYS_CTRL_MODE_SYSD_SCI2_MANUAL (1<<19)
+#define SYS_CTRL_MODE_SYSD_SCI3_AUTOMATIC (0<<20)
+#define SYS_CTRL_MODE_SYSD_SCI3_MANUAL (1<<20)
+#define SYS_CTRL_MODE_SYSD_RF_SPI_AUTOMATIC (0<<21)
+#define SYS_CTRL_MODE_SYSD_RF_SPI_MANUAL (1<<21)
+#define SYS_CTRL_MODE_SYSD_OSC_AUTOMATIC (0<<22)
+#define SYS_CTRL_MODE_SYSD_OSC_MANUAL (1<<22)
+#define SYS_CTRL_MODE_CLK_SYS(n) (((n)&0x3FFFFF)<<1)
+#define SYS_CTRL_MODE_CLK_SYS_MASK (0x3FFFFF<<1)
+#define SYS_CTRL_MODE_CLK_SYS_SHIFT (1)
+
+//Clk_Sys_Enable
+#define SYS_CTRL_ENABLE_SYS_XCPU (1<<0)
+#define SYS_CTRL_ENABLE_SYS_XCPU_INT (1<<1)
+#define SYS_CTRL_ENABLE_SYS_PCLK_CONF (1<<2)
+#define SYS_CTRL_ENABLE_SYS_PCLK_DATA (1<<3)
+#define SYS_CTRL_ENABLE_SYS_AMBA (1<<4)
+#define SYS_CTRL_ENABLE_SYS_DMA (1<<5)
+#define SYS_CTRL_ENABLE_SYS_EBC (1<<6)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH0 (1<<7)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH1 (1<<8)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH2 (1<<9)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH3 (1<<10)
+#define SYS_CTRL_ENABLE_SYS_IFC_DBG (1<<11)
+#define SYS_CTRL_ENABLE_SYS_A2A (1<<12)
+#define SYS_CTRL_ENABLE_SYS_AXI2AHB (1<<13)
+#define SYS_CTRL_ENABLE_SYS_AHB2AXI (1<<14)
+#define SYS_CTRL_ENABLE_SYS_EXT_AHB (1<<15)
+#define SYS_CTRL_ENABLE_SYS_DEBUG_UART (1<<16)
+#define SYS_CTRL_ENABLE_SYS_DBGHST (1<<17)
+#define SYS_CTRL_ENABLE_SYSD_SCI1 (1<<18)
+#define SYS_CTRL_ENABLE_SYSD_SCI2 (1<<19)
+#define SYS_CTRL_ENABLE_SYSD_SCI3 (1<<20)
+#define SYS_CTRL_ENABLE_SYSD_RF_SPI (1<<21)
+#define SYS_CTRL_ENABLE_SYSD_OSC (1<<22)
+#define SYS_CTRL_ENABLE_SYS_GPIO (1<<23)
+#define SYS_CTRL_ENABLE_SYS_IRQ (1<<24)
+#define SYS_CTRL_ENABLE_SYS_TCU (1<<25)
+#define SYS_CTRL_ENABLE_SYS_TIMER (1<<26)
+#define SYS_CTRL_ENABLE_SYS_COM_REGS (1<<27)
+#define SYS_CTRL_ENABLE_SYS_DP_AP (1<<28)
+#define SYS_CTRL_ENABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS_SHIFT (0)
+
+//Clk_Sys_Disable
+#define SYS_CTRL_DISABLE_SYS_XCPU (1<<0)
+#define SYS_CTRL_DISABLE_SYS_XCPU_INT (1<<1)
+#define SYS_CTRL_DISABLE_SYS_PCLK_CONF (1<<2)
+#define SYS_CTRL_DISABLE_SYS_PCLK_DATA (1<<3)
+#define SYS_CTRL_DISABLE_SYS_AMBA (1<<4)
+#define SYS_CTRL_DISABLE_SYS_DMA (1<<5)
+#define SYS_CTRL_DISABLE_SYS_EBC (1<<6)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH0 (1<<7)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH1 (1<<8)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH2 (1<<9)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH3 (1<<10)
+#define SYS_CTRL_DISABLE_SYS_IFC_DBG (1<<11)
+#define SYS_CTRL_DISABLE_SYS_A2A (1<<12)
+#define SYS_CTRL_DISABLE_SYS_AXI2AHB (1<<13)
+#define SYS_CTRL_DISABLE_SYS_AHB2AXI (1<<14)
+#define SYS_CTRL_DISABLE_SYS_EXT_AHB (1<<15)
+#define SYS_CTRL_DISABLE_SYS_DEBUG_UART (1<<16)
+#define SYS_CTRL_DISABLE_SYS_DBGHST (1<<17)
+#define SYS_CTRL_DISABLE_SYSD_SCI1 (1<<18)
+#define SYS_CTRL_DISABLE_SYSD_SCI2 (1<<19)
+#define SYS_CTRL_DISABLE_SYSD_SCI3 (1<<20)
+#define SYS_CTRL_DISABLE_SYSD_RF_SPI (1<<21)
+#define SYS_CTRL_DISABLE_SYSD_OSC (1<<22)
+#define SYS_CTRL_DISABLE_SYS_GPIO (1<<23)
+#define SYS_CTRL_DISABLE_SYS_IRQ (1<<24)
+#define SYS_CTRL_DISABLE_SYS_TCU (1<<25)
+#define SYS_CTRL_DISABLE_SYS_TIMER (1<<26)
+#define SYS_CTRL_DISABLE_SYS_COM_REGS (1<<27)
+#define SYS_CTRL_DISABLE_SYS_DP_AP (1<<28)
+#define SYS_CTRL_DISABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS_SHIFT (0)
+
+//Clk_Per_Mode
+#define SYS_CTRL_MODE_PER_I2C_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_PER_I2C_MANUAL (1<<0)
+#define SYS_CTRL_MODE_PERD_SPI1_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_PERD_SPI1_MANUAL (1<<1)
+#define SYS_CTRL_MODE_PERD_SPI2_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_PERD_SPI2_MANUAL (1<<2)
+#define SYS_CTRL_MODE_CLK_PER(n) (((n)&7)<<0)
+#define SYS_CTRL_MODE_CLK_PER_MASK (7<<0)
+#define SYS_CTRL_MODE_CLK_PER_SHIFT (0)
+
+//Clk_Per_Enable
+#define SYS_CTRL_ENABLE_PER_I2C (1<<0)
+#define SYS_CTRL_ENABLE_PERD_SPI1 (1<<1)
+#define SYS_CTRL_ENABLE_PERD_SPI2 (1<<2)
+#define SYS_CTRL_ENABLE_PER_SPY (1<<3)
+#define SYS_CTRL_ENABLE_PER_TEST (1<<4)
+#define SYS_CTRL_ENABLE_CLK_PER(n) (((n)&31)<<0)
+#define SYS_CTRL_ENABLE_CLK_PER_MASK (31<<0)
+#define SYS_CTRL_ENABLE_CLK_PER_SHIFT (0)
+
+//Clk_Per_Disable
+#define SYS_CTRL_DISABLE_PER_I2C (1<<0)
+#define SYS_CTRL_DISABLE_PERD_SPI1 (1<<1)
+#define SYS_CTRL_DISABLE_PERD_SPI2 (1<<2)
+#define SYS_CTRL_DISABLE_PER_SPY (1<<3)
+#define SYS_CTRL_DISABLE_PER_TEST (1<<4)
+#define SYS_CTRL_DISABLE_CLK_PER(n) (((n)&31)<<0)
+#define SYS_CTRL_DISABLE_CLK_PER_MASK (31<<0)
+#define SYS_CTRL_DISABLE_CLK_PER_SHIFT (0)
+
+//Clk_BB_Mode
+#define SYS_CTRL_MODE_BB_BCPU (1<<0)
+#define SYS_CTRL_MODE_BB_BCPU_INT_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_BB_BCPU_INT_MANUAL (1<<1)
+#define SYS_CTRL_MODE_BB_AMBA_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_BB_AMBA_MANUAL (1<<2)
+#define SYS_CTRL_MODE_BB_PCLK_CONF_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_BB_PCLK_CONF_MANUAL (1<<3)
+#define SYS_CTRL_MODE_BB_PCLK_DATA_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_BB_PCLK_DATA_MANUAL (1<<4)
+#define SYS_CTRL_MODE_BB_EXCOR_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_BB_EXCOR_MANUAL (1<<5)
+#define SYS_CTRL_MODE_BB_IFC_CH2_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_BB_IFC_CH2_MANUAL (1<<6)
+#define SYS_CTRL_MODE_BB_IFC_CH3_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_BB_IFC_CH3_MANUAL (1<<7)
+#define SYS_CTRL_MODE_BB_SRAM_AUTOMATIC (0<<8)
+#define SYS_CTRL_MODE_BB_SRAM_MANUAL (1<<8)
+#define SYS_CTRL_MODE_BB_A2A_AUTOMATIC (0<<9)
+#define SYS_CTRL_MODE_BB_A2A_MANUAL (1<<9)
+#define SYS_CTRL_MODE_BB_ITLV_AUTOMATIC (0<<10)
+#define SYS_CTRL_MODE_BB_ITLV_MANUAL (1<<10)
+#define SYS_CTRL_MODE_BB_VITERBI_AUTOMATIC (0<<11)
+#define SYS_CTRL_MODE_BB_VITERBI_MANUAL (1<<11)
+#define SYS_CTRL_MODE_BB_CIPHER_AUTOMATIC (0<<12)
+#define SYS_CTRL_MODE_BB_CIPHER_MANUAL (1<<12)
+#define SYS_CTRL_MODE_BB_RF_IF_AUTOMATIC (0<<13)
+#define SYS_CTRL_MODE_BB_RF_IF_MANUAL (1<<13)
+#define SYS_CTRL_MODE_BB_COPRO_AUTOMATIC (0<<14)
+#define SYS_CTRL_MODE_BB_COPRO_MANUAL (1<<14)
+#define SYS_CTRL_MODE_BB_CP2_REG_AUTOMATIC (0<<15)
+#define SYS_CTRL_MODE_BB_CP2_REG_MANUAL (1<<15)
+#define SYS_CTRL_MODE_BB_XCOR_AUTOMATIC (0<<16)
+#define SYS_CTRL_MODE_BB_XCOR_MANUAL (1<<16)
+#define SYS_CTRL_MODE_BB_EVITAC_AUTOMATIC (0<<17)
+#define SYS_CTRL_MODE_BB_EVITAC_MANUAL (1<<17)
+#define SYS_CTRL_MODE_CLK_BB(n) (((n)&0x1FFFF)<<1)
+#define SYS_CTRL_MODE_CLK_BB_MASK (0x1FFFF<<1)
+#define SYS_CTRL_MODE_CLK_BB_SHIFT (1)
+
+//Clk_BB_Enable
+#define SYS_CTRL_ENABLE_BB_BCPU (1<<0)
+#define SYS_CTRL_ENABLE_BB_BCPU_INT (1<<1)
+#define SYS_CTRL_ENABLE_BB_AMBA (1<<2)
+#define SYS_CTRL_ENABLE_BB_PCLK_CONF (1<<3)
+#define SYS_CTRL_ENABLE_BB_PCLK_DATA (1<<4)
+#define SYS_CTRL_ENABLE_BB_EXCOR (1<<5)
+#define SYS_CTRL_ENABLE_BB_IFC_CH2 (1<<6)
+#define SYS_CTRL_ENABLE_BB_IFC_CH3 (1<<7)
+#define SYS_CTRL_ENABLE_BB_SRAM (1<<8)
+#define SYS_CTRL_ENABLE_BB_A2A (1<<9)
+#define SYS_CTRL_ENABLE_BB_ITLV (1<<10)
+#define SYS_CTRL_ENABLE_BB_VITERBI (1<<11)
+#define SYS_CTRL_ENABLE_BB_CIPHER (1<<12)
+#define SYS_CTRL_ENABLE_BB_RF_IF (1<<13)
+#define SYS_CTRL_ENABLE_BB_COPRO (1<<14)
+#define SYS_CTRL_ENABLE_BB_CP2_REG (1<<15)
+#define SYS_CTRL_ENABLE_BB_XCOR (1<<16)
+#define SYS_CTRL_ENABLE_BB_EVITAC (1<<17)
+#define SYS_CTRL_ENABLE_BB_IRQ (1<<18)
+#define SYS_CTRL_ENABLE_BB_COM_REGS (1<<19)
+#define SYS_CTRL_ENABLE_BB_CORDIC (1<<20)
+#define SYS_CTRL_ENABLE_CLK_BB(n) (((n)&0x1FFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_BB_MASK (0x1FFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_BB_SHIFT (0)
+
+//Clk_BB_Disable
+#define SYS_CTRL_DISABLE_BB_BCPU (1<<0)
+#define SYS_CTRL_DISABLE_BB_BCPU_INT (1<<1)
+#define SYS_CTRL_DISABLE_BB_AMBA (1<<2)
+#define SYS_CTRL_DISABLE_BB_PCLK_CONF (1<<3)
+#define SYS_CTRL_DISABLE_BB_PCLK_DATA (1<<4)
+#define SYS_CTRL_DISABLE_BB_EXCOR (1<<5)
+#define SYS_CTRL_DISABLE_BB_IFC_CH2 (1<<6)
+#define SYS_CTRL_DISABLE_BB_IFC_CH3 (1<<7)
+#define SYS_CTRL_DISABLE_BB_SRAM (1<<8)
+#define SYS_CTRL_DISABLE_BB_A2A (1<<9)
+#define SYS_CTRL_DISABLE_BB_ITLV (1<<10)
+#define SYS_CTRL_DISABLE_BB_VITERBI (1<<11)
+#define SYS_CTRL_DISABLE_BB_CIPHER (1<<12)
+#define SYS_CTRL_DISABLE_BB_RF_IF (1<<13)
+#define SYS_CTRL_DISABLE_BB_COPRO (1<<14)
+#define SYS_CTRL_DISABLE_BB_CP2_REG (1<<15)
+#define SYS_CTRL_DISABLE_BB_XCOR (1<<16)
+#define SYS_CTRL_DISABLE_BB_EVITAC (1<<17)
+#define SYS_CTRL_DISABLE_BB_IRQ (1<<18)
+#define SYS_CTRL_DISABLE_BB_COM_REGS (1<<19)
+#define SYS_CTRL_DISABLE_BB_CORDIC (1<<20)
+#define SYS_CTRL_DISABLE_CLK_BB(n) (((n)&0x1FFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_BB_MASK (0x1FFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_BB_SHIFT (0)
+
+//Clk_Other_Mode
+#define SYS_CTRL_MODE_OC_DEBUG_UART_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_OC_DEBUG_UART_MANUAL (1<<0)
+#define SYS_CTRL_MODE_OC_RF_RX_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_OC_RF_RX_MANUAL (1<<1)
+#define SYS_CTRL_MODE_OC_RF_TX_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_OC_RF_TX_MANUAL (1<<2)
+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_MANUAL (1<<3)
+#define SYS_CTRL_MODE_CLK_OTHER(n) (((n)&15)<<0)
+#define SYS_CTRL_MODE_CLK_OTHER_MASK (15<<0)
+#define SYS_CTRL_MODE_CLK_OTHER_SHIFT (0)
+
+//Clk_Other_Enable
+#define SYS_CTRL_ENABLE_OC_DEBUG_UART (1<<0)
+#define SYS_CTRL_ENABLE_OC_RF_RX (1<<1)
+#define SYS_CTRL_ENABLE_OC_RF_TX (1<<2)
+#define SYS_CTRL_ENABLE_OC_MEM_BRIDGE (1<<3)
+#define SYS_CTRL_ENABLE_OC_LPS (1<<4)
+#define SYS_CTRL_ENABLE_OC_GPIO (1<<5)
+#define SYS_CTRL_ENABLE_OC_CLK_OUT (1<<6)
+#define SYS_CTRL_ENABLE_OC_MEM_CLK_OUT (1<<7)
+#define SYS_CTRL_ENABLE_OC_TCU (1<<8)
+#define SYS_CTRL_ENABLE_CLK_OTHER(n) (((n)&0x1FF)<<0)
+#define SYS_CTRL_ENABLE_CLK_OTHER_MASK (0x1FF<<0)
+#define SYS_CTRL_ENABLE_CLK_OTHER_SHIFT (0)
+
+//Clk_Other_Disable
+#define SYS_CTRL_DISABLE_OC_DEBUG_UART (1<<0)
+#define SYS_CTRL_DISABLE_OC_RF_RX (1<<1)
+#define SYS_CTRL_DISABLE_OC_RF_TX (1<<2)
+#define SYS_CTRL_DISABLE_OC_MEM_BRIDGE (1<<3)
+#define SYS_CTRL_DISABLE_OC_LPS (1<<4)
+#define SYS_CTRL_DISABLE_OC_GPIO (1<<5)
+#define SYS_CTRL_DISABLE_OC_CLK_OUT (1<<6)
+#define SYS_CTRL_DISABLE_OC_MEM_CLK_OUT (1<<7)
+#define SYS_CTRL_DISABLE_OC_TCU (1<<8)
+#define SYS_CTRL_DISABLE_CLK_OTHER(n) (((n)&0x1FF)<<0)
+#define SYS_CTRL_DISABLE_CLK_OTHER_MASK (0x1FF<<0)
+#define SYS_CTRL_DISABLE_CLK_OTHER_SHIFT (0)
+
+//Pll_Ctrl
+#define SYS_CTRL_PLL_ENABLE (1<<0)
+#define SYS_CTRL_PLL_ENABLE_MASK (1<<0)
+#define SYS_CTRL_PLL_ENABLE_SHIFT (0)
+#define SYS_CTRL_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_PLL_LOCK_RESET (1<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_PLL_BYPASS (1<<8)
+#define SYS_CTRL_PLL_BYPASS_MASK (1<<8)
+#define SYS_CTRL_PLL_BYPASS_SHIFT (8)
+#define SYS_CTRL_PLL_BYPASS_PASS (0<<8)
+#define SYS_CTRL_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_PLL_XP_CFG(n) (((n)&4369)<<0)
+#define SYS_CTRL_PLL_XP_CFG_MASK (4369<<0)
+#define SYS_CTRL_PLL_XP_CFG_SHIFT (0)
+
+//Sel_Clock
+#define SYS_CTRL_SLOW_SEL_RF_OSCILLATOR (1<<0)
+#define SYS_CTRL_SLOW_SEL_RF_RF (0<<0)
+#define SYS_CTRL_SYS_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_SYS_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_TCU_13M_L_26M (1<<5)
+#define SYS_CTRL_TCU_13M_L_13M (0<<5)
+#define SYS_CTRL_PLL_DISABLE_LPS_DISABLE (1<<6)
+#define SYS_CTRL_PLL_DISABLE_LPS_ENABLE (0<<6)
+#define SYS_CTRL_DIGEN_H_ENABLE (1<<7)
+#define SYS_CTRL_DIGEN_H_DISABLE (0<<7)
+#define SYS_CTRL_RF_DETECTED_OK (1<<20)
+#define SYS_CTRL_RF_DETECTED_NO (0<<20)
+#define SYS_CTRL_RF_DETECT_BYPASS (1<<21)
+#define SYS_CTRL_RF_DETECT_RESET (1<<22)
+#define SYS_CTRL_RF_SELECTED_L (1<<23)
+#define SYS_CTRL_PLL_LOCKED (1<<24)
+#define SYS_CTRL_PLL_LOCKED_MASK (1<<24)
+#define SYS_CTRL_PLL_LOCKED_SHIFT (24)
+#define SYS_CTRL_PLL_LOCKED_LOCKED (1<<24)
+#define SYS_CTRL_PLL_LOCKED_NOT_LOCKED (0<<24)
+#define SYS_CTRL_PLL_BYPASS_LOCK (1<<27)
+#define SYS_CTRL_FAST_SELECTED_L (1<<31)
+#define SYS_CTRL_FAST_SELECTED_L_MASK (1<<31)
+#define SYS_CTRL_FAST_SELECTED_L_SHIFT (31)
+
+//Cfg_Clk_Sys
+#define SYS_CTRL_FREQ(n) (((n)&15)<<0)
+#define SYS_CTRL_FREQ_MASK (15<<0)
+#define SYS_CTRL_FREQ_SHIFT (0)
+#define SYS_CTRL_FREQ_312M (13<<0)
+#define SYS_CTRL_FREQ_250M (12<<0)
+#define SYS_CTRL_FREQ_208M (11<<0)
+#define SYS_CTRL_FREQ_178M (10<<0)
+#define SYS_CTRL_FREQ_156M (9<<0)
+#define SYS_CTRL_FREQ_139M (8<<0)
+#define SYS_CTRL_FREQ_125M (7<<0)
+#define SYS_CTRL_FREQ_113M (6<<0)
+#define SYS_CTRL_FREQ_104M (5<<0)
+#define SYS_CTRL_FREQ_89M (4<<0)
+#define SYS_CTRL_FREQ_78M (3<<0)
+#define SYS_CTRL_FREQ_52M (2<<0)
+#define SYS_CTRL_FREQ_39M (1<<0)
+#define SYS_CTRL_FREQ_26M (0<<0)
+#define SYS_CTRL_FORCE_DIV_UPDATE (1<<4)
+#define SYS_CTRL_REQ_DIV_UPDATE (1<<8)
+
+//Cfg_Clk_Mem_Bridge
+#define SYS_CTRL_MEM_FREQ(n) (((n)&15)<<0)
+#define SYS_CTRL_MEM_FREQ_MASK (15<<0)
+#define SYS_CTRL_MEM_FREQ_SHIFT (0)
+#define SYS_CTRL_MEM_FREQ_312M (13<<0)
+#define SYS_CTRL_MEM_FREQ_250M (12<<0)
+#define SYS_CTRL_MEM_FREQ_208M (11<<0)
+#define SYS_CTRL_MEM_FREQ_178M (10<<0)
+#define SYS_CTRL_MEM_FREQ_156M (9<<0)
+#define SYS_CTRL_MEM_FREQ_139M (8<<0)
+#define SYS_CTRL_MEM_FREQ_125M (7<<0)
+#define SYS_CTRL_MEM_FREQ_113M (6<<0)
+#define SYS_CTRL_MEM_FREQ_104M (5<<0)
+#define SYS_CTRL_MEM_FREQ_89M (4<<0)
+#define SYS_CTRL_MEM_FREQ_78M (3<<0)
+#define SYS_CTRL_MEM_FREQ_52M (2<<0)
+#define SYS_CTRL_MEM_FREQ_39M (1<<0)
+#define SYS_CTRL_MEM_FREQ_26M (0<<0)
+#define SYS_CTRL_DDR_MODE_EN_NORMAL_MODE (0<<4)
+#define SYS_CTRL_DDR_MODE_EN_DDR_MODE (1<<4)
+#define SYS_CTRL_DDR_FAST_CLK_POL_INVERT (1<<5)
+#define SYS_CTRL_DDR_FAST_CLK_POL_NORMAL (0<<5)
+#define SYS_CTRL_DDR_DQSL_O(n) (((n)&31)<<6)
+#define SYS_CTRL_DDR_DQSU_O(n) (((n)&31)<<11)
+#define SYS_CTRL_DDR_DQS_OEN(n) (((n)&31)<<16)
+#define SYS_CTRL_DDR_DQSL_I(n) (((n)&31)<<21)
+#define SYS_CTRL_DDR_DQSU_I(n) (((n)&31)<<26)
+#define SYS_CTRL_MEM_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_Out
+#define SYS_CTRL_CLKOUT_DIVIDER(n) (((n)&31)<<0)
+#define SYS_CTRL_CLKOUT_SEL_OSC (0<<8)
+#define SYS_CTRL_CLKOUT_SEL_RF (1<<8)
+#define SYS_CTRL_CLKOUT_SEL_DIVIDER (2<<8)
+
+//Cfg_Clk_Host_Uart
+#define SYS_CTRL_HOST_UART_DIVIDER(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_HOST_UART_DIVIDER_MASK (0x3FF<<0)
+#define SYS_CTRL_HOST_UART_DIVIDER_SHIFT (0)
+#define SYS_CTRL_HOST_UART_SEL_PLL_SLOW (0<<12)
+#define SYS_CTRL_HOST_UART_SEL_PLL_PLL (1<<12)
+
+//Cfg_Clk_Auxclk
+#define SYS_CTRL_AUXCLK_EN_DISABLE (0<<0)
+#define SYS_CTRL_AUXCLK_EN_ENABLE (1<<0)
+
+//Cfg_AHB
+#define SYS_CTRL_SYS_NEW_ARBITRATION_ENABLE (1<<0)
+#define SYS_CTRL_SYS_NEW_ARBITRATION_DISABLE (0<<0)
+#define SYS_CTRL_ENABLE_SYS_MID_BIST_ENABLE (1<<1)
+#define SYS_CTRL_ENABLE_SYS_MID_BIST_DISABLE (0<<1)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA_ENABLE (1<<2)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA_DISABLE (0<<2)
+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_ENABLE (1<<3)
+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_DISABLE (0<<3)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_ENABLE (1<<4)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_DISABLE (0<<4)
+#define SYS_CTRL_ENABLE_SYS_MID_IFC_ENABLE (1<<5)
+#define SYS_CTRL_ENABLE_SYS_MID_IFC_DISABLE (0<<5)
+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_ENABLE (1<<6)
+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_DISABLE (0<<6)
+#define SYS_CTRL_BB_NEW_ARBITRATION_ENABLE (1<<16)
+#define SYS_CTRL_BB_NEW_ARBITRATION_DISABLE (0<<16)
+#define SYS_CTRL_ENABLE_BB_MID_BIST_ENABLE (1<<17)
+#define SYS_CTRL_ENABLE_BB_MID_BIST_DISABLE (0<<17)
+#define SYS_CTRL_ENABLE_BB_MID_IFC_ENABLE (1<<18)
+#define SYS_CTRL_ENABLE_BB_MID_IFC_DISABLE (0<<18)
+#define SYS_CTRL_ENABLE_BB_MID_BCPU_ENABLE (1<<19)
+#define SYS_CTRL_ENABLE_BB_MID_BCPU_DISABLE (0<<19)
+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_ENABLE (1<<20)
+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_DISABLE (0<<20)
+#define SYS_CTRL_SYS_ENABLE(n) (((n)&0x3F)<<1)
+#define SYS_CTRL_SYS_ENABLE_MASK (0x3F<<1)
+#define SYS_CTRL_SYS_ENABLE_SHIFT (1)
+#define SYS_CTRL_BB_ENABLE(n) (((n)&15)<<17)
+#define SYS_CTRL_BB_ENABLE_MASK (15<<17)
+#define SYS_CTRL_BB_ENABLE_SHIFT (17)
+
+//Ctrl_AHB
+#define SYS_CTRL_SPLIT_SYS_MID_BIST_NORMAL (1<<0)
+#define SYS_CTRL_SPLIT_SYS_MID_BIST_FORCE (0<<0)
+#define SYS_CTRL_SPLIT_SYS_MID_DMA_NORMAL (1<<1)
+#define SYS_CTRL_SPLIT_SYS_MID_DMA_FORCE (0<<1)
+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_NORMAL (1<<2)
+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_FORCE (0<<2)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_NORMAL (1<<3)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_FORCE (0<<3)
+#define SYS_CTRL_SPLIT_SYS_MID_IFC_NORMAL (1<<4)
+#define SYS_CTRL_SPLIT_SYS_MID_IFC_FORCE (0<<4)
+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_NORMAL (1<<5)
+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_FORCE (0<<5)
+#define SYS_CTRL_SPLIT_BB_MID_BIST_NORMAL (1<<16)
+#define SYS_CTRL_SPLIT_BB_MID_BIST_FORCE (0<<16)
+#define SYS_CTRL_SPLIT_BB_MID_IFC_NORMAL (1<<17)
+#define SYS_CTRL_SPLIT_BB_MID_IFC_FORCE (0<<17)
+#define SYS_CTRL_SPLIT_BB_MID_BCPU_NORMAL (1<<18)
+#define SYS_CTRL_SPLIT_BB_MID_BCPU_FORCE (0<<18)
+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_NORMAL (1<<19)
+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_FORCE (0<<19)
+#define SYS_CTRL_SYS_FORCE_HSPLIT(n) (((n)&0x3F)<<0)
+#define SYS_CTRL_SYS_FORCE_HSPLIT_MASK (0x3F<<0)
+#define SYS_CTRL_SYS_FORCE_HSPLIT_SHIFT (0)
+#define SYS_CTRL_BB_FORCE_HSPLIT(n) (((n)&15)<<16)
+#define SYS_CTRL_BB_FORCE_HSPLIT_MASK (15<<16)
+#define SYS_CTRL_BB_FORCE_HSPLIT_SHIFT (16)
+
+//XCpu_Dbg_BKP
+#define SYS_CTRL_BKPT_EN (1<<0)
+#define SYS_CTRL_BKPT_MODE(n) (((n)&3)<<4)
+#define SYS_CTRL_BKPT_MODE_I (0<<4)
+#define SYS_CTRL_BKPT_MODE_R (1<<4)
+#define SYS_CTRL_BKPT_MODE_W (2<<4)
+#define SYS_CTRL_BKPT_MODE_RW (3<<4)
+#define SYS_CTRL_STALLED (1<<8)
+
+//XCpu_Dbg_Addr
+#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)
+
+//BCpu_Dbg_BKP
+//#define SYS_CTRL_BKPT_EN (1<<0)
+//#define SYS_CTRL_BKPT_MODE(n) (((n)&3)<<4)
+//#define SYS_CTRL_BKPT_MODE_I (0<<4)
+//#define SYS_CTRL_BKPT_MODE_R (1<<4)
+//#define SYS_CTRL_BKPT_MODE_W (2<<4)
+//#define SYS_CTRL_BKPT_MODE_RW (3<<4)
+//#define SYS_CTRL_STALLED (1<<8)
+
+//BCpu_Dbg_Addr
+//#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)
+
+//Cfg_Cpus_Cache_Ram_Disable
+#define SYS_CTRL_XCPU_USE_MODE (1<<0)
+#define SYS_CTRL_XCPU_CLK_OFF_MODE (1<<1)
+#define SYS_CTRL_BCPU_USE_MODE (1<<16)
+#define SYS_CTRL_BCPU_CLK_OFF_MODE (1<<17)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<0)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_MASK (3<<0)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_SHIFT (0)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<16)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_MASK (3<<16)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_SHIFT (16)
+
+//Reset_Cause
+#define SYS_CTRL_WATCHDOG_RESET_HAPPENED (1<<0)
+#define SYS_CTRL_WATCHDOG_RESET_NO (0<<0)
+#define SYS_CTRL_APSOFT_RESET_HAPPENED (1<<1)
+#define SYS_CTRL_APSOFT_RESET_NO (0<<1)
+#define SYS_CTRL_GLOBALSOFT_RESET_HAPPENED (1<<4)
+#define SYS_CTRL_GLOBALSOFT_RESET_NO (0<<4)
+#define SYS_CTRL_HOSTDEBUG_RESET_HAPPENED (1<<5)
+#define SYS_CTRL_HOSTDEBUG_RESET_NO (0<<5)
+#define SYS_CTRL_ALARMCAUSE_HAPPENED (1<<6)
+#define SYS_CTRL_ALARMCAUSE_NO (0<<6)
+#define SYS_CTRL_MEMCHECKDONE_MASK (1<<7)
+#define SYS_CTRL_MEMCHECKDONE_SHIFT (7)
+#define SYS_CTRL_MEMCHECKDONE_DONE (1<<7)
+#define SYS_CTRL_MEMCHECKDONE_RUNNING (0<<7)
+#define SYS_CTRL_BOOT_MODE(n) (((n)&0xFFFF)<<8)
+#define SYS_CTRL_BOOT_MODE_MASK (0xFFFF<<8)
+#define SYS_CTRL_BOOT_MODE_SHIFT (8)
+#define SYS_CTRL_SW_BOOT_MODE(n) (((n)&0x7F)<<24)
+#define SYS_CTRL_SW_BOOT_MODE_MASK (0x7F<<24)
+#define SYS_CTRL_SW_BOOT_MODE_SHIFT (24)
+#define SYS_CTRL_FONCTIONAL_TEST_MODE (1<<31)
+
+//WakeUp
+#define SYS_CTRL_FORCE_WAKEUP (1<<0)
+
+//AP_Ctrl
+#define SYS_CTRL_AP_INT_STATUS (1<<0)
+#define SYS_CTRL_AP_INT_MASK (1<<16)
+#define SYS_CTRL_AP_DEEPSLEEP_EN (1<<24)
+
+//Ignore_Charger
+#define SYS_CTRL_IGNORE_CHARGER (1<<0)
+
+//Cfg_Reserve
+#define SYS_CTRL_RESERVE_L(n) (((n)&0x3FFF)<<0)
+#define SYS_CTRL_AUIFC_CH0_IRQ_MASK (1<<14)
+#define SYS_CTRL_AUIFC_CH1_IRQ_MASK (1<<15)
+#define SYS_CTRL_RESERVE_H(n) (((n)&0xFFFF)<<16)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8820.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8820.h new file mode 100644 index 0000000000..52ac62f983 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8820.h @@ -0,0 +1,1427 @@ +#ifndef _REG_MD_SYSCTRL_H_
+#define _REG_MD_SYSCTRL_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+// MACROS
+// =============================================================================
+
+// ============================================================================
+// CPU_ID_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// CPU IDs
+ XCPU = 0x00000000,
+ BCPU = 0x00000001,
+ WCPU = 0x00000002
+} CPU_ID_T;
+
+#define NB_MODEM_CPU (3)
+
+// ============================================================================
+// SYS_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// System side System clocks
+ SYS_XCPU = 0x00000000,
+ SYS_XCPU_INT = 0x00000001,
+ SYS_PCLK_CONF = 0x00000002,
+ SYS_PCLK_DATA = 0x00000003,
+ SYS_AMBA = 0x00000004,
+ SYS_DMA = 0x00000005,
+ SYS_EBC = 0x00000006,
+ SYS_IFC_CH0 = 0x00000007,
+ SYS_IFC_CH1 = 0x00000008,
+ SYS_IFC_CH2 = 0x00000009,
+ SYS_IFC_CH3 = 0x0000000A,
+ SYS_IFC_DBG = 0x0000000B,
+ SYS_A2A = 0x0000000C,
+ SYS_AXI2AHB = 0x0000000D,
+ SYS_AHB2AXI = 0x0000000E,
+ SYS_EXT_AHB = 0x0000000F,
+ SYS_DEBUG_UART = 0x00000010,
+ SYS_DBGHST = 0x00000011,
+ SYS_A2A_WD = 0x00000012,
+ SYS_DMA2 = 0x00000013,
+/// System side divided clock (either divided by module or by sys_ctrl)
+ SYSD_SCI1 = 0x00000014,
+ SYSD_SCI2 = 0x00000015,
+ SYSD_SCI3 = 0x00000016,
+ SYSD_RF_SPI = 0x00000017,
+ SYSD_OSC = 0x00000018,
+/// the following don't have an auto enable
+ SYS_GPIO = 0x00000019,
+ SYS_IRQ = 0x0000001A,
+ SYS_TCU = 0x0000001B,
+ SYS_TIMER = 0x0000001C,
+ SYS_COM_REGS = 0x0000001D,
+/// the following are sharing their enable
+ SYS_SCI1 = 0x0000001E,
+ SYS_SCI2 = 0x0000001F,
+ SYS_SCI3 = 0x00000020,
+/// keep last
+ SYS_NOGATE = 0x00000021
+} SYS_CLKS_T;
+
+#define NB_SYS_CLK_XCPU (2)
+#define NB_SYS_CLK_AEN (25)
+#define NB_SYS_CLK_EN (30)
+#define NB_SYS_CLK (34)
+
+// ============================================================================
+// SYS2_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// WCDMA Baseband side System clocks
+ SYS_MPMC = 0x00000000,
+ SYS_MPMCREG = 0x00000001,
+/// the following don't have an auto enable
+ SYS_DP_BB = 0x00000002,
+ SYS_DP_WD = 0x00000003,
+ SYS_DP_AP = 0x00000004
+} SYS2_CLKS_T;
+
+#define NB_SYS2_CLK_AEN (2)
+#define NB_SYS2_CLK_EN (5)
+#define NB_SYS2_CLK (5)
+
+// ============================================================================
+// PER_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+ PER_I2C = 0x00000000,
+/// System side divided clock (either divided by module or by sys_ctrl)
+ PERD_SPI1 = 0x00000001,
+/// System side divided clock (either divided by module or by sys_ctrl)
+ PERD_SPI2 = 0x00000002,
+ PER_SPY = 0x00000003,
+ PER_TEST = 0x00000004
+} PER_CLKS_T;
+
+#define NB_PER_CLK_AEN (3)
+#define NB_PER_CLK_EN (5)
+#define NB_PER_CLK (5)
+
+// ============================================================================
+// BB_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// Baseband side System clocks
+ BB_BCPU = 0x00000000,
+ BB_BCPU_INT = 0x00000001,
+ BB_AMBA = 0x00000002,
+ BB_PCLK_CONF = 0x00000003,
+ BB_PCLK_DATA = 0x00000004,
+ BB_EXCOR = 0x00000005,
+ BB_IFC_CH2 = 0x00000006,
+ BB_IFC_CH3 = 0x00000007,
+ BB_SRAM = 0x00000008,
+ BB_A2A = 0x00000009,
+ BB_ITLV = 0x0000000A,
+ BB_VITERBI = 0x0000000B,
+ BB_CIPHER = 0x0000000C,
+ BB_RF_IF = 0x0000000D,
+ BB_COPRO = 0x0000000E,
+ BB_CP2_REG = 0x0000000F,
+ BB_XCOR = 0x00000010,
+ BB_EVITAC = 0x00000011,
+ BB_ROM = 0x00000012,
+ BB_MPMC = 0x00000013,
+ BB_VTB = 0x00000014,
+/// the following don't have an auto enable
+ BB_IRQ = 0x00000015,
+ BB_COM_REGS = 0x00000016,
+ BB_CORDIC = 0x00000017,
+ BB_DP = 0x00000018
+} BB_CLKS_T;
+
+#define NB_BB_CLK_AEN (21)
+#define NB_BB_CLK_EN (25)
+#define NB_BB_CLK (25)
+
+// ============================================================================
+// WD_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// WCDMA Baseband side System clocks
+ WD_WCPU = 0x00000000,
+ WD_AMBA = 0x00000001,
+ WD_PCLK_CONF = 0x00000002,
+ WD_PCLK_DATA = 0x00000003,
+ WD_A2A = 0x00000004,
+ WD_IFC_CH_SPI = 0x00000005,
+ WD_MPMC = 0x00000006,
+ WD_EXT_AHB = 0x00000007,
+ WDD_OSC = 0x00000008,
+/// the following don't have an auto enable
+ WD_IRQ = 0x00000009,
+ WD_AXI = 0x0000000A,
+ WD_DP = 0x0000000B,
+ WD_MODEM = 0x0000000C,
+ WD_COM_REGS = 0x0000000D,
+ WD_TIMER = 0x0000000E,
+ WD_SDMA = 0x0000000F,
+ WD_SLPC = 0x00000010,
+ WD_SLPT = 0x00000011,
+ WD_SPI1 = 0x00000012,
+ WD_SPI2 = 0x00000013,
+ WD_RFIF = 0x00000014,
+ WD_PAGE_SPY = 0x00000015
+} WD_CLKS_T;
+
+#define NB_WD_CLK_AEN (9)
+#define NB_WD_CLK_EN (22)
+#define NB_WD_CLK (22)
+/// Other clocks
+/// clocks with auto enble
+/// the debug host clock auto enable is not used in host mode, only in uart mode
+#define OC_HOST_UART (0)
+
+// ============================================================================
+// OTHER_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+ OC_DEBUG_UART = 0x00000000,
+ OC_RF_RX = 0x00000001,
+ OC_RF_TX = 0x00000002,
+ OC_MEM_BRIDGE = 0x00000003,
+/// the following don't have an auto enable
+ OC_LPS = 0x00000004,
+ OC_GPIO = 0x00000005,
+ OC_CLK_OUT = 0x00000006,
+ OC_MEM_CLK_OUT = 0x00000007,
+ OC_TCU = 0x00000008,
+ OC_WD_CHIP = 0x00000009,
+ OC_WD_ADC = 0x0000000A,
+ OC_WD_TURBO = 0x0000000B,
+ OC_WD_OSC = 0x0000000C,
+ OC_MPMC = 0x0000000D,
+ OC_BB_VTB = 0x0000000E
+} OTHER_CLKS_T;
+
+#define NB_OTHER_CLK_AEN (4)
+#define NB_OTHER_CLK_EN (15)
+#define NB_OTHER_CLK (15)
+
+// ============================================================================
+// RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// System side resets
+ RST_XCPU = 0x00000000,
+ RST_SYS_IRQ = 0x00000001,
+ RST_SYS_A2A = 0x00000002,
+ RST_SYS_AHB2AXI = 0x00000003,
+ RST_SYS_AXI2AHB = 0x00000004,
+ RST_DMA = 0x00000005,
+ RST_TIMER = 0x00000006,
+ RST_TCU = 0x00000007,
+ RST_GPIO = 0x00000008,
+ RST_I2C = 0x00000009,
+ RST_CFG = 0x0000000A,
+ RST_SPI1 = 0x0000000B,
+ RST_SPI2 = 0x0000000C,
+ RST_RF_SPI = 0x0000000D,
+ RST_SCI1 = 0x0000000E,
+ RST_SCI2 = 0x0000000F,
+ RST_SCI3 = 0x00000010,
+ RST_SPY = 0x00000011,
+ RST_MEM_BRIDGE = 0x00000012,
+ RST_EXT_AHB = 0x00000013,
+ RST_DP_BB = 0x00000014,
+ RST_DP_AP = 0x00000015,
+ RST_COMREGS = 0x00000016,
+ RST_COMREGS_AP = 0x00000017,
+ RST_AP_CLKEN = 0x00000018,
+ RST_AP_RST = 0x00000019,
+ RST_MEM_CHK = 0x0000001A,
+ RST_MPMC = 0x0000001B,
+ RST_SYS_A2A_WD = 0x0000001C,
+ RST_COMREGS_WD = 0x0000001D,
+ RST_BCPU = 0x0000001E,
+ RST_BB_IRQ = 0x0000001F,
+ RST_BB_A2A = 0x00000020,
+ RST_BB_IFC = 0x00000021,
+ RST_BB_SRAM = 0x00000022,
+ RST_ITLV = 0x00000023,
+ RST_VITERBI = 0x00000024,
+ RST_CIPHER = 0x00000025,
+ RST_XCOR = 0x00000026,
+ RST_COPRO = 0x00000027,
+ RST_RF_IF = 0x00000028,
+ RST_EXCOR = 0x00000029,
+ RST_EVITAC = 0x0000002A,
+ RST_CORDIC = 0x0000002B,
+ RST_TCU_BB = 0x0000002C,
+ RST_BB_DP = 0x0000002D,
+ RST_BB_ROM = 0x0000002E,
+ RST_MPMC_BB = 0x0000002F,
+ RST_BB_VTB = 0x00000030,
+ RST_BB_FULL = 0x00000031,
+ RST_SYS_FULL = 0x00000032
+} RESETS_T;
+
+#define NB_SRST (30)
+/// Baseband side resets
+#define BOUND_BRST_FIRST (30)
+#define BOUND_BRST_AFTER (49)
+/// The following reset does not have register
+#define NR_RST_REG (50)
+#define NB_RST (51)
+#define NB_BRST (BOUND_BRST_AFTER-BOUND_BRST_FIRST)
+
+// ============================================================================
+// RESET_OTHERS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// Reset Other : resync on corresponding clock other
+ RSTO_DBG_HOST = 0x00000000,
+ RSTO_RF_RX = 0x00000001,
+ RSTO_RF_TX = 0x00000002,
+ RSTO_MEM_BRIDGE = 0x00000003,
+ RSTO_LPS = 0x00000004,
+ RSTO_GPIO = 0x00000005,
+ RSTO_WDTIMER = 0x00000006,
+ RSTO_TCU = 0x00000007,
+ RSTO_MPMC = 0x00000008,
+ RSTO_VTB = 0x00000009
+} RESET_OTHERS_T;
+
+#define BOUND_RSTO_RF_FIRST (1)
+#define BOUND_RSTO_RF_AFTER (3)
+#define NB_RSTO (10)
+
+// ============================================================================
+// WD_RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// WD side resets
+ WD_RST_WCPU = 0x00000000,
+ WD_RST_IRQ = 0x00000001,
+ WD_RST_DP = 0x00000002,
+ WD_RST_MODEM = 0x00000003,
+ WD_RST_A2A = 0x00000004,
+ WD_RST_IFC = 0x00000005,
+ WD_RST_SDMA = 0x00000006,
+ WD_RST_SLPC = 0x00000007,
+ WD_RST_SLPT = 0x00000008,
+ WD_RST_SPI1 = 0x00000009,
+ WD_RST_SPI2 = 0x0000000A,
+ WD_RST_RFIF = 0x0000000B,
+ WD_RST_COMREGS = 0x0000000C,
+ WD_RST_TIMER = 0x0000000D,
+ WD_RST_MPMC = 0x0000000E,
+ WD_RST_EXT_AHB = 0x0000000F,
+ WD_RST_PAGE_SPY = 0x00000010,
+ WD_RST_FULL = 0x00000011
+} WD_RESETS_T;
+
+#define NB_WD_RST_BOUND (17)
+#define NB_WD_RST (18)
+
+// ============================================================================
+// AP_RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP side resets
+ AP_RST_0 = 0x00000000,
+ AP_RST_1 = 0x00000001,
+ AP_RST_2 = 0x00000002,
+ AP_RST_3 = 0x00000003,
+ AP_RST_4 = 0x00000004
+} AP_RESETS_T;
+
+#define NB_AP_RST_BOUND (5)
+#define NB_AP_RST (5)
+/// For REG_DBG protect lock/unlock value
+#define SYS_CTRL_PROTECT_LOCK (0XA50000)
+#define SYS_CTRL_PROTECT_UNLOCK (0XA50001)
+
+// =============================================================================
+// TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_CTRL_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef volatile struct
+{
+ /// <strong>This register is used to Lock and Unlock the protected registers.</strong>
+ REG32 REG_DBG; //0x00000000
+ /// This register is protected.
+ REG32 Sys_Rst_Set; //0x00000004
+ REG32 Sys_Rst_Clr; //0x00000008
+ /// This register is protected.
+ REG32 BB_Rst_Set; //0x0000000C
+ REG32 BB_Rst_Clr; //0x00000010
+ REG32 Clk_Sys_Mode; //0x00000014
+ REG32 Clk_Sys_Enable; //0x00000018
+ /// This register is protected.
+ REG32 Clk_Sys_Disable; //0x0000001C
+ REG32 Clk_Per_Mode; //0x00000020
+ REG32 Clk_Per_Enable; //0x00000024
+ /// This register is protected.
+ REG32 Clk_Per_Disable; //0x00000028
+ REG32 Clk_BB_Mode; //0x0000002C
+ REG32 Clk_BB_Enable; //0x00000030
+ /// This register is protected.
+ REG32 Clk_BB_Disable; //0x00000034
+ REG32 Clk_Other_Mode; //0x00000038
+ REG32 Clk_Other_Enable; //0x0000003C
+ /// This register is protected.
+ REG32 Clk_Other_Disable; //0x00000040
+ /// Register protected by Write_Unlocked_H.
+ REG32 Pll_Ctrl; //0x00000044
+ /// This register is protected.
+ REG32 Sel_Clock; //0x00000048
+ REG32 Cfg_Clk_Sys; //0x0000004C
+ REG32 Cfg_Clk_Mem_Bridge; //0x00000050
+ /// This register is protected.
+ REG32 Cfg_Clk_Out; //0x00000054
+ REG32 Cfg_Clk_Host_Uart; //0x00000058
+ REG32 Cfg_Clk_Auxclk; //0x0000005C
+ /// This register is protected.
+ REG32 Cfg_AHB; //0x00000060
+ /// This register is protected. Used to unsplit masters manualy.
+ REG32 Ctrl_AHB; //0x00000064
+ REG32 XCpu_Dbg_BKP; //0x00000068
+ REG32 XCpu_Dbg_Addr; //0x0000006C
+ REG32 BCpu_Dbg_BKP; //0x00000070
+ REG32 BCpu_Dbg_Addr; //0x00000074
+ REG32 Cfg_Cpus_Cache_Ram_Disable; //0x00000078
+ REG32 Reset_Cause; //0x0000007C
+ /// This register is protected.
+ REG32 WakeUp; //0x00000080
+ REG32 AP_Ctrl; //0x00000084
+ /// This register is protected.
+ REG32 Ignore_Charger; //0x00000088
+ REG32 Clk_SYS2_Mode; //0x0000008C
+ REG32 Clk_SYS2_Enable; //0x00000090
+ /// This register is protected.
+ REG32 Clk_SYS2_Disable; //0x00000094
+ /// Register protected by Write_Unlocked_H.
+ REG32 WD_Pll_Ctrl; //0x00000098
+ /// This register is protected.
+ REG32 WD_Sel_Clock; //0x0000009C
+ /// This register is protected.
+ REG32 WD_Rst_Set; //0x000000A0
+ REG32 WD_Rst_Clr; //0x000000A4
+ /// This register is protected.
+ REG32 AP_Rst_Set; //0x000000A8
+ REG32 AP_Rst_Clr; //0x000000AC
+ REG32 Clk_WD_Mode; //0x000000B0
+ REG32 Clk_WD_Enable; //0x000000B4
+ /// This register is protected.
+ REG32 Clk_WD_Disable; //0x000000B8
+ REG32 Cfg_Clk_MPMC; //0x000000BC
+ REG32 Cfg_MPMC_DQS; //0x000000C0
+ REG32 Cfg_Clk_BB_VTB; //0x000000C4
+ REG32 Reserved_000000C8[13]; //0x000000C8
+ /// This register is reserved.
+ REG32 Cfg_Reserve; //0x000000FC
+} HWP_SYS_CTRL_T;
+
+#define hwp_sysCtrlMd ((HWP_SYS_CTRL_T*)(RDA_MD_SYSCTRL_BASE))
+
+
+//REG_DBG
+#define SYS_CTRL_SCRATCH(n) (((n)&0xFFFF)<<0)
+#define SYS_CTRL_WRITE_UNLOCK_STATUS (1<<30)
+#define SYS_CTRL_WRITE_UNLOCK (1<<31)
+
+//Sys_Rst_Set
+#define SYS_CTRL_SET_RST_XCPU (1<<0)
+#define SYS_CTRL_SET_RST_SYS_IRQ (1<<1)
+#define SYS_CTRL_SET_RST_SYS_A2A (1<<2)
+#define SYS_CTRL_SET_RST_SYS_AHB2AXI (1<<3)
+#define SYS_CTRL_SET_RST_SYS_AXI2AHB (1<<4)
+#define SYS_CTRL_SET_RST_DMA (1<<5)
+#define SYS_CTRL_SET_RST_TIMER (1<<6)
+#define SYS_CTRL_SET_RST_TCU (1<<7)
+#define SYS_CTRL_SET_RST_GPIO (1<<8)
+#define SYS_CTRL_SET_RST_I2C (1<<9)
+#define SYS_CTRL_SET_RST_CFG (1<<10)
+#define SYS_CTRL_SET_RST_SPI1 (1<<11)
+#define SYS_CTRL_SET_RST_SPI2 (1<<12)
+#define SYS_CTRL_SET_RST_RF_SPI (1<<13)
+#define SYS_CTRL_SET_RST_SCI1 (1<<14)
+#define SYS_CTRL_SET_RST_SCI2 (1<<15)
+#define SYS_CTRL_SET_RST_SCI3 (1<<16)
+#define SYS_CTRL_SET_RST_SPY (1<<17)
+#define SYS_CTRL_SET_RST_MEM_BRIDGE (1<<18)
+#define SYS_CTRL_SET_RST_EXT_AHB (1<<19)
+#define SYS_CTRL_SET_RST_DP_BB (1<<20)
+#define SYS_CTRL_SET_RST_DP_AP (1<<21)
+#define SYS_CTRL_SET_RST_COMREGS (1<<22)
+#define SYS_CTRL_SET_RST_COMREGS_AP (1<<23)
+#define SYS_CTRL_SET_RST_AP_CLKEN (1<<24)
+#define SYS_CTRL_SET_RST_AP_RST (1<<25)
+#define SYS_CTRL_SET_RST_MEM_CHK (1<<26)
+#define SYS_CTRL_SET_RST_MPMC (1<<27)
+#define SYS_CTRL_SET_RST_SYS_A2A_WD (1<<28)
+#define SYS_CTRL_SET_RST_COMREGS_WD (1<<29)
+#define SYS_CTRL_SET_RST_OUT (1<<30)
+#define SYS_CTRL_SOFT_RST (1<<31)
+#define SYS_CTRL_SET_SYS_RST(n) (((n)&0x3FFFFFFF)<<0)
+#define SYS_CTRL_SET_SYS_RST_MASK (0x3FFFFFFF<<0)
+#define SYS_CTRL_SET_SYS_RST_SHIFT (0)
+
+//Sys_Rst_Clr
+#define SYS_CTRL_CLR_RST_XCPU (1<<0)
+#define SYS_CTRL_CLR_RST_SYS_IRQ (1<<1)
+#define SYS_CTRL_CLR_RST_SYS_A2A (1<<2)
+#define SYS_CTRL_CLR_RST_SYS_AHB2AXI (1<<3)
+#define SYS_CTRL_CLR_RST_SYS_AXI2AHB (1<<4)
+#define SYS_CTRL_CLR_RST_DMA (1<<5)
+#define SYS_CTRL_CLR_RST_TIMER (1<<6)
+#define SYS_CTRL_CLR_RST_TCU (1<<7)
+#define SYS_CTRL_CLR_RST_GPIO (1<<8)
+#define SYS_CTRL_CLR_RST_I2C (1<<9)
+#define SYS_CTRL_CLR_RST_CFG (1<<10)
+#define SYS_CTRL_CLR_RST_SPI1 (1<<11)
+#define SYS_CTRL_CLR_RST_SPI2 (1<<12)
+#define SYS_CTRL_CLR_RST_RF_SPI (1<<13)
+#define SYS_CTRL_CLR_RST_SCI1 (1<<14)
+#define SYS_CTRL_CLR_RST_SCI2 (1<<15)
+#define SYS_CTRL_CLR_RST_SCI3 (1<<16)
+#define SYS_CTRL_CLR_RST_SPY (1<<17)
+#define SYS_CTRL_CLR_RST_MEM_BRIDGE (1<<18)
+#define SYS_CTRL_CLR_RST_EXT_AHB (1<<19)
+#define SYS_CTRL_CLR_RST_DP_BB (1<<20)
+#define SYS_CTRL_CLR_RST_DP_AP (1<<21)
+#define SYS_CTRL_CLR_RST_COMREGS (1<<22)
+#define SYS_CTRL_CLR_RST_COMREGS_AP (1<<23)
+#define SYS_CTRL_CLR_RST_AP_CLKEN (1<<24)
+#define SYS_CTRL_CLR_RST_AP_RST (1<<25)
+#define SYS_CTRL_CLR_RST_MEM_CHK (1<<26)
+#define SYS_CTRL_CLR_RST_MPMC (1<<27)
+#define SYS_CTRL_CLR_RST_SYS_A2A_WD (1<<28)
+#define SYS_CTRL_CLR_RST_COMREGS_WD (1<<29)
+#define SYS_CTRL_CLR_RST_OUT (1<<30)
+#define SYS_CTRL_CLR_SYS_RST(n) (((n)&0x3FFFFFFF)<<0)
+#define SYS_CTRL_CLR_SYS_RST_MASK (0x3FFFFFFF<<0)
+#define SYS_CTRL_CLR_SYS_RST_SHIFT (0)
+
+//BB_Rst_Set
+#define SYS_CTRL_SET_RST_BCPU (1<<0)
+#define SYS_CTRL_SET_RST_BB_IRQ (1<<1)
+#define SYS_CTRL_SET_RST_BB_A2A (1<<2)
+#define SYS_CTRL_SET_RST_BB_IFC (1<<3)
+#define SYS_CTRL_SET_RST_BB_SRAM (1<<4)
+#define SYS_CTRL_SET_RST_ITLV (1<<5)
+#define SYS_CTRL_SET_RST_VITERBI (1<<6)
+#define SYS_CTRL_SET_RST_CIPHER (1<<7)
+#define SYS_CTRL_SET_RST_XCOR (1<<8)
+#define SYS_CTRL_SET_RST_COPRO (1<<9)
+#define SYS_CTRL_SET_RST_RF_IF (1<<10)
+#define SYS_CTRL_SET_RST_EXCOR (1<<11)
+#define SYS_CTRL_SET_RST_EVITAC (1<<12)
+#define SYS_CTRL_SET_RST_CORDIC (1<<13)
+#define SYS_CTRL_SET_RST_TCU_BB (1<<14)
+#define SYS_CTRL_SET_RST_BB_DP (1<<15)
+#define SYS_CTRL_SET_RST_BB_ROM (1<<16)
+#define SYS_CTRL_SET_RST_MPMC_BB (1<<17)
+#define SYS_CTRL_SET_RST_BB_VTB (1<<18)
+#define SYS_CTRL_SET_RST_BB_FULL (1<<31)
+#define SYS_CTRL_SET_BB_RST(n) (((n)&0x7FFFF)<<0)
+#define SYS_CTRL_SET_BB_RST_MASK (0x7FFFF<<0)
+#define SYS_CTRL_SET_BB_RST_SHIFT (0)
+
+//BB_Rst_Clr
+#define SYS_CTRL_CLR_RST_BCPU (1<<0)
+#define SYS_CTRL_CLR_RST_BB_IRQ (1<<1)
+#define SYS_CTRL_CLR_RST_BB_A2A (1<<2)
+#define SYS_CTRL_CLR_RST_BB_IFC (1<<3)
+#define SYS_CTRL_CLR_RST_BB_SRAM (1<<4)
+#define SYS_CTRL_CLR_RST_ITLV (1<<5)
+#define SYS_CTRL_CLR_RST_VITERBI (1<<6)
+#define SYS_CTRL_CLR_RST_CIPHER (1<<7)
+#define SYS_CTRL_CLR_RST_XCOR (1<<8)
+#define SYS_CTRL_CLR_RST_COPRO (1<<9)
+#define SYS_CTRL_CLR_RST_RF_IF (1<<10)
+#define SYS_CTRL_CLR_RST_EXCOR (1<<11)
+#define SYS_CTRL_CLR_RST_EVITAC (1<<12)
+#define SYS_CTRL_CLR_RST_CORDIC (1<<13)
+#define SYS_CTRL_CLR_RST_TCU_BB (1<<14)
+#define SYS_CTRL_CLR_RST_BB_DP (1<<15)
+#define SYS_CTRL_CLR_RST_BB_ROM (1<<16)
+#define SYS_CTRL_CLR_RST_MPMC_BB (1<<17)
+#define SYS_CTRL_CLR_RST_BB_VTB (1<<18)
+#define SYS_CTRL_CLR_RST_BB_FULL (1<<31)
+#define SYS_CTRL_CLR_BB_RST(n) (((n)&0x7FFFF)<<0)
+#define SYS_CTRL_CLR_BB_RST_MASK (0x7FFFF<<0)
+#define SYS_CTRL_CLR_BB_RST_SHIFT (0)
+
+//Clk_Sys_Mode
+#define SYS_CTRL_MODE_SYS_XCPU (1<<0)
+#define SYS_CTRL_MODE_SYS_XCPU_INT_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_SYS_XCPU_INT_MANUAL (1<<1)
+#define SYS_CTRL_MODE_SYS_PCLK_CONF_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_SYS_PCLK_CONF_MANUAL (1<<2)
+#define SYS_CTRL_MODE_SYS_PCLK_DATA_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_SYS_PCLK_DATA_MANUAL (1<<3)
+#define SYS_CTRL_MODE_SYS_AMBA_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_SYS_AMBA_MANUAL (1<<4)
+#define SYS_CTRL_MODE_SYS_DMA_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_SYS_DMA_MANUAL (1<<5)
+#define SYS_CTRL_MODE_SYS_EBC_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_SYS_EBC_MANUAL (1<<6)
+#define SYS_CTRL_MODE_SYS_IFC_CH0_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_SYS_IFC_CH0_MANUAL (1<<7)
+#define SYS_CTRL_MODE_SYS_IFC_CH1_AUTOMATIC (0<<8)
+#define SYS_CTRL_MODE_SYS_IFC_CH1_MANUAL (1<<8)
+#define SYS_CTRL_MODE_SYS_IFC_CH2_AUTOMATIC (0<<9)
+#define SYS_CTRL_MODE_SYS_IFC_CH2_MANUAL (1<<9)
+#define SYS_CTRL_MODE_SYS_IFC_CH3_AUTOMATIC (0<<10)
+#define SYS_CTRL_MODE_SYS_IFC_CH3_MANUAL (1<<10)
+#define SYS_CTRL_MODE_SYS_IFC_DBG_AUTOMATIC (0<<11)
+#define SYS_CTRL_MODE_SYS_IFC_DBG_MANUAL (1<<11)
+#define SYS_CTRL_MODE_SYS_A2A_AUTOMATIC (0<<12)
+#define SYS_CTRL_MODE_SYS_A2A_MANUAL (1<<12)
+#define SYS_CTRL_MODE_SYS_AXI2AHB_AUTOMATIC (0<<13)
+#define SYS_CTRL_MODE_SYS_AXI2AHB_MANUAL (1<<13)
+#define SYS_CTRL_MODE_SYS_AHB2AXI_AUTOMATIC (0<<14)
+#define SYS_CTRL_MODE_SYS_AHB2AXI_MANUAL (1<<14)
+#define SYS_CTRL_MODE_SYS_EXT_AHB_AUTOMATIC (0<<15)
+#define SYS_CTRL_MODE_SYS_EXT_AHB_MANUAL (1<<15)
+#define SYS_CTRL_MODE_SYS_DEBUG_UART_AUTOMATIC (0<<16)
+#define SYS_CTRL_MODE_SYS_DEBUG_UART_MANUAL (1<<16)
+#define SYS_CTRL_MODE_SYS_DBGHST_AUTOMATIC (0<<17)
+#define SYS_CTRL_MODE_SYS_DBGHST_MANUAL (1<<17)
+#define SYS_CTRL_MODE_SYS_A2A_WD_AUTOMATIC (0<<18)
+#define SYS_CTRL_MODE_SYS_A2A_WD_MANUAL (1<<18)
+#define SYS_CTRL_MODE_SYS_DMA2_AUTOMATIC (0<<19)
+#define SYS_CTRL_MODE_SYS_DMA2_MANUAL (1<<19)
+#define SYS_CTRL_MODE_SYSD_SCI1_AUTOMATIC (0<<20)
+#define SYS_CTRL_MODE_SYSD_SCI1_MANUAL (1<<20)
+#define SYS_CTRL_MODE_SYSD_SCI2_AUTOMATIC (0<<21)
+#define SYS_CTRL_MODE_SYSD_SCI2_MANUAL (1<<21)
+#define SYS_CTRL_MODE_SYSD_SCI3_AUTOMATIC (0<<22)
+#define SYS_CTRL_MODE_SYSD_SCI3_MANUAL (1<<22)
+#define SYS_CTRL_MODE_SYSD_RF_SPI_AUTOMATIC (0<<23)
+#define SYS_CTRL_MODE_SYSD_RF_SPI_MANUAL (1<<23)
+#define SYS_CTRL_MODE_SYSD_OSC_AUTOMATIC (0<<24)
+#define SYS_CTRL_MODE_SYSD_OSC_MANUAL (1<<24)
+#define SYS_CTRL_MODE_CLK_SYS(n) (((n)&0xFFFFFF)<<1)
+#define SYS_CTRL_MODE_CLK_SYS_MASK (0xFFFFFF<<1)
+#define SYS_CTRL_MODE_CLK_SYS_SHIFT (1)
+
+//Clk_Sys_Enable
+#define SYS_CTRL_ENABLE_SYS_XCPU (1<<0)
+#define SYS_CTRL_ENABLE_SYS_XCPU_INT (1<<1)
+#define SYS_CTRL_ENABLE_SYS_PCLK_CONF (1<<2)
+#define SYS_CTRL_ENABLE_SYS_PCLK_DATA (1<<3)
+#define SYS_CTRL_ENABLE_SYS_AMBA (1<<4)
+#define SYS_CTRL_ENABLE_SYS_DMA (1<<5)
+#define SYS_CTRL_ENABLE_SYS_EBC (1<<6)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH0 (1<<7)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH1 (1<<8)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH2 (1<<9)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH3 (1<<10)
+#define SYS_CTRL_ENABLE_SYS_IFC_DBG (1<<11)
+#define SYS_CTRL_ENABLE_SYS_A2A (1<<12)
+#define SYS_CTRL_ENABLE_SYS_AXI2AHB (1<<13)
+#define SYS_CTRL_ENABLE_SYS_AHB2AXI (1<<14)
+#define SYS_CTRL_ENABLE_SYS_EXT_AHB (1<<15)
+#define SYS_CTRL_ENABLE_SYS_DEBUG_UART (1<<16)
+#define SYS_CTRL_ENABLE_SYS_DBGHST (1<<17)
+#define SYS_CTRL_ENABLE_SYS_A2A_WD (1<<18)
+#define SYS_CTRL_ENABLE_SYS_DMA2 (1<<19)
+#define SYS_CTRL_ENABLE_SYSD_SCI1 (1<<20)
+#define SYS_CTRL_ENABLE_SYSD_SCI2 (1<<21)
+#define SYS_CTRL_ENABLE_SYSD_SCI3 (1<<22)
+#define SYS_CTRL_ENABLE_SYSD_RF_SPI (1<<23)
+#define SYS_CTRL_ENABLE_SYSD_OSC (1<<24)
+#define SYS_CTRL_ENABLE_SYS_GPIO (1<<25)
+#define SYS_CTRL_ENABLE_SYS_IRQ (1<<26)
+#define SYS_CTRL_ENABLE_SYS_TCU (1<<27)
+#define SYS_CTRL_ENABLE_SYS_TIMER (1<<28)
+#define SYS_CTRL_ENABLE_SYS_COM_REGS (1<<29)
+#define SYS_CTRL_ENABLE_CLK_SYS(n) (((n)&0x3FFFFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS_MASK (0x3FFFFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS_SHIFT (0)
+
+//Clk_Sys_Disable
+#define SYS_CTRL_DISABLE_SYS_XCPU (1<<0)
+#define SYS_CTRL_DISABLE_SYS_XCPU_INT (1<<1)
+#define SYS_CTRL_DISABLE_SYS_PCLK_CONF (1<<2)
+#define SYS_CTRL_DISABLE_SYS_PCLK_DATA (1<<3)
+#define SYS_CTRL_DISABLE_SYS_AMBA (1<<4)
+#define SYS_CTRL_DISABLE_SYS_DMA (1<<5)
+#define SYS_CTRL_DISABLE_SYS_EBC (1<<6)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH0 (1<<7)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH1 (1<<8)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH2 (1<<9)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH3 (1<<10)
+#define SYS_CTRL_DISABLE_SYS_IFC_DBG (1<<11)
+#define SYS_CTRL_DISABLE_SYS_A2A (1<<12)
+#define SYS_CTRL_DISABLE_SYS_AXI2AHB (1<<13)
+#define SYS_CTRL_DISABLE_SYS_AHB2AXI (1<<14)
+#define SYS_CTRL_DISABLE_SYS_EXT_AHB (1<<15)
+#define SYS_CTRL_DISABLE_SYS_DEBUG_UART (1<<16)
+#define SYS_CTRL_DISABLE_SYS_DBGHST (1<<17)
+#define SYS_CTRL_DISABLE_SYS_A2A_WD (1<<18)
+#define SYS_CTRL_DISABLE_SYS_DMA2 (1<<19)
+#define SYS_CTRL_DISABLE_SYSD_SCI1 (1<<20)
+#define SYS_CTRL_DISABLE_SYSD_SCI2 (1<<21)
+#define SYS_CTRL_DISABLE_SYSD_SCI3 (1<<22)
+#define SYS_CTRL_DISABLE_SYSD_RF_SPI (1<<23)
+#define SYS_CTRL_DISABLE_SYSD_OSC (1<<24)
+#define SYS_CTRL_DISABLE_SYS_GPIO (1<<25)
+#define SYS_CTRL_DISABLE_SYS_IRQ (1<<26)
+#define SYS_CTRL_DISABLE_SYS_TCU (1<<27)
+#define SYS_CTRL_DISABLE_SYS_TIMER (1<<28)
+#define SYS_CTRL_DISABLE_SYS_COM_REGS (1<<29)
+#define SYS_CTRL_DISABLE_CLK_SYS(n) (((n)&0x3FFFFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS_MASK (0x3FFFFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS_SHIFT (0)
+
+//Clk_Per_Mode
+#define SYS_CTRL_MODE_PER_I2C_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_PER_I2C_MANUAL (1<<0)
+#define SYS_CTRL_MODE_PERD_SPI1_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_PERD_SPI1_MANUAL (1<<1)
+#define SYS_CTRL_MODE_PERD_SPI2_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_PERD_SPI2_MANUAL (1<<2)
+#define SYS_CTRL_MODE_CLK_PER(n) (((n)&7)<<0)
+#define SYS_CTRL_MODE_CLK_PER_MASK (7<<0)
+#define SYS_CTRL_MODE_CLK_PER_SHIFT (0)
+
+//Clk_Per_Enable
+#define SYS_CTRL_ENABLE_PER_I2C (1<<0)
+#define SYS_CTRL_ENABLE_PERD_SPI1 (1<<1)
+#define SYS_CTRL_ENABLE_PERD_SPI2 (1<<2)
+#define SYS_CTRL_ENABLE_PER_SPY (1<<3)
+#define SYS_CTRL_ENABLE_PER_TEST (1<<4)
+#define SYS_CTRL_ENABLE_CLK_PER(n) (((n)&31)<<0)
+#define SYS_CTRL_ENABLE_CLK_PER_MASK (31<<0)
+#define SYS_CTRL_ENABLE_CLK_PER_SHIFT (0)
+
+//Clk_Per_Disable
+#define SYS_CTRL_DISABLE_PER_I2C (1<<0)
+#define SYS_CTRL_DISABLE_PERD_SPI1 (1<<1)
+#define SYS_CTRL_DISABLE_PERD_SPI2 (1<<2)
+#define SYS_CTRL_DISABLE_PER_SPY (1<<3)
+#define SYS_CTRL_DISABLE_PER_TEST (1<<4)
+#define SYS_CTRL_DISABLE_CLK_PER(n) (((n)&31)<<0)
+#define SYS_CTRL_DISABLE_CLK_PER_MASK (31<<0)
+#define SYS_CTRL_DISABLE_CLK_PER_SHIFT (0)
+
+//Clk_BB_Mode
+#define SYS_CTRL_MODE_BB_BCPU (1<<0)
+#define SYS_CTRL_MODE_BB_BCPU_INT_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_BB_BCPU_INT_MANUAL (1<<1)
+#define SYS_CTRL_MODE_BB_AMBA_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_BB_AMBA_MANUAL (1<<2)
+#define SYS_CTRL_MODE_BB_PCLK_CONF_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_BB_PCLK_CONF_MANUAL (1<<3)
+#define SYS_CTRL_MODE_BB_PCLK_DATA_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_BB_PCLK_DATA_MANUAL (1<<4)
+#define SYS_CTRL_MODE_BB_EXCOR_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_BB_EXCOR_MANUAL (1<<5)
+#define SYS_CTRL_MODE_BB_IFC_CH2_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_BB_IFC_CH2_MANUAL (1<<6)
+#define SYS_CTRL_MODE_BB_IFC_CH3_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_BB_IFC_CH3_MANUAL (1<<7)
+#define SYS_CTRL_MODE_BB_SRAM_AUTOMATIC (0<<8)
+#define SYS_CTRL_MODE_BB_SRAM_MANUAL (1<<8)
+#define SYS_CTRL_MODE_BB_A2A_AUTOMATIC (0<<9)
+#define SYS_CTRL_MODE_BB_A2A_MANUAL (1<<9)
+#define SYS_CTRL_MODE_BB_ITLV_AUTOMATIC (0<<10)
+#define SYS_CTRL_MODE_BB_ITLV_MANUAL (1<<10)
+#define SYS_CTRL_MODE_BB_VITERBI_AUTOMATIC (0<<11)
+#define SYS_CTRL_MODE_BB_VITERBI_MANUAL (1<<11)
+#define SYS_CTRL_MODE_BB_CIPHER_AUTOMATIC (0<<12)
+#define SYS_CTRL_MODE_BB_CIPHER_MANUAL (1<<12)
+#define SYS_CTRL_MODE_BB_RF_IF_AUTOMATIC (0<<13)
+#define SYS_CTRL_MODE_BB_RF_IF_MANUAL (1<<13)
+#define SYS_CTRL_MODE_BB_COPRO_AUTOMATIC (0<<14)
+#define SYS_CTRL_MODE_BB_COPRO_MANUAL (1<<14)
+#define SYS_CTRL_MODE_BB_CP2_REG_AUTOMATIC (0<<15)
+#define SYS_CTRL_MODE_BB_CP2_REG_MANUAL (1<<15)
+#define SYS_CTRL_MODE_BB_XCOR_AUTOMATIC (0<<16)
+#define SYS_CTRL_MODE_BB_XCOR_MANUAL (1<<16)
+#define SYS_CTRL_MODE_BB_EVITAC_AUTOMATIC (0<<17)
+#define SYS_CTRL_MODE_BB_EVITAC_MANUAL (1<<17)
+#define SYS_CTRL_MODE_BB_ROM_AUTOMATIC (0<<18)
+#define SYS_CTRL_MODE_BB_ROM_MANUAL (1<<18)
+#define SYS_CTRL_MODE_BB_MPMC_AUTOMATIC (0<<19)
+#define SYS_CTRL_MODE_BB_MPMC_MANUAL (1<<19)
+#define SYS_CTRL_MODE_BB_VTB_AUTOMATIC (0<<20)
+#define SYS_CTRL_MODE_BB_VTB_MANUAL (1<<20)
+#define SYS_CTRL_MODE_CLK_BB(n) (((n)&0xFFFFF)<<1)
+#define SYS_CTRL_MODE_CLK_BB_MASK (0xFFFFF<<1)
+#define SYS_CTRL_MODE_CLK_BB_SHIFT (1)
+
+//Clk_BB_Enable
+#define SYS_CTRL_ENABLE_BB_BCPU (1<<0)
+#define SYS_CTRL_ENABLE_BB_BCPU_INT (1<<1)
+#define SYS_CTRL_ENABLE_BB_AMBA (1<<2)
+#define SYS_CTRL_ENABLE_BB_PCLK_CONF (1<<3)
+#define SYS_CTRL_ENABLE_BB_PCLK_DATA (1<<4)
+#define SYS_CTRL_ENABLE_BB_EXCOR (1<<5)
+#define SYS_CTRL_ENABLE_BB_IFC_CH2 (1<<6)
+#define SYS_CTRL_ENABLE_BB_IFC_CH3 (1<<7)
+#define SYS_CTRL_ENABLE_BB_SRAM (1<<8)
+#define SYS_CTRL_ENABLE_BB_A2A (1<<9)
+#define SYS_CTRL_ENABLE_BB_ITLV (1<<10)
+#define SYS_CTRL_ENABLE_BB_VITERBI (1<<11)
+#define SYS_CTRL_ENABLE_BB_CIPHER (1<<12)
+#define SYS_CTRL_ENABLE_BB_RF_IF (1<<13)
+#define SYS_CTRL_ENABLE_BB_COPRO (1<<14)
+#define SYS_CTRL_ENABLE_BB_CP2_REG (1<<15)
+#define SYS_CTRL_ENABLE_BB_XCOR (1<<16)
+#define SYS_CTRL_ENABLE_BB_EVITAC (1<<17)
+#define SYS_CTRL_ENABLE_BB_ROM (1<<18)
+#define SYS_CTRL_ENABLE_BB_MPMC (1<<19)
+#define SYS_CTRL_ENABLE_BB_VTB (1<<20)
+#define SYS_CTRL_ENABLE_BB_IRQ (1<<21)
+#define SYS_CTRL_ENABLE_BB_COM_REGS (1<<22)
+#define SYS_CTRL_ENABLE_BB_CORDIC (1<<23)
+#define SYS_CTRL_ENABLE_BB_DP (1<<24)
+#define SYS_CTRL_ENABLE_CLK_BB(n) (((n)&0x1FFFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_BB_MASK (0x1FFFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_BB_SHIFT (0)
+
+//Clk_BB_Disable
+#define SYS_CTRL_DISABLE_BB_BCPU (1<<0)
+#define SYS_CTRL_DISABLE_BB_BCPU_INT (1<<1)
+#define SYS_CTRL_DISABLE_BB_AMBA (1<<2)
+#define SYS_CTRL_DISABLE_BB_PCLK_CONF (1<<3)
+#define SYS_CTRL_DISABLE_BB_PCLK_DATA (1<<4)
+#define SYS_CTRL_DISABLE_BB_EXCOR (1<<5)
+#define SYS_CTRL_DISABLE_BB_IFC_CH2 (1<<6)
+#define SYS_CTRL_DISABLE_BB_IFC_CH3 (1<<7)
+#define SYS_CTRL_DISABLE_BB_SRAM (1<<8)
+#define SYS_CTRL_DISABLE_BB_A2A (1<<9)
+#define SYS_CTRL_DISABLE_BB_ITLV (1<<10)
+#define SYS_CTRL_DISABLE_BB_VITERBI (1<<11)
+#define SYS_CTRL_DISABLE_BB_CIPHER (1<<12)
+#define SYS_CTRL_DISABLE_BB_RF_IF (1<<13)
+#define SYS_CTRL_DISABLE_BB_COPRO (1<<14)
+#define SYS_CTRL_DISABLE_BB_CP2_REG (1<<15)
+#define SYS_CTRL_DISABLE_BB_XCOR (1<<16)
+#define SYS_CTRL_DISABLE_BB_EVITAC (1<<17)
+#define SYS_CTRL_DISABLE_BB_ROM (1<<18)
+#define SYS_CTRL_DISABLE_BB_MPMC (1<<19)
+#define SYS_CTRL_DISABLE_BB_VTB (1<<20)
+#define SYS_CTRL_DISABLE_BB_IRQ (1<<21)
+#define SYS_CTRL_DISABLE_BB_COM_REGS (1<<22)
+#define SYS_CTRL_DISABLE_BB_CORDIC (1<<23)
+#define SYS_CTRL_DISABLE_BB_DP (1<<24)
+#define SYS_CTRL_DISABLE_CLK_BB(n) (((n)&0x1FFFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_BB_MASK (0x1FFFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_BB_SHIFT (0)
+
+//Clk_Other_Mode
+#define SYS_CTRL_MODE_OC_DEBUG_UART_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_OC_DEBUG_UART_MANUAL (1<<0)
+#define SYS_CTRL_MODE_OC_RF_RX_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_OC_RF_RX_MANUAL (1<<1)
+#define SYS_CTRL_MODE_OC_RF_TX_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_OC_RF_TX_MANUAL (1<<2)
+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_MANUAL (1<<3)
+#define SYS_CTRL_MODE_CLK_OTHER(n) (((n)&15)<<0)
+#define SYS_CTRL_MODE_CLK_OTHER_MASK (15<<0)
+#define SYS_CTRL_MODE_CLK_OTHER_SHIFT (0)
+
+//Clk_Other_Enable
+#define SYS_CTRL_ENABLE_OC_DEBUG_UART (1<<0)
+#define SYS_CTRL_ENABLE_OC_RF_RX (1<<1)
+#define SYS_CTRL_ENABLE_OC_RF_TX (1<<2)
+#define SYS_CTRL_ENABLE_OC_MEM_BRIDGE (1<<3)
+#define SYS_CTRL_ENABLE_OC_LPS (1<<4)
+#define SYS_CTRL_ENABLE_OC_GPIO (1<<5)
+#define SYS_CTRL_ENABLE_OC_CLK_OUT (1<<6)
+#define SYS_CTRL_ENABLE_OC_MEM_CLK_OUT (1<<7)
+#define SYS_CTRL_ENABLE_OC_TCU (1<<8)
+#define SYS_CTRL_ENABLE_OC_WD_CHIP (1<<9)
+#define SYS_CTRL_ENABLE_OC_WD_ADC (1<<10)
+#define SYS_CTRL_ENABLE_OC_WD_TURBO (1<<11)
+#define SYS_CTRL_ENABLE_OC_WD_OSC (1<<12)
+#define SYS_CTRL_ENABLE_OC_MPMC (1<<13)
+#define SYS_CTRL_ENABLE_OC_BB_VTB (1<<14)
+#define SYS_CTRL_ENABLE_CLK_OTHER(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_OTHER_MASK (0x7FFF<<0)
+#define SYS_CTRL_ENABLE_CLK_OTHER_SHIFT (0)
+
+//Clk_Other_Disable
+#define SYS_CTRL_DISABLE_OC_DEBUG_UART (1<<0)
+#define SYS_CTRL_DISABLE_OC_RF_RX (1<<1)
+#define SYS_CTRL_DISABLE_OC_RF_TX (1<<2)
+#define SYS_CTRL_DISABLE_OC_MEM_BRIDGE (1<<3)
+#define SYS_CTRL_DISABLE_OC_LPS (1<<4)
+#define SYS_CTRL_DISABLE_OC_GPIO (1<<5)
+#define SYS_CTRL_DISABLE_OC_CLK_OUT (1<<6)
+#define SYS_CTRL_DISABLE_OC_MEM_CLK_OUT (1<<7)
+#define SYS_CTRL_DISABLE_OC_TCU (1<<8)
+#define SYS_CTRL_DISABLE_OC_WD_CHIP (1<<9)
+#define SYS_CTRL_DISABLE_OC_WD_ADC (1<<10)
+#define SYS_CTRL_DISABLE_OC_WD_TURBO (1<<11)
+#define SYS_CTRL_DISABLE_OC_WD_OSC (1<<12)
+#define SYS_CTRL_DISABLE_OC_MPMC (1<<13)
+#define SYS_CTRL_DISABLE_OC_BB_VTB (1<<14)
+#define SYS_CTRL_DISABLE_CLK_OTHER(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_OTHER_MASK (0x7FFF<<0)
+#define SYS_CTRL_DISABLE_CLK_OTHER_SHIFT (0)
+
+//Pll_Ctrl
+#define SYS_CTRL_PLL_ENABLE (1<<0)
+#define SYS_CTRL_PLL_ENABLE_MASK (1<<0)
+#define SYS_CTRL_PLL_ENABLE_SHIFT (0)
+#define SYS_CTRL_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_PLL_LOCK_RESET (1<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_PLL_BYPASS (1<<8)
+#define SYS_CTRL_PLL_BYPASS_MASK (1<<8)
+#define SYS_CTRL_PLL_BYPASS_SHIFT (8)
+#define SYS_CTRL_PLL_BYPASS_PASS (0<<8)
+#define SYS_CTRL_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_PLL_XP_CFG(n) (((n)&4369)<<0)
+#define SYS_CTRL_PLL_XP_CFG_MASK (4369<<0)
+#define SYS_CTRL_PLL_XP_CFG_SHIFT (0)
+
+//Sel_Clock
+#define SYS_CTRL_SLOW_SEL_RF_OSCILLATOR (1<<0)
+#define SYS_CTRL_SLOW_SEL_RF_RF (0<<0)
+#define SYS_CTRL_SYS_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_SYS_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_TCU_13M_L_26M (1<<5)
+#define SYS_CTRL_TCU_13M_L_13M (0<<5)
+#define SYS_CTRL_PLL_DISABLE_LPS_DISABLE (1<<6)
+#define SYS_CTRL_PLL_DISABLE_LPS_ENABLE (0<<6)
+#define SYS_CTRL_DIGEN_H_ENABLE (1<<7)
+#define SYS_CTRL_DIGEN_H_DISABLE (0<<7)
+#define SYS_CTRL_RF_DETECTED_OK (1<<20)
+#define SYS_CTRL_RF_DETECTED_NO (0<<20)
+#define SYS_CTRL_RF_DETECT_BYPASS (1<<21)
+#define SYS_CTRL_RF_DETECT_RESET (1<<22)
+#define SYS_CTRL_RF_SELECTED_L (1<<23)
+#define SYS_CTRL_PLL_LOCKED (1<<24)
+#define SYS_CTRL_PLL_LOCKED_MASK (1<<24)
+#define SYS_CTRL_PLL_LOCKED_SHIFT (24)
+#define SYS_CTRL_PLL_LOCKED_LOCKED (1<<24)
+#define SYS_CTRL_PLL_LOCKED_NOT_LOCKED (0<<24)
+#define SYS_CTRL_PLL_BYPASS_LOCK (1<<27)
+#define SYS_CTRL_FAST_SELECTED_L (1<<31)
+#define SYS_CTRL_FAST_SELECTED_L_MASK (1<<31)
+#define SYS_CTRL_FAST_SELECTED_L_SHIFT (31)
+
+//Cfg_Clk_Sys
+#define SYS_CTRL_FREQ(n) (((n)&15)<<0)
+#define SYS_CTRL_FREQ_MASK (15<<0)
+#define SYS_CTRL_FREQ_SHIFT (0)
+#define SYS_CTRL_FREQ_312M (13<<0)
+#define SYS_CTRL_FREQ_250M (12<<0)
+#define SYS_CTRL_FREQ_208M (11<<0)
+#define SYS_CTRL_FREQ_178M (10<<0)
+#define SYS_CTRL_FREQ_156M (9<<0)
+#define SYS_CTRL_FREQ_139M (8<<0)
+#define SYS_CTRL_FREQ_125M (7<<0)
+#define SYS_CTRL_FREQ_113M (6<<0)
+#define SYS_CTRL_FREQ_104M (5<<0)
+#define SYS_CTRL_FREQ_89M (4<<0)
+#define SYS_CTRL_FREQ_78M (3<<0)
+#define SYS_CTRL_FREQ_52M (2<<0)
+#define SYS_CTRL_FREQ_39M (1<<0)
+#define SYS_CTRL_FREQ_26M (0<<0)
+#define SYS_CTRL_FORCE_DIV_UPDATE (1<<4)
+#define SYS_CTRL_REQ_DIV_UPDATE (1<<8)
+
+//Cfg_Clk_Mem_Bridge
+#define SYS_CTRL_MEM_FREQ(n) (((n)&15)<<0)
+#define SYS_CTRL_MEM_FREQ_MASK (15<<0)
+#define SYS_CTRL_MEM_FREQ_SHIFT (0)
+#define SYS_CTRL_MEM_FREQ_312M (13<<0)
+#define SYS_CTRL_MEM_FREQ_250M (12<<0)
+#define SYS_CTRL_MEM_FREQ_208M (11<<0)
+#define SYS_CTRL_MEM_FREQ_178M (10<<0)
+#define SYS_CTRL_MEM_FREQ_156M (9<<0)
+#define SYS_CTRL_MEM_FREQ_139M (8<<0)
+#define SYS_CTRL_MEM_FREQ_125M (7<<0)
+#define SYS_CTRL_MEM_FREQ_113M (6<<0)
+#define SYS_CTRL_MEM_FREQ_104M (5<<0)
+#define SYS_CTRL_MEM_FREQ_89M (4<<0)
+#define SYS_CTRL_MEM_FREQ_78M (3<<0)
+#define SYS_CTRL_MEM_FREQ_52M (2<<0)
+#define SYS_CTRL_MEM_FREQ_39M (1<<0)
+#define SYS_CTRL_MEM_FREQ_26M (0<<0)
+#define SYS_CTRL_DDR_MODE_EN_NORMAL_MODE (0<<4)
+#define SYS_CTRL_DDR_MODE_EN_DDR_MODE (1<<4)
+#define SYS_CTRL_DDR_FAST_CLK_POL_INVERT (1<<5)
+#define SYS_CTRL_DDR_FAST_CLK_POL_NORMAL (0<<5)
+#define SYS_CTRL_DDR_DQSL_O(n) (((n)&31)<<6)
+#define SYS_CTRL_DDR_DQSU_O(n) (((n)&31)<<11)
+#define SYS_CTRL_DDR_DQS_OEN(n) (((n)&31)<<16)
+#define SYS_CTRL_DDR_DQSL_I(n) (((n)&31)<<21)
+#define SYS_CTRL_DDR_DQSU_I(n) (((n)&31)<<26)
+#define SYS_CTRL_MEM_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_Out
+#define SYS_CTRL_CLKOUT_DIVIDER(n) (((n)&31)<<0)
+#define SYS_CTRL_CLKOUT_SEL_OSC (0<<8)
+#define SYS_CTRL_CLKOUT_SEL_RF (1<<8)
+#define SYS_CTRL_CLKOUT_SEL_DIVIDER (2<<8)
+
+//Cfg_Clk_Host_Uart
+#define SYS_CTRL_HOST_UART_DIVIDER(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_HOST_UART_DIVIDER_MASK (0x3FF<<0)
+#define SYS_CTRL_HOST_UART_DIVIDER_SHIFT (0)
+#define SYS_CTRL_HOST_UART_SEL_PLL_SLOW (0<<12)
+#define SYS_CTRL_HOST_UART_SEL_PLL_PLL (1<<12)
+
+//Cfg_Clk_Auxclk
+#define SYS_CTRL_AUXCLK_EN_DISABLE (0<<0)
+#define SYS_CTRL_AUXCLK_EN_ENABLE (1<<0)
+
+//Cfg_AHB
+#define SYS_CTRL_SYS_NEW_ARBITRATION_ENABLE (1<<0)
+#define SYS_CTRL_SYS_NEW_ARBITRATION_DISABLE (0<<0)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA_ENABLE (1<<1)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA_DISABLE (0<<1)
+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_ENABLE (1<<2)
+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_DISABLE (0<<2)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_ENABLE (1<<3)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_DISABLE (0<<3)
+#define SYS_CTRL_ENABLE_SYS_MID_IFC_ENABLE (1<<4)
+#define SYS_CTRL_ENABLE_SYS_MID_IFC_DISABLE (0<<4)
+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_ENABLE (1<<5)
+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_DISABLE (0<<5)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_WD_ENABLE (1<<6)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_WD_DISABLE (0<<6)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA2_ENABLE (1<<7)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA2_DISABLE (0<<7)
+#define SYS_CTRL_BB_NEW_ARBITRATION_ENABLE (1<<16)
+#define SYS_CTRL_BB_NEW_ARBITRATION_DISABLE (0<<16)
+#define SYS_CTRL_ENABLE_BB_MID_IFC_ENABLE (1<<17)
+#define SYS_CTRL_ENABLE_BB_MID_IFC_DISABLE (0<<17)
+#define SYS_CTRL_ENABLE_BB_MID_BCPU_ENABLE (1<<18)
+#define SYS_CTRL_ENABLE_BB_MID_BCPU_DISABLE (0<<18)
+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_ENABLE (1<<19)
+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_DISABLE (0<<19)
+#define SYS_CTRL_SYS_ENABLE(n) (((n)&0x7F)<<1)
+#define SYS_CTRL_SYS_ENABLE_MASK (0x7F<<1)
+#define SYS_CTRL_SYS_ENABLE_SHIFT (1)
+#define SYS_CTRL_BB_ENABLE(n) (((n)&7)<<17)
+#define SYS_CTRL_BB_ENABLE_MASK (7<<17)
+#define SYS_CTRL_BB_ENABLE_SHIFT (17)
+
+//Ctrl_AHB
+#define SYS_CTRL_SPLIT_SYS_MID_DMA_NORMAL (1<<0)
+#define SYS_CTRL_SPLIT_SYS_MID_DMA_FORCE (0<<0)
+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_NORMAL (1<<1)
+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_FORCE (0<<1)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_NORMAL (1<<2)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_FORCE (0<<2)
+#define SYS_CTRL_SPLIT_SYS_MID_IFC_NORMAL (1<<3)
+#define SYS_CTRL_SPLIT_SYS_MID_IFC_FORCE (0<<3)
+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_NORMAL (1<<4)
+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_FORCE (0<<4)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_WD_NORMAL (1<<5)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_WD_FORCE (0<<5)
+#define SYS_CTRL_SPLIT_SYS_MID_DMA2_NORMAL (1<<6)
+#define SYS_CTRL_SPLIT_SYS_MID_DMA2_FORCE (0<<6)
+#define SYS_CTRL_SPLIT_BB_MID_IFC_NORMAL (1<<16)
+#define SYS_CTRL_SPLIT_BB_MID_IFC_FORCE (0<<16)
+#define SYS_CTRL_SPLIT_BB_MID_BCPU_NORMAL (1<<17)
+#define SYS_CTRL_SPLIT_BB_MID_BCPU_FORCE (0<<17)
+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_NORMAL (1<<18)
+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_FORCE (0<<18)
+#define SYS_CTRL_SYS_FORCE_HSPLIT(n) (((n)&0x7F)<<0)
+#define SYS_CTRL_SYS_FORCE_HSPLIT_MASK (0x7F<<0)
+#define SYS_CTRL_SYS_FORCE_HSPLIT_SHIFT (0)
+#define SYS_CTRL_BB_FORCE_HSPLIT(n) (((n)&7)<<16)
+#define SYS_CTRL_BB_FORCE_HSPLIT_MASK (7<<16)
+#define SYS_CTRL_BB_FORCE_HSPLIT_SHIFT (16)
+
+//XCpu_Dbg_BKP
+#define SYS_CTRL_BKPT_EN (1<<0)
+#define SYS_CTRL_BKPT_MODE(n) (((n)&3)<<4)
+#define SYS_CTRL_BKPT_MODE_I (0<<4)
+#define SYS_CTRL_BKPT_MODE_R (1<<4)
+#define SYS_CTRL_BKPT_MODE_W (2<<4)
+#define SYS_CTRL_BKPT_MODE_RW (3<<4)
+#define SYS_CTRL_STALLED (1<<8)
+
+//XCpu_Dbg_Addr
+#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)
+
+//BCpu_Dbg_BKP
+//#define SYS_CTRL_BKPT_EN (1<<0)
+//#define SYS_CTRL_BKPT_MODE(n) (((n)&3)<<4)
+//#define SYS_CTRL_BKPT_MODE_I (0<<4)
+//#define SYS_CTRL_BKPT_MODE_R (1<<4)
+//#define SYS_CTRL_BKPT_MODE_W (2<<4)
+//#define SYS_CTRL_BKPT_MODE_RW (3<<4)
+//#define SYS_CTRL_STALLED (1<<8)
+
+//BCpu_Dbg_Addr
+//#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)
+
+//Cfg_Cpus_Cache_Ram_Disable
+#define SYS_CTRL_XCPU_USE_MODE (1<<0)
+#define SYS_CTRL_XCPU_CLK_OFF_MODE (1<<1)
+#define SYS_CTRL_BCPU_USE_MODE (1<<16)
+#define SYS_CTRL_BCPU_CLK_OFF_MODE (1<<17)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<0)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_MASK (3<<0)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_SHIFT (0)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<16)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_MASK (3<<16)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_SHIFT (16)
+
+//Reset_Cause
+#define SYS_CTRL_WATCHDOG_RESET_HAPPENED (1<<0)
+#define SYS_CTRL_WATCHDOG_RESET_NO (0<<0)
+#define SYS_CTRL_APSOFT_RESET_HAPPENED (1<<1)
+#define SYS_CTRL_APSOFT_RESET_NO (0<<1)
+#define SYS_CTRL_GLOBALSOFT_RESET_HAPPENED (1<<4)
+#define SYS_CTRL_GLOBALSOFT_RESET_NO (0<<4)
+#define SYS_CTRL_HOSTDEBUG_RESET_HAPPENED (1<<5)
+#define SYS_CTRL_HOSTDEBUG_RESET_NO (0<<5)
+#define SYS_CTRL_ALARMCAUSE_HAPPENED (1<<6)
+#define SYS_CTRL_ALARMCAUSE_NO (0<<6)
+#define SYS_CTRL_MEMCHECKDONE_MASK (1<<7)
+#define SYS_CTRL_MEMCHECKDONE_SHIFT (7)
+#define SYS_CTRL_MEMCHECKDONE_DONE (1<<7)
+#define SYS_CTRL_MEMCHECKDONE_RUNNING (0<<7)
+#define SYS_CTRL_BOOT_MODE(n) (((n)&0xFFFF)<<8)
+#define SYS_CTRL_BOOT_MODE_MASK (0xFFFF<<8)
+#define SYS_CTRL_BOOT_MODE_SHIFT (8)
+#define SYS_CTRL_SW_BOOT_MODE(n) (((n)&0x7F)<<24)
+#define SYS_CTRL_SW_BOOT_MODE_MASK (0x7F<<24)
+#define SYS_CTRL_SW_BOOT_MODE_SHIFT (24)
+#define SYS_CTRL_FONCTIONAL_TEST_MODE (1<<31)
+
+//WakeUp
+#define SYS_CTRL_FORCE_WAKEUP (1<<0)
+
+//AP_Ctrl
+#define SYS_CTRL_AP_INT_STATUS (1<<0)
+#define SYS_CTRL_AP_INT_MASK (1<<16)
+#define SYS_CTRL_AP_DEEPSLEEP_EN (1<<24)
+
+//Ignore_Charger
+#define SYS_CTRL_IGNORE_CHARGER (1<<0)
+
+//Clk_SYS2_Mode
+#define SYS_CTRL_MODE_SYS_MPMC_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_SYS_MPMC_MANUAL (1<<0)
+#define SYS_CTRL_MODE_SYS_MPMCREG_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_SYS_MPMCREG_MANUAL (1<<1)
+#define SYS_CTRL_MODE_CLK_SYS2(n) (((n)&3)<<0)
+#define SYS_CTRL_MODE_CLK_SYS2_MASK (3<<0)
+#define SYS_CTRL_MODE_CLK_SYS2_SHIFT (0)
+
+//Clk_SYS2_Enable
+#define SYS_CTRL_ENABLE_SYS_MPMC (1<<0)
+#define SYS_CTRL_ENABLE_SYS_MPMCREG (1<<1)
+#define SYS_CTRL_ENABLE_SYS_DP_BB (1<<2)
+#define SYS_CTRL_ENABLE_SYS_DP_WD (1<<3)
+#define SYS_CTRL_ENABLE_SYS_DP_AP (1<<4)
+#define SYS_CTRL_ENABLE_CLK_SYS2(n) (((n)&31)<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS2_MASK (31<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS2_SHIFT (0)
+
+//Clk_SYS2_Disable
+#define SYS_CTRL_DISABLE_SYS_MPMC (1<<0)
+#define SYS_CTRL_DISABLE_SYS_MPMCREG (1<<1)
+#define SYS_CTRL_DISABLE_SYS_DP_BB (1<<2)
+#define SYS_CTRL_DISABLE_SYS_DP_WD (1<<3)
+#define SYS_CTRL_DISABLE_SYS_DP_AP (1<<4)
+#define SYS_CTRL_DISABLE_CLK_SYS2(n) (((n)&31)<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS2_MASK (31<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS2_SHIFT (0)
+
+//WD_Pll_Ctrl
+#define SYS_CTRL_WD_PLL_ENABLE (1<<0)
+#define SYS_CTRL_WD_PLL_ENABLE_MASK (1<<0)
+#define SYS_CTRL_WD_PLL_ENABLE_SHIFT (0)
+#define SYS_CTRL_WD_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_WD_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_WD_PLL_LOCK_RESET (1<<4)
+#define SYS_CTRL_WD_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_WD_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_WD_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_WD_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_WD_PLL_BYPASS (1<<8)
+#define SYS_CTRL_WD_PLL_BYPASS_MASK (1<<8)
+#define SYS_CTRL_WD_PLL_BYPASS_SHIFT (8)
+#define SYS_CTRL_WD_PLL_BYPASS_PASS (0<<8)
+#define SYS_CTRL_WD_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_PLL_WD_CFG(n) (((n)&4369)<<0)
+#define SYS_CTRL_PLL_WD_CFG_MASK (4369<<0)
+#define SYS_CTRL_PLL_WD_CFG_SHIFT (0)
+
+//WD_Sel_Clock
+#define SYS_CTRL_WD_CLK_ADC_POL_INVERT (1<<0)
+#define SYS_CTRL_WD_CLK_ADC_POL_NORMAL (0<<0)
+#define SYS_CTRL_WD_SYS_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_WD_SYS_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_WD_PLL_BYPASS_LOCK (1<<8)
+#define SYS_CTRL_WD_PLL_LOCKED (1<<20)
+#define SYS_CTRL_WD_PLL_LOCKED_MASK (1<<20)
+#define SYS_CTRL_WD_PLL_LOCKED_SHIFT (20)
+#define SYS_CTRL_WD_PLL_LOCKED_LOCKED (1<<20)
+#define SYS_CTRL_WD_PLL_LOCKED_NOT_LOCKED (0<<20)
+#define SYS_CTRL_WD_FAST_SELECTED_L (1<<24)
+#define SYS_CTRL_WD_FAST_SELECTED_L_MASK (1<<24)
+#define SYS_CTRL_WD_FAST_SELECTED_L_SHIFT (24)
+
+//WD_Rst_Set
+#define SYS_CTRL_SET_WD_RST_WCPU (1<<0)
+#define SYS_CTRL_SET_WD_RST_IRQ (1<<1)
+#define SYS_CTRL_SET_WD_RST_DP (1<<2)
+#define SYS_CTRL_SET_WD_RST_MODEM (1<<3)
+#define SYS_CTRL_SET_WD_RST_A2A (1<<4)
+#define SYS_CTRL_SET_WD_RST_IFC (1<<5)
+#define SYS_CTRL_SET_WD_RST_SDMA (1<<6)
+#define SYS_CTRL_SET_WD_RST_SLPC (1<<7)
+#define SYS_CTRL_SET_WD_RST_SLPT (1<<8)
+#define SYS_CTRL_SET_WD_RST_SPI1 (1<<9)
+#define SYS_CTRL_SET_WD_RST_SPI2 (1<<10)
+#define SYS_CTRL_SET_WD_RST_RFIF (1<<11)
+#define SYS_CTRL_SET_WD_RST_COMREGS (1<<12)
+#define SYS_CTRL_SET_WD_RST_TIMER (1<<13)
+#define SYS_CTRL_SET_WD_RST_MPMC (1<<14)
+#define SYS_CTRL_SET_WD_RST_EXT_AHB (1<<15)
+#define SYS_CTRL_SET_WD_RST_PAGE_SPY (1<<16)
+#define SYS_CTRL_SET_WD_RST_FULL (1<<31)
+#define SYS_CTRL_SET_WD_RST(n) (((n)&0x1FFFF)<<0)
+#define SYS_CTRL_SET_WD_RST_MASK (0x1FFFF<<0)
+#define SYS_CTRL_SET_WD_RST_SHIFT (0)
+
+//WD_Rst_Clr
+#define SYS_CTRL_CLR_WD_RST_WCPU (1<<0)
+#define SYS_CTRL_CLR_WD_RST_IRQ (1<<1)
+#define SYS_CTRL_CLR_WD_RST_DP (1<<2)
+#define SYS_CTRL_CLR_WD_RST_MODEM (1<<3)
+#define SYS_CTRL_CLR_WD_RST_A2A (1<<4)
+#define SYS_CTRL_CLR_WD_RST_IFC (1<<5)
+#define SYS_CTRL_CLR_WD_RST_SDMA (1<<6)
+#define SYS_CTRL_CLR_WD_RST_SLPC (1<<7)
+#define SYS_CTRL_CLR_WD_RST_SLPT (1<<8)
+#define SYS_CTRL_CLR_WD_RST_SPI1 (1<<9)
+#define SYS_CTRL_CLR_WD_RST_SPI2 (1<<10)
+#define SYS_CTRL_CLR_WD_RST_RFIF (1<<11)
+#define SYS_CTRL_CLR_WD_RST_COMREGS (1<<12)
+#define SYS_CTRL_CLR_WD_RST_TIMER (1<<13)
+#define SYS_CTRL_CLR_WD_RST_MPMC (1<<14)
+#define SYS_CTRL_CLR_WD_RST_EXT_AHB (1<<15)
+#define SYS_CTRL_CLR_WD_RST_PAGE_SPY (1<<16)
+#define SYS_CTRL_CLR_WD_RST_FULL (1<<31)
+#define SYS_CTRL_CLR_WD_RST(n) (((n)&0x1FFFF)<<0)
+#define SYS_CTRL_CLR_WD_RST_MASK (0x1FFFF<<0)
+#define SYS_CTRL_CLR_WD_RST_SHIFT (0)
+
+//AP_Rst_Set
+#define SYS_CTRL_SET_AP_RST_0 (1<<0)
+#define SYS_CTRL_SET_AP_RST_1 (1<<1)
+#define SYS_CTRL_SET_AP_RST_2 (1<<2)
+#define SYS_CTRL_SET_AP_RST_3 (1<<3)
+#define SYS_CTRL_SET_AP_RST_4 (1<<4)
+#define SYS_CTRL_SET_AP_RST(n) (((n)&31)<<0)
+#define SYS_CTRL_SET_AP_RST_MASK (31<<0)
+#define SYS_CTRL_SET_AP_RST_SHIFT (0)
+
+//AP_Rst_Clr
+#define SYS_CTRL_CLR_AP_RST_0 (1<<0)
+#define SYS_CTRL_CLR_AP_RST_1 (1<<1)
+#define SYS_CTRL_CLR_AP_RST_2 (1<<2)
+#define SYS_CTRL_CLR_AP_RST_3 (1<<3)
+#define SYS_CTRL_CLR_AP_RST_4 (1<<4)
+#define SYS_CTRL_CLR_AP_RST(n) (((n)&31)<<0)
+#define SYS_CTRL_CLR_AP_RST_MASK (31<<0)
+#define SYS_CTRL_CLR_AP_RST_SHIFT (0)
+
+//Clk_WD_Mode
+#define SYS_CTRL_MODE_WD_WCPU (1<<0)
+#define SYS_CTRL_MODE_WD_AMBA_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_WD_AMBA_MANUAL (1<<1)
+#define SYS_CTRL_MODE_WD_PCLK_CONF_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_WD_PCLK_CONF_MANUAL (1<<2)
+#define SYS_CTRL_MODE_WD_PCLK_DATA_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_WD_PCLK_DATA_MANUAL (1<<3)
+#define SYS_CTRL_MODE_WD_A2A_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_WD_A2A_MANUAL (1<<4)
+#define SYS_CTRL_MODE_WD_IFC_CH_SPI_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_WD_IFC_CH_SPI_MANUAL (1<<5)
+#define SYS_CTRL_MODE_WD_MPMC_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_WD_MPMC_MANUAL (1<<6)
+#define SYS_CTRL_MODE_WD_EXT_AHB_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_WD_EXT_AHB_MANUAL (1<<7)
+#define SYS_CTRL_MODE_WDD_OSC_AUTOMATIC (0<<8)
+#define SYS_CTRL_MODE_WDD_OSC_MANUAL (1<<8)
+#define SYS_CTRL_MODE_CLK_WD(n) (((n)&0xFF)<<1)
+#define SYS_CTRL_MODE_CLK_WD_MASK (0xFF<<1)
+#define SYS_CTRL_MODE_CLK_WD_SHIFT (1)
+
+//Clk_WD_Enable
+#define SYS_CTRL_ENABLE_WD_WCPU (1<<0)
+#define SYS_CTRL_ENABLE_WD_AMBA (1<<1)
+#define SYS_CTRL_ENABLE_WD_PCLK_CONF (1<<2)
+#define SYS_CTRL_ENABLE_WD_PCLK_DATA (1<<3)
+#define SYS_CTRL_ENABLE_WD_A2A (1<<4)
+#define SYS_CTRL_ENABLE_WD_IFC_CH_SPI (1<<5)
+#define SYS_CTRL_ENABLE_WD_MPMC (1<<6)
+#define SYS_CTRL_ENABLE_WD_EXT_AHB (1<<7)
+#define SYS_CTRL_ENABLE_WDD_OSC (1<<8)
+#define SYS_CTRL_ENABLE_WD_IRQ (1<<9)
+#define SYS_CTRL_ENABLE_WD_AXI (1<<10)
+#define SYS_CTRL_ENABLE_WD_DP (1<<11)
+#define SYS_CTRL_ENABLE_WD_MODEM (1<<12)
+#define SYS_CTRL_ENABLE_WD_COM_REGS (1<<13)
+#define SYS_CTRL_ENABLE_WD_TIMER (1<<14)
+#define SYS_CTRL_ENABLE_WD_SDMA (1<<15)
+#define SYS_CTRL_ENABLE_WD_SLPC (1<<16)
+#define SYS_CTRL_ENABLE_WD_SLPT (1<<17)
+#define SYS_CTRL_ENABLE_WD_SPI1 (1<<18)
+#define SYS_CTRL_ENABLE_WD_SPI2 (1<<19)
+#define SYS_CTRL_ENABLE_WD_RFIF (1<<20)
+#define SYS_CTRL_ENABLE_WD_PAGE_SPY (1<<21)
+#define SYS_CTRL_ENABLE_CLK_WD(n) (((n)&0x3FFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_WD_MASK (0x3FFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_WD_SHIFT (0)
+
+//Clk_WD_Disable
+#define SYS_CTRL_DISABLE_WD_WCPU (1<<0)
+#define SYS_CTRL_DISABLE_WD_AMBA (1<<1)
+#define SYS_CTRL_DISABLE_WD_PCLK_CONF (1<<2)
+#define SYS_CTRL_DISABLE_WD_PCLK_DATA (1<<3)
+#define SYS_CTRL_DISABLE_WD_A2A (1<<4)
+#define SYS_CTRL_DISABLE_WD_IFC_CH_SPI (1<<5)
+#define SYS_CTRL_DISABLE_WD_MPMC (1<<6)
+#define SYS_CTRL_DISABLE_WD_EXT_AHB (1<<7)
+#define SYS_CTRL_DISABLE_WDD_OSC (1<<8)
+#define SYS_CTRL_DISABLE_WD_IRQ (1<<9)
+#define SYS_CTRL_DISABLE_WD_AXI (1<<10)
+#define SYS_CTRL_DISABLE_WD_DP (1<<11)
+#define SYS_CTRL_DISABLE_WD_MODEM (1<<12)
+#define SYS_CTRL_DISABLE_WD_COM_REGS (1<<13)
+#define SYS_CTRL_DISABLE_WD_TIMER (1<<14)
+#define SYS_CTRL_DISABLE_WD_SDMA (1<<15)
+#define SYS_CTRL_DISABLE_WD_SLPC (1<<16)
+#define SYS_CTRL_DISABLE_WD_SLPT (1<<17)
+#define SYS_CTRL_DISABLE_WD_SPI1 (1<<18)
+#define SYS_CTRL_DISABLE_WD_SPI2 (1<<19)
+#define SYS_CTRL_DISABLE_WD_RFIF (1<<20)
+#define SYS_CTRL_DISABLE_WD_PAGE_SPY (1<<21)
+#define SYS_CTRL_DISABLE_CLK_WD(n) (((n)&0x3FFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_WD_MASK (0x3FFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_WD_SHIFT (0)
+
+//Cfg_Clk_MPMC
+#define SYS_CTRL_MPMC_FREQ(n) (((n)&15)<<0)
+#define SYS_CTRL_MPMC_FREQ_MASK (15<<0)
+#define SYS_CTRL_MPMC_FREQ_SHIFT (0)
+#define SYS_CTRL_MPMC_FREQ_312M (13<<0)
+#define SYS_CTRL_MPMC_FREQ_250M (12<<0)
+#define SYS_CTRL_MPMC_FREQ_208M (11<<0)
+#define SYS_CTRL_MPMC_FREQ_178M (10<<0)
+#define SYS_CTRL_MPMC_FREQ_156M (9<<0)
+#define SYS_CTRL_MPMC_FREQ_139M (8<<0)
+#define SYS_CTRL_MPMC_FREQ_125M (7<<0)
+#define SYS_CTRL_MPMC_FREQ_113M (6<<0)
+#define SYS_CTRL_MPMC_FREQ_104M (5<<0)
+#define SYS_CTRL_MPMC_FREQ_89M (4<<0)
+#define SYS_CTRL_MPMC_FREQ_78M (3<<0)
+#define SYS_CTRL_MPMC_FREQ_52M (2<<0)
+#define SYS_CTRL_MPMC_FREQ_39M (1<<0)
+#define SYS_CTRL_MPMC_FREQ_26M (0<<0)
+#define SYS_CTRL_CLK_MPMC_DELAY(n) (((n)&31)<<8)
+#define SYS_CTRL_CLK_MPMC_DELAY_POL (1<<13)
+#define SYS_CTRL_CLK_MPMC_FEEDBACK(n) (((n)&31)<<14)
+#define SYS_CTRL_CLK_MPMC_FEEDBACK_POL (1<<19)
+#define SYS_CTRL_MPMC_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_MPMC_DQS
+#define SYS_CTRL_MPMC_DQSL_O(n) (((n)&31)<<0)
+#define SYS_CTRL_MPMC_DQSU_O(n) (((n)&31)<<6)
+#define SYS_CTRL_MPMC_DQS_OEN(n) (((n)&31)<<12)
+#define SYS_CTRL_MPMC_DQSL_I(n) (((n)&31)<<18)
+#define SYS_CTRL_MPMC_DQSU_I(n) (((n)&31)<<24)
+
+//Cfg_Clk_BB_VTB
+#define SYS_CTRL_BB_VTB_FREQ(n) (((n)&15)<<0)
+#define SYS_CTRL_BB_VTB_FREQ_MASK (15<<0)
+#define SYS_CTRL_BB_VTB_FREQ_SHIFT (0)
+#define SYS_CTRL_BB_VTB_FREQ_312M (13<<0)
+#define SYS_CTRL_BB_VTB_FREQ_250M (12<<0)
+#define SYS_CTRL_BB_VTB_FREQ_208M (11<<0)
+#define SYS_CTRL_BB_VTB_FREQ_178M (10<<0)
+#define SYS_CTRL_BB_VTB_FREQ_156M (9<<0)
+#define SYS_CTRL_BB_VTB_FREQ_139M (8<<0)
+#define SYS_CTRL_BB_VTB_FREQ_125M (7<<0)
+#define SYS_CTRL_BB_VTB_FREQ_113M (6<<0)
+#define SYS_CTRL_BB_VTB_FREQ_104M (5<<0)
+#define SYS_CTRL_BB_VTB_FREQ_89M (4<<0)
+#define SYS_CTRL_BB_VTB_FREQ_78M (3<<0)
+#define SYS_CTRL_BB_VTB_FREQ_52M (2<<0)
+#define SYS_CTRL_BB_VTB_FREQ_39M (1<<0)
+#define SYS_CTRL_BB_VTB_FREQ_26M (0<<0)
+#define SYS_CTRL_BB_VTB_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Reserve
+#define SYS_CTRL_RESERVE_L(n) (((n)&0x3FFF)<<0)
+#define SYS_CTRL_AUIFC_CH0_IRQ_MASK (1<<14)
+#define SYS_CTRL_AUIFC_CH1_IRQ_MASK (1<<15)
+#define SYS_CTRL_RESERVE_H(n) (((n)&0xFFFF)<<16)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8850.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8850.h new file mode 100644 index 0000000000..4afdaeea23 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8850.h @@ -0,0 +1,1363 @@ +#ifndef _REG_MD_SYSCTRL_H_
+#define _REG_MD_SYSCTRL_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+// MACROS
+// =============================================================================
+
+// ============================================================================
+// CPU_ID_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// CPU IDs
+ XCPU = 0x00000000,
+ BCPU = 0x00000001,
+ WCPU = 0x00000002
+} CPU_ID_T;
+
+#define NB_MODEM_CPU (3)
+
+// ============================================================================
+// SYS_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// System side System clocks
+ SYS_XCPU = 0x00000000,
+ SYS_XCPU_INT = 0x00000001,
+ SYS_PCLK_CONF = 0x00000002,
+ SYS_PCLK_DATA = 0x00000003,
+ SYS_AMBA = 0x00000004,
+ SYS_DMA = 0x00000005,
+ SYS_EBC = 0x00000006,
+ SYS_IFC_CH0 = 0x00000007,
+ SYS_IFC_CH1 = 0x00000008,
+ SYS_IFC_CH2 = 0x00000009,
+ SYS_IFC_CH3 = 0x0000000A,
+ SYS_IFC_DBG = 0x0000000B,
+ SYS_A2A = 0x0000000C,
+ SYS_AXI2AHB = 0x0000000D,
+ SYS_AHB2AXI = 0x0000000E,
+ SYS_EXT_AHB = 0x0000000F,
+ SYS_DEBUG_UART = 0x00000010,
+ SYS_DBGHST = 0x00000011,
+ SYS_A2A_WD = 0x00000012,
+/// System side divided clock (either divided by module or by sys_ctrl)
+ SYSD_SCI1 = 0x00000013,
+ SYSD_SCI2 = 0x00000014,
+ SYSD_SCI3 = 0x00000015,
+ SYSD_RF_SPI = 0x00000016,
+ SYSD_OSC = 0x00000017,
+/// the following don't have an auto enable
+ SYS_GPIO = 0x00000018,
+ SYS_IRQ = 0x00000019,
+ SYS_TCU = 0x0000001A,
+ SYS_TIMER = 0x0000001B,
+ SYS_COM_REGS = 0x0000001C,
+/// the following are sharing their enable
+ SYS_SCI1 = 0x0000001D,
+ SYS_SCI2 = 0x0000001E,
+ SYS_SCI3 = 0x0000001F,
+/// keep last
+ SYS_NOGATE = 0x00000020
+} SYS_CLKS_T;
+
+#define NB_SYS_CLK_XCPU (2)
+#define NB_SYS_CLK_AEN (24)
+#define NB_SYS_CLK_EN (29)
+#define NB_SYS_CLK (33)
+
+// ============================================================================
+// SYS2_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// WCDMA Baseband side System clocks
+ SYS_MPMC = 0x00000000,
+ SYS_MPMCREG = 0x00000001,
+/// the following don't have an auto enable
+ SYS_DP_BB = 0x00000002,
+ SYS_DP_WD = 0x00000003,
+ SYS_DP_AP = 0x00000004
+} SYS2_CLKS_T;
+
+#define NB_SYS2_CLK_AEN (2)
+#define NB_SYS2_CLK_EN (5)
+#define NB_SYS2_CLK (5)
+
+// ============================================================================
+// PER_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// System side divided clock (either divided by module or by sys_ctrl)
+ PERD_SPI1 = 0x00000000,
+/// System side divided clock (either divided by module or by sys_ctrl)
+ PERD_SPI2 = 0x00000001,
+ PER_SPY = 0x00000002,
+ PER_TEST = 0x00000003
+} PER_CLKS_T;
+
+#define NB_PER_CLK_AEN (2)
+#define NB_PER_CLK_EN (4)
+#define NB_PER_CLK (4)
+
+// ============================================================================
+// BB_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// Baseband side System clocks
+ BB_BCPU = 0x00000000,
+ BB_BCPU_INT = 0x00000001,
+ BB_AMBA = 0x00000002,
+ BB_PCLK_CONF = 0x00000003,
+ BB_PCLK_DATA = 0x00000004,
+ BB_EXCOR = 0x00000005,
+ BB_IFC_CH2 = 0x00000006,
+ BB_IFC_CH3 = 0x00000007,
+ BB_SRAM = 0x00000008,
+ BB_A2A = 0x00000009,
+ BB_ITLV = 0x0000000A,
+ BB_VITERBI = 0x0000000B,
+ BB_CIPHER = 0x0000000C,
+ BB_RF_IF = 0x0000000D,
+ BB_COPRO = 0x0000000E,
+ BB_CP2_REG = 0x0000000F,
+ BB_XCOR = 0x00000010,
+ BB_EVITAC = 0x00000011,
+ BB_ROM = 0x00000012,
+ BB_MPMC = 0x00000013,
+/// the following don't have an auto enable
+ BB_IRQ = 0x00000014,
+ BB_COM_REGS = 0x00000015,
+ BB_CORDIC = 0x00000016,
+ BB_DP = 0x00000017
+} BB_CLKS_T;
+
+#define NB_BB_CLK_AEN (20)
+#define NB_BB_CLK_EN (24)
+#define NB_BB_CLK (24)
+
+// ============================================================================
+// WD_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// WCDMA Baseband side System clocks
+ WD_WCPU = 0x00000000,
+ WD_AMBA = 0x00000001,
+ WD_PCLK_CONF = 0x00000002,
+ WD_PCLK_DATA = 0x00000003,
+ WD_A2A = 0x00000004,
+ WD_IFC_CH_SPI = 0x00000005,
+ WD_MPMC = 0x00000006,
+ WDD_OSC = 0x00000007,
+/// the following don't have an auto enable
+ WD_IRQ = 0x00000008,
+ WD_AXI = 0x00000009,
+ WD_DP = 0x0000000A,
+ WD_MODEM = 0x0000000B,
+ WD_COM_REGS = 0x0000000C,
+ WD_TIMER = 0x0000000D,
+ WD_SDMA = 0x0000000E,
+ WD_SLPC = 0x0000000F,
+ WD_SLPT = 0x00000010,
+ WD_SPI1 = 0x00000011,
+ WD_SPI2 = 0x00000012,
+ WD_RFIF = 0x00000013
+} WD_CLKS_T;
+
+#define NB_WD_CLK_AEN (8)
+#define NB_WD_CLK_EN (20)
+#define NB_WD_CLK (20)
+/// Other clocks
+/// clocks with auto enble
+/// the debug host clock auto enable is not used in host mode, only in uart mode
+#define OC_HOST_UART (0)
+
+// ============================================================================
+// OTHER_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+ OC_DEBUG_UART = 0x00000000,
+ OC_RF_RX = 0x00000001,
+ OC_RF_TX = 0x00000002,
+ OC_MEM_BRIDGE = 0x00000003,
+/// the following don't have an auto enable
+ OC_LPS = 0x00000004,
+ OC_GPIO = 0x00000005,
+ OC_CLK_OUT = 0x00000006,
+ OC_MEM_CLK_OUT = 0x00000007,
+ OC_TCU = 0x00000008,
+ OC_WD_CHIP = 0x00000009,
+ OC_WD_ADC = 0x0000000A,
+ OC_WD_TURBO = 0x0000000B,
+ OC_WD_OSC = 0x0000000C,
+ OC_MPMC = 0x0000000D
+} OTHER_CLKS_T;
+
+#define NB_OTHER_CLK_AEN (4)
+#define NB_OTHER_CLK_EN (14)
+#define NB_OTHER_CLK (14)
+
+// ============================================================================
+// RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// System side resets
+ RST_XCPU = 0x00000000,
+ RST_SYS_IRQ = 0x00000001,
+ RST_SYS_A2A = 0x00000002,
+ RST_SYS_AHB2AXI = 0x00000003,
+ RST_SYS_AXI2AHB = 0x00000004,
+ RST_DMA = 0x00000005,
+ RST_TIMER = 0x00000006,
+ RST_TCU = 0x00000007,
+ RST_GPIO = 0x00000008,
+ RST_CFG = 0x00000009,
+ RST_SPI1 = 0x0000000A,
+ RST_SPI2 = 0x0000000B,
+ RST_RF_SPI = 0x0000000C,
+ RST_SCI1 = 0x0000000D,
+ RST_SCI2 = 0x0000000E,
+ RST_SCI3 = 0x0000000F,
+ RST_SPY = 0x00000010,
+ RST_MEM_BRIDGE = 0x00000011,
+ RST_EXT_AHB = 0x00000012,
+ RST_DP_BB = 0x00000013,
+ RST_DP_AP = 0x00000014,
+ RST_COMREGS = 0x00000015,
+ RST_COMREGS_AP = 0x00000016,
+ RST_AP_CLKEN = 0x00000017,
+ RST_AP_RST = 0x00000018,
+ RST_MEM_CHK = 0x00000019,
+ RST_MPMC = 0x0000001A,
+ RST_SYS_A2A_WD = 0x0000001B,
+ RST_COMREGS_WD = 0x0000001C,
+ RST_BCPU = 0x0000001D,
+ RST_BB_IRQ = 0x0000001E,
+ RST_BB_A2A = 0x0000001F,
+ RST_BB_IFC = 0x00000020,
+ RST_BB_SRAM = 0x00000021,
+ RST_ITLV = 0x00000022,
+ RST_VITERBI = 0x00000023,
+ RST_CIPHER = 0x00000024,
+ RST_XCOR = 0x00000025,
+ RST_COPRO = 0x00000026,
+ RST_RF_IF = 0x00000027,
+ RST_EXCOR = 0x00000028,
+ RST_EVITAC = 0x00000029,
+ RST_CORDIC = 0x0000002A,
+ RST_TCU_BB = 0x0000002B,
+ RST_BB_DP = 0x0000002C,
+ RST_BB_ROM = 0x0000002D,
+ RST_MPMC_BB = 0x0000002E,
+ RST_BB_FULL = 0x0000002F,
+ RST_SYS_FULL = 0x00000030
+} RESETS_T;
+
+#define NB_SRST (29)
+/// Baseband side resets
+#define BOUND_BRST_FIRST (29)
+#define BOUND_BRST_AFTER (47)
+/// The following reset does not have register
+#define NR_RST_REG (48)
+#define NB_RST (49)
+#define NB_BRST (BOUND_BRST_AFTER-BOUND_BRST_FIRST)
+
+// ============================================================================
+// RESET_OTHERS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// Reset Other : resync on corresponding clock other
+ RSTO_DBG_HOST = 0x00000000,
+ RSTO_RF_RX = 0x00000001,
+ RSTO_RF_TX = 0x00000002,
+ RSTO_MEM_BRIDGE = 0x00000003,
+ RSTO_LPS = 0x00000004,
+ RSTO_GPIO = 0x00000005,
+ RSTO_WDTIMER = 0x00000006,
+ RSTO_TCU = 0x00000007,
+ RSTO_MPMC = 0x00000008
+} RESET_OTHERS_T;
+
+#define BOUND_RSTO_RF_FIRST (1)
+#define BOUND_RSTO_RF_AFTER (3)
+#define NB_RSTO (9)
+
+// ============================================================================
+// WD_RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// WD side resets
+ WD_RST_WCPU = 0x00000000,
+ WD_RST_IRQ = 0x00000001,
+ WD_RST_DP = 0x00000002,
+ WD_RST_MODEM = 0x00000003,
+ WD_RST_A2A = 0x00000004,
+ WD_RST_IFC = 0x00000005,
+ WD_RST_SDMA = 0x00000006,
+ WD_RST_SLPC = 0x00000007,
+ WD_RST_SLPT = 0x00000008,
+ WD_RST_SPI1 = 0x00000009,
+ WD_RST_SPI2 = 0x0000000A,
+ WD_RST_RFIF = 0x0000000B,
+ WD_RST_COMREGS = 0x0000000C,
+ WD_RST_TIMER = 0x0000000D,
+ WD_RST_MPMC = 0x0000000E,
+ WD_RST_FULL = 0x0000000F
+} WD_RESETS_T;
+
+#define NB_WD_RST_BOUND (15)
+#define NB_WD_RST (16)
+
+// ============================================================================
+// AP_RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP side resets
+ AP_RST_0 = 0x00000000,
+ AP_RST_1 = 0x00000001,
+ AP_RST_2 = 0x00000002,
+ AP_RST_3 = 0x00000003,
+ AP_RST_4 = 0x00000004
+} AP_RESETS_T;
+
+#define NB_AP_RST_BOUND (5)
+#define NB_AP_RST (5)
+/// For REG_DBG protect lock/unlock value
+#define SYS_CTRL_PROTECT_LOCK (0XA50000)
+#define SYS_CTRL_PROTECT_UNLOCK (0XA50001)
+
+// =============================================================================
+// TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_CTRL_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef volatile struct
+{
+ /// <strong>This register is used to Lock and Unlock the protected registers.</strong>
+ REG32 REG_DBG; //0x00000000
+ /// This register is protected.
+ REG32 Sys_Rst_Set; //0x00000004
+ REG32 Sys_Rst_Clr; //0x00000008
+ /// This register is protected.
+ REG32 BB_Rst_Set; //0x0000000C
+ REG32 BB_Rst_Clr; //0x00000010
+ REG32 Clk_Sys_Mode; //0x00000014
+ REG32 Clk_Sys_Enable; //0x00000018
+ /// This register is protected.
+ REG32 Clk_Sys_Disable; //0x0000001C
+ REG32 Clk_Per_Mode; //0x00000020
+ REG32 Clk_Per_Enable; //0x00000024
+ /// This register is protected.
+ REG32 Clk_Per_Disable; //0x00000028
+ REG32 Clk_BB_Mode; //0x0000002C
+ REG32 Clk_BB_Enable; //0x00000030
+ /// This register is protected.
+ REG32 Clk_BB_Disable; //0x00000034
+ REG32 Clk_Other_Mode; //0x00000038
+ REG32 Clk_Other_Enable; //0x0000003C
+ /// This register is protected.
+ REG32 Clk_Other_Disable; //0x00000040
+ /// Register protected by Write_Unlocked_H.
+ REG32 Pll_Ctrl; //0x00000044
+ /// This register is protected.
+ REG32 Sel_Clock; //0x00000048
+ REG32 Cfg_Clk_Sys; //0x0000004C
+ REG32 Cfg_Clk_Mem_Bridge; //0x00000050
+ /// This register is protected.
+ REG32 Cfg_Clk_Out; //0x00000054
+ REG32 Cfg_Clk_Host_Uart; //0x00000058
+ REG32 Cfg_Clk_Auxclk; //0x0000005C
+ /// This register is protected.
+ REG32 Cfg_AHB; //0x00000060
+ /// This register is protected. Used to unsplit masters manualy.
+ REG32 Ctrl_AHB; //0x00000064
+ REG32 XCpu_Dbg_BKP; //0x00000068
+ REG32 XCpu_Dbg_Addr; //0x0000006C
+ REG32 BCpu_Dbg_BKP; //0x00000070
+ REG32 BCpu_Dbg_Addr; //0x00000074
+ REG32 Cfg_Cpus_Cache_Ram_Disable; //0x00000078
+ REG32 Reset_Cause; //0x0000007C
+ /// This register is protected.
+ REG32 WakeUp; //0x00000080
+ REG32 AP_Ctrl; //0x00000084
+ /// This register is protected.
+ REG32 Ignore_Charger; //0x00000088
+ REG32 Clk_SYS2_Mode; //0x0000008C
+ REG32 Clk_SYS2_Enable; //0x00000090
+ /// This register is protected.
+ REG32 Clk_SYS2_Disable; //0x00000094
+ /// Register protected by Write_Unlocked_H.
+ REG32 WD_Pll_Ctrl; //0x00000098
+ /// This register is protected.
+ REG32 WD_Sel_Clock; //0x0000009C
+ /// This register is protected.
+ REG32 WD_Rst_Set; //0x000000A0
+ REG32 WD_Rst_Clr; //0x000000A4
+ /// This register is protected.
+ REG32 AP_Rst_Set; //0x000000A8
+ REG32 AP_Rst_Clr; //0x000000AC
+ REG32 Clk_WD_Mode; //0x000000B0
+ REG32 Clk_WD_Enable; //0x000000B4
+ /// This register is protected.
+ REG32 Clk_WD_Disable; //0x000000B8
+ REG32 Cfg_Clk_MPMC; //0x000000BC
+ REG32 Cfg_MPMC_DQS; //0x000000C0
+ REG32 Reserved_000000C4[14]; //0x000000C4
+ /// This register is reserved.
+ REG32 Cfg_Reserve; //0x000000FC
+} HWP_SYS_CTRL_T;
+
+#define hwp_sysCtrlMd ((HWP_SYS_CTRL_T*)(RDA_MD_SYSCTRL_BASE))
+
+
+//REG_DBG
+#define SYS_CTRL_SCRATCH(n) (((n)&0xFFFF)<<0)
+#define SYS_CTRL_WRITE_UNLOCK_STATUS (1<<30)
+#define SYS_CTRL_WRITE_UNLOCK (1<<31)
+
+//Sys_Rst_Set
+#define SYS_CTRL_SET_RST_XCPU (1<<0)
+#define SYS_CTRL_SET_RST_SYS_IRQ (1<<1)
+#define SYS_CTRL_SET_RST_SYS_A2A (1<<2)
+#define SYS_CTRL_SET_RST_SYS_AHB2AXI (1<<3)
+#define SYS_CTRL_SET_RST_SYS_AXI2AHB (1<<4)
+#define SYS_CTRL_SET_RST_DMA (1<<5)
+#define SYS_CTRL_SET_RST_TIMER (1<<6)
+#define SYS_CTRL_SET_RST_TCU (1<<7)
+#define SYS_CTRL_SET_RST_GPIO (1<<8)
+#define SYS_CTRL_SET_RST_CFG (1<<9)
+#define SYS_CTRL_SET_RST_SPI1 (1<<10)
+#define SYS_CTRL_SET_RST_SPI2 (1<<11)
+#define SYS_CTRL_SET_RST_RF_SPI (1<<12)
+#define SYS_CTRL_SET_RST_SCI1 (1<<13)
+#define SYS_CTRL_SET_RST_SCI2 (1<<14)
+#define SYS_CTRL_SET_RST_SCI3 (1<<15)
+#define SYS_CTRL_SET_RST_SPY (1<<16)
+#define SYS_CTRL_SET_RST_MEM_BRIDGE (1<<17)
+#define SYS_CTRL_SET_RST_EXT_AHB (1<<18)
+#define SYS_CTRL_SET_RST_DP_BB (1<<19)
+#define SYS_CTRL_SET_RST_DP_AP (1<<20)
+#define SYS_CTRL_SET_RST_COMREGS (1<<21)
+#define SYS_CTRL_SET_RST_COMREGS_AP (1<<22)
+#define SYS_CTRL_SET_RST_AP_CLKEN (1<<23)
+#define SYS_CTRL_SET_RST_AP_RST (1<<24)
+#define SYS_CTRL_SET_RST_MEM_CHK (1<<25)
+#define SYS_CTRL_SET_RST_MPMC (1<<26)
+#define SYS_CTRL_SET_RST_SYS_A2A_WD (1<<27)
+#define SYS_CTRL_SET_RST_COMREGS_WD (1<<28)
+#define SYS_CTRL_SET_RST_OUT (1<<30)
+#define SYS_CTRL_SOFT_RST (1<<31)
+#define SYS_CTRL_SET_SYS_RST(n) (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_SET_SYS_RST_MASK (0x1FFFFFFF<<0)
+#define SYS_CTRL_SET_SYS_RST_SHIFT (0)
+
+//Sys_Rst_Clr
+#define SYS_CTRL_CLR_RST_XCPU (1<<0)
+#define SYS_CTRL_CLR_RST_SYS_IRQ (1<<1)
+#define SYS_CTRL_CLR_RST_SYS_A2A (1<<2)
+#define SYS_CTRL_CLR_RST_SYS_AHB2AXI (1<<3)
+#define SYS_CTRL_CLR_RST_SYS_AXI2AHB (1<<4)
+#define SYS_CTRL_CLR_RST_DMA (1<<5)
+#define SYS_CTRL_CLR_RST_TIMER (1<<6)
+#define SYS_CTRL_CLR_RST_TCU (1<<7)
+#define SYS_CTRL_CLR_RST_GPIO (1<<8)
+#define SYS_CTRL_CLR_RST_CFG (1<<9)
+#define SYS_CTRL_CLR_RST_SPI1 (1<<10)
+#define SYS_CTRL_CLR_RST_SPI2 (1<<11)
+#define SYS_CTRL_CLR_RST_RF_SPI (1<<12)
+#define SYS_CTRL_CLR_RST_SCI1 (1<<13)
+#define SYS_CTRL_CLR_RST_SCI2 (1<<14)
+#define SYS_CTRL_CLR_RST_SCI3 (1<<15)
+#define SYS_CTRL_CLR_RST_SPY (1<<16)
+#define SYS_CTRL_CLR_RST_MEM_BRIDGE (1<<17)
+#define SYS_CTRL_CLR_RST_EXT_AHB (1<<18)
+#define SYS_CTRL_CLR_RST_DP_BB (1<<19)
+#define SYS_CTRL_CLR_RST_DP_AP (1<<20)
+#define SYS_CTRL_CLR_RST_COMREGS (1<<21)
+#define SYS_CTRL_CLR_RST_COMREGS_AP (1<<22)
+#define SYS_CTRL_CLR_RST_AP_CLKEN (1<<23)
+#define SYS_CTRL_CLR_RST_AP_RST (1<<24)
+#define SYS_CTRL_CLR_RST_MEM_CHK (1<<25)
+#define SYS_CTRL_CLR_RST_MPMC (1<<26)
+#define SYS_CTRL_CLR_RST_SYS_A2A_WD (1<<27)
+#define SYS_CTRL_CLR_RST_COMREGS_WD (1<<28)
+#define SYS_CTRL_CLR_RST_OUT (1<<30)
+#define SYS_CTRL_CLR_SYS_RST(n) (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_CLR_SYS_RST_MASK (0x1FFFFFFF<<0)
+#define SYS_CTRL_CLR_SYS_RST_SHIFT (0)
+
+//BB_Rst_Set
+#define SYS_CTRL_SET_RST_BCPU (1<<0)
+#define SYS_CTRL_SET_RST_BB_IRQ (1<<1)
+#define SYS_CTRL_SET_RST_BB_A2A (1<<2)
+#define SYS_CTRL_SET_RST_BB_IFC (1<<3)
+#define SYS_CTRL_SET_RST_BB_SRAM (1<<4)
+#define SYS_CTRL_SET_RST_ITLV (1<<5)
+#define SYS_CTRL_SET_RST_VITERBI (1<<6)
+#define SYS_CTRL_SET_RST_CIPHER (1<<7)
+#define SYS_CTRL_SET_RST_XCOR (1<<8)
+#define SYS_CTRL_SET_RST_COPRO (1<<9)
+#define SYS_CTRL_SET_RST_RF_IF (1<<10)
+#define SYS_CTRL_SET_RST_EXCOR (1<<11)
+#define SYS_CTRL_SET_RST_EVITAC (1<<12)
+#define SYS_CTRL_SET_RST_CORDIC (1<<13)
+#define SYS_CTRL_SET_RST_TCU_BB (1<<14)
+#define SYS_CTRL_SET_RST_BB_DP (1<<15)
+#define SYS_CTRL_SET_RST_BB_ROM (1<<16)
+#define SYS_CTRL_SET_RST_MPMC_BB (1<<17)
+#define SYS_CTRL_SET_RST_BB_FULL (1<<31)
+#define SYS_CTRL_SET_BB_RST(n) (((n)&0x3FFFF)<<0)
+#define SYS_CTRL_SET_BB_RST_MASK (0x3FFFF<<0)
+#define SYS_CTRL_SET_BB_RST_SHIFT (0)
+
+//BB_Rst_Clr
+#define SYS_CTRL_CLR_RST_BCPU (1<<0)
+#define SYS_CTRL_CLR_RST_BB_IRQ (1<<1)
+#define SYS_CTRL_CLR_RST_BB_A2A (1<<2)
+#define SYS_CTRL_CLR_RST_BB_IFC (1<<3)
+#define SYS_CTRL_CLR_RST_BB_SRAM (1<<4)
+#define SYS_CTRL_CLR_RST_ITLV (1<<5)
+#define SYS_CTRL_CLR_RST_VITERBI (1<<6)
+#define SYS_CTRL_CLR_RST_CIPHER (1<<7)
+#define SYS_CTRL_CLR_RST_XCOR (1<<8)
+#define SYS_CTRL_CLR_RST_COPRO (1<<9)
+#define SYS_CTRL_CLR_RST_RF_IF (1<<10)
+#define SYS_CTRL_CLR_RST_EXCOR (1<<11)
+#define SYS_CTRL_CLR_RST_EVITAC (1<<12)
+#define SYS_CTRL_CLR_RST_CORDIC (1<<13)
+#define SYS_CTRL_CLR_RST_TCU_BB (1<<14)
+#define SYS_CTRL_CLR_RST_BB_DP (1<<15)
+#define SYS_CTRL_CLR_RST_BB_ROM (1<<16)
+#define SYS_CTRL_CLR_RST_MPMC_BB (1<<17)
+#define SYS_CTRL_CLR_RST_BB_FULL (1<<31)
+#define SYS_CTRL_CLR_BB_RST(n) (((n)&0x3FFFF)<<0)
+#define SYS_CTRL_CLR_BB_RST_MASK (0x3FFFF<<0)
+#define SYS_CTRL_CLR_BB_RST_SHIFT (0)
+
+//Clk_Sys_Mode
+#define SYS_CTRL_MODE_SYS_XCPU (1<<0)
+#define SYS_CTRL_MODE_SYS_XCPU_INT_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_SYS_XCPU_INT_MANUAL (1<<1)
+#define SYS_CTRL_MODE_SYS_PCLK_CONF_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_SYS_PCLK_CONF_MANUAL (1<<2)
+#define SYS_CTRL_MODE_SYS_PCLK_DATA_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_SYS_PCLK_DATA_MANUAL (1<<3)
+#define SYS_CTRL_MODE_SYS_AMBA_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_SYS_AMBA_MANUAL (1<<4)
+#define SYS_CTRL_MODE_SYS_DMA_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_SYS_DMA_MANUAL (1<<5)
+#define SYS_CTRL_MODE_SYS_EBC_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_SYS_EBC_MANUAL (1<<6)
+#define SYS_CTRL_MODE_SYS_IFC_CH0_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_SYS_IFC_CH0_MANUAL (1<<7)
+#define SYS_CTRL_MODE_SYS_IFC_CH1_AUTOMATIC (0<<8)
+#define SYS_CTRL_MODE_SYS_IFC_CH1_MANUAL (1<<8)
+#define SYS_CTRL_MODE_SYS_IFC_CH2_AUTOMATIC (0<<9)
+#define SYS_CTRL_MODE_SYS_IFC_CH2_MANUAL (1<<9)
+#define SYS_CTRL_MODE_SYS_IFC_CH3_AUTOMATIC (0<<10)
+#define SYS_CTRL_MODE_SYS_IFC_CH3_MANUAL (1<<10)
+#define SYS_CTRL_MODE_SYS_IFC_DBG_AUTOMATIC (0<<11)
+#define SYS_CTRL_MODE_SYS_IFC_DBG_MANUAL (1<<11)
+#define SYS_CTRL_MODE_SYS_A2A_AUTOMATIC (0<<12)
+#define SYS_CTRL_MODE_SYS_A2A_MANUAL (1<<12)
+#define SYS_CTRL_MODE_SYS_AXI2AHB_AUTOMATIC (0<<13)
+#define SYS_CTRL_MODE_SYS_AXI2AHB_MANUAL (1<<13)
+#define SYS_CTRL_MODE_SYS_AHB2AXI_AUTOMATIC (0<<14)
+#define SYS_CTRL_MODE_SYS_AHB2AXI_MANUAL (1<<14)
+#define SYS_CTRL_MODE_SYS_EXT_AHB_AUTOMATIC (0<<15)
+#define SYS_CTRL_MODE_SYS_EXT_AHB_MANUAL (1<<15)
+#define SYS_CTRL_MODE_SYS_DEBUG_UART_AUTOMATIC (0<<16)
+#define SYS_CTRL_MODE_SYS_DEBUG_UART_MANUAL (1<<16)
+#define SYS_CTRL_MODE_SYS_DBGHST_AUTOMATIC (0<<17)
+#define SYS_CTRL_MODE_SYS_DBGHST_MANUAL (1<<17)
+#define SYS_CTRL_MODE_SYS_A2A_WD_AUTOMATIC (0<<18)
+#define SYS_CTRL_MODE_SYS_A2A_WD_MANUAL (1<<18)
+#define SYS_CTRL_MODE_SYSD_SCI1_AUTOMATIC (0<<19)
+#define SYS_CTRL_MODE_SYSD_SCI1_MANUAL (1<<19)
+#define SYS_CTRL_MODE_SYSD_SCI2_AUTOMATIC (0<<20)
+#define SYS_CTRL_MODE_SYSD_SCI2_MANUAL (1<<20)
+#define SYS_CTRL_MODE_SYSD_SCI3_AUTOMATIC (0<<21)
+#define SYS_CTRL_MODE_SYSD_SCI3_MANUAL (1<<21)
+#define SYS_CTRL_MODE_SYSD_RF_SPI_AUTOMATIC (0<<22)
+#define SYS_CTRL_MODE_SYSD_RF_SPI_MANUAL (1<<22)
+#define SYS_CTRL_MODE_SYSD_OSC_AUTOMATIC (0<<23)
+#define SYS_CTRL_MODE_SYSD_OSC_MANUAL (1<<23)
+#define SYS_CTRL_MODE_CLK_SYS(n) (((n)&0x7FFFFF)<<1)
+#define SYS_CTRL_MODE_CLK_SYS_MASK (0x7FFFFF<<1)
+#define SYS_CTRL_MODE_CLK_SYS_SHIFT (1)
+
+//Clk_Sys_Enable
+#define SYS_CTRL_ENABLE_SYS_XCPU (1<<0)
+#define SYS_CTRL_ENABLE_SYS_XCPU_INT (1<<1)
+#define SYS_CTRL_ENABLE_SYS_PCLK_CONF (1<<2)
+#define SYS_CTRL_ENABLE_SYS_PCLK_DATA (1<<3)
+#define SYS_CTRL_ENABLE_SYS_AMBA (1<<4)
+#define SYS_CTRL_ENABLE_SYS_DMA (1<<5)
+#define SYS_CTRL_ENABLE_SYS_EBC (1<<6)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH0 (1<<7)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH1 (1<<8)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH2 (1<<9)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH3 (1<<10)
+#define SYS_CTRL_ENABLE_SYS_IFC_DBG (1<<11)
+#define SYS_CTRL_ENABLE_SYS_A2A (1<<12)
+#define SYS_CTRL_ENABLE_SYS_AXI2AHB (1<<13)
+#define SYS_CTRL_ENABLE_SYS_AHB2AXI (1<<14)
+#define SYS_CTRL_ENABLE_SYS_EXT_AHB (1<<15)
+#define SYS_CTRL_ENABLE_SYS_DEBUG_UART (1<<16)
+#define SYS_CTRL_ENABLE_SYS_DBGHST (1<<17)
+#define SYS_CTRL_ENABLE_SYS_A2A_WD (1<<18)
+#define SYS_CTRL_ENABLE_SYSD_SCI1 (1<<19)
+#define SYS_CTRL_ENABLE_SYSD_SCI2 (1<<20)
+#define SYS_CTRL_ENABLE_SYSD_SCI3 (1<<21)
+#define SYS_CTRL_ENABLE_SYSD_RF_SPI (1<<22)
+#define SYS_CTRL_ENABLE_SYSD_OSC (1<<23)
+#define SYS_CTRL_ENABLE_SYS_GPIO (1<<24)
+#define SYS_CTRL_ENABLE_SYS_IRQ (1<<25)
+#define SYS_CTRL_ENABLE_SYS_TCU (1<<26)
+#define SYS_CTRL_ENABLE_SYS_TIMER (1<<27)
+#define SYS_CTRL_ENABLE_SYS_COM_REGS (1<<28)
+#define SYS_CTRL_ENABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS_SHIFT (0)
+
+//Clk_Sys_Disable
+#define SYS_CTRL_DISABLE_SYS_XCPU (1<<0)
+#define SYS_CTRL_DISABLE_SYS_XCPU_INT (1<<1)
+#define SYS_CTRL_DISABLE_SYS_PCLK_CONF (1<<2)
+#define SYS_CTRL_DISABLE_SYS_PCLK_DATA (1<<3)
+#define SYS_CTRL_DISABLE_SYS_AMBA (1<<4)
+#define SYS_CTRL_DISABLE_SYS_DMA (1<<5)
+#define SYS_CTRL_DISABLE_SYS_EBC (1<<6)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH0 (1<<7)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH1 (1<<8)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH2 (1<<9)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH3 (1<<10)
+#define SYS_CTRL_DISABLE_SYS_IFC_DBG (1<<11)
+#define SYS_CTRL_DISABLE_SYS_A2A (1<<12)
+#define SYS_CTRL_DISABLE_SYS_AXI2AHB (1<<13)
+#define SYS_CTRL_DISABLE_SYS_AHB2AXI (1<<14)
+#define SYS_CTRL_DISABLE_SYS_EXT_AHB (1<<15)
+#define SYS_CTRL_DISABLE_SYS_DEBUG_UART (1<<16)
+#define SYS_CTRL_DISABLE_SYS_DBGHST (1<<17)
+#define SYS_CTRL_DISABLE_SYS_A2A_WD (1<<18)
+#define SYS_CTRL_DISABLE_SYSD_SCI1 (1<<19)
+#define SYS_CTRL_DISABLE_SYSD_SCI2 (1<<20)
+#define SYS_CTRL_DISABLE_SYSD_SCI3 (1<<21)
+#define SYS_CTRL_DISABLE_SYSD_RF_SPI (1<<22)
+#define SYS_CTRL_DISABLE_SYSD_OSC (1<<23)
+#define SYS_CTRL_DISABLE_SYS_GPIO (1<<24)
+#define SYS_CTRL_DISABLE_SYS_IRQ (1<<25)
+#define SYS_CTRL_DISABLE_SYS_TCU (1<<26)
+#define SYS_CTRL_DISABLE_SYS_TIMER (1<<27)
+#define SYS_CTRL_DISABLE_SYS_COM_REGS (1<<28)
+#define SYS_CTRL_DISABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS_SHIFT (0)
+
+//Clk_Per_Mode
+#define SYS_CTRL_MODE_PERD_SPI1_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_PERD_SPI1_MANUAL (1<<0)
+#define SYS_CTRL_MODE_PERD_SPI2_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_PERD_SPI2_MANUAL (1<<1)
+#define SYS_CTRL_MODE_CLK_PER(n) (((n)&3)<<0)
+#define SYS_CTRL_MODE_CLK_PER_MASK (3<<0)
+#define SYS_CTRL_MODE_CLK_PER_SHIFT (0)
+
+//Clk_Per_Enable
+#define SYS_CTRL_ENABLE_PERD_SPI1 (1<<0)
+#define SYS_CTRL_ENABLE_PERD_SPI2 (1<<1)
+#define SYS_CTRL_ENABLE_PER_SPY (1<<2)
+#define SYS_CTRL_ENABLE_PER_TEST (1<<3)
+#define SYS_CTRL_ENABLE_CLK_PER(n) (((n)&15)<<0)
+#define SYS_CTRL_ENABLE_CLK_PER_MASK (15<<0)
+#define SYS_CTRL_ENABLE_CLK_PER_SHIFT (0)
+
+//Clk_Per_Disable
+#define SYS_CTRL_DISABLE_PERD_SPI1 (1<<0)
+#define SYS_CTRL_DISABLE_PERD_SPI2 (1<<1)
+#define SYS_CTRL_DISABLE_PER_SPY (1<<2)
+#define SYS_CTRL_DISABLE_PER_TEST (1<<3)
+#define SYS_CTRL_DISABLE_CLK_PER(n) (((n)&15)<<0)
+#define SYS_CTRL_DISABLE_CLK_PER_MASK (15<<0)
+#define SYS_CTRL_DISABLE_CLK_PER_SHIFT (0)
+
+//Clk_BB_Mode
+#define SYS_CTRL_MODE_BB_BCPU (1<<0)
+#define SYS_CTRL_MODE_BB_BCPU_INT_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_BB_BCPU_INT_MANUAL (1<<1)
+#define SYS_CTRL_MODE_BB_AMBA_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_BB_AMBA_MANUAL (1<<2)
+#define SYS_CTRL_MODE_BB_PCLK_CONF_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_BB_PCLK_CONF_MANUAL (1<<3)
+#define SYS_CTRL_MODE_BB_PCLK_DATA_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_BB_PCLK_DATA_MANUAL (1<<4)
+#define SYS_CTRL_MODE_BB_EXCOR_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_BB_EXCOR_MANUAL (1<<5)
+#define SYS_CTRL_MODE_BB_IFC_CH2_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_BB_IFC_CH2_MANUAL (1<<6)
+#define SYS_CTRL_MODE_BB_IFC_CH3_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_BB_IFC_CH3_MANUAL (1<<7)
+#define SYS_CTRL_MODE_BB_SRAM_AUTOMATIC (0<<8)
+#define SYS_CTRL_MODE_BB_SRAM_MANUAL (1<<8)
+#define SYS_CTRL_MODE_BB_A2A_AUTOMATIC (0<<9)
+#define SYS_CTRL_MODE_BB_A2A_MANUAL (1<<9)
+#define SYS_CTRL_MODE_BB_ITLV_AUTOMATIC (0<<10)
+#define SYS_CTRL_MODE_BB_ITLV_MANUAL (1<<10)
+#define SYS_CTRL_MODE_BB_VITERBI_AUTOMATIC (0<<11)
+#define SYS_CTRL_MODE_BB_VITERBI_MANUAL (1<<11)
+#define SYS_CTRL_MODE_BB_CIPHER_AUTOMATIC (0<<12)
+#define SYS_CTRL_MODE_BB_CIPHER_MANUAL (1<<12)
+#define SYS_CTRL_MODE_BB_RF_IF_AUTOMATIC (0<<13)
+#define SYS_CTRL_MODE_BB_RF_IF_MANUAL (1<<13)
+#define SYS_CTRL_MODE_BB_COPRO_AUTOMATIC (0<<14)
+#define SYS_CTRL_MODE_BB_COPRO_MANUAL (1<<14)
+#define SYS_CTRL_MODE_BB_CP2_REG_AUTOMATIC (0<<15)
+#define SYS_CTRL_MODE_BB_CP2_REG_MANUAL (1<<15)
+#define SYS_CTRL_MODE_BB_XCOR_AUTOMATIC (0<<16)
+#define SYS_CTRL_MODE_BB_XCOR_MANUAL (1<<16)
+#define SYS_CTRL_MODE_BB_EVITAC_AUTOMATIC (0<<17)
+#define SYS_CTRL_MODE_BB_EVITAC_MANUAL (1<<17)
+#define SYS_CTRL_MODE_BB_ROM_AUTOMATIC (0<<18)
+#define SYS_CTRL_MODE_BB_ROM_MANUAL (1<<18)
+#define SYS_CTRL_MODE_BB_MPMC_AUTOMATIC (0<<19)
+#define SYS_CTRL_MODE_BB_MPMC_MANUAL (1<<19)
+#define SYS_CTRL_MODE_CLK_BB(n) (((n)&0x7FFFF)<<1)
+#define SYS_CTRL_MODE_CLK_BB_MASK (0x7FFFF<<1)
+#define SYS_CTRL_MODE_CLK_BB_SHIFT (1)
+
+//Clk_BB_Enable
+#define SYS_CTRL_ENABLE_BB_BCPU (1<<0)
+#define SYS_CTRL_ENABLE_BB_BCPU_INT (1<<1)
+#define SYS_CTRL_ENABLE_BB_AMBA (1<<2)
+#define SYS_CTRL_ENABLE_BB_PCLK_CONF (1<<3)
+#define SYS_CTRL_ENABLE_BB_PCLK_DATA (1<<4)
+#define SYS_CTRL_ENABLE_BB_EXCOR (1<<5)
+#define SYS_CTRL_ENABLE_BB_IFC_CH2 (1<<6)
+#define SYS_CTRL_ENABLE_BB_IFC_CH3 (1<<7)
+#define SYS_CTRL_ENABLE_BB_SRAM (1<<8)
+#define SYS_CTRL_ENABLE_BB_A2A (1<<9)
+#define SYS_CTRL_ENABLE_BB_ITLV (1<<10)
+#define SYS_CTRL_ENABLE_BB_VITERBI (1<<11)
+#define SYS_CTRL_ENABLE_BB_CIPHER (1<<12)
+#define SYS_CTRL_ENABLE_BB_RF_IF (1<<13)
+#define SYS_CTRL_ENABLE_BB_COPRO (1<<14)
+#define SYS_CTRL_ENABLE_BB_CP2_REG (1<<15)
+#define SYS_CTRL_ENABLE_BB_XCOR (1<<16)
+#define SYS_CTRL_ENABLE_BB_EVITAC (1<<17)
+#define SYS_CTRL_ENABLE_BB_ROM (1<<18)
+#define SYS_CTRL_ENABLE_BB_MPMC (1<<19)
+#define SYS_CTRL_ENABLE_BB_IRQ (1<<20)
+#define SYS_CTRL_ENABLE_BB_COM_REGS (1<<21)
+#define SYS_CTRL_ENABLE_BB_CORDIC (1<<22)
+#define SYS_CTRL_ENABLE_BB_DP (1<<23)
+#define SYS_CTRL_ENABLE_CLK_BB(n) (((n)&0xFFFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_BB_MASK (0xFFFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_BB_SHIFT (0)
+
+//Clk_BB_Disable
+#define SYS_CTRL_DISABLE_BB_BCPU (1<<0)
+#define SYS_CTRL_DISABLE_BB_BCPU_INT (1<<1)
+#define SYS_CTRL_DISABLE_BB_AMBA (1<<2)
+#define SYS_CTRL_DISABLE_BB_PCLK_CONF (1<<3)
+#define SYS_CTRL_DISABLE_BB_PCLK_DATA (1<<4)
+#define SYS_CTRL_DISABLE_BB_EXCOR (1<<5)
+#define SYS_CTRL_DISABLE_BB_IFC_CH2 (1<<6)
+#define SYS_CTRL_DISABLE_BB_IFC_CH3 (1<<7)
+#define SYS_CTRL_DISABLE_BB_SRAM (1<<8)
+#define SYS_CTRL_DISABLE_BB_A2A (1<<9)
+#define SYS_CTRL_DISABLE_BB_ITLV (1<<10)
+#define SYS_CTRL_DISABLE_BB_VITERBI (1<<11)
+#define SYS_CTRL_DISABLE_BB_CIPHER (1<<12)
+#define SYS_CTRL_DISABLE_BB_RF_IF (1<<13)
+#define SYS_CTRL_DISABLE_BB_COPRO (1<<14)
+#define SYS_CTRL_DISABLE_BB_CP2_REG (1<<15)
+#define SYS_CTRL_DISABLE_BB_XCOR (1<<16)
+#define SYS_CTRL_DISABLE_BB_EVITAC (1<<17)
+#define SYS_CTRL_DISABLE_BB_ROM (1<<18)
+#define SYS_CTRL_DISABLE_BB_MPMC (1<<19)
+#define SYS_CTRL_DISABLE_BB_IRQ (1<<20)
+#define SYS_CTRL_DISABLE_BB_COM_REGS (1<<21)
+#define SYS_CTRL_DISABLE_BB_CORDIC (1<<22)
+#define SYS_CTRL_DISABLE_BB_DP (1<<23)
+#define SYS_CTRL_DISABLE_CLK_BB(n) (((n)&0xFFFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_BB_MASK (0xFFFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_BB_SHIFT (0)
+
+//Clk_Other_Mode
+#define SYS_CTRL_MODE_OC_DEBUG_UART_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_OC_DEBUG_UART_MANUAL (1<<0)
+#define SYS_CTRL_MODE_OC_RF_RX_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_OC_RF_RX_MANUAL (1<<1)
+#define SYS_CTRL_MODE_OC_RF_TX_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_OC_RF_TX_MANUAL (1<<2)
+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_MANUAL (1<<3)
+#define SYS_CTRL_MODE_CLK_OTHER(n) (((n)&15)<<0)
+#define SYS_CTRL_MODE_CLK_OTHER_MASK (15<<0)
+#define SYS_CTRL_MODE_CLK_OTHER_SHIFT (0)
+
+//Clk_Other_Enable
+#define SYS_CTRL_ENABLE_OC_DEBUG_UART (1<<0)
+#define SYS_CTRL_ENABLE_OC_RF_RX (1<<1)
+#define SYS_CTRL_ENABLE_OC_RF_TX (1<<2)
+#define SYS_CTRL_ENABLE_OC_MEM_BRIDGE (1<<3)
+#define SYS_CTRL_ENABLE_OC_LPS (1<<4)
+#define SYS_CTRL_ENABLE_OC_GPIO (1<<5)
+#define SYS_CTRL_ENABLE_OC_CLK_OUT (1<<6)
+#define SYS_CTRL_ENABLE_OC_MEM_CLK_OUT (1<<7)
+#define SYS_CTRL_ENABLE_OC_TCU (1<<8)
+#define SYS_CTRL_ENABLE_OC_WD_CHIP (1<<9)
+#define SYS_CTRL_ENABLE_OC_WD_ADC (1<<10)
+#define SYS_CTRL_ENABLE_OC_WD_TURBO (1<<11)
+#define SYS_CTRL_ENABLE_OC_WD_OSC (1<<12)
+#define SYS_CTRL_ENABLE_OC_MPMC (1<<13)
+#define SYS_CTRL_ENABLE_CLK_OTHER(n) (((n)&0x3FFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_OTHER_MASK (0x3FFF<<0)
+#define SYS_CTRL_ENABLE_CLK_OTHER_SHIFT (0)
+
+//Clk_Other_Disable
+#define SYS_CTRL_DISABLE_OC_DEBUG_UART (1<<0)
+#define SYS_CTRL_DISABLE_OC_RF_RX (1<<1)
+#define SYS_CTRL_DISABLE_OC_RF_TX (1<<2)
+#define SYS_CTRL_DISABLE_OC_MEM_BRIDGE (1<<3)
+#define SYS_CTRL_DISABLE_OC_LPS (1<<4)
+#define SYS_CTRL_DISABLE_OC_GPIO (1<<5)
+#define SYS_CTRL_DISABLE_OC_CLK_OUT (1<<6)
+#define SYS_CTRL_DISABLE_OC_MEM_CLK_OUT (1<<7)
+#define SYS_CTRL_DISABLE_OC_TCU (1<<8)
+#define SYS_CTRL_DISABLE_OC_WD_CHIP (1<<9)
+#define SYS_CTRL_DISABLE_OC_WD_ADC (1<<10)
+#define SYS_CTRL_DISABLE_OC_WD_TURBO (1<<11)
+#define SYS_CTRL_DISABLE_OC_WD_OSC (1<<12)
+#define SYS_CTRL_DISABLE_OC_MPMC (1<<13)
+#define SYS_CTRL_DISABLE_CLK_OTHER(n) (((n)&0x3FFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_OTHER_MASK (0x3FFF<<0)
+#define SYS_CTRL_DISABLE_CLK_OTHER_SHIFT (0)
+
+//Pll_Ctrl
+#define SYS_CTRL_PLL_ENABLE (1<<0)
+#define SYS_CTRL_PLL_ENABLE_MASK (1<<0)
+#define SYS_CTRL_PLL_ENABLE_SHIFT (0)
+#define SYS_CTRL_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_PLL_LOCK_RESET (1<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_PLL_BYPASS (1<<8)
+#define SYS_CTRL_PLL_BYPASS_MASK (1<<8)
+#define SYS_CTRL_PLL_BYPASS_SHIFT (8)
+#define SYS_CTRL_PLL_BYPASS_PASS (0<<8)
+#define SYS_CTRL_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_PLL_XP_CFG(n) (((n)&4369)<<0)
+#define SYS_CTRL_PLL_XP_CFG_MASK (4369<<0)
+#define SYS_CTRL_PLL_XP_CFG_SHIFT (0)
+
+//Sel_Clock
+#define SYS_CTRL_SLOW_SEL_RF_OSCILLATOR (1<<0)
+#define SYS_CTRL_SLOW_SEL_RF_RF (0<<0)
+#define SYS_CTRL_SYS_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_SYS_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_TCU_13M_L_26M (1<<5)
+#define SYS_CTRL_TCU_13M_L_13M (0<<5)
+#define SYS_CTRL_PLL_DISABLE_LPS_DISABLE (1<<6)
+#define SYS_CTRL_PLL_DISABLE_LPS_ENABLE (0<<6)
+#define SYS_CTRL_DIGEN_H_ENABLE (1<<7)
+#define SYS_CTRL_DIGEN_H_DISABLE (0<<7)
+#define SYS_CTRL_RF_DETECTED_OK (1<<20)
+#define SYS_CTRL_RF_DETECTED_NO (0<<20)
+#define SYS_CTRL_RF_DETECT_BYPASS (1<<21)
+#define SYS_CTRL_RF_DETECT_RESET (1<<22)
+#define SYS_CTRL_RF_SELECTED_L (1<<23)
+#define SYS_CTRL_PLL_LOCKED (1<<24)
+#define SYS_CTRL_PLL_LOCKED_MASK (1<<24)
+#define SYS_CTRL_PLL_LOCKED_SHIFT (24)
+#define SYS_CTRL_PLL_LOCKED_LOCKED (1<<24)
+#define SYS_CTRL_PLL_LOCKED_NOT_LOCKED (0<<24)
+#define SYS_CTRL_PLL_BYPASS_LOCK (1<<27)
+#define SYS_CTRL_FAST_SELECTED_L (1<<31)
+#define SYS_CTRL_FAST_SELECTED_L_MASK (1<<31)
+#define SYS_CTRL_FAST_SELECTED_L_SHIFT (31)
+
+//Cfg_Clk_Sys
+#define SYS_CTRL_FREQ(n) (((n)&15)<<0)
+#define SYS_CTRL_FREQ_MASK (15<<0)
+#define SYS_CTRL_FREQ_SHIFT (0)
+#define SYS_CTRL_FREQ_312M (13<<0)
+#define SYS_CTRL_FREQ_250M (12<<0)
+#define SYS_CTRL_FREQ_208M (11<<0)
+#define SYS_CTRL_FREQ_178M (10<<0)
+#define SYS_CTRL_FREQ_156M (9<<0)
+#define SYS_CTRL_FREQ_139M (8<<0)
+#define SYS_CTRL_FREQ_125M (7<<0)
+#define SYS_CTRL_FREQ_113M (6<<0)
+#define SYS_CTRL_FREQ_104M (5<<0)
+#define SYS_CTRL_FREQ_89M (4<<0)
+#define SYS_CTRL_FREQ_78M (3<<0)
+#define SYS_CTRL_FREQ_52M (2<<0)
+#define SYS_CTRL_FREQ_39M (1<<0)
+#define SYS_CTRL_FREQ_26M (0<<0)
+#define SYS_CTRL_FORCE_DIV_UPDATE (1<<4)
+#define SYS_CTRL_REQ_DIV_UPDATE (1<<8)
+
+//Cfg_Clk_Mem_Bridge
+#define SYS_CTRL_MEM_FREQ(n) (((n)&15)<<0)
+#define SYS_CTRL_MEM_FREQ_MASK (15<<0)
+#define SYS_CTRL_MEM_FREQ_SHIFT (0)
+#define SYS_CTRL_MEM_FREQ_312M (13<<0)
+#define SYS_CTRL_MEM_FREQ_250M (12<<0)
+#define SYS_CTRL_MEM_FREQ_208M (11<<0)
+#define SYS_CTRL_MEM_FREQ_178M (10<<0)
+#define SYS_CTRL_MEM_FREQ_156M (9<<0)
+#define SYS_CTRL_MEM_FREQ_139M (8<<0)
+#define SYS_CTRL_MEM_FREQ_125M (7<<0)
+#define SYS_CTRL_MEM_FREQ_113M (6<<0)
+#define SYS_CTRL_MEM_FREQ_104M (5<<0)
+#define SYS_CTRL_MEM_FREQ_89M (4<<0)
+#define SYS_CTRL_MEM_FREQ_78M (3<<0)
+#define SYS_CTRL_MEM_FREQ_52M (2<<0)
+#define SYS_CTRL_MEM_FREQ_39M (1<<0)
+#define SYS_CTRL_MEM_FREQ_26M (0<<0)
+#define SYS_CTRL_DDR_MODE_EN_NORMAL_MODE (0<<4)
+#define SYS_CTRL_DDR_MODE_EN_DDR_MODE (1<<4)
+#define SYS_CTRL_DDR_FAST_CLK_POL_INVERT (1<<5)
+#define SYS_CTRL_DDR_FAST_CLK_POL_NORMAL (0<<5)
+#define SYS_CTRL_DDR_DQSL_O(n) (((n)&31)<<6)
+#define SYS_CTRL_DDR_DQSU_O(n) (((n)&31)<<11)
+#define SYS_CTRL_DDR_DQS_OEN(n) (((n)&31)<<16)
+#define SYS_CTRL_DDR_DQSL_I(n) (((n)&31)<<21)
+#define SYS_CTRL_DDR_DQSU_I(n) (((n)&31)<<26)
+#define SYS_CTRL_MEM_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_Out
+#define SYS_CTRL_CLKOUT_DIVIDER(n) (((n)&31)<<0)
+#define SYS_CTRL_CLKOUT_SEL_OSC (0<<8)
+#define SYS_CTRL_CLKOUT_SEL_RF (1<<8)
+#define SYS_CTRL_CLKOUT_SEL_DIVIDER (2<<8)
+
+//Cfg_Clk_Host_Uart
+#define SYS_CTRL_HOST_UART_DIVIDER(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_HOST_UART_DIVIDER_MASK (0x3FF<<0)
+#define SYS_CTRL_HOST_UART_DIVIDER_SHIFT (0)
+#define SYS_CTRL_HOST_UART_SEL_PLL_SLOW (0<<12)
+#define SYS_CTRL_HOST_UART_SEL_PLL_PLL (1<<12)
+
+//Cfg_Clk_Auxclk
+#define SYS_CTRL_AUXCLK_EN_DISABLE (0<<0)
+#define SYS_CTRL_AUXCLK_EN_ENABLE (1<<0)
+
+//Cfg_AHB
+#define SYS_CTRL_SYS_NEW_ARBITRATION_ENABLE (1<<0)
+#define SYS_CTRL_SYS_NEW_ARBITRATION_DISABLE (0<<0)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA_ENABLE (1<<1)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA_DISABLE (0<<1)
+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_ENABLE (1<<2)
+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_DISABLE (0<<2)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_ENABLE (1<<3)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_DISABLE (0<<3)
+#define SYS_CTRL_ENABLE_SYS_MID_IFC_ENABLE (1<<4)
+#define SYS_CTRL_ENABLE_SYS_MID_IFC_DISABLE (0<<4)
+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_ENABLE (1<<5)
+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_DISABLE (0<<5)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_WD_ENABLE (1<<6)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_WD_DISABLE (0<<6)
+#define SYS_CTRL_BB_NEW_ARBITRATION_ENABLE (1<<16)
+#define SYS_CTRL_BB_NEW_ARBITRATION_DISABLE (0<<16)
+#define SYS_CTRL_ENABLE_BB_MID_IFC_ENABLE (1<<17)
+#define SYS_CTRL_ENABLE_BB_MID_IFC_DISABLE (0<<17)
+#define SYS_CTRL_ENABLE_BB_MID_BCPU_ENABLE (1<<18)
+#define SYS_CTRL_ENABLE_BB_MID_BCPU_DISABLE (0<<18)
+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_ENABLE (1<<19)
+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_DISABLE (0<<19)
+#define SYS_CTRL_SYS_ENABLE(n) (((n)&0x3F)<<1)
+#define SYS_CTRL_SYS_ENABLE_MASK (0x3F<<1)
+#define SYS_CTRL_SYS_ENABLE_SHIFT (1)
+#define SYS_CTRL_BB_ENABLE(n) (((n)&7)<<17)
+#define SYS_CTRL_BB_ENABLE_MASK (7<<17)
+#define SYS_CTRL_BB_ENABLE_SHIFT (17)
+
+//Ctrl_AHB
+#define SYS_CTRL_SPLIT_SYS_MID_DMA_NORMAL (1<<0)
+#define SYS_CTRL_SPLIT_SYS_MID_DMA_FORCE (0<<0)
+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_NORMAL (1<<1)
+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_FORCE (0<<1)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_NORMAL (1<<2)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_FORCE (0<<2)
+#define SYS_CTRL_SPLIT_SYS_MID_IFC_NORMAL (1<<3)
+#define SYS_CTRL_SPLIT_SYS_MID_IFC_FORCE (0<<3)
+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_NORMAL (1<<4)
+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_FORCE (0<<4)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_WD_NORMAL (1<<5)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_WD_FORCE (0<<5)
+#define SYS_CTRL_SPLIT_BB_MID_IFC_NORMAL (1<<16)
+#define SYS_CTRL_SPLIT_BB_MID_IFC_FORCE (0<<16)
+#define SYS_CTRL_SPLIT_BB_MID_BCPU_NORMAL (1<<17)
+#define SYS_CTRL_SPLIT_BB_MID_BCPU_FORCE (0<<17)
+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_NORMAL (1<<18)
+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_FORCE (0<<18)
+#define SYS_CTRL_SYS_FORCE_HSPLIT(n) (((n)&0x3F)<<0)
+#define SYS_CTRL_SYS_FORCE_HSPLIT_MASK (0x3F<<0)
+#define SYS_CTRL_SYS_FORCE_HSPLIT_SHIFT (0)
+#define SYS_CTRL_BB_FORCE_HSPLIT(n) (((n)&7)<<16)
+#define SYS_CTRL_BB_FORCE_HSPLIT_MASK (7<<16)
+#define SYS_CTRL_BB_FORCE_HSPLIT_SHIFT (16)
+
+//XCpu_Dbg_BKP
+#define SYS_CTRL_BKPT_EN (1<<0)
+#define SYS_CTRL_BKPT_MODE(n) (((n)&3)<<4)
+#define SYS_CTRL_BKPT_MODE_I (0<<4)
+#define SYS_CTRL_BKPT_MODE_R (1<<4)
+#define SYS_CTRL_BKPT_MODE_W (2<<4)
+#define SYS_CTRL_BKPT_MODE_RW (3<<4)
+#define SYS_CTRL_STALLED (1<<8)
+
+//XCpu_Dbg_Addr
+#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)
+
+//BCpu_Dbg_BKP
+//#define SYS_CTRL_BKPT_EN (1<<0)
+//#define SYS_CTRL_BKPT_MODE(n) (((n)&3)<<4)
+//#define SYS_CTRL_BKPT_MODE_I (0<<4)
+//#define SYS_CTRL_BKPT_MODE_R (1<<4)
+//#define SYS_CTRL_BKPT_MODE_W (2<<4)
+//#define SYS_CTRL_BKPT_MODE_RW (3<<4)
+//#define SYS_CTRL_STALLED (1<<8)
+
+//BCpu_Dbg_Addr
+//#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)
+
+//Cfg_Cpus_Cache_Ram_Disable
+#define SYS_CTRL_XCPU_USE_MODE (1<<0)
+#define SYS_CTRL_XCPU_CLK_OFF_MODE (1<<1)
+#define SYS_CTRL_BCPU_USE_MODE (1<<16)
+#define SYS_CTRL_BCPU_CLK_OFF_MODE (1<<17)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<0)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_MASK (3<<0)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_SHIFT (0)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<16)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_MASK (3<<16)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_SHIFT (16)
+
+//Reset_Cause
+#define SYS_CTRL_WATCHDOG_RESET_HAPPENED (1<<0)
+#define SYS_CTRL_WATCHDOG_RESET_NO (0<<0)
+#define SYS_CTRL_APSOFT_RESET_HAPPENED (1<<1)
+#define SYS_CTRL_APSOFT_RESET_NO (0<<1)
+#define SYS_CTRL_GLOBALSOFT_RESET_HAPPENED (1<<4)
+#define SYS_CTRL_GLOBALSOFT_RESET_NO (0<<4)
+#define SYS_CTRL_HOSTDEBUG_RESET_HAPPENED (1<<5)
+#define SYS_CTRL_HOSTDEBUG_RESET_NO (0<<5)
+#define SYS_CTRL_ALARMCAUSE_HAPPENED (1<<6)
+#define SYS_CTRL_ALARMCAUSE_NO (0<<6)
+#define SYS_CTRL_MEMCHECKDONE_MASK (1<<7)
+#define SYS_CTRL_MEMCHECKDONE_SHIFT (7)
+#define SYS_CTRL_MEMCHECKDONE_DONE (1<<7)
+#define SYS_CTRL_MEMCHECKDONE_RUNNING (0<<7)
+#define SYS_CTRL_BOOT_MODE(n) (((n)&0xFFFF)<<8)
+#define SYS_CTRL_BOOT_MODE_MASK (0xFFFF<<8)
+#define SYS_CTRL_BOOT_MODE_SHIFT (8)
+#define SYS_CTRL_SW_BOOT_MODE(n) (((n)&0x7F)<<24)
+#define SYS_CTRL_SW_BOOT_MODE_MASK (0x7F<<24)
+#define SYS_CTRL_SW_BOOT_MODE_SHIFT (24)
+#define SYS_CTRL_FONCTIONAL_TEST_MODE (1<<31)
+
+//WakeUp
+#define SYS_CTRL_FORCE_WAKEUP (1<<0)
+
+//AP_Ctrl
+#define SYS_CTRL_AP_INT_STATUS (1<<0)
+#define SYS_CTRL_AP_INT_MASK (1<<16)
+#define SYS_CTRL_AP_DEEPSLEEP_EN (1<<24)
+
+//Ignore_Charger
+#define SYS_CTRL_IGNORE_CHARGER (1<<0)
+
+//Clk_SYS2_Mode
+#define SYS_CTRL_MODE_SYS_MPMC_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_SYS_MPMC_MANUAL (1<<0)
+#define SYS_CTRL_MODE_SYS_MPMCREG_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_SYS_MPMCREG_MANUAL (1<<1)
+#define SYS_CTRL_MODE_CLK_SYS2(n) (((n)&3)<<0)
+#define SYS_CTRL_MODE_CLK_SYS2_MASK (3<<0)
+#define SYS_CTRL_MODE_CLK_SYS2_SHIFT (0)
+
+//Clk_SYS2_Enable
+#define SYS_CTRL_ENABLE_SYS_MPMC (1<<0)
+#define SYS_CTRL_ENABLE_SYS_MPMCREG (1<<1)
+#define SYS_CTRL_ENABLE_SYS_DP_BB (1<<2)
+#define SYS_CTRL_ENABLE_SYS_DP_WD (1<<3)
+#define SYS_CTRL_ENABLE_SYS_DP_AP (1<<4)
+#define SYS_CTRL_ENABLE_CLK_SYS2(n) (((n)&31)<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS2_MASK (31<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS2_SHIFT (0)
+
+//Clk_SYS2_Disable
+#define SYS_CTRL_DISABLE_SYS_MPMC (1<<0)
+#define SYS_CTRL_DISABLE_SYS_MPMCREG (1<<1)
+#define SYS_CTRL_DISABLE_SYS_DP_BB (1<<2)
+#define SYS_CTRL_DISABLE_SYS_DP_WD (1<<3)
+#define SYS_CTRL_DISABLE_SYS_DP_AP (1<<4)
+#define SYS_CTRL_DISABLE_CLK_SYS2(n) (((n)&31)<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS2_MASK (31<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS2_SHIFT (0)
+
+//WD_Pll_Ctrl
+#define SYS_CTRL_WD_PLL_ENABLE (1<<0)
+#define SYS_CTRL_WD_PLL_ENABLE_MASK (1<<0)
+#define SYS_CTRL_WD_PLL_ENABLE_SHIFT (0)
+#define SYS_CTRL_WD_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_WD_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_WD_PLL_LOCK_RESET (1<<4)
+#define SYS_CTRL_WD_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_WD_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_WD_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_WD_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_WD_PLL_BYPASS (1<<8)
+#define SYS_CTRL_WD_PLL_BYPASS_MASK (1<<8)
+#define SYS_CTRL_WD_PLL_BYPASS_SHIFT (8)
+#define SYS_CTRL_WD_PLL_BYPASS_PASS (0<<8)
+#define SYS_CTRL_WD_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_PLL_WD_CFG(n) (((n)&4369)<<0)
+#define SYS_CTRL_PLL_WD_CFG_MASK (4369<<0)
+#define SYS_CTRL_PLL_WD_CFG_SHIFT (0)
+
+//WD_Sel_Clock
+#define SYS_CTRL_WD_CLK_ADC_POL_INVERT (1<<0)
+#define SYS_CTRL_WD_CLK_ADC_POL_NORMAL (0<<0)
+#define SYS_CTRL_WD_SYS_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_WD_SYS_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_WD_PLL_BYPASS_LOCK (1<<8)
+#define SYS_CTRL_WD_PLL_LOCKED (1<<20)
+#define SYS_CTRL_WD_PLL_LOCKED_MASK (1<<20)
+#define SYS_CTRL_WD_PLL_LOCKED_SHIFT (20)
+#define SYS_CTRL_WD_PLL_LOCKED_LOCKED (1<<20)
+#define SYS_CTRL_WD_PLL_LOCKED_NOT_LOCKED (0<<20)
+#define SYS_CTRL_WD_FAST_SELECTED_L (1<<24)
+#define SYS_CTRL_WD_FAST_SELECTED_L_MASK (1<<24)
+#define SYS_CTRL_WD_FAST_SELECTED_L_SHIFT (24)
+
+//WD_Rst_Set
+#define SYS_CTRL_SET_WD_RST_WCPU (1<<0)
+#define SYS_CTRL_SET_WD_RST_IRQ (1<<1)
+#define SYS_CTRL_SET_WD_RST_DP (1<<2)
+#define SYS_CTRL_SET_WD_RST_MODEM (1<<3)
+#define SYS_CTRL_SET_WD_RST_A2A (1<<4)
+#define SYS_CTRL_SET_WD_RST_IFC (1<<5)
+#define SYS_CTRL_SET_WD_RST_SDMA (1<<6)
+#define SYS_CTRL_SET_WD_RST_SLPC (1<<7)
+#define SYS_CTRL_SET_WD_RST_SLPT (1<<8)
+#define SYS_CTRL_SET_WD_RST_SPI1 (1<<9)
+#define SYS_CTRL_SET_WD_RST_SPI2 (1<<10)
+#define SYS_CTRL_SET_WD_RST_RFIF (1<<11)
+#define SYS_CTRL_SET_WD_RST_COMREGS (1<<12)
+#define SYS_CTRL_SET_WD_RST_TIMER (1<<13)
+#define SYS_CTRL_SET_WD_RST_MPMC (1<<14)
+#define SYS_CTRL_SET_WD_RST_FULL (1<<31)
+#define SYS_CTRL_SET_WD_RST(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_SET_WD_RST_MASK (0x7FFF<<0)
+#define SYS_CTRL_SET_WD_RST_SHIFT (0)
+
+//WD_Rst_Clr
+#define SYS_CTRL_CLR_WD_RST_WCPU (1<<0)
+#define SYS_CTRL_CLR_WD_RST_IRQ (1<<1)
+#define SYS_CTRL_CLR_WD_RST_DP (1<<2)
+#define SYS_CTRL_CLR_WD_RST_MODEM (1<<3)
+#define SYS_CTRL_CLR_WD_RST_A2A (1<<4)
+#define SYS_CTRL_CLR_WD_RST_IFC (1<<5)
+#define SYS_CTRL_CLR_WD_RST_SDMA (1<<6)
+#define SYS_CTRL_CLR_WD_RST_SLPC (1<<7)
+#define SYS_CTRL_CLR_WD_RST_SLPT (1<<8)
+#define SYS_CTRL_CLR_WD_RST_SPI1 (1<<9)
+#define SYS_CTRL_CLR_WD_RST_SPI2 (1<<10)
+#define SYS_CTRL_CLR_WD_RST_RFIF (1<<11)
+#define SYS_CTRL_CLR_WD_RST_COMREGS (1<<12)
+#define SYS_CTRL_CLR_WD_RST_TIMER (1<<13)
+#define SYS_CTRL_CLR_WD_RST_MPMC (1<<14)
+#define SYS_CTRL_CLR_WD_RST_FULL (1<<31)
+#define SYS_CTRL_CLR_WD_RST(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_CLR_WD_RST_MASK (0x7FFF<<0)
+#define SYS_CTRL_CLR_WD_RST_SHIFT (0)
+
+//AP_Rst_Set
+#define SYS_CTRL_SET_AP_RST_0 (1<<0)
+#define SYS_CTRL_SET_AP_RST_1 (1<<1)
+#define SYS_CTRL_SET_AP_RST_2 (1<<2)
+#define SYS_CTRL_SET_AP_RST_3 (1<<3)
+#define SYS_CTRL_SET_AP_RST_4 (1<<4)
+#define SYS_CTRL_SET_AP_RST(n) (((n)&31)<<0)
+#define SYS_CTRL_SET_AP_RST_MASK (31<<0)
+#define SYS_CTRL_SET_AP_RST_SHIFT (0)
+
+//AP_Rst_Clr
+#define SYS_CTRL_CLR_AP_RST_0 (1<<0)
+#define SYS_CTRL_CLR_AP_RST_1 (1<<1)
+#define SYS_CTRL_CLR_AP_RST_2 (1<<2)
+#define SYS_CTRL_CLR_AP_RST_3 (1<<3)
+#define SYS_CTRL_CLR_AP_RST_4 (1<<4)
+#define SYS_CTRL_CLR_AP_RST(n) (((n)&31)<<0)
+#define SYS_CTRL_CLR_AP_RST_MASK (31<<0)
+#define SYS_CTRL_CLR_AP_RST_SHIFT (0)
+
+//Clk_WD_Mode
+#define SYS_CTRL_MODE_WD_WCPU (1<<0)
+#define SYS_CTRL_MODE_WD_AMBA_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_WD_AMBA_MANUAL (1<<1)
+#define SYS_CTRL_MODE_WD_PCLK_CONF_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_WD_PCLK_CONF_MANUAL (1<<2)
+#define SYS_CTRL_MODE_WD_PCLK_DATA_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_WD_PCLK_DATA_MANUAL (1<<3)
+#define SYS_CTRL_MODE_WD_A2A_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_WD_A2A_MANUAL (1<<4)
+#define SYS_CTRL_MODE_WD_IFC_CH_SPI_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_WD_IFC_CH_SPI_MANUAL (1<<5)
+#define SYS_CTRL_MODE_WD_MPMC_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_WD_MPMC_MANUAL (1<<6)
+#define SYS_CTRL_MODE_WDD_OSC_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_WDD_OSC_MANUAL (1<<7)
+#define SYS_CTRL_MODE_CLK_WD(n) (((n)&0x7F)<<1)
+#define SYS_CTRL_MODE_CLK_WD_MASK (0x7F<<1)
+#define SYS_CTRL_MODE_CLK_WD_SHIFT (1)
+
+//Clk_WD_Enable
+#define SYS_CTRL_ENABLE_WD_WCPU (1<<0)
+#define SYS_CTRL_ENABLE_WD_AMBA (1<<1)
+#define SYS_CTRL_ENABLE_WD_PCLK_CONF (1<<2)
+#define SYS_CTRL_ENABLE_WD_PCLK_DATA (1<<3)
+#define SYS_CTRL_ENABLE_WD_A2A (1<<4)
+#define SYS_CTRL_ENABLE_WD_IFC_CH_SPI (1<<5)
+#define SYS_CTRL_ENABLE_WD_MPMC (1<<6)
+#define SYS_CTRL_ENABLE_WDD_OSC (1<<7)
+#define SYS_CTRL_ENABLE_WD_IRQ (1<<8)
+#define SYS_CTRL_ENABLE_WD_AXI (1<<9)
+#define SYS_CTRL_ENABLE_WD_DP (1<<10)
+#define SYS_CTRL_ENABLE_WD_MODEM (1<<11)
+#define SYS_CTRL_ENABLE_WD_COM_REGS (1<<12)
+#define SYS_CTRL_ENABLE_WD_TIMER (1<<13)
+#define SYS_CTRL_ENABLE_WD_SDMA (1<<14)
+#define SYS_CTRL_ENABLE_WD_SLPC (1<<15)
+#define SYS_CTRL_ENABLE_WD_SLPT (1<<16)
+#define SYS_CTRL_ENABLE_WD_SPI1 (1<<17)
+#define SYS_CTRL_ENABLE_WD_SPI2 (1<<18)
+#define SYS_CTRL_ENABLE_WD_RFIF (1<<19)
+#define SYS_CTRL_ENABLE_CLK_WD(n) (((n)&0xFFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_WD_MASK (0xFFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_WD_SHIFT (0)
+
+//Clk_WD_Disable
+#define SYS_CTRL_DISABLE_WD_WCPU (1<<0)
+#define SYS_CTRL_DISABLE_WD_AMBA (1<<1)
+#define SYS_CTRL_DISABLE_WD_PCLK_CONF (1<<2)
+#define SYS_CTRL_DISABLE_WD_PCLK_DATA (1<<3)
+#define SYS_CTRL_DISABLE_WD_A2A (1<<4)
+#define SYS_CTRL_DISABLE_WD_IFC_CH_SPI (1<<5)
+#define SYS_CTRL_DISABLE_WD_MPMC (1<<6)
+#define SYS_CTRL_DISABLE_WDD_OSC (1<<7)
+#define SYS_CTRL_DISABLE_WD_IRQ (1<<8)
+#define SYS_CTRL_DISABLE_WD_AXI (1<<9)
+#define SYS_CTRL_DISABLE_WD_DP (1<<10)
+#define SYS_CTRL_DISABLE_WD_MODEM (1<<11)
+#define SYS_CTRL_DISABLE_WD_COM_REGS (1<<12)
+#define SYS_CTRL_DISABLE_WD_TIMER (1<<13)
+#define SYS_CTRL_DISABLE_WD_SDMA (1<<14)
+#define SYS_CTRL_DISABLE_WD_SLPC (1<<15)
+#define SYS_CTRL_DISABLE_WD_SLPT (1<<16)
+#define SYS_CTRL_DISABLE_WD_SPI1 (1<<17)
+#define SYS_CTRL_DISABLE_WD_SPI2 (1<<18)
+#define SYS_CTRL_DISABLE_WD_RFIF (1<<19)
+#define SYS_CTRL_DISABLE_CLK_WD(n) (((n)&0xFFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_WD_MASK (0xFFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_WD_SHIFT (0)
+
+//Cfg_Clk_MPMC
+#define SYS_CTRL_MPMC_FREQ(n) (((n)&15)<<0)
+#define SYS_CTRL_MPMC_FREQ_MASK (15<<0)
+#define SYS_CTRL_MPMC_FREQ_SHIFT (0)
+#define SYS_CTRL_MPMC_FREQ_312M (13<<0)
+#define SYS_CTRL_MPMC_FREQ_250M (12<<0)
+#define SYS_CTRL_MPMC_FREQ_208M (11<<0)
+#define SYS_CTRL_MPMC_FREQ_178M (10<<0)
+#define SYS_CTRL_MPMC_FREQ_156M (9<<0)
+#define SYS_CTRL_MPMC_FREQ_139M (8<<0)
+#define SYS_CTRL_MPMC_FREQ_125M (7<<0)
+#define SYS_CTRL_MPMC_FREQ_113M (6<<0)
+#define SYS_CTRL_MPMC_FREQ_104M (5<<0)
+#define SYS_CTRL_MPMC_FREQ_89M (4<<0)
+#define SYS_CTRL_MPMC_FREQ_78M (3<<0)
+#define SYS_CTRL_MPMC_FREQ_52M (2<<0)
+#define SYS_CTRL_MPMC_FREQ_39M (1<<0)
+#define SYS_CTRL_MPMC_FREQ_26M (0<<0)
+#define SYS_CTRL_CLK_MPMC_DELAY(n) (((n)&31)<<8)
+#define SYS_CTRL_CLK_MPMC_DELAY_POL (1<<13)
+#define SYS_CTRL_CLK_MPMC_FEEDBACK(n) (((n)&31)<<14)
+#define SYS_CTRL_CLK_MPMC_FEEDBACK_POL (1<<19)
+#define SYS_CTRL_MPMC_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_MPMC_DQS
+#define SYS_CTRL_MPMC_DQSL_O(n) (((n)&31)<<0)
+#define SYS_CTRL_MPMC_DQSU_O(n) (((n)&31)<<6)
+#define SYS_CTRL_MPMC_DQS_OEN(n) (((n)&31)<<12)
+#define SYS_CTRL_MPMC_DQSL_I(n) (((n)&31)<<18)
+#define SYS_CTRL_MPMC_DQSU_I(n) (((n)&31)<<24)
+
+//Cfg_Reserve
+#define SYS_CTRL_RESERVE(n) (((n)&0x3FFF)<<0)
+#define SYS_CTRL_AUIFC_CH0_IRQ_MASK (1<<14)
+#define SYS_CTRL_AUIFC_CH1_IRQ_MASK (1<<15)
+#define SYS_CTRL_RESERVE2(n) (((n)&0xFFFF)<<16)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8850e.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8850e.h new file mode 100644 index 0000000000..f0928a1d6e --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8850e.h @@ -0,0 +1,1363 @@ +#ifndef _REG_MD_SYSCTRL_H_ +#define _REG_MD_SYSCTRL_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= + +// ============================================================================ +// CPU_ID_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// CPU IDs + XCPU = 0x00000000, + BCPU = 0x00000001, + WCPU = 0x00000002 +} CPU_ID_T; + +#define NB_MODEM_CPU (3) + +// ============================================================================ +// SYS_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// System side System clocks + SYS_XCPU = 0x00000000, + SYS_XCPU_INT = 0x00000001, + SYS_PCLK_CONF = 0x00000002, + SYS_PCLK_DATA = 0x00000003, + SYS_AMBA = 0x00000004, + SYS_DMA = 0x00000005, + SYS_EBC = 0x00000006, + SYS_IFC_CH0 = 0x00000007, + SYS_IFC_CH1 = 0x00000008, + SYS_IFC_CH2 = 0x00000009, + SYS_IFC_CH3 = 0x0000000A, + SYS_IFC_DBG = 0x0000000B, + SYS_A2A = 0x0000000C, + SYS_AXI2AHB = 0x0000000D, + SYS_AHB2AXI = 0x0000000E, + SYS_EXT_AHB = 0x0000000F, + SYS_DEBUG_UART = 0x00000010, + SYS_DBGHST = 0x00000011, + SYS_A2A_WD = 0x00000012, +/// System side divided clock (either divided by module or by sys_ctrl) + SYSD_SCI1 = 0x00000013, + SYSD_SCI2 = 0x00000014, + SYSD_SCI3 = 0x00000015, + SYSD_RF_SPI = 0x00000016, + SYSD_OSC = 0x00000017, +/// the following don't have an auto enable + SYS_GPIO = 0x00000018, + SYS_IRQ = 0x00000019, + SYS_TCU = 0x0000001A, + SYS_TIMER = 0x0000001B, + SYS_COM_REGS = 0x0000001C, +/// the following are sharing their enable + SYS_SCI1 = 0x0000001D, + SYS_SCI2 = 0x0000001E, + SYS_SCI3 = 0x0000001F, +/// keep last + SYS_NOGATE = 0x00000020 +} SYS_CLKS_T; + +#define NB_SYS_CLK_XCPU (2) +#define NB_SYS_CLK_AEN (24) +#define NB_SYS_CLK_EN (29) +#define NB_SYS_CLK (33) + +// ============================================================================ +// SYS2_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// WCDMA Baseband side System clocks + SYS_MPMC = 0x00000000, + SYS_MPMCREG = 0x00000001, +/// the following don't have an auto enable + SYS_DP_BB = 0x00000002, + SYS_DP_WD = 0x00000003, + SYS_DP_AP = 0x00000004 +} SYS2_CLKS_T; + +#define NB_SYS2_CLK_AEN (2) +#define NB_SYS2_CLK_EN (5) +#define NB_SYS2_CLK (5) + +// ============================================================================ +// PER_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// System side divided clock (either divided by module or by sys_ctrl) + PERD_SPI1 = 0x00000000, +/// System side divided clock (either divided by module or by sys_ctrl) + PERD_SPI2 = 0x00000001, + PER_SPY = 0x00000002, + PER_TEST = 0x00000003 +} PER_CLKS_T; + +#define NB_PER_CLK_AEN (2) +#define NB_PER_CLK_EN (4) +#define NB_PER_CLK (4) + +// ============================================================================ +// BB_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// Baseband side System clocks + BB_BCPU = 0x00000000, + BB_BCPU_INT = 0x00000001, + BB_AMBA = 0x00000002, + BB_PCLK_CONF = 0x00000003, + BB_PCLK_DATA = 0x00000004, + BB_EXCOR = 0x00000005, + BB_IFC_CH2 = 0x00000006, + BB_IFC_CH3 = 0x00000007, + BB_SRAM = 0x00000008, + BB_A2A = 0x00000009, + BB_ITLV = 0x0000000A, + BB_VITERBI = 0x0000000B, + BB_CIPHER = 0x0000000C, + BB_RF_IF = 0x0000000D, + BB_COPRO = 0x0000000E, + BB_CP2_REG = 0x0000000F, + BB_XCOR = 0x00000010, + BB_EVITAC = 0x00000011, + BB_ROM = 0x00000012, + BB_MPMC = 0x00000013, +/// the following don't have an auto enable + BB_IRQ = 0x00000014, + BB_COM_REGS = 0x00000015, + BB_CORDIC = 0x00000016, + BB_DP = 0x00000017 +} BB_CLKS_T; + +#define NB_BB_CLK_AEN (20) +#define NB_BB_CLK_EN (24) +#define NB_BB_CLK (24) + +// ============================================================================ +// WD_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// WCDMA Baseband side System clocks + WD_WCPU = 0x00000000, + WD_AMBA = 0x00000001, + WD_PCLK_CONF = 0x00000002, + WD_PCLK_DATA = 0x00000003, + WD_A2A = 0x00000004, + WD_IFC_CH_SPI = 0x00000005, + WD_MPMC = 0x00000006, + WDD_OSC = 0x00000007, +/// the following don't have an auto enable + WD_IRQ = 0x00000008, + WD_AXI = 0x00000009, + WD_DP = 0x0000000A, + WD_MODEM = 0x0000000B, + WD_COM_REGS = 0x0000000C, + WD_TIMER = 0x0000000D, + WD_SDMA = 0x0000000E, + WD_SLPC = 0x0000000F, + WD_SLPT = 0x00000010, + WD_SPI1 = 0x00000011, + WD_SPI2 = 0x00000012, + WD_RFIF = 0x00000013 +} WD_CLKS_T; + +#define NB_WD_CLK_AEN (8) +#define NB_WD_CLK_EN (20) +#define NB_WD_CLK (20) +/// Other clocks +/// clocks with auto enble +/// the debug host clock auto enable is not used in host mode, only in uart mode +#define OC_HOST_UART (0) + +// ============================================================================ +// OTHER_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ + OC_DEBUG_UART = 0x00000000, + OC_RF_RX = 0x00000001, + OC_RF_TX = 0x00000002, + OC_MEM_BRIDGE = 0x00000003, +/// the following don't have an auto enable + OC_LPS = 0x00000004, + OC_GPIO = 0x00000005, + OC_CLK_OUT = 0x00000006, + OC_MEM_CLK_OUT = 0x00000007, + OC_TCU = 0x00000008, + OC_WD_CHIP = 0x00000009, + OC_WD_ADC = 0x0000000A, + OC_WD_TURBO = 0x0000000B, + OC_WD_OSC = 0x0000000C, + OC_MPMC = 0x0000000D +} OTHER_CLKS_T; + +#define NB_OTHER_CLK_AEN (4) +#define NB_OTHER_CLK_EN (14) +#define NB_OTHER_CLK (14) + +// ============================================================================ +// RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// System side resets + RST_XCPU = 0x00000000, + RST_SYS_IRQ = 0x00000001, + RST_SYS_A2A = 0x00000002, + RST_SYS_AHB2AXI = 0x00000003, + RST_SYS_AXI2AHB = 0x00000004, + RST_DMA = 0x00000005, + RST_TIMER = 0x00000006, + RST_TCU = 0x00000007, + RST_GPIO = 0x00000008, + RST_CFG = 0x00000009, + RST_SPI1 = 0x0000000A, + RST_SPI2 = 0x0000000B, + RST_RF_SPI = 0x0000000C, + RST_SCI1 = 0x0000000D, + RST_SCI2 = 0x0000000E, + RST_SCI3 = 0x0000000F, + RST_SPY = 0x00000010, + RST_MEM_BRIDGE = 0x00000011, + RST_EXT_AHB = 0x00000012, + RST_DP_BB = 0x00000013, + RST_DP_AP = 0x00000014, + RST_COMREGS = 0x00000015, + RST_COMREGS_AP = 0x00000016, + RST_AP_CLKEN = 0x00000017, + RST_AP_RST = 0x00000018, + RST_MEM_CHK = 0x00000019, + RST_MPMC = 0x0000001A, + RST_SYS_A2A_WD = 0x0000001B, + RST_COMREGS_WD = 0x0000001C, + RST_BCPU = 0x0000001D, + RST_BB_IRQ = 0x0000001E, + RST_BB_A2A = 0x0000001F, + RST_BB_IFC = 0x00000020, + RST_BB_SRAM = 0x00000021, + RST_ITLV = 0x00000022, + RST_VITERBI = 0x00000023, + RST_CIPHER = 0x00000024, + RST_XCOR = 0x00000025, + RST_COPRO = 0x00000026, + RST_RF_IF = 0x00000027, + RST_EXCOR = 0x00000028, + RST_EVITAC = 0x00000029, + RST_CORDIC = 0x0000002A, + RST_TCU_BB = 0x0000002B, + RST_BB_DP = 0x0000002C, + RST_BB_ROM = 0x0000002D, + RST_MPMC_BB = 0x0000002E, + RST_BB_FULL = 0x0000002F, + RST_SYS_FULL = 0x00000030 +} RESETS_T; + +#define NB_SRST (29) +/// Baseband side resets +#define BOUND_BRST_FIRST (29) +#define BOUND_BRST_AFTER (47) +/// The following reset does not have register +#define NR_RST_REG (48) +#define NB_RST (49) +#define NB_BRST (BOUND_BRST_AFTER-BOUND_BRST_FIRST) + +// ============================================================================ +// RESET_OTHERS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// Reset Other : resync on corresponding clock other + RSTO_DBG_HOST = 0x00000000, + RSTO_RF_RX = 0x00000001, + RSTO_RF_TX = 0x00000002, + RSTO_MEM_BRIDGE = 0x00000003, + RSTO_LPS = 0x00000004, + RSTO_GPIO = 0x00000005, + RSTO_WDTIMER = 0x00000006, + RSTO_TCU = 0x00000007, + RSTO_MPMC = 0x00000008 +} RESET_OTHERS_T; + +#define BOUND_RSTO_RF_FIRST (1) +#define BOUND_RSTO_RF_AFTER (3) +#define NB_RSTO (9) + +// ============================================================================ +// WD_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// WD side resets + WD_RST_WCPU = 0x00000000, + WD_RST_IRQ = 0x00000001, + WD_RST_DP = 0x00000002, + WD_RST_MODEM = 0x00000003, + WD_RST_A2A = 0x00000004, + WD_RST_IFC = 0x00000005, + WD_RST_SDMA = 0x00000006, + WD_RST_SLPC = 0x00000007, + WD_RST_SLPT = 0x00000008, + WD_RST_SPI1 = 0x00000009, + WD_RST_SPI2 = 0x0000000A, + WD_RST_RFIF = 0x0000000B, + WD_RST_COMREGS = 0x0000000C, + WD_RST_TIMER = 0x0000000D, + WD_RST_MPMC = 0x0000000E, + WD_RST_FULL = 0x0000000F +} WD_RESETS_T; + +#define NB_WD_RST_BOUND (15) +#define NB_WD_RST (16) + +// ============================================================================ +// AP_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP side resets + AP_RST_0 = 0x00000000, + AP_RST_1 = 0x00000001, + AP_RST_2 = 0x00000002, + AP_RST_3 = 0x00000003, + AP_RST_4 = 0x00000004 +} AP_RESETS_T; + +#define NB_AP_RST_BOUND (5) +#define NB_AP_RST (5) +/// For REG_DBG protect lock/unlock value +#define SYS_CTRL_PROTECT_LOCK (0XA50000) +#define SYS_CTRL_PROTECT_UNLOCK (0XA50001) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// SYS_CTRL_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + /// <strong>This register is used to Lock and Unlock the protected registers.</strong> + REG32 REG_DBG; //0x00000000 + /// This register is protected. + REG32 Sys_Rst_Set; //0x00000004 + REG32 Sys_Rst_Clr; //0x00000008 + /// This register is protected. + REG32 BB_Rst_Set; //0x0000000C + REG32 BB_Rst_Clr; //0x00000010 + REG32 Clk_Sys_Mode; //0x00000014 + REG32 Clk_Sys_Enable; //0x00000018 + /// This register is protected. + REG32 Clk_Sys_Disable; //0x0000001C + REG32 Clk_Per_Mode; //0x00000020 + REG32 Clk_Per_Enable; //0x00000024 + /// This register is protected. + REG32 Clk_Per_Disable; //0x00000028 + REG32 Clk_BB_Mode; //0x0000002C + REG32 Clk_BB_Enable; //0x00000030 + /// This register is protected. + REG32 Clk_BB_Disable; //0x00000034 + REG32 Clk_Other_Mode; //0x00000038 + REG32 Clk_Other_Enable; //0x0000003C + /// This register is protected. + REG32 Clk_Other_Disable; //0x00000040 + /// Register protected by Write_Unlocked_H. + REG32 Pll_Ctrl; //0x00000044 + /// This register is protected. + REG32 Sel_Clock; //0x00000048 + REG32 Cfg_Clk_Sys; //0x0000004C + REG32 Cfg_Clk_Mem_Bridge; //0x00000050 + /// This register is protected. + REG32 Cfg_Clk_Out; //0x00000054 + REG32 Cfg_Clk_Host_Uart; //0x00000058 + REG32 Cfg_Clk_Auxclk; //0x0000005C + /// This register is protected. + REG32 Cfg_AHB; //0x00000060 + /// This register is protected. Used to unsplit masters manualy. + REG32 Ctrl_AHB; //0x00000064 + REG32 XCpu_Dbg_BKP; //0x00000068 + REG32 XCpu_Dbg_Addr; //0x0000006C + REG32 BCpu_Dbg_BKP; //0x00000070 + REG32 BCpu_Dbg_Addr; //0x00000074 + REG32 Cfg_Cpus_Cache_Ram_Disable; //0x00000078 + REG32 Reset_Cause; //0x0000007C + /// This register is protected. + REG32 WakeUp; //0x00000080 + REG32 AP_Ctrl; //0x00000084 + /// This register is protected. + REG32 Ignore_Charger; //0x00000088 + REG32 Clk_SYS2_Mode; //0x0000008C + REG32 Clk_SYS2_Enable; //0x00000090 + /// This register is protected. + REG32 Clk_SYS2_Disable; //0x00000094 + /// Register protected by Write_Unlocked_H. + REG32 WD_Pll_Ctrl; //0x00000098 + /// This register is protected. + REG32 WD_Sel_Clock; //0x0000009C + /// This register is protected. + REG32 WD_Rst_Set; //0x000000A0 + REG32 WD_Rst_Clr; //0x000000A4 + /// This register is protected. + REG32 AP_Rst_Set; //0x000000A8 + REG32 AP_Rst_Clr; //0x000000AC + REG32 Clk_WD_Mode; //0x000000B0 + REG32 Clk_WD_Enable; //0x000000B4 + /// This register is protected. + REG32 Clk_WD_Disable; //0x000000B8 + REG32 Cfg_Clk_MPMC; //0x000000BC + REG32 Cfg_MPMC_DQS; //0x000000C0 + REG32 Reserved_000000C4[14]; //0x000000C4 + /// This register is reserved. + REG32 Cfg_Reserve; //0x000000FC +} HWP_SYS_CTRL_T; + +#define hwp_sysCtrlMd ((HWP_SYS_CTRL_T*)(RDA_MD_SYSCTRL_BASE)) + + +//REG_DBG +#define SYS_CTRL_SCRATCH(n) (((n)&0xFFFF)<<0) +#define SYS_CTRL_WRITE_UNLOCK_STATUS (1<<30) +#define SYS_CTRL_WRITE_UNLOCK (1<<31) + +//Sys_Rst_Set +#define SYS_CTRL_SET_RST_XCPU (1<<0) +#define SYS_CTRL_SET_RST_SYS_IRQ (1<<1) +#define SYS_CTRL_SET_RST_SYS_A2A (1<<2) +#define SYS_CTRL_SET_RST_SYS_AHB2AXI (1<<3) +#define SYS_CTRL_SET_RST_SYS_AXI2AHB (1<<4) +#define SYS_CTRL_SET_RST_DMA (1<<5) +#define SYS_CTRL_SET_RST_TIMER (1<<6) +#define SYS_CTRL_SET_RST_TCU (1<<7) +#define SYS_CTRL_SET_RST_GPIO (1<<8) +#define SYS_CTRL_SET_RST_CFG (1<<9) +#define SYS_CTRL_SET_RST_SPI1 (1<<10) +#define SYS_CTRL_SET_RST_SPI2 (1<<11) +#define SYS_CTRL_SET_RST_RF_SPI (1<<12) +#define SYS_CTRL_SET_RST_SCI1 (1<<13) +#define SYS_CTRL_SET_RST_SCI2 (1<<14) +#define SYS_CTRL_SET_RST_SCI3 (1<<15) +#define SYS_CTRL_SET_RST_SPY (1<<16) +#define SYS_CTRL_SET_RST_MEM_BRIDGE (1<<17) +#define SYS_CTRL_SET_RST_EXT_AHB (1<<18) +#define SYS_CTRL_SET_RST_DP_BB (1<<19) +#define SYS_CTRL_SET_RST_DP_AP (1<<20) +#define SYS_CTRL_SET_RST_COMREGS (1<<21) +#define SYS_CTRL_SET_RST_COMREGS_AP (1<<22) +#define SYS_CTRL_SET_RST_AP_CLKEN (1<<23) +#define SYS_CTRL_SET_RST_AP_RST (1<<24) +#define SYS_CTRL_SET_RST_MEM_CHK (1<<25) +#define SYS_CTRL_SET_RST_MPMC (1<<26) +#define SYS_CTRL_SET_RST_SYS_A2A_WD (1<<27) +#define SYS_CTRL_SET_RST_COMREGS_WD (1<<28) +#define SYS_CTRL_SET_RST_OUT (1<<30) +#define SYS_CTRL_SOFT_RST (1<<31) +#define SYS_CTRL_SET_SYS_RST(n) (((n)&0x1FFFFFFF)<<0) +#define SYS_CTRL_SET_SYS_RST_MASK (0x1FFFFFFF<<0) +#define SYS_CTRL_SET_SYS_RST_SHIFT (0) + +//Sys_Rst_Clr +#define SYS_CTRL_CLR_RST_XCPU (1<<0) +#define SYS_CTRL_CLR_RST_SYS_IRQ (1<<1) +#define SYS_CTRL_CLR_RST_SYS_A2A (1<<2) +#define SYS_CTRL_CLR_RST_SYS_AHB2AXI (1<<3) +#define SYS_CTRL_CLR_RST_SYS_AXI2AHB (1<<4) +#define SYS_CTRL_CLR_RST_DMA (1<<5) +#define SYS_CTRL_CLR_RST_TIMER (1<<6) +#define SYS_CTRL_CLR_RST_TCU (1<<7) +#define SYS_CTRL_CLR_RST_GPIO (1<<8) +#define SYS_CTRL_CLR_RST_CFG (1<<9) +#define SYS_CTRL_CLR_RST_SPI1 (1<<10) +#define SYS_CTRL_CLR_RST_SPI2 (1<<11) +#define SYS_CTRL_CLR_RST_RF_SPI (1<<12) +#define SYS_CTRL_CLR_RST_SCI1 (1<<13) +#define SYS_CTRL_CLR_RST_SCI2 (1<<14) +#define SYS_CTRL_CLR_RST_SCI3 (1<<15) +#define SYS_CTRL_CLR_RST_SPY (1<<16) +#define SYS_CTRL_CLR_RST_MEM_BRIDGE (1<<17) +#define SYS_CTRL_CLR_RST_EXT_AHB (1<<18) +#define SYS_CTRL_CLR_RST_DP_BB (1<<19) +#define SYS_CTRL_CLR_RST_DP_AP (1<<20) +#define SYS_CTRL_CLR_RST_COMREGS (1<<21) +#define SYS_CTRL_CLR_RST_COMREGS_AP (1<<22) +#define SYS_CTRL_CLR_RST_AP_CLKEN (1<<23) +#define SYS_CTRL_CLR_RST_AP_RST (1<<24) +#define SYS_CTRL_CLR_RST_MEM_CHK (1<<25) +#define SYS_CTRL_CLR_RST_MPMC (1<<26) +#define SYS_CTRL_CLR_RST_SYS_A2A_WD (1<<27) +#define SYS_CTRL_CLR_RST_COMREGS_WD (1<<28) +#define SYS_CTRL_CLR_RST_OUT (1<<30) +#define SYS_CTRL_CLR_SYS_RST(n) (((n)&0x1FFFFFFF)<<0) +#define SYS_CTRL_CLR_SYS_RST_MASK (0x1FFFFFFF<<0) +#define SYS_CTRL_CLR_SYS_RST_SHIFT (0) + +//BB_Rst_Set +#define SYS_CTRL_SET_RST_BCPU (1<<0) +#define SYS_CTRL_SET_RST_BB_IRQ (1<<1) +#define SYS_CTRL_SET_RST_BB_A2A (1<<2) +#define SYS_CTRL_SET_RST_BB_IFC (1<<3) +#define SYS_CTRL_SET_RST_BB_SRAM (1<<4) +#define SYS_CTRL_SET_RST_ITLV (1<<5) +#define SYS_CTRL_SET_RST_VITERBI (1<<6) +#define SYS_CTRL_SET_RST_CIPHER (1<<7) +#define SYS_CTRL_SET_RST_XCOR (1<<8) +#define SYS_CTRL_SET_RST_COPRO (1<<9) +#define SYS_CTRL_SET_RST_RF_IF (1<<10) +#define SYS_CTRL_SET_RST_EXCOR (1<<11) +#define SYS_CTRL_SET_RST_EVITAC (1<<12) +#define SYS_CTRL_SET_RST_CORDIC (1<<13) +#define SYS_CTRL_SET_RST_TCU_BB (1<<14) +#define SYS_CTRL_SET_RST_BB_DP (1<<15) +#define SYS_CTRL_SET_RST_BB_ROM (1<<16) +#define SYS_CTRL_SET_RST_MPMC_BB (1<<17) +#define SYS_CTRL_SET_RST_BB_FULL (1<<31) +#define SYS_CTRL_SET_BB_RST(n) (((n)&0x3FFFF)<<0) +#define SYS_CTRL_SET_BB_RST_MASK (0x3FFFF<<0) +#define SYS_CTRL_SET_BB_RST_SHIFT (0) + +//BB_Rst_Clr +#define SYS_CTRL_CLR_RST_BCPU (1<<0) +#define SYS_CTRL_CLR_RST_BB_IRQ (1<<1) +#define SYS_CTRL_CLR_RST_BB_A2A (1<<2) +#define SYS_CTRL_CLR_RST_BB_IFC (1<<3) +#define SYS_CTRL_CLR_RST_BB_SRAM (1<<4) +#define SYS_CTRL_CLR_RST_ITLV (1<<5) +#define SYS_CTRL_CLR_RST_VITERBI (1<<6) +#define SYS_CTRL_CLR_RST_CIPHER (1<<7) +#define SYS_CTRL_CLR_RST_XCOR (1<<8) +#define SYS_CTRL_CLR_RST_COPRO (1<<9) +#define SYS_CTRL_CLR_RST_RF_IF (1<<10) +#define SYS_CTRL_CLR_RST_EXCOR (1<<11) +#define SYS_CTRL_CLR_RST_EVITAC (1<<12) +#define SYS_CTRL_CLR_RST_CORDIC (1<<13) +#define SYS_CTRL_CLR_RST_TCU_BB (1<<14) +#define SYS_CTRL_CLR_RST_BB_DP (1<<15) +#define SYS_CTRL_CLR_RST_BB_ROM (1<<16) +#define SYS_CTRL_CLR_RST_MPMC_BB (1<<17) +#define SYS_CTRL_CLR_RST_BB_FULL (1<<31) +#define SYS_CTRL_CLR_BB_RST(n) (((n)&0x3FFFF)<<0) +#define SYS_CTRL_CLR_BB_RST_MASK (0x3FFFF<<0) +#define SYS_CTRL_CLR_BB_RST_SHIFT (0) + +//Clk_Sys_Mode +#define SYS_CTRL_MODE_SYS_XCPU (1<<0) +#define SYS_CTRL_MODE_SYS_XCPU_INT_AUTOMATIC (0<<1) +#define SYS_CTRL_MODE_SYS_XCPU_INT_MANUAL (1<<1) +#define SYS_CTRL_MODE_SYS_PCLK_CONF_AUTOMATIC (0<<2) +#define SYS_CTRL_MODE_SYS_PCLK_CONF_MANUAL (1<<2) +#define SYS_CTRL_MODE_SYS_PCLK_DATA_AUTOMATIC (0<<3) +#define SYS_CTRL_MODE_SYS_PCLK_DATA_MANUAL (1<<3) +#define SYS_CTRL_MODE_SYS_AMBA_AUTOMATIC (0<<4) +#define SYS_CTRL_MODE_SYS_AMBA_MANUAL (1<<4) +#define SYS_CTRL_MODE_SYS_DMA_AUTOMATIC (0<<5) +#define SYS_CTRL_MODE_SYS_DMA_MANUAL (1<<5) +#define SYS_CTRL_MODE_SYS_EBC_AUTOMATIC (0<<6) +#define SYS_CTRL_MODE_SYS_EBC_MANUAL (1<<6) +#define SYS_CTRL_MODE_SYS_IFC_CH0_AUTOMATIC (0<<7) +#define SYS_CTRL_MODE_SYS_IFC_CH0_MANUAL (1<<7) +#define SYS_CTRL_MODE_SYS_IFC_CH1_AUTOMATIC (0<<8) +#define SYS_CTRL_MODE_SYS_IFC_CH1_MANUAL (1<<8) +#define SYS_CTRL_MODE_SYS_IFC_CH2_AUTOMATIC (0<<9) +#define SYS_CTRL_MODE_SYS_IFC_CH2_MANUAL (1<<9) +#define SYS_CTRL_MODE_SYS_IFC_CH3_AUTOMATIC (0<<10) +#define SYS_CTRL_MODE_SYS_IFC_CH3_MANUAL (1<<10) +#define SYS_CTRL_MODE_SYS_IFC_DBG_AUTOMATIC (0<<11) +#define SYS_CTRL_MODE_SYS_IFC_DBG_MANUAL (1<<11) +#define SYS_CTRL_MODE_SYS_A2A_AUTOMATIC (0<<12) +#define SYS_CTRL_MODE_SYS_A2A_MANUAL (1<<12) +#define SYS_CTRL_MODE_SYS_AXI2AHB_AUTOMATIC (0<<13) +#define SYS_CTRL_MODE_SYS_AXI2AHB_MANUAL (1<<13) +#define SYS_CTRL_MODE_SYS_AHB2AXI_AUTOMATIC (0<<14) +#define SYS_CTRL_MODE_SYS_AHB2AXI_MANUAL (1<<14) +#define SYS_CTRL_MODE_SYS_EXT_AHB_AUTOMATIC (0<<15) +#define SYS_CTRL_MODE_SYS_EXT_AHB_MANUAL (1<<15) +#define SYS_CTRL_MODE_SYS_DEBUG_UART_AUTOMATIC (0<<16) +#define SYS_CTRL_MODE_SYS_DEBUG_UART_MANUAL (1<<16) +#define SYS_CTRL_MODE_SYS_DBGHST_AUTOMATIC (0<<17) +#define SYS_CTRL_MODE_SYS_DBGHST_MANUAL (1<<17) +#define SYS_CTRL_MODE_SYS_A2A_WD_AUTOMATIC (0<<18) +#define SYS_CTRL_MODE_SYS_A2A_WD_MANUAL (1<<18) +#define SYS_CTRL_MODE_SYSD_SCI1_AUTOMATIC (0<<19) +#define SYS_CTRL_MODE_SYSD_SCI1_MANUAL (1<<19) +#define SYS_CTRL_MODE_SYSD_SCI2_AUTOMATIC (0<<20) +#define SYS_CTRL_MODE_SYSD_SCI2_MANUAL (1<<20) +#define SYS_CTRL_MODE_SYSD_SCI3_AUTOMATIC (0<<21) +#define SYS_CTRL_MODE_SYSD_SCI3_MANUAL (1<<21) +#define SYS_CTRL_MODE_SYSD_RF_SPI_AUTOMATIC (0<<22) +#define SYS_CTRL_MODE_SYSD_RF_SPI_MANUAL (1<<22) +#define SYS_CTRL_MODE_SYSD_OSC_AUTOMATIC (0<<23) +#define SYS_CTRL_MODE_SYSD_OSC_MANUAL (1<<23) +#define SYS_CTRL_MODE_CLK_SYS(n) (((n)&0x7FFFFF)<<1) +#define SYS_CTRL_MODE_CLK_SYS_MASK (0x7FFFFF<<1) +#define SYS_CTRL_MODE_CLK_SYS_SHIFT (1) + +//Clk_Sys_Enable +#define SYS_CTRL_ENABLE_SYS_XCPU (1<<0) +#define SYS_CTRL_ENABLE_SYS_XCPU_INT (1<<1) +#define SYS_CTRL_ENABLE_SYS_PCLK_CONF (1<<2) +#define SYS_CTRL_ENABLE_SYS_PCLK_DATA (1<<3) +#define SYS_CTRL_ENABLE_SYS_AMBA (1<<4) +#define SYS_CTRL_ENABLE_SYS_DMA (1<<5) +#define SYS_CTRL_ENABLE_SYS_EBC (1<<6) +#define SYS_CTRL_ENABLE_SYS_IFC_CH0 (1<<7) +#define SYS_CTRL_ENABLE_SYS_IFC_CH1 (1<<8) +#define SYS_CTRL_ENABLE_SYS_IFC_CH2 (1<<9) +#define SYS_CTRL_ENABLE_SYS_IFC_CH3 (1<<10) +#define SYS_CTRL_ENABLE_SYS_IFC_DBG (1<<11) +#define SYS_CTRL_ENABLE_SYS_A2A (1<<12) +#define SYS_CTRL_ENABLE_SYS_AXI2AHB (1<<13) +#define SYS_CTRL_ENABLE_SYS_AHB2AXI (1<<14) +#define SYS_CTRL_ENABLE_SYS_EXT_AHB (1<<15) +#define SYS_CTRL_ENABLE_SYS_DEBUG_UART (1<<16) +#define SYS_CTRL_ENABLE_SYS_DBGHST (1<<17) +#define SYS_CTRL_ENABLE_SYS_A2A_WD (1<<18) +#define SYS_CTRL_ENABLE_SYSD_SCI1 (1<<19) +#define SYS_CTRL_ENABLE_SYSD_SCI2 (1<<20) +#define SYS_CTRL_ENABLE_SYSD_SCI3 (1<<21) +#define SYS_CTRL_ENABLE_SYSD_RF_SPI (1<<22) +#define SYS_CTRL_ENABLE_SYSD_OSC (1<<23) +#define SYS_CTRL_ENABLE_SYS_GPIO (1<<24) +#define SYS_CTRL_ENABLE_SYS_IRQ (1<<25) +#define SYS_CTRL_ENABLE_SYS_TCU (1<<26) +#define SYS_CTRL_ENABLE_SYS_TIMER (1<<27) +#define SYS_CTRL_ENABLE_SYS_COM_REGS (1<<28) +#define SYS_CTRL_ENABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0) +#define SYS_CTRL_ENABLE_CLK_SYS_MASK (0x1FFFFFFF<<0) +#define SYS_CTRL_ENABLE_CLK_SYS_SHIFT (0) + +//Clk_Sys_Disable +#define SYS_CTRL_DISABLE_SYS_XCPU (1<<0) +#define SYS_CTRL_DISABLE_SYS_XCPU_INT (1<<1) +#define SYS_CTRL_DISABLE_SYS_PCLK_CONF (1<<2) +#define SYS_CTRL_DISABLE_SYS_PCLK_DATA (1<<3) +#define SYS_CTRL_DISABLE_SYS_AMBA (1<<4) +#define SYS_CTRL_DISABLE_SYS_DMA (1<<5) +#define SYS_CTRL_DISABLE_SYS_EBC (1<<6) +#define SYS_CTRL_DISABLE_SYS_IFC_CH0 (1<<7) +#define SYS_CTRL_DISABLE_SYS_IFC_CH1 (1<<8) +#define SYS_CTRL_DISABLE_SYS_IFC_CH2 (1<<9) +#define SYS_CTRL_DISABLE_SYS_IFC_CH3 (1<<10) +#define SYS_CTRL_DISABLE_SYS_IFC_DBG (1<<11) +#define SYS_CTRL_DISABLE_SYS_A2A (1<<12) +#define SYS_CTRL_DISABLE_SYS_AXI2AHB (1<<13) +#define SYS_CTRL_DISABLE_SYS_AHB2AXI (1<<14) +#define SYS_CTRL_DISABLE_SYS_EXT_AHB (1<<15) +#define SYS_CTRL_DISABLE_SYS_DEBUG_UART (1<<16) +#define SYS_CTRL_DISABLE_SYS_DBGHST (1<<17) +#define SYS_CTRL_DISABLE_SYS_A2A_WD (1<<18) +#define SYS_CTRL_DISABLE_SYSD_SCI1 (1<<19) +#define SYS_CTRL_DISABLE_SYSD_SCI2 (1<<20) +#define SYS_CTRL_DISABLE_SYSD_SCI3 (1<<21) +#define SYS_CTRL_DISABLE_SYSD_RF_SPI (1<<22) +#define SYS_CTRL_DISABLE_SYSD_OSC (1<<23) +#define SYS_CTRL_DISABLE_SYS_GPIO (1<<24) +#define SYS_CTRL_DISABLE_SYS_IRQ (1<<25) +#define SYS_CTRL_DISABLE_SYS_TCU (1<<26) +#define SYS_CTRL_DISABLE_SYS_TIMER (1<<27) +#define SYS_CTRL_DISABLE_SYS_COM_REGS (1<<28) +#define SYS_CTRL_DISABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0) +#define SYS_CTRL_DISABLE_CLK_SYS_MASK (0x1FFFFFFF<<0) +#define SYS_CTRL_DISABLE_CLK_SYS_SHIFT (0) + +//Clk_Per_Mode +#define SYS_CTRL_MODE_PERD_SPI1_AUTOMATIC (0<<0) +#define SYS_CTRL_MODE_PERD_SPI1_MANUAL (1<<0) +#define SYS_CTRL_MODE_PERD_SPI2_AUTOMATIC (0<<1) +#define SYS_CTRL_MODE_PERD_SPI2_MANUAL (1<<1) +#define SYS_CTRL_MODE_CLK_PER(n) (((n)&3)<<0) +#define SYS_CTRL_MODE_CLK_PER_MASK (3<<0) +#define SYS_CTRL_MODE_CLK_PER_SHIFT (0) + +//Clk_Per_Enable +#define SYS_CTRL_ENABLE_PERD_SPI1 (1<<0) +#define SYS_CTRL_ENABLE_PERD_SPI2 (1<<1) +#define SYS_CTRL_ENABLE_PER_SPY (1<<2) +#define SYS_CTRL_ENABLE_PER_TEST (1<<3) +#define SYS_CTRL_ENABLE_CLK_PER(n) (((n)&15)<<0) +#define SYS_CTRL_ENABLE_CLK_PER_MASK (15<<0) +#define SYS_CTRL_ENABLE_CLK_PER_SHIFT (0) + +//Clk_Per_Disable +#define SYS_CTRL_DISABLE_PERD_SPI1 (1<<0) +#define SYS_CTRL_DISABLE_PERD_SPI2 (1<<1) +#define SYS_CTRL_DISABLE_PER_SPY (1<<2) +#define SYS_CTRL_DISABLE_PER_TEST (1<<3) +#define SYS_CTRL_DISABLE_CLK_PER(n) (((n)&15)<<0) +#define SYS_CTRL_DISABLE_CLK_PER_MASK (15<<0) +#define SYS_CTRL_DISABLE_CLK_PER_SHIFT (0) + +//Clk_BB_Mode +#define SYS_CTRL_MODE_BB_BCPU (1<<0) +#define SYS_CTRL_MODE_BB_BCPU_INT_AUTOMATIC (0<<1) +#define SYS_CTRL_MODE_BB_BCPU_INT_MANUAL (1<<1) +#define SYS_CTRL_MODE_BB_AMBA_AUTOMATIC (0<<2) +#define SYS_CTRL_MODE_BB_AMBA_MANUAL (1<<2) +#define SYS_CTRL_MODE_BB_PCLK_CONF_AUTOMATIC (0<<3) +#define SYS_CTRL_MODE_BB_PCLK_CONF_MANUAL (1<<3) +#define SYS_CTRL_MODE_BB_PCLK_DATA_AUTOMATIC (0<<4) +#define SYS_CTRL_MODE_BB_PCLK_DATA_MANUAL (1<<4) +#define SYS_CTRL_MODE_BB_EXCOR_AUTOMATIC (0<<5) +#define SYS_CTRL_MODE_BB_EXCOR_MANUAL (1<<5) +#define SYS_CTRL_MODE_BB_IFC_CH2_AUTOMATIC (0<<6) +#define SYS_CTRL_MODE_BB_IFC_CH2_MANUAL (1<<6) +#define SYS_CTRL_MODE_BB_IFC_CH3_AUTOMATIC (0<<7) +#define SYS_CTRL_MODE_BB_IFC_CH3_MANUAL (1<<7) +#define SYS_CTRL_MODE_BB_SRAM_AUTOMATIC (0<<8) +#define SYS_CTRL_MODE_BB_SRAM_MANUAL (1<<8) +#define SYS_CTRL_MODE_BB_A2A_AUTOMATIC (0<<9) +#define SYS_CTRL_MODE_BB_A2A_MANUAL (1<<9) +#define SYS_CTRL_MODE_BB_ITLV_AUTOMATIC (0<<10) +#define SYS_CTRL_MODE_BB_ITLV_MANUAL (1<<10) +#define SYS_CTRL_MODE_BB_VITERBI_AUTOMATIC (0<<11) +#define SYS_CTRL_MODE_BB_VITERBI_MANUAL (1<<11) +#define SYS_CTRL_MODE_BB_CIPHER_AUTOMATIC (0<<12) +#define SYS_CTRL_MODE_BB_CIPHER_MANUAL (1<<12) +#define SYS_CTRL_MODE_BB_RF_IF_AUTOMATIC (0<<13) +#define SYS_CTRL_MODE_BB_RF_IF_MANUAL (1<<13) +#define SYS_CTRL_MODE_BB_COPRO_AUTOMATIC (0<<14) +#define SYS_CTRL_MODE_BB_COPRO_MANUAL (1<<14) +#define SYS_CTRL_MODE_BB_CP2_REG_AUTOMATIC (0<<15) +#define SYS_CTRL_MODE_BB_CP2_REG_MANUAL (1<<15) +#define SYS_CTRL_MODE_BB_XCOR_AUTOMATIC (0<<16) +#define SYS_CTRL_MODE_BB_XCOR_MANUAL (1<<16) +#define SYS_CTRL_MODE_BB_EVITAC_AUTOMATIC (0<<17) +#define SYS_CTRL_MODE_BB_EVITAC_MANUAL (1<<17) +#define SYS_CTRL_MODE_BB_ROM_AUTOMATIC (0<<18) +#define SYS_CTRL_MODE_BB_ROM_MANUAL (1<<18) +#define SYS_CTRL_MODE_BB_MPMC_AUTOMATIC (0<<19) +#define SYS_CTRL_MODE_BB_MPMC_MANUAL (1<<19) +#define SYS_CTRL_MODE_CLK_BB(n) (((n)&0x7FFFF)<<1) +#define SYS_CTRL_MODE_CLK_BB_MASK (0x7FFFF<<1) +#define SYS_CTRL_MODE_CLK_BB_SHIFT (1) + +//Clk_BB_Enable +#define SYS_CTRL_ENABLE_BB_BCPU (1<<0) +#define SYS_CTRL_ENABLE_BB_BCPU_INT (1<<1) +#define SYS_CTRL_ENABLE_BB_AMBA (1<<2) +#define SYS_CTRL_ENABLE_BB_PCLK_CONF (1<<3) +#define SYS_CTRL_ENABLE_BB_PCLK_DATA (1<<4) +#define SYS_CTRL_ENABLE_BB_EXCOR (1<<5) +#define SYS_CTRL_ENABLE_BB_IFC_CH2 (1<<6) +#define SYS_CTRL_ENABLE_BB_IFC_CH3 (1<<7) +#define SYS_CTRL_ENABLE_BB_SRAM (1<<8) +#define SYS_CTRL_ENABLE_BB_A2A (1<<9) +#define SYS_CTRL_ENABLE_BB_ITLV (1<<10) +#define SYS_CTRL_ENABLE_BB_VITERBI (1<<11) +#define SYS_CTRL_ENABLE_BB_CIPHER (1<<12) +#define SYS_CTRL_ENABLE_BB_RF_IF (1<<13) +#define SYS_CTRL_ENABLE_BB_COPRO (1<<14) +#define SYS_CTRL_ENABLE_BB_CP2_REG (1<<15) +#define SYS_CTRL_ENABLE_BB_XCOR (1<<16) +#define SYS_CTRL_ENABLE_BB_EVITAC (1<<17) +#define SYS_CTRL_ENABLE_BB_ROM (1<<18) +#define SYS_CTRL_ENABLE_BB_MPMC (1<<19) +#define SYS_CTRL_ENABLE_BB_IRQ (1<<20) +#define SYS_CTRL_ENABLE_BB_COM_REGS (1<<21) +#define SYS_CTRL_ENABLE_BB_CORDIC (1<<22) +#define SYS_CTRL_ENABLE_BB_DP (1<<23) +#define SYS_CTRL_ENABLE_CLK_BB(n) (((n)&0xFFFFFF)<<0) +#define SYS_CTRL_ENABLE_CLK_BB_MASK (0xFFFFFF<<0) +#define SYS_CTRL_ENABLE_CLK_BB_SHIFT (0) + +//Clk_BB_Disable +#define SYS_CTRL_DISABLE_BB_BCPU (1<<0) +#define SYS_CTRL_DISABLE_BB_BCPU_INT (1<<1) +#define SYS_CTRL_DISABLE_BB_AMBA (1<<2) +#define SYS_CTRL_DISABLE_BB_PCLK_CONF (1<<3) +#define SYS_CTRL_DISABLE_BB_PCLK_DATA (1<<4) +#define SYS_CTRL_DISABLE_BB_EXCOR (1<<5) +#define SYS_CTRL_DISABLE_BB_IFC_CH2 (1<<6) +#define SYS_CTRL_DISABLE_BB_IFC_CH3 (1<<7) +#define SYS_CTRL_DISABLE_BB_SRAM (1<<8) +#define SYS_CTRL_DISABLE_BB_A2A (1<<9) +#define SYS_CTRL_DISABLE_BB_ITLV (1<<10) +#define SYS_CTRL_DISABLE_BB_VITERBI (1<<11) +#define SYS_CTRL_DISABLE_BB_CIPHER (1<<12) +#define SYS_CTRL_DISABLE_BB_RF_IF (1<<13) +#define SYS_CTRL_DISABLE_BB_COPRO (1<<14) +#define SYS_CTRL_DISABLE_BB_CP2_REG (1<<15) +#define SYS_CTRL_DISABLE_BB_XCOR (1<<16) +#define SYS_CTRL_DISABLE_BB_EVITAC (1<<17) +#define SYS_CTRL_DISABLE_BB_ROM (1<<18) +#define SYS_CTRL_DISABLE_BB_MPMC (1<<19) +#define SYS_CTRL_DISABLE_BB_IRQ (1<<20) +#define SYS_CTRL_DISABLE_BB_COM_REGS (1<<21) +#define SYS_CTRL_DISABLE_BB_CORDIC (1<<22) +#define SYS_CTRL_DISABLE_BB_DP (1<<23) +#define SYS_CTRL_DISABLE_CLK_BB(n) (((n)&0xFFFFFF)<<0) +#define SYS_CTRL_DISABLE_CLK_BB_MASK (0xFFFFFF<<0) +#define SYS_CTRL_DISABLE_CLK_BB_SHIFT (0) + +//Clk_Other_Mode +#define SYS_CTRL_MODE_OC_DEBUG_UART_AUTOMATIC (0<<0) +#define SYS_CTRL_MODE_OC_DEBUG_UART_MANUAL (1<<0) +#define SYS_CTRL_MODE_OC_RF_RX_AUTOMATIC (0<<1) +#define SYS_CTRL_MODE_OC_RF_RX_MANUAL (1<<1) +#define SYS_CTRL_MODE_OC_RF_TX_AUTOMATIC (0<<2) +#define SYS_CTRL_MODE_OC_RF_TX_MANUAL (1<<2) +#define SYS_CTRL_MODE_OC_MEM_BRIDGE_AUTOMATIC (0<<3) +#define SYS_CTRL_MODE_OC_MEM_BRIDGE_MANUAL (1<<3) +#define SYS_CTRL_MODE_CLK_OTHER(n) (((n)&15)<<0) +#define SYS_CTRL_MODE_CLK_OTHER_MASK (15<<0) +#define SYS_CTRL_MODE_CLK_OTHER_SHIFT (0) + +//Clk_Other_Enable +#define SYS_CTRL_ENABLE_OC_DEBUG_UART (1<<0) +#define SYS_CTRL_ENABLE_OC_RF_RX (1<<1) +#define SYS_CTRL_ENABLE_OC_RF_TX (1<<2) +#define SYS_CTRL_ENABLE_OC_MEM_BRIDGE (1<<3) +#define SYS_CTRL_ENABLE_OC_LPS (1<<4) +#define SYS_CTRL_ENABLE_OC_GPIO (1<<5) +#define SYS_CTRL_ENABLE_OC_CLK_OUT (1<<6) +#define SYS_CTRL_ENABLE_OC_MEM_CLK_OUT (1<<7) +#define SYS_CTRL_ENABLE_OC_TCU (1<<8) +#define SYS_CTRL_ENABLE_OC_WD_CHIP (1<<9) +#define SYS_CTRL_ENABLE_OC_WD_ADC (1<<10) +#define SYS_CTRL_ENABLE_OC_WD_TURBO (1<<11) +#define SYS_CTRL_ENABLE_OC_WD_OSC (1<<12) +#define SYS_CTRL_ENABLE_OC_MPMC (1<<13) +#define SYS_CTRL_ENABLE_CLK_OTHER(n) (((n)&0x3FFF)<<0) +#define SYS_CTRL_ENABLE_CLK_OTHER_MASK (0x3FFF<<0) +#define SYS_CTRL_ENABLE_CLK_OTHER_SHIFT (0) + +//Clk_Other_Disable +#define SYS_CTRL_DISABLE_OC_DEBUG_UART (1<<0) +#define SYS_CTRL_DISABLE_OC_RF_RX (1<<1) +#define SYS_CTRL_DISABLE_OC_RF_TX (1<<2) +#define SYS_CTRL_DISABLE_OC_MEM_BRIDGE (1<<3) +#define SYS_CTRL_DISABLE_OC_LPS (1<<4) +#define SYS_CTRL_DISABLE_OC_GPIO (1<<5) +#define SYS_CTRL_DISABLE_OC_CLK_OUT (1<<6) +#define SYS_CTRL_DISABLE_OC_MEM_CLK_OUT (1<<7) +#define SYS_CTRL_DISABLE_OC_TCU (1<<8) +#define SYS_CTRL_DISABLE_OC_WD_CHIP (1<<9) +#define SYS_CTRL_DISABLE_OC_WD_ADC (1<<10) +#define SYS_CTRL_DISABLE_OC_WD_TURBO (1<<11) +#define SYS_CTRL_DISABLE_OC_WD_OSC (1<<12) +#define SYS_CTRL_DISABLE_OC_MPMC (1<<13) +#define SYS_CTRL_DISABLE_CLK_OTHER(n) (((n)&0x3FFF)<<0) +#define SYS_CTRL_DISABLE_CLK_OTHER_MASK (0x3FFF<<0) +#define SYS_CTRL_DISABLE_CLK_OTHER_SHIFT (0) + +//Pll_Ctrl +#define SYS_CTRL_PLL_ENABLE (1<<0) +#define SYS_CTRL_PLL_ENABLE_MASK (1<<0) +#define SYS_CTRL_PLL_ENABLE_SHIFT (0) +#define SYS_CTRL_PLL_ENABLE_POWER_DOWN (0<<0) +#define SYS_CTRL_PLL_ENABLE_ENABLE (1<<0) +#define SYS_CTRL_PLL_LOCK_RESET (1<<4) +#define SYS_CTRL_PLL_LOCK_RESET_MASK (1<<4) +#define SYS_CTRL_PLL_LOCK_RESET_SHIFT (4) +#define SYS_CTRL_PLL_LOCK_RESET_RESET (0<<4) +#define SYS_CTRL_PLL_LOCK_RESET_NO_RESET (1<<4) +#define SYS_CTRL_PLL_BYPASS (1<<8) +#define SYS_CTRL_PLL_BYPASS_MASK (1<<8) +#define SYS_CTRL_PLL_BYPASS_SHIFT (8) +#define SYS_CTRL_PLL_BYPASS_PASS (0<<8) +#define SYS_CTRL_PLL_BYPASS_BYPASS (1<<8) +#define SYS_CTRL_PLL_CLK_FAST_ENABLE (1<<12) +#define SYS_CTRL_PLL_CLK_FAST_ENABLE_MASK (1<<12) +#define SYS_CTRL_PLL_CLK_FAST_ENABLE_SHIFT (12) +#define SYS_CTRL_PLL_CLK_FAST_ENABLE_ENABLE (1<<12) +#define SYS_CTRL_PLL_CLK_FAST_ENABLE_DISABLE (0<<12) +#define SYS_CTRL_PLL_XP_CFG(n) (((n)&4369)<<0) +#define SYS_CTRL_PLL_XP_CFG_MASK (4369<<0) +#define SYS_CTRL_PLL_XP_CFG_SHIFT (0) + +//Sel_Clock +#define SYS_CTRL_SLOW_SEL_RF_OSCILLATOR (1<<0) +#define SYS_CTRL_SLOW_SEL_RF_RF (0<<0) +#define SYS_CTRL_SYS_SEL_FAST_SLOW (1<<4) +#define SYS_CTRL_SYS_SEL_FAST_FAST (0<<4) +#define SYS_CTRL_TCU_13M_L_26M (1<<5) +#define SYS_CTRL_TCU_13M_L_13M (0<<5) +#define SYS_CTRL_PLL_DISABLE_LPS_DISABLE (1<<6) +#define SYS_CTRL_PLL_DISABLE_LPS_ENABLE (0<<6) +#define SYS_CTRL_DIGEN_H_ENABLE (1<<7) +#define SYS_CTRL_DIGEN_H_DISABLE (0<<7) +#define SYS_CTRL_RF_DETECTED_OK (1<<20) +#define SYS_CTRL_RF_DETECTED_NO (0<<20) +#define SYS_CTRL_RF_DETECT_BYPASS (1<<21) +#define SYS_CTRL_RF_DETECT_RESET (1<<22) +#define SYS_CTRL_RF_SELECTED_L (1<<23) +#define SYS_CTRL_PLL_LOCKED (1<<24) +#define SYS_CTRL_PLL_LOCKED_MASK (1<<24) +#define SYS_CTRL_PLL_LOCKED_SHIFT (24) +#define SYS_CTRL_PLL_LOCKED_LOCKED (1<<24) +#define SYS_CTRL_PLL_LOCKED_NOT_LOCKED (0<<24) +#define SYS_CTRL_PLL_BYPASS_LOCK (1<<27) +#define SYS_CTRL_FAST_SELECTED_L (1<<31) +#define SYS_CTRL_FAST_SELECTED_L_MASK (1<<31) +#define SYS_CTRL_FAST_SELECTED_L_SHIFT (31) + +//Cfg_Clk_Sys +#define SYS_CTRL_FREQ(n) (((n)&15)<<0) +#define SYS_CTRL_FREQ_MASK (15<<0) +#define SYS_CTRL_FREQ_SHIFT (0) +#define SYS_CTRL_FREQ_312M (13<<0) +#define SYS_CTRL_FREQ_250M (12<<0) +#define SYS_CTRL_FREQ_208M (11<<0) +#define SYS_CTRL_FREQ_178M (10<<0) +#define SYS_CTRL_FREQ_156M (9<<0) +#define SYS_CTRL_FREQ_139M (8<<0) +#define SYS_CTRL_FREQ_125M (7<<0) +#define SYS_CTRL_FREQ_113M (6<<0) +#define SYS_CTRL_FREQ_104M (5<<0) +#define SYS_CTRL_FREQ_89M (4<<0) +#define SYS_CTRL_FREQ_78M (3<<0) +#define SYS_CTRL_FREQ_52M (2<<0) +#define SYS_CTRL_FREQ_39M (1<<0) +#define SYS_CTRL_FREQ_26M (0<<0) +#define SYS_CTRL_FORCE_DIV_UPDATE (1<<4) +#define SYS_CTRL_REQ_DIV_UPDATE (1<<8) + +//Cfg_Clk_Mem_Bridge +#define SYS_CTRL_MEM_FREQ(n) (((n)&15)<<0) +#define SYS_CTRL_MEM_FREQ_MASK (15<<0) +#define SYS_CTRL_MEM_FREQ_SHIFT (0) +#define SYS_CTRL_MEM_FREQ_312M (13<<0) +#define SYS_CTRL_MEM_FREQ_250M (12<<0) +#define SYS_CTRL_MEM_FREQ_208M (11<<0) +#define SYS_CTRL_MEM_FREQ_178M (10<<0) +#define SYS_CTRL_MEM_FREQ_156M (9<<0) +#define SYS_CTRL_MEM_FREQ_139M (8<<0) +#define SYS_CTRL_MEM_FREQ_125M (7<<0) +#define SYS_CTRL_MEM_FREQ_113M (6<<0) +#define SYS_CTRL_MEM_FREQ_104M (5<<0) +#define SYS_CTRL_MEM_FREQ_89M (4<<0) +#define SYS_CTRL_MEM_FREQ_78M (3<<0) +#define SYS_CTRL_MEM_FREQ_52M (2<<0) +#define SYS_CTRL_MEM_FREQ_39M (1<<0) +#define SYS_CTRL_MEM_FREQ_26M (0<<0) +#define SYS_CTRL_DDR_MODE_EN_NORMAL_MODE (0<<4) +#define SYS_CTRL_DDR_MODE_EN_DDR_MODE (1<<4) +#define SYS_CTRL_DDR_FAST_CLK_POL_INVERT (1<<5) +#define SYS_CTRL_DDR_FAST_CLK_POL_NORMAL (0<<5) +#define SYS_CTRL_DDR_DQSL_O(n) (((n)&31)<<6) +#define SYS_CTRL_DDR_DQSU_O(n) (((n)&31)<<11) +#define SYS_CTRL_DDR_DQS_OEN(n) (((n)&31)<<16) +#define SYS_CTRL_DDR_DQSL_I(n) (((n)&31)<<21) +#define SYS_CTRL_DDR_DQSU_I(n) (((n)&31)<<26) +#define SYS_CTRL_MEM_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_Out +#define SYS_CTRL_CLKOUT_DIVIDER(n) (((n)&31)<<0) +#define SYS_CTRL_CLKOUT_SEL_OSC (0<<8) +#define SYS_CTRL_CLKOUT_SEL_RF (1<<8) +#define SYS_CTRL_CLKOUT_SEL_DIVIDER (2<<8) + +//Cfg_Clk_Host_Uart +#define SYS_CTRL_HOST_UART_DIVIDER(n) (((n)&0x3FF)<<0) +#define SYS_CTRL_HOST_UART_DIVIDER_MASK (0x3FF<<0) +#define SYS_CTRL_HOST_UART_DIVIDER_SHIFT (0) +#define SYS_CTRL_HOST_UART_SEL_PLL_SLOW (0<<12) +#define SYS_CTRL_HOST_UART_SEL_PLL_PLL (1<<12) + +//Cfg_Clk_Auxclk +#define SYS_CTRL_AUXCLK_EN_DISABLE (0<<0) +#define SYS_CTRL_AUXCLK_EN_ENABLE (1<<0) + +//Cfg_AHB +#define SYS_CTRL_SYS_NEW_ARBITRATION_ENABLE (1<<0) +#define SYS_CTRL_SYS_NEW_ARBITRATION_DISABLE (0<<0) +#define SYS_CTRL_ENABLE_SYS_MID_DMA_ENABLE (1<<1) +#define SYS_CTRL_ENABLE_SYS_MID_DMA_DISABLE (0<<1) +#define SYS_CTRL_ENABLE_SYS_MID_XCPU_ENABLE (1<<2) +#define SYS_CTRL_ENABLE_SYS_MID_XCPU_DISABLE (0<<2) +#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_ENABLE (1<<3) +#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_DISABLE (0<<3) +#define SYS_CTRL_ENABLE_SYS_MID_IFC_ENABLE (1<<4) +#define SYS_CTRL_ENABLE_SYS_MID_IFC_DISABLE (0<<4) +#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_ENABLE (1<<5) +#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_DISABLE (0<<5) +#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_WD_ENABLE (1<<6) +#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_WD_DISABLE (0<<6) +#define SYS_CTRL_BB_NEW_ARBITRATION_ENABLE (1<<16) +#define SYS_CTRL_BB_NEW_ARBITRATION_DISABLE (0<<16) +#define SYS_CTRL_ENABLE_BB_MID_IFC_ENABLE (1<<17) +#define SYS_CTRL_ENABLE_BB_MID_IFC_DISABLE (0<<17) +#define SYS_CTRL_ENABLE_BB_MID_BCPU_ENABLE (1<<18) +#define SYS_CTRL_ENABLE_BB_MID_BCPU_DISABLE (0<<18) +#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_ENABLE (1<<19) +#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_DISABLE (0<<19) +#define SYS_CTRL_SYS_ENABLE(n) (((n)&0x3F)<<1) +#define SYS_CTRL_SYS_ENABLE_MASK (0x3F<<1) +#define SYS_CTRL_SYS_ENABLE_SHIFT (1) +#define SYS_CTRL_BB_ENABLE(n) (((n)&7)<<17) +#define SYS_CTRL_BB_ENABLE_MASK (7<<17) +#define SYS_CTRL_BB_ENABLE_SHIFT (17) + +//Ctrl_AHB +#define SYS_CTRL_SPLIT_SYS_MID_DMA_NORMAL (1<<0) +#define SYS_CTRL_SPLIT_SYS_MID_DMA_FORCE (0<<0) +#define SYS_CTRL_SPLIT_SYS_MID_XCPU_NORMAL (1<<1) +#define SYS_CTRL_SPLIT_SYS_MID_XCPU_FORCE (0<<1) +#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_NORMAL (1<<2) +#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_FORCE (0<<2) +#define SYS_CTRL_SPLIT_SYS_MID_IFC_NORMAL (1<<3) +#define SYS_CTRL_SPLIT_SYS_MID_IFC_FORCE (0<<3) +#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_NORMAL (1<<4) +#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_FORCE (0<<4) +#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_WD_NORMAL (1<<5) +#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_WD_FORCE (0<<5) +#define SYS_CTRL_SPLIT_BB_MID_IFC_NORMAL (1<<16) +#define SYS_CTRL_SPLIT_BB_MID_IFC_FORCE (0<<16) +#define SYS_CTRL_SPLIT_BB_MID_BCPU_NORMAL (1<<17) +#define SYS_CTRL_SPLIT_BB_MID_BCPU_FORCE (0<<17) +#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_NORMAL (1<<18) +#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_FORCE (0<<18) +#define SYS_CTRL_SYS_FORCE_HSPLIT(n) (((n)&0x3F)<<0) +#define SYS_CTRL_SYS_FORCE_HSPLIT_MASK (0x3F<<0) +#define SYS_CTRL_SYS_FORCE_HSPLIT_SHIFT (0) +#define SYS_CTRL_BB_FORCE_HSPLIT(n) (((n)&7)<<16) +#define SYS_CTRL_BB_FORCE_HSPLIT_MASK (7<<16) +#define SYS_CTRL_BB_FORCE_HSPLIT_SHIFT (16) + +//XCpu_Dbg_BKP +#define SYS_CTRL_BKPT_EN (1<<0) +#define SYS_CTRL_BKPT_MODE(n) (((n)&3)<<4) +#define SYS_CTRL_BKPT_MODE_I (0<<4) +#define SYS_CTRL_BKPT_MODE_R (1<<4) +#define SYS_CTRL_BKPT_MODE_W (2<<4) +#define SYS_CTRL_BKPT_MODE_RW (3<<4) +#define SYS_CTRL_STALLED (1<<8) + +//XCpu_Dbg_Addr +#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0) + +//BCpu_Dbg_BKP +//#define SYS_CTRL_BKPT_EN (1<<0) +//#define SYS_CTRL_BKPT_MODE(n) (((n)&3)<<4) +//#define SYS_CTRL_BKPT_MODE_I (0<<4) +//#define SYS_CTRL_BKPT_MODE_R (1<<4) +//#define SYS_CTRL_BKPT_MODE_W (2<<4) +//#define SYS_CTRL_BKPT_MODE_RW (3<<4) +//#define SYS_CTRL_STALLED (1<<8) + +//BCpu_Dbg_Addr +//#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0) + +//Cfg_Cpus_Cache_Ram_Disable +#define SYS_CTRL_XCPU_USE_MODE (1<<0) +#define SYS_CTRL_XCPU_CLK_OFF_MODE (1<<1) +#define SYS_CTRL_BCPU_USE_MODE (1<<16) +#define SYS_CTRL_BCPU_CLK_OFF_MODE (1<<17) +#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<0) +#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_MASK (3<<0) +#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_SHIFT (0) +#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<16) +#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_MASK (3<<16) +#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_SHIFT (16) + +//Reset_Cause +#define SYS_CTRL_WATCHDOG_RESET_HAPPENED (1<<0) +#define SYS_CTRL_WATCHDOG_RESET_NO (0<<0) +#define SYS_CTRL_APSOFT_RESET_HAPPENED (1<<1) +#define SYS_CTRL_APSOFT_RESET_NO (0<<1) +#define SYS_CTRL_GLOBALSOFT_RESET_HAPPENED (1<<4) +#define SYS_CTRL_GLOBALSOFT_RESET_NO (0<<4) +#define SYS_CTRL_HOSTDEBUG_RESET_HAPPENED (1<<5) +#define SYS_CTRL_HOSTDEBUG_RESET_NO (0<<5) +#define SYS_CTRL_ALARMCAUSE_HAPPENED (1<<6) +#define SYS_CTRL_ALARMCAUSE_NO (0<<6) +#define SYS_CTRL_MEMCHECKDONE_MASK (1<<7) +#define SYS_CTRL_MEMCHECKDONE_SHIFT (7) +#define SYS_CTRL_MEMCHECKDONE_DONE (1<<7) +#define SYS_CTRL_MEMCHECKDONE_RUNNING (0<<7) +#define SYS_CTRL_BOOT_MODE(n) (((n)&0xFFFF)<<8) +#define SYS_CTRL_BOOT_MODE_MASK (0xFFFF<<8) +#define SYS_CTRL_BOOT_MODE_SHIFT (8) +#define SYS_CTRL_SW_BOOT_MODE(n) (((n)&0x7F)<<24) +#define SYS_CTRL_SW_BOOT_MODE_MASK (0x7F<<24) +#define SYS_CTRL_SW_BOOT_MODE_SHIFT (24) +#define SYS_CTRL_FONCTIONAL_TEST_MODE (1<<31) + +//WakeUp +#define SYS_CTRL_FORCE_WAKEUP (1<<0) + +//AP_Ctrl +#define SYS_CTRL_AP_INT_STATUS (1<<0) +#define SYS_CTRL_AP_INT_MASK (1<<16) +#define SYS_CTRL_AP_DEEPSLEEP_EN (1<<24) + +//Ignore_Charger +#define SYS_CTRL_IGNORE_CHARGER (1<<0) + +//Clk_SYS2_Mode +#define SYS_CTRL_MODE_SYS_MPMC_AUTOMATIC (0<<0) +#define SYS_CTRL_MODE_SYS_MPMC_MANUAL (1<<0) +#define SYS_CTRL_MODE_SYS_MPMCREG_AUTOMATIC (0<<1) +#define SYS_CTRL_MODE_SYS_MPMCREG_MANUAL (1<<1) +#define SYS_CTRL_MODE_CLK_SYS2(n) (((n)&3)<<0) +#define SYS_CTRL_MODE_CLK_SYS2_MASK (3<<0) +#define SYS_CTRL_MODE_CLK_SYS2_SHIFT (0) + +//Clk_SYS2_Enable +#define SYS_CTRL_ENABLE_SYS_MPMC (1<<0) +#define SYS_CTRL_ENABLE_SYS_MPMCREG (1<<1) +#define SYS_CTRL_ENABLE_SYS_DP_BB (1<<2) +#define SYS_CTRL_ENABLE_SYS_DP_WD (1<<3) +#define SYS_CTRL_ENABLE_SYS_DP_AP (1<<4) +#define SYS_CTRL_ENABLE_CLK_SYS2(n) (((n)&31)<<0) +#define SYS_CTRL_ENABLE_CLK_SYS2_MASK (31<<0) +#define SYS_CTRL_ENABLE_CLK_SYS2_SHIFT (0) + +//Clk_SYS2_Disable +#define SYS_CTRL_DISABLE_SYS_MPMC (1<<0) +#define SYS_CTRL_DISABLE_SYS_MPMCREG (1<<1) +#define SYS_CTRL_DISABLE_SYS_DP_BB (1<<2) +#define SYS_CTRL_DISABLE_SYS_DP_WD (1<<3) +#define SYS_CTRL_DISABLE_SYS_DP_AP (1<<4) +#define SYS_CTRL_DISABLE_CLK_SYS2(n) (((n)&31)<<0) +#define SYS_CTRL_DISABLE_CLK_SYS2_MASK (31<<0) +#define SYS_CTRL_DISABLE_CLK_SYS2_SHIFT (0) + +//WD_Pll_Ctrl +#define SYS_CTRL_WD_PLL_ENABLE (1<<0) +#define SYS_CTRL_WD_PLL_ENABLE_MASK (1<<0) +#define SYS_CTRL_WD_PLL_ENABLE_SHIFT (0) +#define SYS_CTRL_WD_PLL_ENABLE_POWER_DOWN (0<<0) +#define SYS_CTRL_WD_PLL_ENABLE_ENABLE (1<<0) +#define SYS_CTRL_WD_PLL_LOCK_RESET (1<<4) +#define SYS_CTRL_WD_PLL_LOCK_RESET_MASK (1<<4) +#define SYS_CTRL_WD_PLL_LOCK_RESET_SHIFT (4) +#define SYS_CTRL_WD_PLL_LOCK_RESET_RESET (0<<4) +#define SYS_CTRL_WD_PLL_LOCK_RESET_NO_RESET (1<<4) +#define SYS_CTRL_WD_PLL_BYPASS (1<<8) +#define SYS_CTRL_WD_PLL_BYPASS_MASK (1<<8) +#define SYS_CTRL_WD_PLL_BYPASS_SHIFT (8) +#define SYS_CTRL_WD_PLL_BYPASS_PASS (0<<8) +#define SYS_CTRL_WD_PLL_BYPASS_BYPASS (1<<8) +#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE (1<<12) +#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_MASK (1<<12) +#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_SHIFT (12) +#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_ENABLE (1<<12) +#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_DISABLE (0<<12) +#define SYS_CTRL_PLL_WD_CFG(n) (((n)&4369)<<0) +#define SYS_CTRL_PLL_WD_CFG_MASK (4369<<0) +#define SYS_CTRL_PLL_WD_CFG_SHIFT (0) + +//WD_Sel_Clock +#define SYS_CTRL_WD_CLK_ADC_POL_INVERT (1<<0) +#define SYS_CTRL_WD_CLK_ADC_POL_NORMAL (0<<0) +#define SYS_CTRL_WD_SYS_SEL_FAST_SLOW (1<<4) +#define SYS_CTRL_WD_SYS_SEL_FAST_FAST (0<<4) +#define SYS_CTRL_WD_PLL_BYPASS_LOCK (1<<8) +#define SYS_CTRL_WD_PLL_LOCKED (1<<20) +#define SYS_CTRL_WD_PLL_LOCKED_MASK (1<<20) +#define SYS_CTRL_WD_PLL_LOCKED_SHIFT (20) +#define SYS_CTRL_WD_PLL_LOCKED_LOCKED (1<<20) +#define SYS_CTRL_WD_PLL_LOCKED_NOT_LOCKED (0<<20) +#define SYS_CTRL_WD_FAST_SELECTED_L (1<<24) +#define SYS_CTRL_WD_FAST_SELECTED_L_MASK (1<<24) +#define SYS_CTRL_WD_FAST_SELECTED_L_SHIFT (24) + +//WD_Rst_Set +#define SYS_CTRL_SET_WD_RST_WCPU (1<<0) +#define SYS_CTRL_SET_WD_RST_IRQ (1<<1) +#define SYS_CTRL_SET_WD_RST_DP (1<<2) +#define SYS_CTRL_SET_WD_RST_MODEM (1<<3) +#define SYS_CTRL_SET_WD_RST_A2A (1<<4) +#define SYS_CTRL_SET_WD_RST_IFC (1<<5) +#define SYS_CTRL_SET_WD_RST_SDMA (1<<6) +#define SYS_CTRL_SET_WD_RST_SLPC (1<<7) +#define SYS_CTRL_SET_WD_RST_SLPT (1<<8) +#define SYS_CTRL_SET_WD_RST_SPI1 (1<<9) +#define SYS_CTRL_SET_WD_RST_SPI2 (1<<10) +#define SYS_CTRL_SET_WD_RST_RFIF (1<<11) +#define SYS_CTRL_SET_WD_RST_COMREGS (1<<12) +#define SYS_CTRL_SET_WD_RST_TIMER (1<<13) +#define SYS_CTRL_SET_WD_RST_MPMC (1<<14) +#define SYS_CTRL_SET_WD_RST_FULL (1<<31) +#define SYS_CTRL_SET_WD_RST(n) (((n)&0x7FFF)<<0) +#define SYS_CTRL_SET_WD_RST_MASK (0x7FFF<<0) +#define SYS_CTRL_SET_WD_RST_SHIFT (0) + +//WD_Rst_Clr +#define SYS_CTRL_CLR_WD_RST_WCPU (1<<0) +#define SYS_CTRL_CLR_WD_RST_IRQ (1<<1) +#define SYS_CTRL_CLR_WD_RST_DP (1<<2) +#define SYS_CTRL_CLR_WD_RST_MODEM (1<<3) +#define SYS_CTRL_CLR_WD_RST_A2A (1<<4) +#define SYS_CTRL_CLR_WD_RST_IFC (1<<5) +#define SYS_CTRL_CLR_WD_RST_SDMA (1<<6) +#define SYS_CTRL_CLR_WD_RST_SLPC (1<<7) +#define SYS_CTRL_CLR_WD_RST_SLPT (1<<8) +#define SYS_CTRL_CLR_WD_RST_SPI1 (1<<9) +#define SYS_CTRL_CLR_WD_RST_SPI2 (1<<10) +#define SYS_CTRL_CLR_WD_RST_RFIF (1<<11) +#define SYS_CTRL_CLR_WD_RST_COMREGS (1<<12) +#define SYS_CTRL_CLR_WD_RST_TIMER (1<<13) +#define SYS_CTRL_CLR_WD_RST_MPMC (1<<14) +#define SYS_CTRL_CLR_WD_RST_FULL (1<<31) +#define SYS_CTRL_CLR_WD_RST(n) (((n)&0x7FFF)<<0) +#define SYS_CTRL_CLR_WD_RST_MASK (0x7FFF<<0) +#define SYS_CTRL_CLR_WD_RST_SHIFT (0) + +//AP_Rst_Set +#define SYS_CTRL_SET_AP_RST_0 (1<<0) +#define SYS_CTRL_SET_AP_RST_1 (1<<1) +#define SYS_CTRL_SET_AP_RST_2 (1<<2) +#define SYS_CTRL_SET_AP_RST_3 (1<<3) +#define SYS_CTRL_SET_AP_RST_4 (1<<4) +#define SYS_CTRL_SET_AP_RST(n) (((n)&31)<<0) +#define SYS_CTRL_SET_AP_RST_MASK (31<<0) +#define SYS_CTRL_SET_AP_RST_SHIFT (0) + +//AP_Rst_Clr +#define SYS_CTRL_CLR_AP_RST_0 (1<<0) +#define SYS_CTRL_CLR_AP_RST_1 (1<<1) +#define SYS_CTRL_CLR_AP_RST_2 (1<<2) +#define SYS_CTRL_CLR_AP_RST_3 (1<<3) +#define SYS_CTRL_CLR_AP_RST_4 (1<<4) +#define SYS_CTRL_CLR_AP_RST(n) (((n)&31)<<0) +#define SYS_CTRL_CLR_AP_RST_MASK (31<<0) +#define SYS_CTRL_CLR_AP_RST_SHIFT (0) + +//Clk_WD_Mode +#define SYS_CTRL_MODE_WD_WCPU (1<<0) +#define SYS_CTRL_MODE_WD_AMBA_AUTOMATIC (0<<1) +#define SYS_CTRL_MODE_WD_AMBA_MANUAL (1<<1) +#define SYS_CTRL_MODE_WD_PCLK_CONF_AUTOMATIC (0<<2) +#define SYS_CTRL_MODE_WD_PCLK_CONF_MANUAL (1<<2) +#define SYS_CTRL_MODE_WD_PCLK_DATA_AUTOMATIC (0<<3) +#define SYS_CTRL_MODE_WD_PCLK_DATA_MANUAL (1<<3) +#define SYS_CTRL_MODE_WD_A2A_AUTOMATIC (0<<4) +#define SYS_CTRL_MODE_WD_A2A_MANUAL (1<<4) +#define SYS_CTRL_MODE_WD_IFC_CH_SPI_AUTOMATIC (0<<5) +#define SYS_CTRL_MODE_WD_IFC_CH_SPI_MANUAL (1<<5) +#define SYS_CTRL_MODE_WD_MPMC_AUTOMATIC (0<<6) +#define SYS_CTRL_MODE_WD_MPMC_MANUAL (1<<6) +#define SYS_CTRL_MODE_WDD_OSC_AUTOMATIC (0<<7) +#define SYS_CTRL_MODE_WDD_OSC_MANUAL (1<<7) +#define SYS_CTRL_MODE_CLK_WD(n) (((n)&0x7F)<<1) +#define SYS_CTRL_MODE_CLK_WD_MASK (0x7F<<1) +#define SYS_CTRL_MODE_CLK_WD_SHIFT (1) + +//Clk_WD_Enable +#define SYS_CTRL_ENABLE_WD_WCPU (1<<0) +#define SYS_CTRL_ENABLE_WD_AMBA (1<<1) +#define SYS_CTRL_ENABLE_WD_PCLK_CONF (1<<2) +#define SYS_CTRL_ENABLE_WD_PCLK_DATA (1<<3) +#define SYS_CTRL_ENABLE_WD_A2A (1<<4) +#define SYS_CTRL_ENABLE_WD_IFC_CH_SPI (1<<5) +#define SYS_CTRL_ENABLE_WD_MPMC (1<<6) +#define SYS_CTRL_ENABLE_WDD_OSC (1<<7) +#define SYS_CTRL_ENABLE_WD_IRQ (1<<8) +#define SYS_CTRL_ENABLE_WD_AXI (1<<9) +#define SYS_CTRL_ENABLE_WD_DP (1<<10) +#define SYS_CTRL_ENABLE_WD_MODEM (1<<11) +#define SYS_CTRL_ENABLE_WD_COM_REGS (1<<12) +#define SYS_CTRL_ENABLE_WD_TIMER (1<<13) +#define SYS_CTRL_ENABLE_WD_SDMA (1<<14) +#define SYS_CTRL_ENABLE_WD_SLPC (1<<15) +#define SYS_CTRL_ENABLE_WD_SLPT (1<<16) +#define SYS_CTRL_ENABLE_WD_SPI1 (1<<17) +#define SYS_CTRL_ENABLE_WD_SPI2 (1<<18) +#define SYS_CTRL_ENABLE_WD_RFIF (1<<19) +#define SYS_CTRL_ENABLE_CLK_WD(n) (((n)&0xFFFFF)<<0) +#define SYS_CTRL_ENABLE_CLK_WD_MASK (0xFFFFF<<0) +#define SYS_CTRL_ENABLE_CLK_WD_SHIFT (0) + +//Clk_WD_Disable +#define SYS_CTRL_DISABLE_WD_WCPU (1<<0) +#define SYS_CTRL_DISABLE_WD_AMBA (1<<1) +#define SYS_CTRL_DISABLE_WD_PCLK_CONF (1<<2) +#define SYS_CTRL_DISABLE_WD_PCLK_DATA (1<<3) +#define SYS_CTRL_DISABLE_WD_A2A (1<<4) +#define SYS_CTRL_DISABLE_WD_IFC_CH_SPI (1<<5) +#define SYS_CTRL_DISABLE_WD_MPMC (1<<6) +#define SYS_CTRL_DISABLE_WDD_OSC (1<<7) +#define SYS_CTRL_DISABLE_WD_IRQ (1<<8) +#define SYS_CTRL_DISABLE_WD_AXI (1<<9) +#define SYS_CTRL_DISABLE_WD_DP (1<<10) +#define SYS_CTRL_DISABLE_WD_MODEM (1<<11) +#define SYS_CTRL_DISABLE_WD_COM_REGS (1<<12) +#define SYS_CTRL_DISABLE_WD_TIMER (1<<13) +#define SYS_CTRL_DISABLE_WD_SDMA (1<<14) +#define SYS_CTRL_DISABLE_WD_SLPC (1<<15) +#define SYS_CTRL_DISABLE_WD_SLPT (1<<16) +#define SYS_CTRL_DISABLE_WD_SPI1 (1<<17) +#define SYS_CTRL_DISABLE_WD_SPI2 (1<<18) +#define SYS_CTRL_DISABLE_WD_RFIF (1<<19) +#define SYS_CTRL_DISABLE_CLK_WD(n) (((n)&0xFFFFF)<<0) +#define SYS_CTRL_DISABLE_CLK_WD_MASK (0xFFFFF<<0) +#define SYS_CTRL_DISABLE_CLK_WD_SHIFT (0) + +//Cfg_Clk_MPMC +#define SYS_CTRL_MPMC_FREQ(n) (((n)&15)<<0) +#define SYS_CTRL_MPMC_FREQ_MASK (15<<0) +#define SYS_CTRL_MPMC_FREQ_SHIFT (0) +#define SYS_CTRL_MPMC_FREQ_312M (13<<0) +#define SYS_CTRL_MPMC_FREQ_250M (12<<0) +#define SYS_CTRL_MPMC_FREQ_208M (11<<0) +#define SYS_CTRL_MPMC_FREQ_178M (10<<0) +#define SYS_CTRL_MPMC_FREQ_156M (9<<0) +#define SYS_CTRL_MPMC_FREQ_139M (8<<0) +#define SYS_CTRL_MPMC_FREQ_125M (7<<0) +#define SYS_CTRL_MPMC_FREQ_113M (6<<0) +#define SYS_CTRL_MPMC_FREQ_104M (5<<0) +#define SYS_CTRL_MPMC_FREQ_89M (4<<0) +#define SYS_CTRL_MPMC_FREQ_78M (3<<0) +#define SYS_CTRL_MPMC_FREQ_52M (2<<0) +#define SYS_CTRL_MPMC_FREQ_39M (1<<0) +#define SYS_CTRL_MPMC_FREQ_26M (0<<0) +#define SYS_CTRL_CLK_MPMC_DELAY(n) (((n)&31)<<8) +#define SYS_CTRL_CLK_MPMC_DELAY_POL (1<<13) +#define SYS_CTRL_CLK_MPMC_FEEDBACK(n) (((n)&31)<<14) +#define SYS_CTRL_CLK_MPMC_FEEDBACK_POL (1<<19) +#define SYS_CTRL_MPMC_REQ_DIV_UPDATE (1<<31) + +//Cfg_MPMC_DQS +#define SYS_CTRL_MPMC_DQSL_O(n) (((n)&31)<<0) +#define SYS_CTRL_MPMC_DQSU_O(n) (((n)&31)<<6) +#define SYS_CTRL_MPMC_DQS_OEN(n) (((n)&31)<<12) +#define SYS_CTRL_MPMC_DQSL_I(n) (((n)&31)<<18) +#define SYS_CTRL_MPMC_DQSU_I(n) (((n)&31)<<24) + +//Cfg_Reserve +#define SYS_CTRL_RESERVE(n) (((n)&0x3FFF)<<0) +#define SYS_CTRL_AUIFC_CH0_IRQ_MASK (1<<14) +#define SYS_CTRL_AUIFC_CH1_IRQ_MASK (1<<15) +#define SYS_CTRL_RESERVE2(n) (((n)&0xFFFF)<<16) + + + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_mdcom.h b/arch/arm/include/asm/arch-rda/reg_mdcom.h new file mode 100644 index 0000000000..a9223a4f21 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_mdcom.h @@ -0,0 +1,80 @@ +#ifndef _REG_MDCOM_H_ +#define _REG_MDCOM_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +typedef volatile struct +{ + REG32 Snapshot; //0x00000000 + REG32 Snapshot_Cfg; //0x00000004 + REG32 Cause; //0x00000008 + REG32 Mask_Set; //0x0000000C + REG32 Mask_Clr; //0x00000010 + /// If accesses to ItReg_Set and ItReg_Clr registers are done simultaneously + /// from both CPUs and affecting the same bits, the priority is given to set + /// a bit. + REG32 ItReg_Set; //0x00000014 + /// If accesses to ItReg_Set and ItReg_Clr registers are done simultaneously + /// from both CPUs and affecting the same bits, the priority is given to set + /// a bit. + REG32 ItReg_Clr; //0x00000018 +} HWP_COMREGS_T; + +#define hwp_mdComregs ((HWP_COMREGS_T*)(RDA_COMREGS_BASE)) + + +//Snapshot +#define COMREGS_SNAPSHOT(n) (((n)&3)<<0) + +//Snapshot_Cfg +#define COMREGS_SNAPSHOT_CFG_WRAP_2 (2<<0) +#define COMREGS_SNAPSHOT_CFG_WRAP_3 (3<<0) + +//Cause +#define COMREGS_IRQ0_CAUSE(n) (((n)&0xFF)<<0) +#define COMREGS_IRQ0_CAUSE_MASK (0xFF<<0) +#define COMREGS_IRQ0_CAUSE_SHIFT (0) +#define COMREGS_IRQ1_CAUSE(n) (((n)&0xFF)<<8) +#define COMREGS_IRQ1_CAUSE_MASK (0xFF<<8) +#define COMREGS_IRQ1_CAUSE_SHIFT (8) + +//Mask_Set +#define COMREGS_IRQ0_MASK_SET(n) (((n)&0xFF)<<0) +#define COMREGS_IRQ0_MASK_SET_MASK (0xFF<<0) +#define COMREGS_IRQ0_MASK_SET_SHIFT (0) +#define COMREGS_IRQ1_MASK_SET(n) (((n)&0xFF)<<8) +#define COMREGS_IRQ1_MASK_SET_MASK (0xFF<<8) +#define COMREGS_IRQ1_MASK_SET_SHIFT (8) + +//Mask_Clr +#define COMREGS_IRQ0_MASK_CLR(n) (((n)&0xFF)<<0) +#define COMREGS_IRQ0_MASK_CLR_MASK (0xFF<<0) +#define COMREGS_IRQ0_MASK_CLR_SHIFT (0) +#define COMREGS_IRQ1_MASK_CLR(n) (((n)&0xFF)<<8) +#define COMREGS_IRQ1_MASK_CLR_MASK (0xFF<<8) +#define COMREGS_IRQ1_MASK_CLR_SHIFT (8) + +//ItReg_Set +#define COMREGS_IRQ0_SET(n) (((n)&0xFF)<<0) +#define COMREGS_IRQ0_SET_MASK (0xFF<<0) +#define COMREGS_IRQ0_SET_SHIFT (0) +#define COMREGS_IRQ1_SET(n) (((n)&0xFF)<<8) +#define COMREGS_IRQ1_SET_MASK (0xFF<<8) +#define COMREGS_IRQ1_SET_SHIFT (8) +#define COMREGS_IRQ(n) (((n)&0xFFFF)<<0) +#define COMREGS_IRQ_MASK (0xFFFF<<0) +#define COMREGS_IRQ_SHIFT (0) + +//ItReg_Clr +#define COMREGS_IRQ0_CLR(n) (((n)&0xFF)<<0) +#define COMREGS_IRQ0_CLR_MASK (0xFF<<0) +#define COMREGS_IRQ0_CLR_SHIFT (0) +#define COMREGS_IRQ1_CLR(n) (((n)&0xFF)<<8) +#define COMREGS_IRQ1_CLR_MASK (0xFF<<8) +#define COMREGS_IRQ1_CLR_SHIFT (8) +//#define COMREGS_IRQ(n) (((n)&0xFFFF)<<0) +//#define COMREGS_IRQ_MASK (0xFFFF<<0) +//#define COMREGS_IRQ_SHIFT (0) + +#endif diff --git a/arch/arm/include/asm/arch-rda/reg_mmc.h b/arch/arm/include/asm/arch-rda/reg_mmc.h new file mode 100644 index 0000000000..87d8e3e3c3 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_mmc.h @@ -0,0 +1,245 @@ +#ifndef _REG_SDMMC_H_ +#define _REG_SDMMC_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================ +// SDMMC_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + REG32 apbi_ctrl_sdmmc; //0x00000000 + REG32 Reserved_00000004; //0x00000004 + REG32 APBI_FIFO_TxRx; //0x00000008 + REG32 Reserved_0000000C[509]; //0x0000000C + REG32 SDMMC_CONFIG; //0x00000800 + REG32 SDMMC_STATUS; //0x00000804 + REG32 SDMMC_CMD_INDEX; //0x00000808 + REG32 SDMMC_CMD_ARG; //0x0000080C + REG32 SDMMC_RESP_INDEX; //0x00000810 + REG32 SDMMC_RESP_ARG3; //0x00000814 + REG32 SDMMC_RESP_ARG2; //0x00000818 + REG32 SDMMC_RESP_ARG1; //0x0000081C + REG32 SDMMC_RESP_ARG0; //0x00000820 + REG32 SDMMC_DATA_WIDTH; //0x00000824 + REG32 SDMMC_BLOCK_SIZE; //0x00000828 + REG32 SDMMC_BLOCK_CNT; //0x0000082C + REG32 SDMMC_INT_STATUS; //0x00000830 + REG32 SDMMC_INT_MASK; //0x00000834 + REG32 SDMMC_INT_CLEAR; //0x00000838 + REG32 SDMMC_TRANS_SPEED; //0x0000083C + REG32 SDMMC_MCLK_ADJUST; //0x00000840 +} HWP_SDMMC_T; + +//apbi_ctrl_sdmmc +#define SDMMC_L_ENDIAN(n) (((n)&7)<<0) +#define SDMMC_SOFT_RST_L (1<<3) + +//APBI_FIFO_TxRx +#define SDMMC_DATA_IN(n) (((n)&0xFFFFFFFF)<<0) +#define SDMMC_DATA_OUT(n) (((n)&0xFFFFFFFF)<<0) + +//SDMMC_CONFIG +#define SDMMC_SDMMC_SENDCMD (1<<0) +#define SDMMC_SDMMC_SUSPEND (1<<1) +#define SDMMC_RSP_EN (1<<4) +#define SDMMC_RSP_SEL(n) (((n)&3)<<5) +#define SDMMC_RSP_SEL_R2 (2<<5) +#define SDMMC_RSP_SEL_R3 (1<<5) +#define SDMMC_RSP_SEL_OTHER (0<<5) +#define SDMMC_RD_WT_EN (1<<8) +#define SDMMC_RD_WT_SEL (1<<9) +#define SDMMC_RD_WT_SEL_READ (0<<9) +#define SDMMC_RD_WT_SEL_WRITE (1<<9) +#define SDMMC_S_M_SEL (1<<10) +#define SDMMC_S_M_SEL_SIMPLE (0<<10) +#define SDMMC_S_M_SEL_MULTIPLE (1<<10) +#define SDMMC_AUTO_FLAG_EN (1<<16) + +//SDMMC_STATUS +#define SDMMC_NOT_SDMMC_OVER (1<<0) +#define SDMMC_BUSY (1<<1) +#define SDMMC_DL_BUSY (1<<2) +#define SDMMC_SUSPEND (1<<3) +#define SDMMC_RSP_ERROR (1<<8) +#define SDMMC_NO_RSP_ERROR (1<<9) +#define SDMMC_CRC_STATUS(n) (((n)&7)<<12) +#define SDMMC_DATA_ERROR(n) (((n)&0xFF)<<16) +#define SDMMC_DAT3_VAL (1<<24) +#define SDMMC_DATA0_VAL (1 << 26) + +//SDMMC_CMD_INDEX +#define SDMMC_COMMAND(n) (((n)&0x3F)<<0) + +//SDMMC_CMD_ARG +#define SDMMC_ARGUMENT(n) (((n)&0xFFFFFFFF)<<0) + +//SDMMC_RESP_INDEX +#define SDMMC_RESPONSE(n) (((n)&0x3F)<<0) + +//SDMMC_RESP_ARG3 +#define SDMMC_ARGUMENT3(n) (((n)&0xFFFFFFFF)<<0) + +//SDMMC_RESP_ARG2 +#define SDMMC_ARGUMENT2(n) (((n)&0xFFFFFFFF)<<0) + +//SDMMC_RESP_ARG1 +#define SDMMC_ARGUMENT1(n) (((n)&0xFFFFFFFF)<<0) + +//SDMMC_RESP_ARG0 +#define SDMMC_ARGUMENT0(n) (((n)&0xFFFFFFFF)<<0) + +//SDMMC_DATA_WIDTH +#define SDMMC_SDMMC_DATA_WIDTH(n) (((n)&15)<<0) + +//SDMMC_BLOCK_SIZE +#define SDMMC_SDMMC_BLOCK_SIZE(n) (((n)&15)<<0) + +//SDMMC_BLOCK_CNT +#define SDMMC_SDMMC_BLOCK_CNT(n) (((n)&0xFFFF)<<0) + +//SDMMC_INT_STATUS +#define SDMMC_NO_RSP_INT (1<<0) +#define SDMMC_RSP_ERR_INT (1<<1) +#define SDMMC_RD_ERR_INT (1<<2) +#define SDMMC_WR_ERR_INT (1<<3) +#define SDMMC_DAT_OVER_INT (1<<4) +#define SDMMC_TXDMA_DONE_INT (1<<5) +#define SDMMC_RXDMA_DONE_INT (1<<6) +#define SDMMC_NO_RSP_SC (1<<8) +#define SDMMC_RSP_ERR_SC (1<<9) +#define SDMMC_RD_ERR_SC (1<<10) +#define SDMMC_WR_ERR_SC (1<<11) +#define SDMMC_DAT_OVER_SC (1<<12) +#define SDMMC_TXDMA_DONE_SC (1<<13) +#define SDMMC_RXDMA_DONE_SC (1<<14) + +//SDMMC_INT_MASK +#define SDMMC_NO_RSP_MK (1<<0) +#define SDMMC_RSP_ERR_MK (1<<1) +#define SDMMC_RD_ERR_MK (1<<2) +#define SDMMC_WR_ERR_MK (1<<3) +#define SDMMC_DAT_OVER_MK (1<<4) +#define SDMMC_TXDMA_DONE_MK (1<<5) +#define SDMMC_RXDMA_DONE_MK (1<<6) + +//SDMMC_INT_CLEAR +#define SDMMC_NO_RSP_CL (1<<0) +#define SDMMC_RSP_ERR_CL (1<<1) +#define SDMMC_RD_ERR_CL (1<<2) +#define SDMMC_WR_ERR_CL (1<<3) +#define SDMMC_DAT_OVER_CL (1<<4) +#define SDMMC_TXDMA_DONE_CL (1<<5) +#define SDMMC_RXDMA_DONE_CL (1<<6) + +//SDMMC_TRANS_SPEED +#define SDMMC_SDMMC_TRANS_SPEED(n) (((n)&0xFF)<<0) + +//SDMMC_MCLK_ADJUST +#define SDMMC_SDMMC_MCLK_ADJUST(n) (((n)&15)<<0) +#define SDMMC_CLK_INV (1<<4) + +// ============================================================================= +// MACROS +// ============================================================================= +// ============================================================================= +// HAL_SDMMC_ACMD_SEL +// ----------------------------------------------------------------------------- +/// Macro to mark a command as application specific +// ============================================================================= +#define HAL_SDMMC_ACMD_SEL 0x80000000 + + +// ============================================================================= +// HAL_SDMMC_CMD_MASK +// ----------------------------------------------------------------------------- +/// Mask to get from a HAL_SDMMC_CMD_T value the corresponding +/// command index +// ============================================================================= +#define HAL_SDMMC_CMD_MASK 0x3F + + + +// ============================================================================= +// HAL_SDMMC_CMD_T +// ----------------------------------------------------------------------------- +// SD commands +// ============================================================================= +typedef enum +{ + HAL_SDMMC_CMD_GO_IDLE_STATE = 0, + HAL_SDMMC_CMD_MMC_SEND_OP_COND = 1, + HAL_SDMMC_CMD_ALL_SEND_CID = 2, + HAL_SDMMC_CMD_SEND_RELATIVE_ADDR = 3, + HAL_SDMMC_CMD_SET_DSR = 4, + HAL_SDMMC_CMD_SWITCH = 6, + HAL_SDMMC_CMD_SELECT_CARD = 7, + HAL_SDMMC_CMD_SEND_IF_COND = 8, + HAL_SDMMC_CMD_SEND_CSD = 9, + HAL_SDMMC_CMD_STOP_TRANSMISSION = 12, + HAL_SDMMC_CMD_SEND_STATUS = 13, + HAL_SDMMC_CMD_SET_BLOCKLEN = 16, + HAL_SDMMC_CMD_READ_SINGLE_BLOCK = 17, + HAL_SDMMC_CMD_READ_MULT_BLOCK = 18, + HAL_SDMMC_CMD_WRITE_SINGLE_BLOCK = 24, + HAL_SDMMC_CMD_WRITE_MULT_BLOCK = 25, + HAL_SDMMC_CMD_APP_CMD = 55, + HAL_SDMMC_CMD_SET_BUS_WIDTH = (6 | HAL_SDMMC_ACMD_SEL), + HAL_SDMMC_CMD_SEND_NUM_WR_BLOCKS = (22| HAL_SDMMC_ACMD_SEL), + HAL_SDMMC_CMD_SET_WR_BLK_COUNT = (23| HAL_SDMMC_ACMD_SEL), + HAL_SDMMC_CMD_SEND_OP_COND = (41| HAL_SDMMC_ACMD_SEL) +} HAL_SDMMC_CMD_T; + +// ============================================================================= +// HAL_SDMMC_OP_STATUS_T +// ----------------------------------------------------------------------------- +/// This structure is used the module operation status. It is different from the +/// IRQ status. +// ============================================================================= +typedef union +{ + u32 reg; + struct + { + u32 operationNotOver :1; + /// Module is busy ? + u32 busy :1; + u32 dataLineBusy :1; + /// '1' means the controller will not perform the new command when SDMMC_SENDCMD= '1'. + u32 suspend :1; + u32 :4; + u32 responseCrcError :1; + /// 1 as long as no reponse to a command has been received. + u32 noResponseReceived :1; + u32 :2; + /// CRC check for SD/MMC write operation + /// "101" transmission error + /// "010" transmission right + /// "111" flash programming error + u32 crcStatus :3; + u32 :1; + /// 8 bits data CRC check, "00000000" means no data error, + /// "00000001" means DATA0 CRC check error, "10000000" means + /// DATA7 CRC check error, each bit match one data line. + u32 dataError :8; + } fields; +} HAL_SDMMC_OP_STATUS_T; + +typedef enum +{ + HAL_SDMMC_DIRECTION_READ, + HAL_SDMMC_DIRECTION_WRITE, + HAL_SDMMC_DIRECTION_QTY +} HAL_SDMMC_DIRECTION_T; + +typedef enum +{ + HAL_SDMMC_DATA_BUS_WIDTH_1 = 0x0, + HAL_SDMMC_DATA_BUS_WIDTH_4 = 0x2 +} HAL_SDMMC_DATA_BUS_WIDTH_T; + +#endif /* _REG_SDMMC_H_ */ + diff --git a/arch/arm/include/asm/arch-rda/reg_nand.h b/arch/arm/include/asm/arch-rda/reg_nand.h new file mode 100644 index 0000000000..5fd490c606 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_nand.h @@ -0,0 +1,17 @@ +#ifndef _REG_NAND_H_ +#define _REG_NAND_H_ + +#include <common.h> + +#ifdef CONFIG_NAND_RDA_V1 +#include "reg_nand_v1.h" +#elif defined(CONFIG_NAND_RDA_V2) +#include "reg_nand_v2.h" +#elif defined(CONFIG_NAND_RDA_V3) +#include "reg_nand_v3.h" +#else +#error "undefined RDA NAND Controller Version" +#endif + +#endif /* _REG_NAND_H_ */ + diff --git a/arch/arm/include/asm/arch-rda/reg_nand_v1.h b/arch/arm/include/asm/arch-rda/reg_nand_v1.h new file mode 100644 index 0000000000..8b5b5ddb13 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_nand_v1.h @@ -0,0 +1,106 @@ +#ifndef _REG_NAND_V1_H_ +#define _REG_NAND_V1_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +#define REG_NANDFC_BASE RDA_NAND_BASE + +#define NANDFC_DATA_BUF (REG_NANDFC_BASE + 0x0000) +#define NANDFC_OOB_BUF (REG_NANDFC_BASE + 0x1000) + +#if defined(CONFIG_MACH_RDA8810) || defined(CONFIG_MACH_RDA8850) || \ + defined(CONFIG_MACH_RDAARM926EJS) +#define NANDFC_REG_DCMD_ADDR (REG_NANDFC_BASE + 0x2000) +//#define NANDFC_REG_OP_START (REG_NANDFC_BASE + 0x2004) +//#define NANDFC_REG_CMD_PTR (REG_NANDFC_BASE + 0x2008) +#define NANDFC_REG_COL_ADDR (REG_NANDFC_BASE + 0x200c) +#define NANDFC_REG_CONFIG_A (REG_NANDFC_BASE + 0x2010) +#define NANDFC_REG_CONFIG_B (REG_NANDFC_BASE + 0x2014) +#define NANDFC_REG_BUF_CTRL (REG_NANDFC_BASE + 0x2018) +#define NANDFC_REG_BUSY_FLAG (REG_NANDFC_BASE + 0x201c) +#define NANDFC_REG_INT_MASK (REG_NANDFC_BASE + 0x2020) +#define NANDFC_REG_INT_STAT (REG_NANDFC_BASE + 0x2024) +#define NANDFC_REG_IDCODE_A (REG_NANDFC_BASE + 0x2028) +#define NANDFC_REG_IDCODE_B (REG_NANDFC_BASE + 0x202c) +//#define NANDFC_REG_DMA_REQ (REG_NANDFC_BASE + 0x2030) +//#define NANDFC_REG_CMD_DEF_A (REG_NANDFC_BASE + 0x2034) +#define NANDFC_REG_CMD_DEF_B (REG_NANDFC_BASE + 0x2038) +#define NANDFC_REG_OP_STATUS (REG_NANDFC_BASE + 0x203c) +#define NANDFC_REG_IDTPYE (REG_NANDFC_BASE + 0x2040) +#define NANDFC_REG_DELAY (REG_NANDFC_BASE + 0x2054) +#else +/* for 8810e, 8820, or later */ +#define NANDFC_REG_DCMD_ADDR (REG_NANDFC_BASE + 0x3000) +//#define NANDFC_REG_OP_START (REG_NANDFC_BASE + 0x3004) +//#define NANDFC_REG_CMD_PTR (REG_NANDFC_BASE + 0x3008) +#define NANDFC_REG_COL_ADDR (REG_NANDFC_BASE + 0x300c) +#define NANDFC_REG_CONFIG_A (REG_NANDFC_BASE + 0x3010) +#define NANDFC_REG_CONFIG_B (REG_NANDFC_BASE + 0x3014) +#define NANDFC_REG_BUF_CTRL (REG_NANDFC_BASE + 0x3018) +#define NANDFC_REG_BUSY_FLAG (REG_NANDFC_BASE + 0x301c) +#define NANDFC_REG_INT_MASK (REG_NANDFC_BASE + 0x3020) +#define NANDFC_REG_INT_STAT (REG_NANDFC_BASE + 0x3024) +#define NANDFC_REG_IDCODE_A (REG_NANDFC_BASE + 0x3028) +#define NANDFC_REG_IDCODE_B (REG_NANDFC_BASE + 0x302c) +//#define NANDFC_REG_DMA_REQ (REG_NANDFC_BASE + 0x3030) +//#define NANDFC_REG_CMD_DEF_A (REG_NANDFC_BASE + 0x3034) +//#define NANDFC_REG_CMD_DEF_B (REG_NANDFC_BASE + 0x3038) +#define NANDFC_REG_OP_STATUS (REG_NANDFC_BASE + 0x303c) +#define NANDFC_REG_IDTPYE (REG_NANDFC_BASE + 0x3040) +#define NANDFC_REG_DELAY (REG_NANDFC_BASE + 0x3054) +#endif + +// NANDFC_REG_DCMD_ADDR +#define NANDFC_DCMD(n) (((n)&0xFF)<<24) +#define NANDFC_PAGE_ADDR(n) (((n)&0x000FFFFF)<<0) + +// NANDFC_REG_CONFIG_A +#define NANDFC_CYCLE(n) (((n)&0x0F)<<0) +#define NANDFC_CHIP_SEL(n) (((n)&0x0F)<<4) +#define NANDFC_TIMING(n) (((n)&0xFF)<<8) +#define NANDFC_POLARITY_IO(n) (((n)&0x01)<<16) +#define NANDFC_POLARITY_MEM(n) (((n)&0x01)<<17) +#define NANDFC_WDITH_16BIT(n) (((n)&0x01)<<18) + +// NANDFC_REG_CONFIG_B +#define NANDFC_HWECC(n) (((n)&0x01)<<7) +#define NANDFC_ECC_MODE(n) (((n)&0x0F)<<0) + +// NANDFC_REG_BUF_CTRL +#define NANDFC_BUF_DIRECT(n) (((n)&0x01)<<2) + +// NANDFC_REG_INT_STAT +#define NANDFC_INT_ECC_ERR (1<<0) +#define NANDFC_INT_PROG_ERR (1<<1) +#define NANDFC_INT_ERASE_ERR (1<<2) +#define NANDFC_INT_TIMEOUT (1<<3) +#define NANDFC_INT_DONE (1<<4) +#define NANDFC_INT_CRC_FAIL (1<<5) +#define NANDFC_INT_ECC_ERR_0 (1<<6) +#define NANDFC_INT_ECC_ERR_1 (1<<7) +#define NANDFC_INT_ECC_ERR_2 (1<<8) +#define NANDFC_INT_ECC_CRC_0 (1<<9) +#define NANDFC_INT_ECC_CRC_1 (1<<10) +#define NANDFC_INT_ECC_CRC_2 (1<<11) +#define NANDFC_INT_ERR_ALL (0x0FEF) +#define NANDFC_INT_CLR_MASK (0x0FDE) + +typedef enum +{ + NAND_TYPE_512S = 0, // 512+16, 64Mb, 128Mb, 256Mb + NAND_TYPE_512L = 1, // 512+16, 512Mb, 1Gb, 2Gb + NAND_TYPE_2KS = 2, // 2048+64, 1Gb (2 byte Row addresses) + NAND_TYPE_2KL = 3, // 2048+64, 2Gb, 4Gb, 8Gb, 16Gb (3 byte Row Addresses) + NAND_TYPE_MLC2K = 4, // MLC, 2048+64 + NAND_TYPE_MLC4K = 5, // MLC, 4096+224, 16Gb, 32Gb + NAND_TYPE_SLC4K = 6, // SLC, 4096+224, 16Gb, 32Gb + NAND_TYPE_MLC8K = 7, // MLC, 8192+224, 16Gb, 32Gb + NAND_TYPE_SLC8K = 8, // SLC, 8192+224, 16Gb, 32Gb + NAND_TYPE_MLC16K = 9, // MLC, + NAND_TYPE_SLC16K = 10, // SLC, + NAND_TYPE_INVALID = 0xff +} NAND_FLASH_TYPE; + +#endif /* _REG_NAND_V1_H_ */ + diff --git a/arch/arm/include/asm/arch-rda/reg_nand_v2.h b/arch/arm/include/asm/arch-rda/reg_nand_v2.h new file mode 100644 index 0000000000..78c68e916b --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_nand_v2.h @@ -0,0 +1,111 @@ +#ifndef _REG_NAND_V2_H_ +#define _REG_NAND_V2_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +#define REG_NANDFC_BASE RDA_NAND_BASE + +#define NANDFC_DATA_BUF (REG_NANDFC_BASE + 0x0000) +#define NANDFC_OOB_BUF (REG_NANDFC_BASE + 0x1000) + +#if defined(CONFIG_MACH_RDA8810) || defined(CONFIG_MACH_RDA8850) || \ + defined(CONFIG_MACH_RDAARM926EJS) +#define NANDFC_REG_DCMD_ADDR (REG_NANDFC_BASE + 0x2000) +//#define NANDFC_REG_OP_START (REG_NANDFC_BASE + 0x2004) +//#define NANDFC_REG_CMD_PTR (REG_NANDFC_BASE + 0x2008) +#define NANDFC_REG_COL_ADDR (REG_NANDFC_BASE + 0x200c) +#define NANDFC_REG_CONFIG_A (REG_NANDFC_BASE + 0x2010) +#define NANDFC_REG_CONFIG_B (REG_NANDFC_BASE + 0x2014) +#define NANDFC_REG_BUF_CTRL (REG_NANDFC_BASE + 0x2018) +#define NANDFC_REG_BUSY_FLAG (REG_NANDFC_BASE + 0x201c) +#define NANDFC_REG_INT_MASK (REG_NANDFC_BASE + 0x2020) +#define NANDFC_REG_INT_STAT (REG_NANDFC_BASE + 0x2024) +#define NANDFC_REG_IDCODE_A (REG_NANDFC_BASE + 0x2028) +#define NANDFC_REG_IDCODE_B (REG_NANDFC_BASE + 0x202c) +//#define NANDFC_REG_DMA_REQ (REG_NANDFC_BASE + 0x2030) +//#define NANDFC_REG_CMD_DEF_A (REG_NANDFC_BASE + 0x2034) +//#define NANDFC_REG_CMD_DEF_B (REG_NANDFC_BASE + 0x2038) +#define NANDFC_REG_OP_STATUS (REG_NANDFC_BASE + 0x203c) +#define NANDFC_REG_IDTPYE (REG_NANDFC_BASE + 0x2040) +#define NANDFC_REG_DELAY (REG_NANDFC_BASE + 0x2054) +#else +/* for 8810e, 8820, or later */ +#define NANDFC_REG_DCMD_ADDR (REG_NANDFC_BASE + 0x3000) +//#define NANDFC_REG_OP_START (REG_NANDFC_BASE + 0x3004) +//#define NANDFC_REG_CMD_PTR (REG_NANDFC_BASE + 0x3008) +#define NANDFC_REG_COL_ADDR (REG_NANDFC_BASE + 0x300c) +#define NANDFC_REG_CONFIG_A (REG_NANDFC_BASE + 0x3010) +#define NANDFC_REG_CONFIG_B (REG_NANDFC_BASE + 0x3014) +#define NANDFC_REG_BUF_CTRL (REG_NANDFC_BASE + 0x3018) +#define NANDFC_REG_BUSY_FLAG (REG_NANDFC_BASE + 0x301c) +#define NANDFC_REG_INT_MASK (REG_NANDFC_BASE + 0x3020) +#define NANDFC_REG_INT_STAT (REG_NANDFC_BASE + 0x3024) +#define NANDFC_REG_IDCODE_A (REG_NANDFC_BASE + 0x3028) +#define NANDFC_REG_IDCODE_B (REG_NANDFC_BASE + 0x302c) +//#define NANDFC_REG_DMA_REQ (REG_NANDFC_BASE + 0x3030) +//#define NANDFC_REG_CMD_DEF_A (REG_NANDFC_BASE + 0x3034) +//#define NANDFC_REG_CMD_DEF_B (REG_NANDFC_BASE + 0x3038) +#define NANDFC_REG_OP_STATUS (REG_NANDFC_BASE + 0x303c) +#define NANDFC_REG_IDTPYE (REG_NANDFC_BASE + 0x3040) +#define NANDFC_REG_DELAY (REG_NANDFC_BASE + 0x3054) +#endif + +// NANDFC_REG_DCMD_ADDR +#define NANDFC_DCMD(n) (((n)&0xFF)<<24) +#define NANDFC_PAGE_ADDR(n) (((n)&0x000FFFFF)<<0) + +// NANDFC_REG_CONFIG_A +#define NANDFC_CYCLE(n) (((n)&0x0F)<<0) +#define NANDFC_CHIP_SEL(n) (((n)&0x0F)<<4) +#define NANDFC_TIMING(n) (((n)&0xFF)<<8) +#define NANDFC_POLARITY_IO(n) (((n)&0x01)<<16) +#define NANDFC_POLARITY_MEM(n) (((n)&0x01)<<17) +#define NANDFC_WDITH_16BIT(n) (((n)&0x01)<<18) + +// NANDFC_REG_CONFIG_B +#define NANDFC_HWECC(n) (((n)&0x01)<<7) +#define NANDFC_ECC_MODE(n) (((n)&0x0F)<<0) + +// NANDFC_REG_BUF_CTRL +#define NANDFC_BUF_DIRECT(n) (((n)&0x01)<<2) + +// NANDFC_REG_INT_STAT +#define NANDFC_INT_ECC_ERR (1<<0) +#define NANDFC_INT_PROG_ERR (1<<1) +#define NANDFC_INT_ERASE_ERR (1<<2) +#define NANDFC_INT_TIMEOUT (1<<3) +#define NANDFC_INT_DONE (1<<4) +#define NANDFC_INT_CRC_FAIL (1<<5) +#define NANDFC_INT_ECC_ERR_0 (1<<6) +#define NANDFC_INT_ECC_ERR_1 (1<<7) +#define NANDFC_INT_ECC_ERR_2 (1<<8) +#define NANDFC_INT_ECC_CRC_0 (1<<9) +#define NANDFC_INT_ECC_CRC_1 (1<<10) +#define NANDFC_INT_ECC_CRC_2 (1<<11) +#define NANDFC_INT_STAT_IDLE (1<<21) +#define NANDFC_INT_ERR_ALL (0x01EF) /* CRC bits do not work anymore */ +#define NANDFC_INT_CLR_MASK (0x0FDE) + +typedef enum +{ + NAND_TYPE_2K = 0, // support 3 byte Row Addresses only + NAND_TYPE_4K = 1, + NAND_TYPE_8K = 2, + NAND_TYPE_INVALID = 0xff +} NAND_FLASH_TYPE; + +typedef enum +{ + NAND_ECC_2K24BIT = 0, // support 2K nand only + NAND_ECC_RESERVE = 1, + NAND_ECC_1K96BIT = 2, // 4K use as 3K or 8K use as 6K + NAND_ECC_1K64BIT = 3, // 8K only, use as 8K, need 7xx spare, leave 1x oob + NAND_ECC_1K56BIT = 4, // 8K only, use as 8K, need 7xx spare, leave more oob + NAND_ECC_1K40BIT = 5, // 8K only, use as 8K, need 6xx spare + NAND_ECC_1K24BIT = 6, // 4K/8K, 4K need 224 spare + NAND_ECC_INVALID = 0xFF, +} NAND_ECC_TYPE; + +#endif /* _REG_NAND_V2_H_ */ + diff --git a/arch/arm/include/asm/arch-rda/reg_nand_v3.h b/arch/arm/include/asm/arch-rda/reg_nand_v3.h new file mode 100644 index 0000000000..042c88bf06 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_nand_v3.h @@ -0,0 +1,151 @@ +#ifndef _REG_NAND_V3_H_ +#define _REG_NAND_V3_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +#define REG_NANDFC_BASE RDA_NAND_BASE + +#define NANDFC_DATA_BUF (REG_NANDFC_BASE + 0x0000) +#define NANDFC_OOB_BUF (REG_NANDFC_BASE + 0x1000) + +/* for 8810e, 8820, or later */ +#define NANDFC_REG_DCMD_ADDR (REG_NANDFC_BASE + 0x3000) +//#define NANDFC_REG_OP_START (REG_NANDFC_BASE + 0x3004) +//#define NANDFC_REG_CMD_PTR (REG_NANDFC_BASE + 0x3008) +#define NANDFC_REG_COL_ADDR (REG_NANDFC_BASE + 0x300c) +#define NANDFC_REG_CONFIG_A (REG_NANDFC_BASE + 0x3010) +#define NANDFC_REG_CONFIG_B (REG_NANDFC_BASE + 0x3014) +#define NANDFC_REG_BUF_CTRL (REG_NANDFC_BASE + 0x3018) +#define NANDFC_REG_BUSY_FLAG (REG_NANDFC_BASE + 0x301c) +#define NANDFC_REG_INT_MASK (REG_NANDFC_BASE + 0x3020) +#define NANDFC_REG_INT_STAT (REG_NANDFC_BASE + 0x3024) +#define NANDFC_REG_IDCODE_A (REG_NANDFC_BASE + 0x3028) +#define NANDFC_REG_IDCODE_B (REG_NANDFC_BASE + 0x302c) +//#define NANDFC_REG_DMA_REQ (REG_NANDFC_BASE + 0x3030) +//#define NANDFC_REG_CMD_DEF_A (REG_NANDFC_BASE + 0x3034) +//#define NANDFC_REG_CMD_DEF_B (REG_NANDFC_BASE + 0x3038) +#define NANDFC_REG_OP_STATUS (REG_NANDFC_BASE + 0x303c) +#define NANDFC_REG_IDTPYE (REG_NANDFC_BASE + 0x3040) +#define NANDFC_REG_TIMING_MODE (REG_NANDFC_BASE + 0x3048) +#define NANDFC_REG_SYNC_DELAY (REG_NANDFC_BASE + 0x304c) +#define NANDFC_REG_IRBN_COUNT (REG_NANDFC_BASE + 0x3054) +#define NANDFC_REG_PAGE_PARA (REG_NANDFC_BASE + 0x305c) +#define NANDFC_REG_COMMAND_FIFO (REG_NANDFC_BASE + 0x3070) +#define NANDFC_REG_COMMAND_EXEC_STATUS (REG_NANDFC_BASE + 0x3074) +#define NANDFC_REG_COMMAND_STATUS0 (REG_NANDFC_BASE + 0x3078) +#define NANDFC_REG_COMMAND_STATUS1 (REG_NANDFC_BASE + 0x307c) +#define NANDFC_REG_SCRAMBLE_START_DATA (REG_NANDFC_BASE + 0x3080) +#define NANDFC_REG_BRICK_FSM_TIME0 (REG_NANDFC_BASE + 0x3084) +#define NANDFC_REG_BRICK_FSM_TIME1 (REG_NANDFC_BASE + 0x3088) +#define NANDFC_REG_BRICK_FSM_TIME2 (REG_NANDFC_BASE + 0x308c) +#define NANDFC_REG_BRICK_FIFO_WRITE_POINTER (REG_NANDFC_BASE + 0x3090) +#define NANDFC_REG_BCH_DATA (REG_NANDFC_BASE + 0x3094) +#define NANDFC_REG_BCH_OOB (REG_NANDFC_BASE + 0x3098) +#define NANDFC_REG_MESSAGE_OOB_SIZE (REG_NANDFC_BASE + 0x309c) + +// NANDFC_REG_DCMD_ADDR +#define NANDFC_DCMD(n) (((n)&0xFF)<<24) +#define NANDFC_PAGE_ADDR(n) (((n)&0x00FFFFFF)<<0) + +// NANDFC_REG_CONFIG_A +#define NANDFC_CYCLE(n) ((((n)&0x0F)<<0) | ((((n) >> 4)&0x1)<<30)) +#define NANDFC_CHIP_SEL(n) (((n)&0x0F)<<4) +#define NANDFC_TIMING(n) (((n)&0xFF)<<8) +#define NANDFC_POLARITY_IO(n) (((n)&0x01)<<16) +#define NANDFC_POLARITY_MEM(n) (((n)&0x01)<<17) +#define NANDFC_CMDFULL_STA(n) (((n)&0x01)<<31) +#define NANDFC_BRICK_COMMAND(n) (((n)&0x01)<<25) +#define NANDFC_WDITH_16BIT(n) (((n)&0x01)<<18) +#define NANDFC_SCRAMBLE_ENABLE(n) (((n)&0x01)<<24) + +//NNADFC_REG_BCH_DATA +#define NANDFC_BCH_KK_DATA(n) (((n)&0x1FFF) << 0) +#define NANDFC_BCH_NN_DATA(n) (((n)&0x1FFF) << 16) + +//NNADFC_REG_BCH_DATA +#define NANDFC_BCH_KK_OOB(n) (((n)&0x1FFF) << 0) +#define NANDFC_BCH_NN_OOB(n) (((n)&0x1FFF) << 16) + +//NNADFC_REG_MESSAGE_OOB_SIZE +#define NANDFC_OOB_SIZE(n) (((n)&0xFFF) << 0) +#define NANDFC_MESSAGE_SIZE(n) (((n)&0x3FFF) << 16) + +//NANDFC_REG_BRICK_FIFO_WRITE_POINTER +#define NANDFC_BRICK_DATA(n) (((n)&0xFF) << 24) +#define NANDFC_BRICK_R_WIDTH(n) (((n)&0x1) << 18) +#define NANDFC_BRICK_W_WIDTH(n) (((n)&0x1) << 19) +#define NANDFC_BRICK_DATA_NUM(n) (((n)&0x3FFF) << 4) +#define NANDFC_BRICK_NEXT_ACT(n) (((n)&0xF) << 0) + +typedef enum +{ + NAND_ECC_24BIT = 0, + NAND_ECC_96BIT_WITHOUT_CRC = 1, + NAND_ECC_96BIT_WITH_CRC = 2, + NAND_ECC_64BIT = 3, + NAND_ECC_56BIT = 4, + NAND_ECC_40BIT = 5, + NAND_ECC_24BIT_1 = 6, + NAND_ECC_48BIT = 7, + NAND_ECC_32BIT = 8, + NAND_ECC_16BIT = 9, + NAND_ECC_8BIT = 10, + NAND_ECC_72BIT = 11, + NAND_ECC_80BIT = 12, + NAND_ECC_88BIT = 13, +} NAND_BCHMODE_TYPE; + +#define NANDFC_SCRAMBLE(n) (((n)&0x01)<<24) + +// NANDFC_REG_CONFIG_B +#define NANDFC_HWECC(n) (((n)&0x01)<<7) +#define NANDFC_ECC_MODE(n) (((n)&0x0f)<<0) + +// NANDFC_REG_BUF_CTRL +#define NANDFC_BUF_DIRECT(n) (((n)&0x01)<<2) + +// NANDFC_REG_INT_STAT +#define NANDFC_INT_ECC_ERR (1<<0) +#define NANDFC_INT_PROG_ERR (1<<1) +#define NANDFC_INT_ERASE_ERR (1<<2) +#define NANDFC_INT_TIMEOUT (1<<3) +#define NANDFC_INT_DONE (1<<4) +#define NANDFC_INT_CRC_FAIL (1<<5) +#define NANDFC_INT_COMMAND_FIFO_EMPTY (1<<6) +#define NANDFC_INT_ECC_ERR_0 (1<<7) +#define NANDFC_INT_ECC_ERR_1 (1<<8) +#define NANDFC_INT_ECC_ERR_1 (1<<8) +#define NANDFC_INT_ECC_ERR_2 (1<<10) +#define NANDFC_INT_ECC_ERR_3 (1<<10) +#define NANDFC_INT_ECC_ERR_4 (1<<11) +#define NANDFC_INT_ECC_ERR_5 (1<<12) +#define NANDFC_INT_ECC_ERR_6 (1<<13) +#define NANDFC_INT_ECC_ERR_7 (1<<14) +#define NANDFC_INT_ECC_CRC_0 (1<<15) +#define NANDFC_INT_ECC_CRC_1 (1<<16) +#define NANDFC_INT_ECC_CRC_2 (1<<17) +#define NANDFC_INT_ECC_CRC_3 (1<<18) +#define NANDFC_INT_ECC_CRC_4 (1<<19) +#define NANDFC_INT_ECC_CRC_5 (1<<20) +#define NANDFC_INT_ECC_CRC_6 (1<<21) +#define NANDFC_COMMAND_FIFO_OVERFLOW (1 << 22) +#define NANDFC_INT_ERR_ALL (0x3FFF87) +#define NANDFC_INT_CLR_MASK (0x3FFF9F) + +typedef enum +{ + NAND_TYPE_4K = 0, + NAND_TYPE_2K = 1, + NAND_TYPE_8K = 2, + NAND_TYPE_16K = 3, + NAND_TYPE_3K = 4, + NAND_TYPE_7K = 5, + NAND_TYPE_14K = 6 +} NAND_FLASH_TYPE; + +//NANDFC_REG_PAGE_PARA +#define NANDFC_PAGE_SIZE(n) (((n)&0x07FFF)<<16) +#define NANDFC_PACKAGE_NUM(n) (((n)&0x0F)<<0) +#endif /* _REG_NAND_V3_H_ */ + diff --git a/arch/arm/include/asm/arch-rda/reg_rf_spi.h b/arch/arm/include/asm/arch-rda/reg_rf_spi.h new file mode 100644 index 0000000000..ac7b35bdf6 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_rf_spi.h @@ -0,0 +1,152 @@ +#ifndef _RF_SPI_H_ +#define _RF_SPI_H_ +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= +#define SPI_TX_FIFO_SIZE (16) +#define SPI_RX_FIFO_SIZE (16) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// SPI_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= + +typedef volatile struct +{ + REG32 Ctrl; //0x00000000 + REG32 Status; //0x00000004 + REG32 Rx_Data; //0x00000008 + REG32 Command; //0x0000000C + REG32 Cmd_Size; //0x00000010 + REG32 Cmd_Data; //0x00000014 + REG32 Gain_Size; //0x00000018 + REG32 Gain_Data; //0x0000001C + REG32 IRQ; //0x00000020 + REG32 IRQ_Mask; //0x00000024 + REG32 IRQ_Threshold; //0x00000028 + REG32 Divider; //0x0000002C +} HWP_RF_SPI_T; + +#define hwp_rfSpi ((HWP_RF_SPI_T*) (RDA_CFG_RF_SPI_BASE)) + +//Ctrl +#define RF_SPI_ENABLE (1<<0) +#define RF_SPI_CS_POLARITY (1<<1) +#define RF_SPI_DIGRF_READ (1<<2) +#define RF_SPI_CLOCKED_BACK2BACK (1<<3) +#define RF_SPI_INPUT_MODE (1<<4) +#define RF_SPI_CLOCK_POLARITY (1<<5) +#define RF_SPI_CLOCK_DELAY(n) (((n)&3)<<6) +#define RF_SPI_DO_DELAY(n) (((n)&3)<<8) +#define RF_SPI_DI_DELAY(n) (((n)&3)<<10) +#define RF_SPI_CS_DELAY(n) (((n)&3)<<12) +#define RF_SPI_CS_END_HOLD(n) (((n)&3)<<14) +#define RF_SPI_FRAME_SIZE(n) (((n)&31)<<16) +#define RF_SPI_FRAME_SIZE_MASK (31<<16) +#define RF_SPI_FRAME_SIZE_SHIFT (16) +#define RF_SPI_CS_END_PULSE(n) (((n)&3)<<22) +#define RF_SPI_INPUT_FRAME_SIZE(n) (((n)&31)<<24) +#define RF_SPI_INPUT_FRAME_SIZE_MASK (31<<24) +#define RF_SPI_INPUT_FRAME_SIZE_SHIFT (24) +#define RF_SPI_TURNAROUND_TIME(n) (((n)&3)<<30) + +//Status +#define RF_SPI_ACTIVE_STATUS (1<<0) +#define RF_SPI_ERROR_CMD (1<<1) +#define RF_SPI_TABLE_OVF (1<<6) +#define RF_SPI_TABLE_UDF (1<<7) +#define RF_SPI_CMD_LEVEL(n) (((n)&0x3F)<<8) +#define RF_SPI_CMD_LEVEL_MASK (0x3F<<8) +#define RF_SPI_CMD_LEVEL_SHIFT (8) +#define RF_SPI_CMD_OVF (1<<14) +#define RF_SPI_CMD_UDF (1<<15) +#define RF_SPI_CMD_DATA_LEVEL(n) (((n)&0x1FF)<<16) +#define RF_SPI_CMD_DATA_LEVEL_MASK (0x1FF<<16) +#define RF_SPI_CMD_DATA_LEVEL_SHIFT (16) +#define RF_SPI_CMD_DATA_OVF (1<<25) +#define RF_SPI_CMD_DATA_UDF (1<<26) +#define RF_SPI_RX_LEVEL(n) (((n)&7)<<27) +#define RF_SPI_RX_LEVEL_MASK (7<<27) +#define RF_SPI_RX_LEVEL_SHIFT (27) +#define RF_SPI_RX_OVF (1<<30) +#define RF_SPI_RX_UDF (1<<31) + +//Rx_Data +#define RF_SPI_RX_DATA(n) (((n)&0xFF)<<0) + +//Command +#define RF_SPI_SEND_CMD (1<<0) +#define RF_SPI_FLUSH_CMD_FIFO (1<<8) +#define RF_SPI_FLUSH_RX_FIFO (1<<16) +#define RF_SPI_RESTART_GAIN (1<<24) +#define RF_SPI_RELOAD_GAIN (1<<28) +#define RF_SPI_DRIVE_ZERO (1<<31) + +//Cmd_Size +#define RF_SPI_CMD_SIZE(n) (((n)&0xFF)<<0) +#define RF_SPI_CMD_MARK (1<<31) + +//Cmd_Data +#define RF_SPI_CMD_DATA(n) (((n)&0xFF)<<0) + +//Gain_Size +#define RF_SPI_GAIN_SIZE(n) (((n)&15)<<0) + +//Gain_Data +#define RF_SPI_GAIN_DATA(n) (((n)&0xFF)<<0) + +//IRQ +#define RF_SPI_CMD_DATA_DMA_DONE_CAUSE (1<<0) +#define RF_SPI_CMD_FIFO_EMPTY_CAUSE (1<<2) +#define RF_SPI_CMD_THRESHOLD_CAUSE (1<<3) +#define RF_SPI_RX_FIFO_FULL_CAUSE (1<<4) +#define RF_SPI_RX_THRESHOLD_CAUSE (1<<5) +#define RF_SPI_ERROR_CAUSE (1<<6) +#define RF_SPI_CMD_DATA_DMA_DONE_STATUS (1<<16) +#define RF_SPI_CMD_FIFO_EMPTY_STATUS (1<<18) +#define RF_SPI_CMD_THRESHOLD_STATUS (1<<19) +#define RF_SPI_RX_FIFO_FULL_STATUS (1<<20) +#define RF_SPI_RX_THRESHOLD_STATUS (1<<21) +#define RF_SPI_ERROR_STATUS (1<<22) +#define RF_SPI_ALL_CAUSE(n) (((n)&0x7D)<<0) +#define RF_SPI_ALL_CAUSE_MASK (0x7D<<0) +#define RF_SPI_ALL_CAUSE_SHIFT (0) +#define RF_SPI_ALL_STATUS(n) (((n)&0x7D)<<16) +#define RF_SPI_ALL_STATUS_MASK (0x7D<<16) +#define RF_SPI_ALL_STATUS_SHIFT (16) + +//IRQ_Mask +#define RF_SPI_CMD_DATA_DMA_DONE_MASK (1<<0) +#define RF_SPI_CMD_FIFO_EMPTY_MASK (1<<2) +#define RF_SPI_CMD_THRESHOLD_MASK (1<<3) +#define RF_SPI_RX_FIFO_FULL_MASK (1<<4) +#define RF_SPI_RX_THRESHOLD_MASK (1<<5) +#define RF_SPI_ERROR_MASK (1<<6) +#define RF_SPI_ALL_MASK(n) (((n)&0x7D)<<0) +#define RF_SPI_ALL_MASK_MASK (0x7D<<0) +#define RF_SPI_ALL_MASK_SHIFT (0) + +//IRQ_Threshold +#define RF_SPI_CMD_THRESHOLD(n) (((n)&0x3F)<<8) +#define RF_SPI_RX_THRESHOLD(n) (((n)&3)<<24) + +//Divider +#define RF_SPI_DIVIDER(n) (((n)&0x3F)<<1) +#define RF_SPI_DIVIDER_MASK (0x3F<<1) +#define RF_SPI_DIVIDER_SHIFT (1) +#define RF_SPI_CLOCK_LIMITER (1<<28) +#define RF_SPI_CLOCK_LIMITER_MASK (1<<28) +#define RF_SPI_CLOCK_LIMITER_SHIFT (28) + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_spi.h b/arch/arm/include/asm/arch-rda/reg_spi.h new file mode 100644 index 0000000000..8664bc2215 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_spi.h @@ -0,0 +1,245 @@ +#ifndef _SPI_H_ +#define _SPI_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= +#define SPI_TX_FIFO_SIZE (16) +#define SPI_RX_FIFO_SIZE (16) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// SPI_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= + +typedef volatile struct +{ + REG32 ctrl; //0x00000000 + REG32 status; //0x00000004 + /// Spi1 fifo size (rxtx_buffer): 8bits. + /// Spi2 fifo size (rxtx_buffer): 8bits. + /// Spi3 fifo size (rxtx_buffer): 32bits. + /// <table border="1"> <!-- border should be in css--> <caption> <big>32b FIFO + /// only </big> </caption> <tr> <th>rxtx_buffer: </th> <th>Range [31]</th> <th>Range + /// [30:29]</th> <th>Range [28:26]</th> <th>Range [25]</th> <th>Range [24:16]</th> + /// <th>Range [15:0]</th> </tr> <tr> <td>DATA_IN: </td> <td>READ_ENA</td> <td>CS</td> + /// <td/> <td>R/W</td> <td>ADDRESS</td> <td>DATA</td> </tr> <tr> <td>DATA_OUT: + /// </td> <td>READ_ENA</td> <td>CS</td> <td/> <td>R/W</td> <td>ADDRESS</td> <td>DATA</td> + /// </tr> </table> + REG32 rxtx_buffer; //0x00000008 + REG32 cfg; //0x0000000C + REG32 pattern; //0x00000010 + REG32 stream; //0x00000014 + REG32 pin_control; //0x00000018 + REG32 irq; //0x0000001C +} HWP_SPI_T; + +#define hwp_spi1 ((HWP_SPI_T*) (RDA_SPI1_BASE)) +#define hwp_spi2 ((HWP_SPI_T*) (RDA_SPI2_BASE)) +#define hwp_spi3 ((HWP_SPI_T*) (RDA_SPI3_BASE)) +#define hwp_mspi2 ((HWP_SPI_T*) (RDA_MODEM_SPI2_BASE)) + +//ctrl +#define SPI_ENABLE (1<<0) +#define SPI_CS_SEL(n) (((n)&3)<<1) +#define SPI_CS_SEL_MASK (3<<1) +#define SPI_CS_SEL_SHIFT (1) +#define SPI_CS_SEL_CS0 (0<<1) +#define SPI_CS_SEL_CS1 (1<<1) +#define SPI_CS_SEL_CS2 (2<<1) +#define SPI_CS_SEL_CS3 (3<<1) +#define SPI_INPUT_MODE (1<<4) +#define SPI_CLOCK_POLARITY (1<<5) +#define SPI_CLOCK_DELAY(n) (((n)&3)<<6) +#define SPI_DO_DELAY(n) (((n)&3)<<8) +#define SPI_DI_DELAY(n) (((n)&3)<<10) +#define SPI_CS_DELAY(n) (((n)&3)<<12) +#define SPI_CS_PULSE(n) (((n)&3)<<14) +#define SPI_FRAME_SIZE(n) (((n)&31)<<16) +#define SPI_TX_SW_SHIFT (1<<21) +#define SPI_OE_DELAY(n) (((n)&31)<<24) +#define SPI_CTRL_DATA_MUX_SEL (1<<29) +#define SPI_CTRL_DATA_MUX_SEL_MASK (1<<29) +#define SPI_CTRL_DATA_MUX_SEL_SHIFT (29) +#define SPI_CTRL_DATA_MUX_SEL_CTRL_REG_SEL (0<<29) +#define SPI_CTRL_DATA_MUX_SEL_DATA_REG_SEL (1<<29) +#define SPI_INPUT_SEL(n) (((n)&3)<<30) + +//status +#define SPI_ACTIVE_STATUS (1<<0) +#define SPI_CAUSE_RX_OVF_IRQ (1<<3) +#define SPI_CAUSE_TX_TH_IRQ (1<<4) +#define SPI_CAUSE_TX_DMA_IRQ (1<<5) +#define SPI_CAUSE_RX_TH_IRQ (1<<6) +#define SPI_CAUSE_RX_DMA_IRQ (1<<7) +#define SPI_TX_OVF (1<<9) +#define SPI_RX_UDF (1<<10) +#define SPI_RX_OVF (1<<11) +#define SPI_TX_TH (1<<12) +#define SPI_TX_DMA_DONE (1<<13) +#define SPI_RX_TH (1<<14) +#define SPI_RX_DMA_DONE (1<<15) +#define SPI_TX_SPACE(n) (((n)&31)<<16) +#define SPI_TX_SPACE_MASK (31<<16) +#define SPI_TX_SPACE_SHIFT (16) +#define SPI_RX_LEVEL(n) (((n)&31)<<24) +#define SPI_RX_LEVEL_MASK (31<<24) +#define SPI_RX_LEVEL_SHIFT (24) +#define SPI_FIFO_FLUSH (1<<30) +#define SPI_IRQ_CAUSE(n) (((n)&31)<<3) +#define SPI_IRQ_CAUSE_MASK (31<<3) +#define SPI_IRQ_CAUSE_SHIFT (3) + +//rxtx_buffer +#define SPI_DATA_IN(n) (((n)&0xFFFFFFFF)<<0) +#define SPI_DATA_OUT(n) (((n)&0xFFFFFFFF)<<0) +#define SPI_CS(n) (((n)&3)<<29) +#define SPI_CS_MASK (3<<29) +#define SPI_CS_SHIFT (29) +#define SPI_READ_ENA (1<<31) +#define SPI_READ_ENA_MASK (1<<31) +#define SPI_READ_ENA_SHIFT (31) + +//cfg +#define SPI_CS_POLARITY_0 (1<<0) +#define SPI_CS_POLARITY_0_MASK (1<<0) +#define SPI_CS_POLARITY_0_SHIFT (0) +#define SPI_CS_POLARITY_0_ACTIVE_HIGH (0<<0) +#define SPI_CS_POLARITY_0_ACTIVE_LOW (1<<0) +#define SPI_CS_POLARITY_1 (1<<1) +#define SPI_CS_POLARITY_1_MASK (1<<1) +#define SPI_CS_POLARITY_1_SHIFT (1) +#define SPI_CS_POLARITY_1_ACTIVE_HIGH (0<<1) +#define SPI_CS_POLARITY_1_ACTIVE_LOW (1<<1) +#define SPI_CS_POLARITY_2 (1<<2) +#define SPI_CS_POLARITY_2_MASK (1<<2) +#define SPI_CS_POLARITY_2_SHIFT (2) +#define SPI_CS_POLARITY_2_ACTIVE_HIGH (0<<2) +#define SPI_CS_POLARITY_2_ACTIVE_LOW (1<<2) +#define SPI_CS_POLARITY_3 (1<<3) +#define SPI_CS_POLARITY_3_MASK (1<<3) +#define SPI_CS_POLARITY_3_SHIFT (3) +#define SPI_CS_POLARITY_3_ACTIVE_HIGH (0<<3) +#define SPI_CS_POLARITY_3_ACTIVE_LOW (1<<3) +#define SPI_CLOCK_DIVIDER(n) (((n)&0x3FF)<<16) +#define SPI_CLOCK_DIVIDER_MASK (0x3FF<<16) +#define SPI_CLOCK_DIVIDER_SHIFT (16) +#define SPI_CLOCK_LIMITER (1<<28) +#define SPI_CLOCK_LIMITER_MASK (1<<28) +#define SPI_CLOCK_LIMITER_SHIFT (28) +#define SPI_CS_POLARITY(n) (((n)&15)<<0) +#define SPI_CS_POLARITY_MASK (15<<0) +#define SPI_CS_POLARITY_SHIFT (0) + +//pattern +#define SPI_PATTERN(n) (((n)&0xFF)<<0) +#define SPI_PATTERN_MODE (1<<8) +#define SPI_PATTERN_MODE_MASK (1<<8) +#define SPI_PATTERN_MODE_SHIFT (8) +#define SPI_PATTERN_MODE_DISABLED (0<<8) +#define SPI_PATTERN_MODE_ENABLED (1<<8) +#define SPI_PATTERN_SELECTOR (1<<9) +#define SPI_PATTERN_SELECTOR_MASK (1<<9) +#define SPI_PATTERN_SELECTOR_SHIFT (9) +#define SPI_PATTERN_SELECTOR_UNTIL (0<<9) +#define SPI_PATTERN_SELECTOR_WHILE (1<<9) + +//stream +#define SPI_TX_STREAM_BIT (1<<0) +#define SPI_TX_STREAM_BIT_MASK (1<<0) +#define SPI_TX_STREAM_BIT_SHIFT (0) +#define SPI_TX_STREAM_BIT_ZERO (0<<0) +#define SPI_TX_STREAM_BIT_ONE (1<<0) +#define SPI_TX_STREAM_MODE (1<<8) +#define SPI_TX_STREAM_MODE_MASK (1<<8) +#define SPI_TX_STREAM_MODE_SHIFT (8) +#define SPI_TX_STREAM_MODE_DISABLED (0<<8) +#define SPI_TX_STREAM_MODE_ENABLED (1<<8) +#define SPI_TX_STREAM_STOP_WITH_RX_DMA_DONE (1<<16) +#define SPI_TX_STREAM_STOP_WITH_RX_DMA_DONE_MASK (1<<16) +#define SPI_TX_STREAM_STOP_WITH_RX_DMA_DONE_SHIFT (16) +#define SPI_TX_STREAM_STOP_WITH_RX_DMA_DONE_DISABLED (0<<16) +#define SPI_TX_STREAM_STOP_WITH_RX_DMA_DONE_ENABLED (1<<16) + +//pin_control +#define SPI_CLK_CTRL(n) (((n)&3)<<0) +#define SPI_CLK_CTRL_MASK (3<<0) +#define SPI_CLK_CTRL_SHIFT (0) +#define SPI_CLK_CTRL_SPI_CTRL (0<<0) +#define SPI_CLK_CTRL_INPUT_CTRL (1<<0) +#define SPI_CLK_CTRL_FORCE_0_CTRL (2<<0) +#define SPI_CLK_CTRL_FORCE_1_CTRL (3<<0) +#define SPI_DO_CTRL(n) (((n)&3)<<2) +#define SPI_DO_CTRL_MASK (3<<2) +#define SPI_DO_CTRL_SHIFT (2) +#define SPI_DO_CTRL_SPI_CTRL (0<<2) +#define SPI_DO_CTRL_INPUT_CTRL (1<<2) +#define SPI_DO_CTRL_FORCE_0_CTRL (2<<2) +#define SPI_DO_CTRL_FORCE_1_CTRL (3<<2) +#define SPI_CS0_CTRL(n) (((n)&3)<<4) +#define SPI_CS0_CTRL_MASK (3<<4) +#define SPI_CS0_CTRL_SHIFT (4) +#define SPI_CS0_CTRL_SPI_CTRL (0<<4) +#define SPI_CS0_CTRL_INPUT_CTRL (1<<4) +#define SPI_CS0_CTRL_FORCE_0_CTRL (2<<4) +#define SPI_CS0_CTRL_FORCE_1_CTRL (3<<4) +#define SPI_CS1_CTRL(n) (((n)&3)<<6) +#define SPI_CS1_CTRL_MASK (3<<6) +#define SPI_CS1_CTRL_SHIFT (6) +#define SPI_CS1_CTRL_SPI_CTRL (0<<6) +#define SPI_CS1_CTRL_INPUT_CTRL (1<<6) +#define SPI_CS1_CTRL_FORCE_0_CTRL (2<<6) +#define SPI_CS1_CTRL_FORCE_1_CTRL (3<<6) +#define SPI_CS2_CTRL(n) (((n)&3)<<8) +#define SPI_CS2_CTRL_MASK (3<<8) +#define SPI_CS2_CTRL_SHIFT (8) +#define SPI_CS2_CTRL_SPI_CTRL (0<<8) +#define SPI_CS2_CTRL_INPUT_CTRL (1<<8) +#define SPI_CS2_CTRL_FORCE_0_CTRL (2<<8) +#define SPI_CS2_CTRL_FORCE_1_CTRL (3<<8) +#define SPI_CS3_CTRL(n) (((n)&3)<<10) +#define SPI_CS3_CTRL_MASK (3<<10) +#define SPI_CS3_CTRL_SHIFT (10) +#define SPI_CS3_CTRL_SPI_CTRL (0<<10) +#define SPI_CS3_CTRL_INPUT_CTRL (1<<10) +#define SPI_CS3_CTRL_FORCE_0_CTRL (2<<10) +#define SPI_CS3_CTRL_FORCE_1_CTRL (3<<10) + +//irq +#define SPI_MASK_RX_OVF_IRQ (1<<0) +#define SPI_MASK_TX_TH_IRQ (1<<1) +#define SPI_MASK_TX_DMA_IRQ (1<<2) +#define SPI_MASK_RX_TH_IRQ (1<<3) +#define SPI_MASK_RX_DMA_IRQ (1<<4) +#define SPI_TX_THRESHOLD(n) (((n)&3)<<5) +#define SPI_TX_THRESHOLD_MASK (3<<5) +#define SPI_TX_THRESHOLD_SHIFT (5) +#define SPI_TX_THRESHOLD_1_EMPTY_SLOT (0<<5) +#define SPI_TX_THRESHOLD_4_EMPTY_SLOTS (1<<5) +#define SPI_TX_THRESHOLD_8_EMPTY_SLOTS (2<<5) +#define SPI_TX_THRESHOLD_12_EMPTY_SLOTS (3<<5) +#define SPI_RX_THRESHOLD(n) (((n)&3)<<7) +#define SPI_RX_THRESHOLD_MASK (3<<7) +#define SPI_RX_THRESHOLD_SHIFT (7) +#define SPI_RX_THRESHOLD_1_VALID_DATA (0<<7) +#define SPI_RX_THRESHOLD_4_VALID_DATA (1<<7) +#define SPI_RX_THRESHOLD_8_VALID_DATA (2<<7) +#define SPI_RX_THRESHOLD_12_VALID_DATA (3<<7) +#define SPI_IRQ_MASK(n) (((n)&31)<<0) +#define SPI_IRQ_MASK_MASK (31<<0) +#define SPI_IRQ_MASK_SHIFT (0) + + + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl.h b/arch/arm/include/asm/arch-rda/reg_sysctrl.h new file mode 100644 index 0000000000..f4678e51eb --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_sysctrl.h @@ -0,0 +1,15 @@ +#ifdef CONFIG_MACH_RDA8810 +#include "reg_sysctrl_rda8810.h" +#elif defined(CONFIG_MACH_RDA8810E) +#include "reg_sysctrl_rda8810e.h" +#elif defined(CONFIG_MACH_RDA8820) +#include "reg_sysctrl_rda8820.h" +#elif defined(CONFIG_MACH_RDA8850) +#include "reg_sysctrl_rda8850.h" +#elif defined(CONFIG_MACH_RDA8850E) +#include "reg_sysctrl_rda8850e.h" +#elif defined(CONFIG_MACH_RDA8810H) +#include "reg_sysctrl_rda8810h.h" +#else +#error "unknown MACH" +#endif diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810.h b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810.h new file mode 100644 index 0000000000..a0a7181a54 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810.h @@ -0,0 +1,1471 @@ +#ifndef _REG_SYSCTRL_H_ +#define _REG_SYSCTRL_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= + +// ============================================================================ +// AP_CPU_ID_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// CPU IDs + CPU0 = 0x00000000, + CPU1 = 0x00000001 +} AP_CPU_ID_T; + + +// ============================================================================ +// CPU_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP CPU side System clocks + CPU_CORE = 0x00000000, +/// the following don't have an auto enable + CPU_DUMMY = 0x00000001 +} CPU_CLKS_T; + +#define NB_CPU_CLK_AEN (1) +#define NB_CPU_CLK_EN (2) +#define NB_CPU_CLK (2) + +// ============================================================================ +// AXI_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXI side System clocks: AXI and AHB0 and APB0 + AHB0_CONF = 0x00000000, + APB0_CONF = 0x00000001, + AXI_VOC = 0x00000002, + AXI_DMA = 0x00000003, +/// the following don't have an auto enable + AXI_ALWAYS = 0x00000004, + AXI_CONNECT = 0x00000005, + APB0_IRQ = 0x00000006 +} AXI_CLKS_T; + +#define NB_AXI_CLK_AEN (4) +#define NB_AXI_CLK_EN (7) +#define NB_AXI_CLK (7) + +// ============================================================================ +// AXIDIV2_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXIdiv2 side System clocks + AXIDIV2_IMEM = 0x00000000, +/// the following don't have an auto enable + AXIDIV2_ALWAYS = 0x00000001, + AXIDIV2_CONNECT = 0x00000002, + AXIDIV2_VPU = 0x00000003 +} AXIDIV2_CLKS_T; + +#define NB_AXIDIV2_CLK_AEN (1) +#define NB_AXIDIV2_CLK_EN (4) +#define NB_AXIDIV2_CLK (4) + +// ============================================================================ +// GCG_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GCG side System clocks + GCG_APB_CONF = 0x00000000, + GCG_GOUDA = 0x00000001, + GCG_CAMERA = 0x00000002, +/// the following don't have an auto enable + GCG_ALWAYS = 0x00000003, + GCG_CONNECT = 0x00000004 +} GCG_CLKS_T; + +#define NB_GCG_CLK_AEN (3) +#define NB_GCG_CLK_EN (5) +#define NB_GCG_CLK (5) + +// ============================================================================ +// AHB1_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AHB1 side System clocks + AHB1_USBC = 0x00000000, +/// the following don't have an auto enable + AHB1_ALWAYS = 0x00000001, + AHB1_SPIFLASH = 0x00000002 +} AHB1_CLKS_T; + +#define NB_AHB1_CLK_AEN (1) +#define NB_AHB1_CLK_EN (3) +#define NB_AHB1_CLK (3) + +// ============================================================================ +// APB1_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB1 side System clocks + APB1_CONF = 0x00000000, + APB1_AIF = 0x00000001, + APB1_AUIFC = 0x00000002, + APB1_AUIFC_CH0 = 0x00000003, + APB1_AUIFC_CH1 = 0x00000004, + APB1_I2C1 = 0x00000005, + APB1_I2C2 = 0x00000006, + APB1_I2C3 = 0x00000007, +/// AP APB1 side divided clock (either divided by module or by clock_ctrl) + APB1D_OSC = 0x00000008, + APB1D_PWM = 0x00000009, +/// the following don't have an auto enable + APB1_ALWAYS = 0x0000000A, + APB1_DAPLITE = 0x0000000B, + APB1_TIMER = 0x0000000C, + APB1_GPIO = 0x0000000D +} APB1_CLKS_T; + +#define NB_APB1_CLK_AEN (10) +#define NB_APB1_CLK_EN (14) +#define NB_APB1_CLK (14) + +// ============================================================================ +// APB2_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB2 side System clocks + APB2_CONF = 0x00000000, + APB2_IFC = 0x00000001, + APB2_IFC_CH0 = 0x00000002, + APB2_IFC_CH1 = 0x00000003, + APB2_IFC_CH2 = 0x00000004, + APB2_IFC_CH3 = 0x00000005, + APB2_IFC_CH4 = 0x00000006, + APB2_IFC_CH5 = 0x00000007, + APB2_IFC_CH6 = 0x00000008, + APB2_IFC_CH7 = 0x00000009, + APB2_UART1 = 0x0000000A, + APB2_UART2 = 0x0000000B, + APB2_UART3 = 0x0000000C, + APB2_SPI1 = 0x0000000D, + APB2_SPI2 = 0x0000000E, + APB2_SPI3 = 0x0000000F, + APB2_SDMMC1 = 0x00000010, + APB2_SDMMC2 = 0x00000011, + APB2_SDMMC3 = 0x00000012, +/// the following don't have an auto enable + APB2_ALWAYS = 0x00000013, + APB2_NANDFLASH = 0x00000014 +} APB2_CLKS_T; + +#define NB_APB2_CLK_AEN (19) +#define NB_APB2_CLK_EN (21) +#define NB_APB2_CLK (21) + +// ============================================================================ +// MEM_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP MEM side System clocks + MEM_CONF = 0x00000000, +/// the following don't have an auto enable + MEM_DMC = 0x00000001, + MEM_GPU = 0x00000002, + MEM_VPU = 0x00000003, + MEM_DDRPHY_P = 0x00000004, + MEM_CONNECT = 0x00000005 +} MEM_CLKS_T; + +#define NB_MEM_CLK_AEN (1) +#define NB_MEM_CLK_EN (6) +#define NB_MEM_CLK (6) + +// ============================================================================ +// APO_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP side Other clocks +/// clocks with auto enble + APOC_VPU = 0x00000000, + APOC_BCK = 0x00000001, + APOC_UART1 = 0x00000002, + APOC_UART2 = 0x00000003, + APOC_UART3 = 0x00000004, + APOC_VOC_CORE = 0x00000005, + APOC_VOC = 0x00000006, +/// the following don't have an auto enable + APOC_VOC_ALWAYS = 0x00000007, + APOC_DDRPHY_N = 0x00000008, + APOC_DDRPHY2XP = 0x00000009, + APOC_DDRPHY2XN = 0x0000000A, + APOC_GPU = 0x0000000B, + APOC_USBPHY = 0x0000000C, + APOC_CSI = 0x0000000D, + APOC_DSI = 0x0000000E, + APOC_GPIO = 0x0000000F, + APOC_SPIFLASH = 0x00000010, + APOC_PIX = 0x00000011, + APOC_PDGB = 0x00000012 +} APO_CLKS_T; + +#define NB_CLK_VOC_AEN_SYNC (5) +#define NB_CLK_VOC_CORE (6) +#define NB_APO_CLK_AEN (7) +#define NB_CLK_VOC_END (8) +#define NB_APO_CLK_EN (19) +#define NB_APO_CLK (19) + +// ============================================================================ +// CPU_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP CPU side resets + CPU_RST_CORE = 0x00000000, + CPU_RST_SYS = 0x00000001 +} CPU_RESETS_T; + +#define NB_CPU_RST (2) + +// ============================================================================ +// AXI_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXI side resets: AXI and AHB0 and APB0 + AXI_RST_VOC = 0x00000000, + AXI_RST_DMA = 0x00000001, + AXI_RST_SYS = 0x00000002, + AXI_RST_CONNECT = 0x00000003, + AHB0_RST_GPU = 0x00000004, + APB0_RST_VPU = 0x00000005, + APB0_RST_IRQ = 0x00000006 +} AXI_RESETS_T; + +#define NB_AXI_RST (7) + +// ============================================================================ +// AXIDIV2_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXIDIV2 side resets + AXIDIV2_RST_IMEM = 0x00000000, + AXIDIV2_RST_SYS = 0x00000001, + AXIDIV2_RST_VPU = 0x00000002 +} AXIDIV2_RESETS_T; + +#define NB_AXIDIV2_RST (3) + +// ============================================================================ +// GCG_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GCG side resets + GCG_RST_SYS = 0x00000000, + GCG_RST_GOUDA = 0x00000001, + GCG_RST_CAMERA = 0x00000002 +} GCG_RESETS_T; + +#define NB_GCG_RST (3) + +// ============================================================================ +// AHB1_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AHB1 side resets + AHB1_RST_SYS = 0x00000000, + AHB1_RST_USBC = 0x00000001, + AHB1_RST_SPIFLASH = 0x00000002 +} AHB1_RESETS_T; + +#define NB_AHB1_RST (3) + +// ============================================================================ +// APB1_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB1 side resets + APB1_RST_SYS = 0x00000000, + APB1_RST_TIMER = 0x00000001, + APB1_RST_KEYPAD = 0x00000002, + APB1_RST_GPIO = 0x00000003, + APB1_RST_PWM = 0x00000004, + APB1_RST_AIF = 0x00000005, + APB1_RST_AUIFC = 0x00000006, + APB1_RST_I2C1 = 0x00000007, + APB1_RST_I2C2 = 0x00000008, + APB1_RST_I2C3 = 0x00000009, + APB1_RST_COM_REGS = 0x0000000A, + APB1_RST_DMC = 0x0000000B, + APB1_RST_DDRPHY_P = 0x0000000C, + APB1_RST_BB2G_XCPU = 0x0000000D, + APB1_RST_BB2G_BCPU = 0x0000000E, + APB1_RST_BB2G_AHBC = 0x0000000F, + APB1_RST_BB2G_DMA = 0x00000010, + APB1_RST_BB2G_A2A = 0x00000011, + APB1_RST_BB2G_XIFC = 0x00000012, + APB1_RST_BB2G_BIFC = 0x00000013, + APB1_RST_BB2G_BAHBC = 0x00000014, + APB1_RST_BB2G_MEM_BRIDGE = 0x00000015 +} APB1_RESETS_T; + +#define NB_APB1_RST (22) + +// ============================================================================ +// APB2_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB2 side resets + APB2_RST_SYS = 0x00000000, + APB2_RST_IFC = 0x00000001, + APB2_RST_UART1 = 0x00000002, + APB2_RST_UART2 = 0x00000003, + APB2_RST_UART3 = 0x00000004, + APB2_RST_SPI1 = 0x00000005, + APB2_RST_SPI2 = 0x00000006, + APB2_RST_SPI3 = 0x00000007, + APB2_RST_SDMMC1 = 0x00000008, + APB2_RST_SDMMC2 = 0x00000009, + APB2_RST_SDMMC3 = 0x0000000A, + APB2_RST_NANDFLASH = 0x0000000B +} APB2_RESETS_T; + +#define NB_APB2_RST (12) + +// ============================================================================ +// MEM_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP MEM side resets + MEM_RST_SYS = 0x00000000, + MEM_RST_GPU = 0x00000001, + MEM_RST_VPU = 0x00000002, + MEM_RST_DMC = 0x00000003, + MEM_RST_DDRPHY_P = 0x00000004 +} MEM_RESETS_T; + +#define NB_MEM_RST (5) + +// ============================================================================ +// AP_OTHERS_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP Reset Other : resync on corresponding clock other + AP_RSTO_VOC = 0x00000000, + AP_RSTO_DDRPHY_N = 0x00000001, + AP_RSTO_DDRPHY2XP = 0x00000002, + AP_RSTO_DDRPHY2XN = 0x00000003, + AP_RSTO_GPU = 0x00000004, + AP_RSTO_VPU = 0x00000005, + AP_RSTO_BCK = 0x00000006, + AP_RSTO_UART1 = 0x00000007, + AP_RSTO_UART2 = 0x00000008, + AP_RSTO_UART3 = 0x00000009, + AP_RSTO_GPIO = 0x0000000A, + AP_RSTO_TIMER = 0x0000000B, + AP_RSTO_USBC = 0x0000000C, + AP_RSTO_DSI = 0x0000000D, + AP_RSTO_SPIFLASH = 0x0000000E, + AP_RSTO_TCK = 0x0000000F, + AP_RSTO_PDBG_XTAL = 0x00000010 +} AP_OTHERS_RESETS_T; + +#define NB_AP_RSTO (17) +/// For REG_DBG protect lock/unlock value +#define AP_CTRL_PROTECT_LOCK (0XA50000) +#define AP_CTRL_PROTECT_UNLOCK (0XA50001) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// SYS_CTRL_AP_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + /// <strong>This register is used to Lock and Unlock the protected registers.</strong> + REG32 REG_DBG; //0x00000000 + /// Register protected by Write_Unlocked_H. + REG32 Cfg_Pll_Ctrl[4]; //0x00000004 + /// This register is protected. + REG32 Sel_Clock; //0x00000014 + REG32 Reset_Cause; //0x00000018 + /// This register is protected. + REG32 CPU_Rst_Set; //0x0000001C + REG32 CPU_Rst_Clr; //0x00000020 + /// This register is protected. + REG32 AXI_Rst_Set; //0x00000024 + REG32 AXI_Rst_Clr; //0x00000028 + /// This register is protected. + REG32 AXIDIV2_Rst_Set; //0x0000002C + REG32 AXIDIV2_Rst_Clr; //0x00000030 + /// This register is protected. + REG32 GCG_Rst_Set; //0x00000034 + REG32 GCG_Rst_Clr; //0x00000038 + /// This register is protected. + REG32 AHB1_Rst_Set; //0x0000003C + REG32 AHB1_Rst_Clr; //0x00000040 + /// This register is protected. + REG32 APB1_Rst_Set; //0x00000044 + REG32 APB1_Rst_Clr; //0x00000048 + /// This register is protected. + REG32 APB2_Rst_Set; //0x0000004C + REG32 APB2_Rst_Clr; //0x00000050 + /// This register is protected. + REG32 MEM_Rst_Set; //0x00000054 + REG32 MEM_Rst_Clr; //0x00000058 + REG32 Clk_CPU_Mode; //0x0000005C + REG32 Clk_CPU_Enable; //0x00000060 + /// This register is protected. + REG32 Clk_CPU_Disable; //0x00000064 + REG32 Clk_AXI_Mode; //0x00000068 + REG32 Clk_AXI_Enable; //0x0000006C + /// This register is protected. + REG32 Clk_AXI_Disable; //0x00000070 + REG32 Clk_AXIDIV2_Mode; //0x00000074 + REG32 Clk_AXIDIV2_Enable; //0x00000078 + /// This register is protected. + REG32 Clk_AXIDIV2_Disable; //0x0000007C + REG32 Clk_GCG_Mode; //0x00000080 + REG32 Clk_GCG_Enable; //0x00000084 + /// This register is protected. + REG32 Clk_GCG_Disable; //0x00000088 + REG32 Clk_AHB1_Mode; //0x0000008C + REG32 Clk_AHB1_Enable; //0x00000090 + /// This register is protected. + REG32 Clk_AHB1_Disable; //0x00000094 + REG32 Clk_APB1_Mode; //0x00000098 + REG32 Clk_APB1_Enable; //0x0000009C + /// This register is protected. + REG32 Clk_APB1_Disable; //0x000000A0 + REG32 Clk_APB2_Mode; //0x000000A4 + REG32 Clk_APB2_Enable; //0x000000A8 + /// This register is protected. + REG32 Clk_APB2_Disable; //0x000000AC + REG32 Clk_MEM_Mode; //0x000000B0 + REG32 Clk_MEM_Enable; //0x000000B4 + /// This register is protected. + REG32 Clk_MEM_Disable; //0x000000B8 + REG32 Clk_APO_Mode; //0x000000BC + REG32 Clk_APO_Enable; //0x000000C0 + /// This register is protected. + REG32 Clk_APO_Disable; //0x000000C4 + REG32 Cfg_Clk_AP_CPU; //0x000000C8 + REG32 Cfg_Clk_AP_AXI; //0x000000CC + REG32 Cfg_Clk_AP_GCG; //0x000000D0 + REG32 Cfg_Clk_AP_AHB1; //0x000000D4 + REG32 Cfg_Clk_AP_APB1; //0x000000D8 + REG32 Cfg_Clk_AP_APB2; //0x000000DC + REG32 Cfg_Clk_AP_MEM; //0x000000E0 + REG32 Cfg_Clk_AP_GPU; //0x000000E4 + REG32 Cfg_Clk_AP_VPU; //0x000000E8 + REG32 Cfg_Clk_AP_VOC; //0x000000EC + REG32 Cfg_Clk_AP_SFLSH; //0x000000F0 + REG32 Cfg_Clk_Uart[3]; //0x000000F4 + REG32 L2cc_Ctrl; //0x00000100 + REG32 Spi_Ctrl; //0x00000104 + REG32 Memory_Margin; //0x00000108 + REG32 Memory_Margin2; //0x0000010C + REG32 Memory_Observe; //0x00000110 + REG32 Reserved_00000114[58]; //0x00000114 + /// This register is reserved. + REG32 Cfg_Reserve; //0x000001FC +} HWP_SYS_CTRL_AP_T; + +#define hwp_sysCtrlAp ((HWP_SYS_CTRL_AP_T*)(RDA_SYSCTRL_BASE)) + + +//REG_DBG +#define SYS_CTRL_AP_SCRATCH(n) (((n)&0xFFFF)<<0) +#define SYS_CTRL_AP_WRITE_UNLOCK_STATUS (1<<30) +#define SYS_CTRL_AP_WRITE_UNLOCK (1<<31) + +//Cfg_Pll_Ctrl +#define SYS_CTRL_AP_AP_PLL_ENABLE (1<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_MASK (1<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_SHIFT (0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN (0<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE (1<<0) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET (1<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK (1<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_SHIFT (4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET (0<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET (1<<4) +#define SYS_CTRL_AP_AP_PLL_BYPASS (1<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_MASK (1<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_SHIFT (8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_PASS (0<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_BYPASS (1<<8) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_MASK (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_SHIFT (12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_DISABLE (0<<12) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(n) (((n)&31)<<16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_MASK (31<<16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_SHIFT (16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(n) (((n)&31)<<24) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_MASK (31<<24) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_SHIFT (24) +#define SYS_CTRL_AP_PLL_AP_CFG(n) (((n)&0x1F1F1111)<<0) +#define SYS_CTRL_AP_PLL_AP_CFG_MASK (0x1F1F1111<<0) +#define SYS_CTRL_AP_PLL_AP_CFG_SHIFT (0) + +//Sel_Clock +#define SYS_CTRL_AP_SLOW_SEL_RF_OSCILLATOR (1<<0) +#define SYS_CTRL_AP_SLOW_SEL_RF_RF (0<<0) +#define SYS_CTRL_AP_CPU_SEL_FAST_SLOW (1<<4) +#define SYS_CTRL_AP_CPU_SEL_FAST_FAST (0<<4) +#define SYS_CTRL_AP_BUS_SEL_FAST_SLOW (1<<5) +#define SYS_CTRL_AP_BUS_SEL_FAST_FAST (0<<5) +#define SYS_CTRL_AP_TIMER_SEL_FAST_SLOW (1<<7) +#define SYS_CTRL_AP_TIMER_SEL_FAST_FAST (0<<7) +#define SYS_CTRL_AP_RF_DETECTED_OK (1<<8) +#define SYS_CTRL_AP_RF_DETECTED_NO (0<<8) +#define SYS_CTRL_AP_RF_DETECT_BYPASS (1<<9) +#define SYS_CTRL_AP_RF_DETECT_RESET (1<<10) +#define SYS_CTRL_AP_RF_SELECTED_L (1<<11) +#define SYS_CTRL_AP_PLL_LOCKED_CPU (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_MASK (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_SHIFT (12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_NOT_LOCKED (0<<12) +#define SYS_CTRL_AP_PLL_LOCKED_BUS (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_MASK (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_SHIFT (13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_NOT_LOCKED (0<<13) +#define SYS_CTRL_AP_PLL_LOCKED_MEM (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_MASK (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_SHIFT (14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_NOT_LOCKED (0<<14) +#define SYS_CTRL_AP_PLL_LOCKED_USB (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_MASK (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_SHIFT (15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_NOT_LOCKED (0<<15) +#define SYS_CTRL_AP_PLL_BYPASS_LOCK_CPU (1<<20) +#define SYS_CTRL_AP_PLL_BYPASS_LOCK_BUS (1<<21) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L (1<<30) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_MASK (1<<30) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_SHIFT (30) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L (1<<31) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_MASK (1<<31) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_SHIFT (31) + +//Reset_Cause +#define SYS_CTRL_AP_WATCHDOG_RESET_HAPPENED (1<<0) +#define SYS_CTRL_AP_WATCHDOG_RESET_NO (0<<0) +#define SYS_CTRL_AP_GLOBALSOFT_RESET_HAPPENED (1<<4) +#define SYS_CTRL_AP_GLOBALSOFT_RESET_NO (0<<4) +#define SYS_CTRL_AP_HOSTDEBUG_RESET_HAPPENED (1<<5) +#define SYS_CTRL_AP_HOSTDEBUG_RESET_NO (0<<5) +#define SYS_CTRL_AP_ALARMCAUSE_HAPPENED (1<<6) +#define SYS_CTRL_AP_ALARMCAUSE_NO (0<<6) +#define SYS_CTRL_AP_BOOT_MODE(n) (((n)&0xFFFF)<<8) +#define SYS_CTRL_AP_BOOT_MODE_MASK (0xFFFF<<8) +#define SYS_CTRL_AP_BOOT_MODE_SHIFT (8) +#define SYS_CTRL_AP_SW_BOOT_MODE(n) (((n)&0x7F)<<24) +#define SYS_CTRL_AP_SW_BOOT_MODE_MASK (0x7F<<24) +#define SYS_CTRL_AP_SW_BOOT_MODE_SHIFT (24) +#define SYS_CTRL_AP_FONCTIONAL_TEST_MODE (1<<31) + +//CPU_Rst_Set +#define SYS_CTRL_AP_SET_CPU_RST_CORE (1<<0) +#define SYS_CTRL_AP_SET_CPU_RST_SYS (1<<1) +#define SYS_CTRL_AP_SOFT_RST (1<<31) +#define SYS_CTRL_AP_SET_CPU_RST(n) (((n)&3)<<0) +#define SYS_CTRL_AP_SET_CPU_RST_MASK (3<<0) +#define SYS_CTRL_AP_SET_CPU_RST_SHIFT (0) + +//CPU_Rst_Clr +#define SYS_CTRL_AP_CLR_CPU_RST_CORE (1<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_SYS (1<<1) +#define SYS_CTRL_AP_CLR_CPU_RST(n) (((n)&3)<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_MASK (3<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_SHIFT (0) + +//AXI_Rst_Set +#define SYS_CTRL_AP_SET_AXI_RST_VOC (1<<0) +#define SYS_CTRL_AP_SET_AXI_RST_DMA (1<<1) +#define SYS_CTRL_AP_SET_AXI_RST_SYS (1<<2) +#define SYS_CTRL_AP_SET_AXI_RST_CONNECT (1<<3) +#define SYS_CTRL_AP_SET_AHB0_RST_GPU (1<<4) +#define SYS_CTRL_AP_SET_APB0_RST_VPU (1<<5) +#define SYS_CTRL_AP_SET_APB0_RST_IRQ (1<<6) +#define SYS_CTRL_AP_SET_AXI_RST(n) (((n)&0x7F)<<0) +#define SYS_CTRL_AP_SET_AXI_RST_MASK (0x7F<<0) +#define SYS_CTRL_AP_SET_AXI_RST_SHIFT (0) + +//AXI_Rst_Clr +#define SYS_CTRL_AP_CLR_AXI_RST_VOC (1<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_DMA (1<<1) +#define SYS_CTRL_AP_CLR_AXI_RST_SYS (1<<2) +#define SYS_CTRL_AP_CLR_AXI_RST_CONNECT (1<<3) +#define SYS_CTRL_AP_CLR_AHB0_RST_GPU (1<<4) +#define SYS_CTRL_AP_CLR_APB0_RST_VPU (1<<5) +#define SYS_CTRL_AP_CLR_APB0_RST_IRQ (1<<6) +#define SYS_CTRL_AP_CLR_AXI_RST(n) (((n)&0x7F)<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_MASK (0x7F<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_SHIFT (0) + +//AXIDIV2_Rst_Set +#define SYS_CTRL_AP_SET_AXIDIV2_RST_IMEM (1<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_SYS (1<<1) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_VPU (1<<2) +#define SYS_CTRL_AP_SET_AXIDIV2_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_MASK (7<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_SHIFT (0) + +//AXIDIV2_Rst_Clr +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_IMEM (1<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SYS (1<<1) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_VPU (1<<2) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_MASK (7<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SHIFT (0) + +//GCG_Rst_Set +#define SYS_CTRL_AP_SET_GCG_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_GCG_RST_GOUDA (1<<1) +#define SYS_CTRL_AP_SET_GCG_RST_CAMERA (1<<2) +#define SYS_CTRL_AP_SET_GCG_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_SET_GCG_RST_MASK (7<<0) +#define SYS_CTRL_AP_SET_GCG_RST_SHIFT (0) + +//GCG_Rst_Clr +#define SYS_CTRL_AP_CLR_GCG_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_GOUDA (1<<1) +#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA (1<<2) +#define SYS_CTRL_AP_CLR_GCG_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_MASK (7<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_SHIFT (0) + +//AHB1_Rst_Set +#define SYS_CTRL_AP_SET_AHB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_USBC (1<<1) +#define SYS_CTRL_AP_SET_AHB1_RST_SPIFLASH (1<<2) +#define SYS_CTRL_AP_SET_AHB1_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_MASK (7<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_SHIFT (0) + +//AHB1_Rst_Clr +#define SYS_CTRL_AP_CLR_AHB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_USBC (1<<1) +#define SYS_CTRL_AP_CLR_AHB1_RST_SPIFLASH (1<<2) +#define SYS_CTRL_AP_CLR_AHB1_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_MASK (7<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_SHIFT (0) + +//APB1_Rst_Set +#define SYS_CTRL_AP_SET_APB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_APB1_RST_TIMER (1<<1) +#define SYS_CTRL_AP_SET_APB1_RST_KEYPAD (1<<2) +#define SYS_CTRL_AP_SET_APB1_RST_GPIO (1<<3) +#define SYS_CTRL_AP_SET_APB1_RST_PWM (1<<4) +#define SYS_CTRL_AP_SET_APB1_RST_AIF (1<<5) +#define SYS_CTRL_AP_SET_APB1_RST_AUIFC (1<<6) +#define SYS_CTRL_AP_SET_APB1_RST_I2C1 (1<<7) +#define SYS_CTRL_AP_SET_APB1_RST_I2C2 (1<<8) +#define SYS_CTRL_AP_SET_APB1_RST_I2C3 (1<<9) +#define SYS_CTRL_AP_SET_APB1_RST_COM_REGS (1<<10) +#define SYS_CTRL_AP_SET_APB1_RST_DMC (1<<11) +#define SYS_CTRL_AP_SET_APB1_RST_DDRPHY_P (1<<12) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XCPU (1<<13) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BCPU (1<<14) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_AHBC (1<<15) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_DMA (1<<16) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_A2A (1<<17) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XIFC (1<<18) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BIFC (1<<19) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BAHBC (1<<20) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_MEM_BRIDGE (1<<21) +#define SYS_CTRL_AP_SET_APB1_RST(n) (((n)&0x3FFFFF)<<0) +#define SYS_CTRL_AP_SET_APB1_RST_MASK (0x3FFFFF<<0) +#define SYS_CTRL_AP_SET_APB1_RST_SHIFT (0) + +//APB1_Rst_Clr +#define SYS_CTRL_AP_CLR_APB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_TIMER (1<<1) +#define SYS_CTRL_AP_CLR_APB1_RST_KEYPAD (1<<2) +#define SYS_CTRL_AP_CLR_APB1_RST_GPIO (1<<3) +#define SYS_CTRL_AP_CLR_APB1_RST_PWM (1<<4) +#define SYS_CTRL_AP_CLR_APB1_RST_AIF (1<<5) +#define SYS_CTRL_AP_CLR_APB1_RST_AUIFC (1<<6) +#define SYS_CTRL_AP_CLR_APB1_RST_I2C1 (1<<7) +#define SYS_CTRL_AP_CLR_APB1_RST_I2C2 (1<<8) +#define SYS_CTRL_AP_CLR_APB1_RST_I2C3 (1<<9) +#define SYS_CTRL_AP_CLR_APB1_RST_COM_REGS (1<<10) +#define SYS_CTRL_AP_CLR_APB1_RST_DMC (1<<11) +#define SYS_CTRL_AP_CLR_APB1_RST_DDRPHY_P (1<<12) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XCPU (1<<13) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BCPU (1<<14) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_AHBC (1<<15) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_DMA (1<<16) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_A2A (1<<17) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XIFC (1<<18) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BIFC (1<<19) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BAHBC (1<<20) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_MEM_BRIDGE (1<<21) +#define SYS_CTRL_AP_CLR_APB1_RST(n) (((n)&0x3FFFFF)<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_MASK (0x3FFFFF<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_SHIFT (0) + +//APB2_Rst_Set +#define SYS_CTRL_AP_SET_APB2_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_APB2_RST_IFC (1<<1) +#define SYS_CTRL_AP_SET_APB2_RST_UART1 (1<<2) +#define SYS_CTRL_AP_SET_APB2_RST_UART2 (1<<3) +#define SYS_CTRL_AP_SET_APB2_RST_UART3 (1<<4) +#define SYS_CTRL_AP_SET_APB2_RST_SPI1 (1<<5) +#define SYS_CTRL_AP_SET_APB2_RST_SPI2 (1<<6) +#define SYS_CTRL_AP_SET_APB2_RST_SPI3 (1<<7) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC1 (1<<8) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC2 (1<<9) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC3 (1<<10) +#define SYS_CTRL_AP_SET_APB2_RST_NANDFLASH (1<<11) +#define SYS_CTRL_AP_SET_APB2_RST(n) (((n)&0xFFF)<<0) +#define SYS_CTRL_AP_SET_APB2_RST_MASK (0xFFF<<0) +#define SYS_CTRL_AP_SET_APB2_RST_SHIFT (0) + +//APB2_Rst_Clr +#define SYS_CTRL_AP_CLR_APB2_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_IFC (1<<1) +#define SYS_CTRL_AP_CLR_APB2_RST_UART1 (1<<2) +#define SYS_CTRL_AP_CLR_APB2_RST_UART2 (1<<3) +#define SYS_CTRL_AP_CLR_APB2_RST_UART3 (1<<4) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI1 (1<<5) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI2 (1<<6) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI3 (1<<7) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC1 (1<<8) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC2 (1<<9) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC3 (1<<10) +#define SYS_CTRL_AP_CLR_APB2_RST_NANDFLASH (1<<11) +#define SYS_CTRL_AP_CLR_APB2_RST(n) (((n)&0xFFF)<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_MASK (0xFFF<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_SHIFT (0) + +//MEM_Rst_Set +#define SYS_CTRL_AP_SET_MEM_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_MEM_RST_GPU (1<<1) +#define SYS_CTRL_AP_SET_MEM_RST_VPU (1<<2) +#define SYS_CTRL_AP_SET_MEM_RST_DMC (1<<3) +#define SYS_CTRL_AP_SET_MEM_RST_DDRPHY_P (1<<4) +#define SYS_CTRL_AP_SET_MEM_RST(n) (((n)&31)<<0) +#define SYS_CTRL_AP_SET_MEM_RST_MASK (31<<0) +#define SYS_CTRL_AP_SET_MEM_RST_SHIFT (0) + +//MEM_Rst_Clr +#define SYS_CTRL_AP_CLR_MEM_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_GPU (1<<1) +#define SYS_CTRL_AP_CLR_MEM_RST_VPU (1<<2) +#define SYS_CTRL_AP_CLR_MEM_RST_DMC (1<<3) +#define SYS_CTRL_AP_CLR_MEM_RST_DDRPHY_P (1<<4) +#define SYS_CTRL_AP_CLR_MEM_RST(n) (((n)&31)<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_MASK (31<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_SHIFT (0) + +//Clk_CPU_Mode +#define SYS_CTRL_AP_MODE_CLK_CPU_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_CPU_MANUAL (1<<0) + +//Clk_CPU_Enable +#define SYS_CTRL_AP_ENABLE_CPU_CORE (1<<0) +#define SYS_CTRL_AP_ENABLE_CPU_DUMMY (1<<1) +#define SYS_CTRL_AP_ENABLE_CLK_CPU(n) (((n)&3)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_CPU_MASK (3<<0) +#define SYS_CTRL_AP_ENABLE_CLK_CPU_SHIFT (0) + +//Clk_CPU_Disable +#define SYS_CTRL_AP_DISABLE_CPU_CORE (1<<0) +#define SYS_CTRL_AP_DISABLE_CPU_DUMMY (1<<1) +#define SYS_CTRL_AP_DISABLE_CLK_CPU(n) (((n)&3)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_CPU_MASK (3<<0) +#define SYS_CTRL_AP_DISABLE_CLK_CPU_SHIFT (0) + +//Clk_AXI_Mode +#define SYS_CTRL_AP_MODE_AHB0_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_AHB0_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB0_CONF_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB0_CONF_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_AXI_VOC_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_AXI_VOC_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_AXI_DMA_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_AXI_DMA_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_CLK_AXI(n) (((n)&15)<<0) +#define SYS_CTRL_AP_MODE_CLK_AXI_MASK (15<<0) +#define SYS_CTRL_AP_MODE_CLK_AXI_SHIFT (0) + +//Clk_AXI_Enable +#define SYS_CTRL_AP_ENABLE_AHB0_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB0_CONF (1<<1) +#define SYS_CTRL_AP_ENABLE_AXI_VOC (1<<2) +#define SYS_CTRL_AP_ENABLE_AXI_DMA (1<<3) +#define SYS_CTRL_AP_ENABLE_AXI_ALWAYS (1<<4) +#define SYS_CTRL_AP_ENABLE_AXI_CONNECT (1<<5) +#define SYS_CTRL_AP_ENABLE_APB0_IRQ (1<<6) +#define SYS_CTRL_AP_ENABLE_CLK_AXI(n) (((n)&0x7F)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXI_MASK (0x7F<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXI_SHIFT (0) + +//Clk_AXI_Disable +#define SYS_CTRL_AP_DISABLE_AHB0_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB0_CONF (1<<1) +#define SYS_CTRL_AP_DISABLE_AXI_VOC (1<<2) +#define SYS_CTRL_AP_DISABLE_AXI_DMA (1<<3) +#define SYS_CTRL_AP_DISABLE_AXI_ALWAYS (1<<4) +#define SYS_CTRL_AP_DISABLE_AXI_CONNECT (1<<5) +#define SYS_CTRL_AP_DISABLE_APB0_IRQ (1<<6) +#define SYS_CTRL_AP_DISABLE_CLK_AXI(n) (((n)&0x7F)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXI_MASK (0x7F<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXI_SHIFT (0) + +//Clk_AXIDIV2_Mode +#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_MANUAL (1<<0) + +//Clk_AXIDIV2_Enable +#define SYS_CTRL_AP_ENABLE_AXIDIV2_IMEM (1<<0) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_ALWAYS (1<<1) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_CONNECT (1<<2) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_VPU (1<<3) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2(n) (((n)&15)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_MASK (15<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_SHIFT (0) + +//Clk_AXIDIV2_Disable +#define SYS_CTRL_AP_DISABLE_AXIDIV2_IMEM (1<<0) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_ALWAYS (1<<1) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_CONNECT (1<<2) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_VPU (1<<3) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2(n) (((n)&15)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_MASK (15<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_SHIFT (0) + +//Clk_GCG_Mode +#define SYS_CTRL_AP_MODE_GCG_APB_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_GCG_APB_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_GCG_GOUDA_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_GCG_CAMERA_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_CLK_GCG(n) (((n)&7)<<0) +#define SYS_CTRL_AP_MODE_CLK_GCG_MASK (7<<0) +#define SYS_CTRL_AP_MODE_CLK_GCG_SHIFT (0) + +//Clk_GCG_Enable +#define SYS_CTRL_AP_ENABLE_GCG_APB_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_GCG_GOUDA (1<<1) +#define SYS_CTRL_AP_ENABLE_GCG_CAMERA (1<<2) +#define SYS_CTRL_AP_ENABLE_GCG_ALWAYS (1<<3) +#define SYS_CTRL_AP_ENABLE_GCG_CONNECT (1<<4) +#define SYS_CTRL_AP_ENABLE_CLK_GCG(n) (((n)&31)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_GCG_MASK (31<<0) +#define SYS_CTRL_AP_ENABLE_CLK_GCG_SHIFT (0) + +//Clk_GCG_Disable +#define SYS_CTRL_AP_DISABLE_GCG_APB_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_GCG_GOUDA (1<<1) +#define SYS_CTRL_AP_DISABLE_GCG_CAMERA (1<<2) +#define SYS_CTRL_AP_DISABLE_GCG_ALWAYS (1<<3) +#define SYS_CTRL_AP_DISABLE_GCG_CONNECT (1<<4) +#define SYS_CTRL_AP_DISABLE_CLK_GCG(n) (((n)&31)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_GCG_MASK (31<<0) +#define SYS_CTRL_AP_DISABLE_CLK_GCG_SHIFT (0) + +//Clk_AHB1_Mode +#define SYS_CTRL_AP_MODE_CLK_AHB1_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_AHB1_MANUAL (1<<0) + +//Clk_AHB1_Enable +#define SYS_CTRL_AP_ENABLE_AHB1_USBC (1<<0) +#define SYS_CTRL_AP_ENABLE_AHB1_ALWAYS (1<<1) +#define SYS_CTRL_AP_ENABLE_AHB1_SPIFLASH (1<<2) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1(n) (((n)&7)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1_MASK (7<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1_SHIFT (0) + +//Clk_AHB1_Disable +#define SYS_CTRL_AP_DISABLE_AHB1_USBC (1<<0) +#define SYS_CTRL_AP_DISABLE_AHB1_ALWAYS (1<<1) +#define SYS_CTRL_AP_DISABLE_AHB1_SPIFLASH (1<<2) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1(n) (((n)&7)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1_MASK (7<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1_SHIFT (0) + +//Clk_APB1_Mode +#define SYS_CTRL_AP_MODE_APB1_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APB1_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB1_AIF_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB1_AIF_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APB1_I2C1_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APB1_I2C1_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APB1_I2C2_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APB1_I2C2_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APB1_I2C3_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APB1_I2C3_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APB1D_OSC_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APB1D_OSC_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_APB1D_PWM_AUTOMATIC (0<<9) +#define SYS_CTRL_AP_MODE_APB1D_PWM_MANUAL (1<<9) +#define SYS_CTRL_AP_MODE_CLK_APB1(n) (((n)&0x3FF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APB1_MASK (0x3FF<<0) +#define SYS_CTRL_AP_MODE_CLK_APB1_SHIFT (0) + +//Clk_APB1_Enable +#define SYS_CTRL_AP_ENABLE_APB1_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB1_AIF (1<<1) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC (1<<2) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH0 (1<<3) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH1 (1<<4) +#define SYS_CTRL_AP_ENABLE_APB1_I2C1 (1<<5) +#define SYS_CTRL_AP_ENABLE_APB1_I2C2 (1<<6) +#define SYS_CTRL_AP_ENABLE_APB1_I2C3 (1<<7) +#define SYS_CTRL_AP_ENABLE_APB1D_OSC (1<<8) +#define SYS_CTRL_AP_ENABLE_APB1D_PWM (1<<9) +#define SYS_CTRL_AP_ENABLE_APB1_ALWAYS (1<<10) +#define SYS_CTRL_AP_ENABLE_APB1_DAPLITE (1<<11) +#define SYS_CTRL_AP_ENABLE_APB1_TIMER (1<<12) +#define SYS_CTRL_AP_ENABLE_APB1_GPIO (1<<13) +#define SYS_CTRL_AP_ENABLE_CLK_APB1(n) (((n)&0x3FFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB1_MASK (0x3FFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB1_SHIFT (0) + +//Clk_APB1_Disable +#define SYS_CTRL_AP_DISABLE_APB1_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB1_AIF (1<<1) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC (1<<2) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH0 (1<<3) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH1 (1<<4) +#define SYS_CTRL_AP_DISABLE_APB1_I2C1 (1<<5) +#define SYS_CTRL_AP_DISABLE_APB1_I2C2 (1<<6) +#define SYS_CTRL_AP_DISABLE_APB1_I2C3 (1<<7) +#define SYS_CTRL_AP_DISABLE_APB1D_OSC (1<<8) +#define SYS_CTRL_AP_DISABLE_APB1D_PWM (1<<9) +#define SYS_CTRL_AP_DISABLE_APB1_ALWAYS (1<<10) +#define SYS_CTRL_AP_DISABLE_APB1_DAPLITE (1<<11) +#define SYS_CTRL_AP_DISABLE_APB1_TIMER (1<<12) +#define SYS_CTRL_AP_DISABLE_APB1_GPIO (1<<13) +#define SYS_CTRL_AP_DISABLE_CLK_APB1(n) (((n)&0x3FFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB1_MASK (0x3FFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB1_SHIFT (0) + +//Clk_APB2_Mode +#define SYS_CTRL_AP_MODE_APB2_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APB2_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB2_IFC_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB2_IFC_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_AUTOMATIC (0<<9) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_MANUAL (1<<9) +#define SYS_CTRL_AP_MODE_APB2_UART1_AUTOMATIC (0<<10) +#define SYS_CTRL_AP_MODE_APB2_UART1_MANUAL (1<<10) +#define SYS_CTRL_AP_MODE_APB2_UART2_AUTOMATIC (0<<11) +#define SYS_CTRL_AP_MODE_APB2_UART2_MANUAL (1<<11) +#define SYS_CTRL_AP_MODE_APB2_UART3_AUTOMATIC (0<<12) +#define SYS_CTRL_AP_MODE_APB2_UART3_MANUAL (1<<12) +#define SYS_CTRL_AP_MODE_APB2_SPI1_AUTOMATIC (0<<13) +#define SYS_CTRL_AP_MODE_APB2_SPI1_MANUAL (1<<13) +#define SYS_CTRL_AP_MODE_APB2_SPI2_AUTOMATIC (0<<14) +#define SYS_CTRL_AP_MODE_APB2_SPI2_MANUAL (1<<14) +#define SYS_CTRL_AP_MODE_APB2_SPI3_AUTOMATIC (0<<15) +#define SYS_CTRL_AP_MODE_APB2_SPI3_MANUAL (1<<15) +#define SYS_CTRL_AP_MODE_APB2_SDMMC1_AUTOMATIC (0<<16) +#define SYS_CTRL_AP_MODE_APB2_SDMMC1_MANUAL (1<<16) +#define SYS_CTRL_AP_MODE_APB2_SDMMC2_AUTOMATIC (0<<17) +#define SYS_CTRL_AP_MODE_APB2_SDMMC2_MANUAL (1<<17) +#define SYS_CTRL_AP_MODE_APB2_SDMMC3_AUTOMATIC (0<<18) +#define SYS_CTRL_AP_MODE_APB2_SDMMC3_MANUAL (1<<18) +#define SYS_CTRL_AP_MODE_CLK_APB2(n) (((n)&0x7FFFF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APB2_MASK (0x7FFFF<<0) +#define SYS_CTRL_AP_MODE_CLK_APB2_SHIFT (0) + +//Clk_APB2_Enable +#define SYS_CTRL_AP_ENABLE_APB2_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB2_IFC (1<<1) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH0 (1<<2) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH1 (1<<3) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH2 (1<<4) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH3 (1<<5) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH4 (1<<6) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH5 (1<<7) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH6 (1<<8) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH7 (1<<9) +#define SYS_CTRL_AP_ENABLE_APB2_UART1 (1<<10) +#define SYS_CTRL_AP_ENABLE_APB2_UART2 (1<<11) +#define SYS_CTRL_AP_ENABLE_APB2_UART3 (1<<12) +#define SYS_CTRL_AP_ENABLE_APB2_SPI1 (1<<13) +#define SYS_CTRL_AP_ENABLE_APB2_SPI2 (1<<14) +#define SYS_CTRL_AP_ENABLE_APB2_SPI3 (1<<15) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC1 (1<<16) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC2 (1<<17) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC3 (1<<18) +#define SYS_CTRL_AP_ENABLE_APB2_ALWAYS (1<<19) +#define SYS_CTRL_AP_ENABLE_APB2_NANDFLASH (1<<20) +#define SYS_CTRL_AP_ENABLE_CLK_APB2(n) (((n)&0x1FFFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB2_MASK (0x1FFFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB2_SHIFT (0) + +//Clk_APB2_Disable +#define SYS_CTRL_AP_DISABLE_APB2_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB2_IFC (1<<1) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH0 (1<<2) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH1 (1<<3) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH2 (1<<4) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH3 (1<<5) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH4 (1<<6) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH5 (1<<7) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH6 (1<<8) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH7 (1<<9) +#define SYS_CTRL_AP_DISABLE_APB2_UART1 (1<<10) +#define SYS_CTRL_AP_DISABLE_APB2_UART2 (1<<11) +#define SYS_CTRL_AP_DISABLE_APB2_UART3 (1<<12) +#define SYS_CTRL_AP_DISABLE_APB2_SPI1 (1<<13) +#define SYS_CTRL_AP_DISABLE_APB2_SPI2 (1<<14) +#define SYS_CTRL_AP_DISABLE_APB2_SPI3 (1<<15) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC1 (1<<16) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC2 (1<<17) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC3 (1<<18) +#define SYS_CTRL_AP_DISABLE_APB2_ALWAYS (1<<19) +#define SYS_CTRL_AP_DISABLE_APB2_NANDFLASH (1<<20) +#define SYS_CTRL_AP_DISABLE_CLK_APB2(n) (((n)&0x1FFFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB2_MASK (0x1FFFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB2_SHIFT (0) + +//Clk_MEM_Mode +#define SYS_CTRL_AP_MODE_CLK_MEM_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_MEM_MANUAL (1<<0) + +//Clk_MEM_Enable +#define SYS_CTRL_AP_ENABLE_MEM_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_MEM_DMC (1<<1) +#define SYS_CTRL_AP_ENABLE_MEM_GPU (1<<2) +#define SYS_CTRL_AP_ENABLE_MEM_VPU (1<<3) +#define SYS_CTRL_AP_ENABLE_MEM_DDRPHY_P (1<<4) +#define SYS_CTRL_AP_ENABLE_MEM_CONNECT (1<<5) +#define SYS_CTRL_AP_ENABLE_CLK_MEM(n) (((n)&0x3F)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_MEM_MASK (0x3F<<0) +#define SYS_CTRL_AP_ENABLE_CLK_MEM_SHIFT (0) + +//Clk_MEM_Disable +#define SYS_CTRL_AP_DISABLE_MEM_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_MEM_DMC (1<<1) +#define SYS_CTRL_AP_DISABLE_MEM_GPU (1<<2) +#define SYS_CTRL_AP_DISABLE_MEM_VPU (1<<3) +#define SYS_CTRL_AP_DISABLE_MEM_DDRPHY_P (1<<4) +#define SYS_CTRL_AP_DISABLE_MEM_CONNECT (1<<5) +#define SYS_CTRL_AP_DISABLE_CLK_MEM(n) (((n)&0x3F)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_MEM_MASK (0x3F<<0) +#define SYS_CTRL_AP_DISABLE_CLK_MEM_SHIFT (0) + +//Clk_APO_Mode +#define SYS_CTRL_AP_MODE_APOC_VPU_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APOC_VPU_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APOC_BCK_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APOC_BCK_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APOC_UART1_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APOC_UART1_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APOC_UART2_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APOC_UART2_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APOC_UART3_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APOC_UART3_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APOC_VOC_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APOC_VOC_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_CLK_APO(n) (((n)&0x7F)<<0) +#define SYS_CTRL_AP_MODE_CLK_APO_MASK (0x7F<<0) +#define SYS_CTRL_AP_MODE_CLK_APO_SHIFT (0) + +//Clk_APO_Enable +#define SYS_CTRL_AP_ENABLE_APOC_VPU (1<<0) +#define SYS_CTRL_AP_ENABLE_APOC_BCK (1<<1) +#define SYS_CTRL_AP_ENABLE_APOC_UART1 (1<<2) +#define SYS_CTRL_AP_ENABLE_APOC_UART2 (1<<3) +#define SYS_CTRL_AP_ENABLE_APOC_UART3 (1<<4) +#define SYS_CTRL_AP_ENABLE_APOC_VOC_CORE (1<<5) +#define SYS_CTRL_AP_ENABLE_APOC_VOC (1<<6) +#define SYS_CTRL_AP_ENABLE_APOC_VOC_ALWAYS (1<<7) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY_N (1<<8) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XP (1<<9) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XN (1<<10) +#define SYS_CTRL_AP_ENABLE_APOC_GPU (1<<11) +#define SYS_CTRL_AP_ENABLE_APOC_USBPHY (1<<12) +#define SYS_CTRL_AP_ENABLE_APOC_CSI (1<<13) +#define SYS_CTRL_AP_ENABLE_APOC_DSI (1<<14) +#define SYS_CTRL_AP_ENABLE_APOC_GPIO (1<<15) +#define SYS_CTRL_AP_ENABLE_APOC_SPIFLASH (1<<16) +#define SYS_CTRL_AP_ENABLE_APOC_PIX (1<<17) +#define SYS_CTRL_AP_ENABLE_APOC_PDGB (1<<18) +#define SYS_CTRL_AP_ENABLE_CLK_APO(n) (((n)&0x7FFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APO_MASK (0x7FFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APO_SHIFT (0) + +//Clk_APO_Disable +#define SYS_CTRL_AP_DISABLE_APOC_VPU (1<<0) +#define SYS_CTRL_AP_DISABLE_APOC_BCK (1<<1) +#define SYS_CTRL_AP_DISABLE_APOC_UART1 (1<<2) +#define SYS_CTRL_AP_DISABLE_APOC_UART2 (1<<3) +#define SYS_CTRL_AP_DISABLE_APOC_UART3 (1<<4) +#define SYS_CTRL_AP_DISABLE_APOC_VOC_CORE (1<<5) +#define SYS_CTRL_AP_DISABLE_APOC_VOC (1<<6) +#define SYS_CTRL_AP_DISABLE_APOC_VOC_ALWAYS (1<<7) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY_N (1<<8) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XP (1<<9) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XN (1<<10) +#define SYS_CTRL_AP_DISABLE_APOC_GPU (1<<11) +#define SYS_CTRL_AP_DISABLE_APOC_USBPHY (1<<12) +#define SYS_CTRL_AP_DISABLE_APOC_CSI (1<<13) +#define SYS_CTRL_AP_DISABLE_APOC_DSI (1<<14) +#define SYS_CTRL_AP_DISABLE_APOC_GPIO (1<<15) +#define SYS_CTRL_AP_DISABLE_APOC_SPIFLASH (1<<16) +#define SYS_CTRL_AP_DISABLE_APOC_PIX (1<<17) +#define SYS_CTRL_AP_DISABLE_APOC_PDGB (1<<18) +#define SYS_CTRL_AP_DISABLE_CLK_APO(n) (((n)&0x7FFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APO_MASK (0x7FFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APO_SHIFT (0) + +//Cfg_Clk_AP_CPU +#define SYS_CTRL_AP_AP_CPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_CPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_BUS_DIV_SEL(n) (((n)&3)<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_MASK (3<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_SHIFT (16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV2 (0<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV3 (1<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV4 (2<<16) +#define SYS_CTRL_AP_AP_CPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_AXI +#define SYS_CTRL_AP_AP_AXI_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_AXI_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_AXI_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_AXI_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_GCG +#define SYS_CTRL_AP_AP_GCG_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_GCG_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_GCG_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_GCG_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_AHB1 +#define SYS_CTRL_AP_AP_AHB1_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_AHB1_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_AHB1_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_APB1 +#define SYS_CTRL_AP_AP_APB1_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_APB1_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_APB1_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_APB1_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_APB2 +#define SYS_CTRL_AP_AP_APB2_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_APB2_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_APB2_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_APB2_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_MEM +#define SYS_CTRL_AP_AP_MEM_SRC_DIV2 (1<<12) + +//Cfg_Clk_AP_GPU +#define SYS_CTRL_AP_AP_GPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_GPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_GPU_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_GPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_VPU +#define SYS_CTRL_AP_AP_VPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_VPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_VPU_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_VPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_VOC +#define SYS_CTRL_AP_AP_VOC_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_SFLSH +#define SYS_CTRL_AP_AP_SFLSH_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_SFLSH_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_SFLSH_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_Uart +#define SYS_CTRL_AP_UART_DIVIDER(n) (((n)&0x3FF)<<0) +#define SYS_CTRL_AP_UART_DIVIDER_MASK (0x3FF<<0) +#define SYS_CTRL_AP_UART_DIVIDER_SHIFT (0) +#define SYS_CTRL_AP_UART_SEL_PLL_SLOW (0<<12) +#define SYS_CTRL_AP_UART_SEL_PLL_PLL (1<<12) + +//L2cc_Ctrl +#define SYS_CTRL_AP_ARQOS_L2CC_1_M(n) (((n)&15)<<0) +#define SYS_CTRL_AP_ARQOS_L2CC_1_M_MASK (15<<0) +#define SYS_CTRL_AP_ARQOS_L2CC_1_M_SHIFT (0) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M(n) (((n)&15)<<4) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M_MASK (15<<4) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M_SHIFT (4) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<8) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_MASK (15<<8) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_SHIFT (8) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<12) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_MASK (15<<12) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_SHIFT (12) +#define SYS_CTRL_AP_ARAP_L2CC_1_M (1<<16) +#define SYS_CTRL_AP_AWAP_L2CC_1_M (1<<17) +#define SYS_CTRL_AP_ARAP_MODEM_MEM_AHBS_M (1<<18) +#define SYS_CTRL_AP_AWAP_MODEM_MEM_AHBS_M (1<<19) +#define SYS_CTRL_AP_ARAP_MERGE1M (1<<20) +#define SYS_CTRL_AP_AWAP_MERGE1M (1<<21) +#define SYS_CTRL_AP_ARAP_MERGE2M (1<<22) +#define SYS_CTRL_AP_AWAP_MERGE2M (1<<23) +#define SYS_CTRL_AP_RESERVE1(n) (((n)&0xFF)<<24) +#define SYS_CTRL_AP_RESERVE1_MASK (0xFF<<24) +#define SYS_CTRL_AP_RESERVE1_SHIFT (24) + +//Spi_Ctrl +#define SYS_CTRL_AP_LIMITED_EN_SPI1 (1<<0) +#define SYS_CTRL_AP_LPSEN_SPI1 (1<<1) +#define SYS_CTRL_AP_LIMITED_EN_SPI2 (1<<2) +#define SYS_CTRL_AP_LPSEN_SPI2 (1<<3) +#define SYS_CTRL_AP_LIMITED_EN_SPI3 (1<<4) +#define SYS_CTRL_AP_LPSEN_SPI3 (1<<5) +#define SYS_CTRL_AP_FBUSWID_NFSC (1<<6) +#define SYS_CTRL_AP_RESERVE3 (1<<7) +#define SYS_CTRL_AP_DMC_CFG(n) (((n)&0x3FF)<<8) +#define SYS_CTRL_AP_DMC_CFG_MASK (0x3FF<<8) +#define SYS_CTRL_AP_DMC_CFG_SHIFT (8) +#define SYS_CTRL_AP_RESERVE2(n) (((n)&0x3FFF)<<18) +#define SYS_CTRL_AP_RESERVE2_MASK (0x3FFF<<18) +#define SYS_CTRL_AP_RESERVE2_SHIFT (18) + +//Memory_Margin +#define SYS_CTRL_AP_EMAW_VOC(n) (((n)&3)<<0) +#define SYS_CTRL_AP_EMAW_VOC_MASK (3<<0) +#define SYS_CTRL_AP_EMAW_VOC_SHIFT (0) +#define SYS_CTRL_AP_EMA_VOC(n) (((n)&7)<<2) +#define SYS_CTRL_AP_EMA_VOC_MASK (7<<2) +#define SYS_CTRL_AP_EMA_VOC_SHIFT (2) +#define SYS_CTRL_AP_EMAW_VPU(n) (((n)&3)<<5) +#define SYS_CTRL_AP_EMAW_VPU_MASK (3<<5) +#define SYS_CTRL_AP_EMAW_VPU_SHIFT (5) +#define SYS_CTRL_AP_EMA_VPU(n) (((n)&7)<<7) +#define SYS_CTRL_AP_EMA_VPU_MASK (7<<7) +#define SYS_CTRL_AP_EMA_VPU_SHIFT (7) +#define SYS_CTRL_AP_EMAW_GPU(n) (((n)&3)<<10) +#define SYS_CTRL_AP_EMAW_GPU_MASK (3<<10) +#define SYS_CTRL_AP_EMAW_GPU_SHIFT (10) +#define SYS_CTRL_AP_EMA_GPU(n) (((n)&7)<<12) +#define SYS_CTRL_AP_EMA_GPU_MASK (7<<12) +#define SYS_CTRL_AP_EMA_GPU_SHIFT (12) +#define SYS_CTRL_AP_EMAW_GOUDA(n) (((n)&3)<<15) +#define SYS_CTRL_AP_EMAW_GOUDA_MASK (3<<15) +#define SYS_CTRL_AP_EMAW_GOUDA_SHIFT (15) +#define SYS_CTRL_AP_EMA_GOUDA(n) (((n)&7)<<17) +#define SYS_CTRL_AP_EMA_GOUDA_MASK (7<<17) +#define SYS_CTRL_AP_EMA_GOUDA_SHIFT (17) +#define SYS_CTRL_AP_EMAW_IMEM(n) (((n)&3)<<20) +#define SYS_CTRL_AP_EMAW_IMEM_MASK (3<<20) +#define SYS_CTRL_AP_EMAW_IMEM_SHIFT (20) +#define SYS_CTRL_AP_EMA_IMEM(n) (((n)&7)<<22) +#define SYS_CTRL_AP_EMA_IMEM_MASK (7<<22) +#define SYS_CTRL_AP_EMA_IMEM_SHIFT (22) +#define SYS_CTRL_AP_EMAW_USB(n) (((n)&3)<<25) +#define SYS_CTRL_AP_EMAW_USB_MASK (3<<25) +#define SYS_CTRL_AP_EMAW_USB_SHIFT (25) +#define SYS_CTRL_AP_EMA_USB(n) (((n)&7)<<27) +#define SYS_CTRL_AP_EMA_USB_MASK (7<<27) +#define SYS_CTRL_AP_EMA_USB_SHIFT (27) + +//Memory_Margin2 +#define SYS_CTRL_AP_EMAW_NFSC(n) (((n)&3)<<0) +#define SYS_CTRL_AP_EMAW_NFSC_MASK (3<<0) +#define SYS_CTRL_AP_EMAW_NFSC_SHIFT (0) +#define SYS_CTRL_AP_EMA_NFSC(n) (((n)&7)<<2) +#define SYS_CTRL_AP_EMA_NFSC_MASK (7<<2) +#define SYS_CTRL_AP_EMA_NFSC_SHIFT (2) +#define SYS_CTRL_AP_EMA_VPUROM(n) (((n)&7)<<5) +#define SYS_CTRL_AP_EMA_VPUROM_MASK (7<<5) +#define SYS_CTRL_AP_EMA_VPUROM_SHIFT (5) +#define SYS_CTRL_AP_EMA_IMEMROM(n) (((n)&7)<<8) +#define SYS_CTRL_AP_EMA_IMEMROM_MASK (7<<8) +#define SYS_CTRL_AP_EMA_IMEMROM_SHIFT (8) +#define SYS_CTRL_AP_KEN_VPUROM (1<<11) +#define SYS_CTRL_AP_PGEN_VPUROM (1<<12) +#define SYS_CTRL_AP_KEN_IMEMROM (1<<13) +#define SYS_CTRL_AP_PGEN_IMEMROM (1<<14) + +//Memory_Observe +#define SYS_CTRL_AP_MEM_OBSERVE(n) (((n)&0xFFFFFFFF)<<0) + +//Cfg_Reserve +#define SYS_CTRL_AP_RESERVE(n) (((n)&0xFFFFFFFF)<<0) + +#endif diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810e.h b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810e.h new file mode 100644 index 0000000000..ab7ba4c951 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810e.h @@ -0,0 +1,1578 @@ +#ifndef _REG_SYSCTRL_H_ +#define _REG_SYSCTRL_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= + +// ============================================================================ +// AP_CPU_ID_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// CPU IDs + CPU0 = 0x00000000, + CPU1 = 0x00000001 +} AP_CPU_ID_T; + + +// ============================================================================ +// CPU_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP CPU side System clocks + CPU_CORE = 0x00000000, +/// the following don't have an auto enable + CPU_DUMMY = 0x00000001 +} CPU_CLKS_T; + +#define NB_CPU_CLK_AEN (1) +#define NB_CPU_CLK_EN (2) +#define NB_CPU_CLK (2) + +// ============================================================================ +// AXI_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXI side System clocks: AXI and AHB0 and APB0 + AHB0_CONF = 0x00000000, + APB0_CONF = 0x00000001, + AXI_VOC = 0x00000002, + AXI_DMA = 0x00000003, +/// the following don't have an auto enable + AXI_ALWAYS = 0x00000004, + AXI_CONNECT = 0x00000005, + APB0_IRQ = 0x00000006 +} AXI_CLKS_T; + +#define NB_AXI_CLK_AEN (4) +#define NB_AXI_CLK_EN (7) +#define NB_AXI_CLK (7) + +// ============================================================================ +// AXIDIV2_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXIdiv2 side System clocks + AXIDIV2_IMEM = 0x00000000, +/// the following don't have an auto enable + AXIDIV2_ALWAYS = 0x00000001, + AXIDIV2_CONNECT = 0x00000002, + AXIDIV2_VPU = 0x00000003 +} AXIDIV2_CLKS_T; + +#define NB_AXIDIV2_CLK_AEN (1) +#define NB_AXIDIV2_CLK_EN (4) +#define NB_AXIDIV2_CLK (4) + +// ============================================================================ +// GCG_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GCG side System clocks + GCG_APB_CONF = 0x00000000, + GCG_GOUDA = 0x00000001, + GCG_CAMERA = 0x00000002, +/// the following don't have an auto enable + GCG_ALWAYS = 0x00000003, + GCG_CONNECT = 0x00000004 +} GCG_CLKS_T; + +#define NB_GCG_CLK_AEN (3) +#define NB_GCG_CLK_EN (5) +#define NB_GCG_CLK (5) + +// ============================================================================ +// AHB1_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AHB1 side System clocks + AHB1_USBC = 0x00000000, +/// the following don't have an auto enable + AHB1_ALWAYS = 0x00000001, + AHB1_SPIFLASH = 0x00000002 +} AHB1_CLKS_T; + +#define NB_AHB1_CLK_AEN (1) +#define NB_AHB1_CLK_EN (3) +#define NB_AHB1_CLK (3) + +// ============================================================================ +// APB1_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB1 side System clocks + APB1_CONF = 0x00000000, + APB1_AIF = 0x00000001, + APB1_AUIFC = 0x00000002, + APB1_AUIFC_CH0 = 0x00000003, + APB1_AUIFC_CH1 = 0x00000004, + APB1_I2C1 = 0x00000005, + APB1_I2C2 = 0x00000006, + APB1_I2C3 = 0x00000007, +/// AP APB1 side divided clock (either divided by module or by clock_ctrl) + APB1D_OSC = 0x00000008, + APB1D_PWM = 0x00000009, +/// the following don't have an auto enable + APB1_ALWAYS = 0x0000000A, + APB1_DAPLITE = 0x0000000B, + APB1_TIMER = 0x0000000C, + APB1_GPIO = 0x0000000D +} APB1_CLKS_T; + +#define NB_APB1_CLK_AEN (10) +#define NB_APB1_CLK_EN (14) +#define NB_APB1_CLK (14) + +// ============================================================================ +// APB2_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB2 side System clocks + APB2_CONF = 0x00000000, + APB2_IFC = 0x00000001, + APB2_IFC_CH0 = 0x00000002, + APB2_IFC_CH1 = 0x00000003, + APB2_IFC_CH2 = 0x00000004, + APB2_IFC_CH3 = 0x00000005, + APB2_IFC_CH4 = 0x00000006, + APB2_IFC_CH5 = 0x00000007, + APB2_IFC_CH6 = 0x00000008, + APB2_IFC_CH7 = 0x00000009, + APB2_UART1 = 0x0000000A, + APB2_UART2 = 0x0000000B, + APB2_UART3 = 0x0000000C, + APB2_SPI1 = 0x0000000D, + APB2_SPI2 = 0x0000000E, + APB2_SPI3 = 0x0000000F, + APB2_SDMMC1 = 0x00000010, + APB2_SDMMC2 = 0x00000011, + APB2_SDMMC3 = 0x00000012, +/// the following don't have an auto enable + APB2_ALWAYS = 0x00000013, + APB2_NANDFLASH = 0x00000014 +} APB2_CLKS_T; + +#define NB_APB2_CLK_AEN (19) +#define NB_APB2_CLK_EN (21) +#define NB_APB2_CLK (21) + +// ============================================================================ +// MEM_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP MEM side System clocks + MEM_CONF = 0x00000000, +/// the following don't have an auto enable + MEM_DMC = 0x00000001, + MEM_GPU = 0x00000002, + MEM_VPU = 0x00000003, + MEM_DDRPHY_P = 0x00000004, + MEM_CONNECT = 0x00000005 +} MEM_CLKS_T; + +#define NB_MEM_CLK_AEN (1) +#define NB_MEM_CLK_EN (6) +#define NB_MEM_CLK (6) + +// ============================================================================ +// APO_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP side Other clocks +/// clocks with auto enble + APOC_VPU = 0x00000000, + APOC_BCK = 0x00000001, + APOC_UART1 = 0x00000002, + APOC_UART2 = 0x00000003, + APOC_UART3 = 0x00000004, + APOC_VOC_CORE = 0x00000005, + APOC_VOC = 0x00000006, +/// the following don't have an auto enable + APOC_VOC_ALWAYS = 0x00000007, + APOC_DDRPHY_N = 0x00000008, + APOC_DDRPHY2XP = 0x00000009, + APOC_DDRPHY2XN = 0x0000000A, + APOC_GPU = 0x0000000B, + APOC_USBPHY = 0x0000000C, + APOC_CSI = 0x0000000D, + APOC_DSI = 0x0000000E, + APOC_GPIO = 0x0000000F, + APOC_SPIFLASH = 0x00000010, + APOC_PIX = 0x00000011, + APOC_PDGB = 0x00000012 +} APO_CLKS_T; + +#define NB_CLK_VOC_AEN_SYNC (5) +#define NB_CLK_VOC_CORE (6) +#define NB_APO_CLK_AEN (7) +#define NB_CLK_VOC_END (8) +#define NB_APO_CLK_EN (19) +#define NB_APO_CLK (19) + +// ============================================================================ +// CPU_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP CPU side resets + CPU_RST_CORE = 0x00000000, + CPU_RST_SYS = 0x00000001 +} CPU_RESETS_T; + +#define NB_CPU_RST (2) + +// ============================================================================ +// AXI_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXI side resets: AXI and AHB0 and APB0 + AXI_RST_VOC = 0x00000000, + AXI_RST_DMA = 0x00000001, + AXI_RST_SYS = 0x00000002, + AXI_RST_CONNECT = 0x00000003, + AHB0_RST_GPU = 0x00000004, + APB0_RST_VPU = 0x00000005, + APB0_RST_IRQ = 0x00000006 +} AXI_RESETS_T; + +#define NB_AXI_RST (7) + +// ============================================================================ +// AXIDIV2_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXIDIV2 side resets + AXIDIV2_RST_IMEM = 0x00000000, + AXIDIV2_RST_SYS = 0x00000001, + AXIDIV2_RST_VPU = 0x00000002 +} AXIDIV2_RESETS_T; + +#define NB_AXIDIV2_RST (3) + +// ============================================================================ +// GCG_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GCG side resets + GCG_RST_SYS = 0x00000000, + GCG_RST_GOUDA = 0x00000001, + GCG_RST_CAMERA = 0x00000002 +} GCG_RESETS_T; + +#define NB_GCG_RST (3) + +// ============================================================================ +// AHB1_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AHB1 side resets + AHB1_RST_SYS = 0x00000000, + AHB1_RST_USBC = 0x00000001, + AHB1_RST_SPIFLASH = 0x00000002 +} AHB1_RESETS_T; + +#define NB_AHB1_RST (3) + +// ============================================================================ +// APB1_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB1 side resets + APB1_RST_SYS = 0x00000000, + APB1_RST_TIMER = 0x00000001, + APB1_RST_KEYPAD = 0x00000002, + APB1_RST_GPIO = 0x00000003, + APB1_RST_PWM = 0x00000004, + APB1_RST_AIF = 0x00000005, + APB1_RST_AUIFC = 0x00000006, + APB1_RST_I2C1 = 0x00000007, + APB1_RST_I2C2 = 0x00000008, + APB1_RST_I2C3 = 0x00000009, + APB1_RST_COM_REGS = 0x0000000A, + APB1_RST_DMC = 0x0000000B, + APB1_RST_DDRPHY_P = 0x0000000C, + APB1_RST_BB2G_XCPU = 0x0000000D, + APB1_RST_BB2G_BCPU = 0x0000000E, + APB1_RST_BB2G_AHBC = 0x0000000F, + APB1_RST_BB2G_DMA = 0x00000010, + APB1_RST_BB2G_A2A = 0x00000011, + APB1_RST_BB2G_XIFC = 0x00000012, + APB1_RST_BB2G_BIFC = 0x00000013, + APB1_RST_BB2G_BAHBC = 0x00000014, + APB1_RST_BB2G_MEM_BRIDGE = 0x00000015 +} APB1_RESETS_T; + +#define NB_APB1_RST (22) + +// ============================================================================ +// APB2_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB2 side resets + APB2_RST_SYS = 0x00000000, + APB2_RST_IFC = 0x00000001, + APB2_RST_UART1 = 0x00000002, + APB2_RST_UART2 = 0x00000003, + APB2_RST_UART3 = 0x00000004, + APB2_RST_SPI1 = 0x00000005, + APB2_RST_SPI2 = 0x00000006, + APB2_RST_SPI3 = 0x00000007, + APB2_RST_SDMMC1 = 0x00000008, + APB2_RST_SDMMC2 = 0x00000009, + APB2_RST_SDMMC3 = 0x0000000A, + APB2_RST_NANDFLASH = 0x0000000B +} APB2_RESETS_T; + +#define NB_APB2_RST (12) + +// ============================================================================ +// MEM_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP MEM side resets + MEM_RST_SYS = 0x00000000, + MEM_RST_GPU = 0x00000001, + MEM_RST_VPU = 0x00000002, + MEM_RST_DMC = 0x00000003, + MEM_RST_DDRPHY_P = 0x00000004 +} MEM_RESETS_T; + +#define NB_MEM_RST (5) + +// ============================================================================ +// AP_OTHERS_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP Reset Other : resync on corresponding clock other + AP_RSTO_VOC = 0x00000000, + AP_RSTO_DDRPHY_N = 0x00000001, + AP_RSTO_DDRPHY2XP = 0x00000002, + AP_RSTO_DDRPHY2XN = 0x00000003, + AP_RSTO_GPU = 0x00000004, + AP_RSTO_VPU = 0x00000005, + AP_RSTO_BCK = 0x00000006, + AP_RSTO_UART1 = 0x00000007, + AP_RSTO_UART2 = 0x00000008, + AP_RSTO_UART3 = 0x00000009, + AP_RSTO_GPIO = 0x0000000A, + AP_RSTO_TIMER = 0x0000000B, + AP_RSTO_USBC = 0x0000000C, + AP_RSTO_DSI = 0x0000000D, + AP_RSTO_SPIFLASH = 0x0000000E, + AP_RSTO_TCK = 0x0000000F, + AP_RSTO_PDBG_XTAL = 0x00000010 +} AP_OTHERS_RESETS_T; + +#define NB_AP_RSTO (17) +/// For REG_DBG protect lock/unlock value +#define AP_CTRL_PROTECT_LOCK (0XA50000) +#define AP_CTRL_PROTECT_UNLOCK (0XA50001) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// SYS_CTRL_AP_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + /// <strong>This register is used to Lock and Unlock the protected registers.</strong> + REG32 REG_DBG; //0x00000000 + /// Register protected by Write_Unlocked_H. + REG32 Cfg_Pll_Ctrl[4]; //0x00000004 + /// This register is protected. + REG32 Sel_Clock; //0x00000014 + REG32 Reset_Cause; //0x00000018 + /// This register is protected. + REG32 CPU_Rst_Set; //0x0000001C + REG32 CPU_Rst_Clr; //0x00000020 + /// This register is protected. + REG32 AXI_Rst_Set; //0x00000024 + REG32 AXI_Rst_Clr; //0x00000028 + /// This register is protected. + REG32 AXIDIV2_Rst_Set; //0x0000002C + REG32 AXIDIV2_Rst_Clr; //0x00000030 + /// This register is protected. + REG32 GCG_Rst_Set; //0x00000034 + REG32 GCG_Rst_Clr; //0x00000038 + /// This register is protected. + REG32 AHB1_Rst_Set; //0x0000003C + REG32 AHB1_Rst_Clr; //0x00000040 + /// This register is protected. + REG32 APB1_Rst_Set; //0x00000044 + REG32 APB1_Rst_Clr; //0x00000048 + /// This register is protected. + REG32 APB2_Rst_Set; //0x0000004C + REG32 APB2_Rst_Clr; //0x00000050 + /// This register is protected. + REG32 MEM_Rst_Set; //0x00000054 + REG32 MEM_Rst_Clr; //0x00000058 + REG32 Clk_CPU_Mode; //0x0000005C + REG32 Clk_CPU_Enable; //0x00000060 + /// This register is protected. + REG32 Clk_CPU_Disable; //0x00000064 + REG32 Clk_AXI_Mode; //0x00000068 + REG32 Clk_AXI_Enable; //0x0000006C + /// This register is protected. + REG32 Clk_AXI_Disable; //0x00000070 + REG32 Clk_AXIDIV2_Mode; //0x00000074 + REG32 Clk_AXIDIV2_Enable; //0x00000078 + /// This register is protected. + REG32 Clk_AXIDIV2_Disable; //0x0000007C + REG32 Clk_GCG_Mode; //0x00000080 + REG32 Clk_GCG_Enable; //0x00000084 + /// This register is protected. + REG32 Clk_GCG_Disable; //0x00000088 + REG32 Clk_AHB1_Mode; //0x0000008C + REG32 Clk_AHB1_Enable; //0x00000090 + /// This register is protected. + REG32 Clk_AHB1_Disable; //0x00000094 + REG32 Clk_APB1_Mode; //0x00000098 + REG32 Clk_APB1_Enable; //0x0000009C + /// This register is protected. + REG32 Clk_APB1_Disable; //0x000000A0 + REG32 Clk_APB2_Mode; //0x000000A4 + REG32 Clk_APB2_Enable; //0x000000A8 + /// This register is protected. + REG32 Clk_APB2_Disable; //0x000000AC + REG32 Clk_MEM_Mode; //0x000000B0 + REG32 Clk_MEM_Enable; //0x000000B4 + /// This register is protected. + REG32 Clk_MEM_Disable; //0x000000B8 + REG32 Clk_APO_Mode; //0x000000BC + REG32 Clk_APO_Enable; //0x000000C0 + /// This register is protected. + REG32 Clk_APO_Disable; //0x000000C4 + REG32 Cfg_Clk_AP_CPU; //0x000000C8 + REG32 Cfg_Clk_AP_AXI; //0x000000CC + REG32 Cfg_Clk_AP_GCG; //0x000000D0 + REG32 Cfg_Clk_AP_AHB1; //0x000000D4 + REG32 Cfg_Clk_AP_APB1; //0x000000D8 + REG32 Cfg_Clk_AP_APB2; //0x000000DC + REG32 Cfg_Clk_AP_MEM; //0x000000E0 + REG32 Cfg_Clk_AP_GPU; //0x000000E4 + REG32 Cfg_Clk_AP_VPU; //0x000000E8 + REG32 Cfg_Clk_AP_VOC; //0x000000EC + REG32 Cfg_Clk_AP_SFLSH; //0x000000F0 + REG32 Cfg_Clk_Uart[3]; //0x000000F4 + REG32 L2cc_Ctrl; //0x00000100 + REG32 Spi_Ctrl; //0x00000104 + REG32 Memory_Margin; //0x00000108 + REG32 Memory_Margin2; //0x0000010C + REG32 Memory_Observe; //0x00000110 + REG32 Cfg_Clk_AP_VOC2; //0x00000114 + REG32 Cfg_Clk_EMMC; //0x00000118 + REG32 Test_Pulse; //0x0000011C + REG32 Reserved_00000114[49]; //0x00000120 + /// This register is reserved. + REG32 Cfg_Cpu_Reserve0; //0x000001E4 + REG32 Cfg_Cpu_Reserve1; //0x000001E8 + REG32 Cfg_Cpu_Reserve2; //0x000001EC + REG32 Cfg_Cpu_Reserve3; //0x000001F0 + REG32 Cfg_Cpu_Reserve4; //0x000001F4 + REG32 Cfg_Cpu_Reserve5; //0x000001F8 + REG32 Cfg_Reserve; //0x000001FC +} HWP_SYS_CTRL_AP_T; + +#define hwp_sysCtrlAp ((HWP_SYS_CTRL_AP_T*)(RDA_SYSCTRL_BASE)) + + +//REG_DBG +#define SYS_CTRL_AP_SCRATCH(n) (((n)&0xFFFF)<<0) +#define SYS_CTRL_AP_WRITE_UNLOCK_STATUS (1<<30) +#define SYS_CTRL_AP_WRITE_UNLOCK (1<<31) + +//Cfg_Pll_Ctrl +#define SYS_CTRL_AP_AP_PLL_ENABLE (1<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_MASK (1<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_SHIFT (0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN (0<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE (1<<0) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET (1<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK (1<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_SHIFT (4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET (0<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET (1<<4) +#define SYS_CTRL_AP_AP_PLL_BYPASS (1<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_MASK (1<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_SHIFT (8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_PASS (0<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_BYPASS (1<<8) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_MASK (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_SHIFT (12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_DISABLE (0<<12) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(n) (((n)&31)<<16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_MASK (31<<16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_SHIFT (16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(n) (((n)&31)<<24) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_MASK (31<<24) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_SHIFT (24) +#define SYS_CTRL_AP_PLL_AP_CFG(n) (((n)&0x1F1F1111)<<0) +#define SYS_CTRL_AP_PLL_AP_CFG_MASK (0x1F1F1111<<0) +#define SYS_CTRL_AP_PLL_AP_CFG_SHIFT (0) + +//Sel_Clock +#define SYS_CTRL_AP_SLOW_SEL_RF_OSCILLATOR (1<<0) +#define SYS_CTRL_AP_SLOW_SEL_RF_RF (0<<0) +#define SYS_CTRL_AP_TIMER_SEL_FAST_SLOW (1<<1) +#define SYS_CTRL_AP_TIMER_SEL_FAST_FAST (0<<1) +#define SYS_CTRL_AP_TIMER2_SEL_FAST_SLOW (1<<2) +#define SYS_CTRL_AP_TIMER2_SEL_FAST_FAST (0<<2) +#define SYS_CTRL_AP_TIMER3_SEL_FAST_SLOW (1<<3) +#define SYS_CTRL_AP_TIMER3_SEL_FAST_FAST (0<<3) +#define SYS_CTRL_AP_CPU_SEL_FAST_SLOW (1<<4) +#define SYS_CTRL_AP_CPU_SEL_FAST_FAST (0<<4) +#define SYS_CTRL_AP_BUS_SEL_FAST_SLOW (1<<5) +#define SYS_CTRL_AP_BUS_SEL_FAST_FAST (0<<5) +#define SYS_CTRL_AP_RF_DETECTED_OK (1<<8) +#define SYS_CTRL_AP_RF_DETECTED_NO (0<<8) +#define SYS_CTRL_AP_RF_DETECT_BYPASS (1<<9) +#define SYS_CTRL_AP_RF_DETECT_RESET (1<<10) +#define SYS_CTRL_AP_RF_SELECTED_L (1<<11) +#define SYS_CTRL_AP_PLL_LOCKED_CPU (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_MASK (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_SHIFT (12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_NOT_LOCKED (0<<12) +#define SYS_CTRL_AP_PLL_LOCKED_BUS (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_MASK (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_SHIFT (13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_NOT_LOCKED (0<<13) +#define SYS_CTRL_AP_PLL_LOCKED_MEM (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_MASK (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_SHIFT (14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_NOT_LOCKED (0<<14) +#define SYS_CTRL_AP_PLL_LOCKED_USB (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_MASK (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_SHIFT (15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_NOT_LOCKED (0<<15) +#define SYS_CTRL_AP_PLL_BYPASS_LOCK_CPU (1<<20) +#define SYS_CTRL_AP_PLL_BYPASS_LOCK_BUS (1<<21) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L (1<<30) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_MASK (1<<30) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_SHIFT (30) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L (1<<31) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_MASK (1<<31) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_SHIFT (31) + +//Reset_Cause +#define SYS_CTRL_AP_WATCHDOG_RESET_HAPPENED (1<<0) +#define SYS_CTRL_AP_WATCHDOG_RESET_NO (0<<0) +#define SYS_CTRL_AP_GLOBALSOFT_RESET_HAPPENED (1<<4) +#define SYS_CTRL_AP_GLOBALSOFT_RESET_NO (0<<4) +#define SYS_CTRL_AP_HOSTDEBUG_RESET_HAPPENED (1<<5) +#define SYS_CTRL_AP_HOSTDEBUG_RESET_NO (0<<5) +#define SYS_CTRL_AP_ALARMCAUSE_HAPPENED (1<<6) +#define SYS_CTRL_AP_ALARMCAUSE_NO (0<<6) +#define SYS_CTRL_AP_BOOT_MODE(n) (((n)&0xFFFF)<<8) +#define SYS_CTRL_AP_BOOT_MODE_MASK (0xFFFF<<8) +#define SYS_CTRL_AP_BOOT_MODE_SHIFT (8) +#define SYS_CTRL_AP_SW_BOOT_MODE(n) (((n)&0x7F)<<24) +#define SYS_CTRL_AP_SW_BOOT_MODE_MASK (0x7F<<24) +#define SYS_CTRL_AP_SW_BOOT_MODE_SHIFT (24) +#define SYS_CTRL_AP_FONCTIONAL_TEST_MODE (1<<31) + +//CPU_Rst_Set +#define SYS_CTRL_AP_SET_CPU_RST_CORE (1<<0) +#define SYS_CTRL_AP_SET_CPU_RST_CORE1 (1<<1) +#define SYS_CTRL_AP_SET_CPU_RST_CORE2 (1<<2) +#define SYS_CTRL_AP_SET_CPU_RST_CORE3 (1<<3) +#define SYS_CTRL_AP_SET_CPU_RST_L2 (1<<4) +#define SYS_CTRL_AP_SET_CPU_RST_SYS (1<<5) +#define SYS_CTRL_AP_SOFT_RST (1<<31) +#define SYS_CTRL_AP_SET_CPU_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_SET_CPU_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_SET_CPU_RST_SHIFT (0) + +//CPU_Rst_Clr +#define SYS_CTRL_AP_CLR_CPU_RST_CORE (1<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_CORE1 (1<<1) +#define SYS_CTRL_AP_CLR_CPU_RST_CORE2 (1<<2) +#define SYS_CTRL_AP_CLR_CPU_RST_CORE3 (1<<3) +#define SYS_CTRL_AP_CLR_CPU_RST_L2 (1<<4) +#define SYS_CTRL_AP_CLR_CPU_RST_SYS (1<<5) +#define SYS_CTRL_AP_CLR_CPU_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_SHIFT (0) + +//AXI_Rst_Set +#define SYS_CTRL_AP_SET_AXI_RST_VOC (1<<0) +#define SYS_CTRL_AP_SET_AXI_RST_VOC2 (1<<1) +#define SYS_CTRL_AP_SET_AXI_RST_DMA (1<<2) +#define SYS_CTRL_AP_SET_AXI_RST_SYS (1<<3) +#define SYS_CTRL_AP_SET_AXI_RST_CONNECT (1<<4) +#define SYS_CTRL_AP_SET_APB0_RST_GPU (1<<5) +#define SYS_CTRL_AP_SET_APB0_RST_VPU (1<<6) +#define SYS_CTRL_AP_SET_APB0_RST_IRQ (1<<7) +#define SYS_CTRL_AP_SET_AXI_RST(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_SET_AXI_RST_MASK (0xFF<<0) +#define SYS_CTRL_AP_SET_AXI_RST_SHIFT (0) + +//AXI_Rst_Clr +#define SYS_CTRL_AP_CLR_AXI_RST_VOC (1<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_VOC2 (1<<1) +#define SYS_CTRL_AP_CLR_AXI_RST_DMA (1<<2) +#define SYS_CTRL_AP_CLR_AXI_RST_SYS (1<<3) +#define SYS_CTRL_AP_CLR_AXI_RST_CONNECT (1<<4) +#define SYS_CTRL_AP_CLR_APB0_RST_GPU (1<<5) +#define SYS_CTRL_AP_CLR_APB0_RST_VPU (1<<6) +#define SYS_CTRL_AP_CLR_APB0_RST_IRQ (1<<7) +#define SYS_CTRL_AP_CLR_AXI_RST(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_MASK (0xFF<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_SHIFT (0) + +//AXIDIV2_Rst_Set +#define SYS_CTRL_AP_SET_AXIDIV2_RST_IMEM (1<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_SYS (1<<1) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_VPU (1<<2) +#define SYS_CTRL_AP_SET_AXIDIV2_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_MASK (7<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_SHIFT (0) + +//AXIDIV2_Rst_Clr +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_IMEM (1<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SYS (1<<1) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_VPU (1<<2) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_MASK (7<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SHIFT (0) + +//GCG_Rst_Set +#define SYS_CTRL_AP_SET_GCG_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_GCG_RST_GOUDA (1<<1) +#define SYS_CTRL_AP_SET_GCG_RST_CAMERA (1<<2) +#define SYS_CTRL_AP_SET_GCG_RST_CAMERA2 (1<<3) +#define SYS_CTRL_AP_SET_GCG_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_SET_GCG_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_SET_GCG_RST_SHIFT (0) + +//GCG_Rst_Clr +#define SYS_CTRL_AP_CLR_GCG_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_GOUDA (1<<1) +#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA (1<<2) +#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA2 (1<<3) +#define SYS_CTRL_AP_CLR_GCG_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_SHIFT (0) + +//AHB1_Rst_Set +#define SYS_CTRL_AP_SET_AHB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_USBC (1<<1) +#define SYS_CTRL_AP_SET_AHB1_RST_SPIFLASH (1<<2) +#define SYS_CTRL_AP_SET_AHB1_RST_EMAC (1<<3) +#define SYS_CTRL_AP_SET_AHB1_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_SHIFT (0) + +//AHB1_Rst_Clr +#define SYS_CTRL_AP_CLR_AHB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_USBC (1<<1) +#define SYS_CTRL_AP_CLR_AHB1_RST_SPIFLASH (1<<2) +#define SYS_CTRL_AP_CLR_AHB1_RST_EMAC (1<<3) +#define SYS_CTRL_AP_CLR_AHB1_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_SHIFT (0) + +//APB1_Rst_Set +#define SYS_CTRL_AP_SET_APB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_APB1_RST_TIMER (1<<1) +#define SYS_CTRL_AP_SET_APB1_RST_KEYPAD (1<<2) +#define SYS_CTRL_AP_SET_APB1_RST_GPIO (1<<3) +#define SYS_CTRL_AP_SET_APB1_RST_PWM (1<<4) +#define SYS_CTRL_AP_SET_APB1_RST_AIF (1<<5) +#define SYS_CTRL_AP_SET_APB1_RST_AIF2 (1<<6) +#define SYS_CTRL_AP_SET_APB1_RST_AUIFC (1<<7) +#define SYS_CTRL_AP_SET_APB1_RST_COM_REGS (1<<8) +#define SYS_CTRL_AP_SET_APB1_RST_DMC (1<<9) +#define SYS_CTRL_AP_SET_APB1_RST_DDRPHY_P (1<<10) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XCPU (1<<11) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BCPU (1<<12) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_AHBC (1<<13) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_DMA (1<<14) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_A2A (1<<15) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XIFC (1<<16) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BIFC (1<<17) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BAHBC (1<<18) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_MEM_BRIDGE (1<<19) +#define SYS_CTRL_AP_SET_APB1_RST(n) (((n)&0xFFFFF)<<0) +#define SYS_CTRL_AP_SET_APB1_RST_MASK (0xFFFFF<<0) +#define SYS_CTRL_AP_SET_APB1_RST_SHIFT (0) + +//APB1_Rst_Clr +#define SYS_CTRL_AP_CLR_APB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_TIMER (1<<1) +#define SYS_CTRL_AP_CLR_APB1_RST_KEYPAD (1<<2) +#define SYS_CTRL_AP_CLR_APB1_RST_GPIO (1<<3) +#define SYS_CTRL_AP_CLR_APB1_RST_PWM (1<<4) +#define SYS_CTRL_AP_CLR_APB1_RST_AIF (1<<5) +#define SYS_CTRL_AP_CLR_APB1_RST_AIF2 (1<<6) +#define SYS_CTRL_AP_CLR_APB1_RST_AUIFC (1<<7) +#define SYS_CTRL_AP_CLR_APB1_RST_COM_REGS (1<<8) +#define SYS_CTRL_AP_CLR_APB1_RST_DMC (1<<9) +#define SYS_CTRL_AP_CLR_APB1_RST_DDRPHY_P (1<<10) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XCPU (1<<11) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BCPU (1<<12) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_AHBC (1<<13) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_DMA (1<<14) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_A2A (1<<15) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XIFC (1<<16) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BIFC (1<<17) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BAHBC (1<<18) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_MEM_BRIDGE (1<<19) +#define SYS_CTRL_AP_CLR_APB1_RST(n) (((n)&0xFFFFF)<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_MASK (0xFFFFF<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_SHIFT (0) + +//APB2_Rst_Set +#define SYS_CTRL_AP_SET_APB2_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_APB2_RST_IFC (1<<1) +#define SYS_CTRL_AP_SET_APB2_RST_UART1 (1<<2) +#define SYS_CTRL_AP_SET_APB2_RST_UART2 (1<<3) +#define SYS_CTRL_AP_SET_APB2_RST_UART3 (1<<4) +#define SYS_CTRL_AP_SET_APB2_RST_SPI1 (1<<5) +#define SYS_CTRL_AP_SET_APB2_RST_SPI2 (1<<6) +#define SYS_CTRL_AP_SET_APB2_RST_SPI3 (1<<7) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC1 (1<<8) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC2 (1<<9) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC3 (1<<10) +#define SYS_CTRL_AP_SET_APB2_RST_NANDFLASH (1<<11) +#define SYS_CTRL_AP_SET_APB2_RST_I2C1 (1<<12) +#define SYS_CTRL_AP_SET_APB2_RST_I2C2 (1<<13) +#define SYS_CTRL_AP_SET_APB2_RST_I2C3 (1<<14) +#define SYS_CTRL_AP_SET_APB2_RST(n) (((n)&0x7FFF)<<0) +#define SYS_CTRL_AP_SET_APB2_RST_MASK (0x7FFF<<0) +#define SYS_CTRL_AP_SET_APB2_RST_SHIFT (0) + +//APB2_Rst_Clr +#define SYS_CTRL_AP_CLR_APB2_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_IFC (1<<1) +#define SYS_CTRL_AP_CLR_APB2_RST_UART1 (1<<2) +#define SYS_CTRL_AP_CLR_APB2_RST_UART2 (1<<3) +#define SYS_CTRL_AP_CLR_APB2_RST_UART3 (1<<4) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI1 (1<<5) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI2 (1<<6) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI3 (1<<7) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC1 (1<<8) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC2 (1<<9) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC3 (1<<10) +#define SYS_CTRL_AP_CLR_APB2_RST_NANDFLASH (1<<11) +#define SYS_CTRL_AP_CLR_APB2_RST_I2C1 (1<<12) +#define SYS_CTRL_AP_CLR_APB2_RST_I2C2 (1<<13) +#define SYS_CTRL_AP_CLR_APB2_RST_I2C3 (1<<14) +#define SYS_CTRL_AP_CLR_APB2_RST(n) (((n)&0x7FFF)<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_MASK (0x7FFF<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_SHIFT (0) + +//MEM_Rst_Set +#define SYS_CTRL_AP_SET_MEM_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_MEM_RST_DMC (1<<1) +#define SYS_CTRL_AP_SET_MEM_RST_DDRPHY_P (1<<2) +#define SYS_CTRL_AP_SET_MEM_RST(n) (((n)&0x7)<<0) +#define SYS_CTRL_AP_SET_MEM_RST_MASK (0x7<<0) +#define SYS_CTRL_AP_SET_MEM_RST_SHIFT (0) + +//MEM_Rst_Clr +#define SYS_CTRL_AP_CLR_MEM_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_DMC (1<<1) +#define SYS_CTRL_AP_CLR_MEM_RST_DDRPHY_P (1<<2) +#define SYS_CTRL_AP_CLR_MEM_RST(n) (((n)&0x7)<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_MASK (0x7<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_SHIFT (0) + +//Clk_CPU_Mode +#define SYS_CTRL_AP_MODE_CLK_CPU_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_CPU_MANUAL (1<<0) + +//Clk_CPU_Enable +#define SYS_CTRL_AP_ENABLE_CPU_CORE (1<<0) +#define SYS_CTRL_AP_ENABLE_CPU_DUMMY (1<<1) +#define SYS_CTRL_AP_ENABLE_CLK_CPU(n) (((n)&3)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_CPU_MASK (3<<0) +#define SYS_CTRL_AP_ENABLE_CLK_CPU_SHIFT (0) + +//Clk_CPU_Disable +#define SYS_CTRL_AP_DISABLE_CPU_CORE (1<<0) +#define SYS_CTRL_AP_DISABLE_CPU_DUMMY (1<<1) +#define SYS_CTRL_AP_DISABLE_CLK_CPU(n) (((n)&3)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_CPU_MASK (3<<0) +#define SYS_CTRL_AP_DISABLE_CLK_CPU_SHIFT (0) + +//Clk_AXI_Mode +#define SYS_CTRL_AP_MODE_AHB0_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_AHB0_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB0_CONF_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB0_CONF_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_AXI_VOC_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_AXI_VOC_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_AXI_VOC2_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_AXI_VOC2_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_AXI_DMA_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_AXI_DMA_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_CLK_AXI(n) (((n)&0x1F)<<0) +#define SYS_CTRL_AP_MODE_CLK_AXI_MASK (0x1F<<0) +#define SYS_CTRL_AP_MODE_CLK_AXI_SHIFT (0) + +//Clk_AXI_Enable +#define SYS_CTRL_AP_ENABLE_AHB0_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB0_CONF (1<<1) +#define SYS_CTRL_AP_ENABLE_AXI_VOC (1<<2) +#define SYS_CTRL_AP_ENABLE_AXI_VOC2 (1<<3) +#define SYS_CTRL_AP_ENABLE_AXI_DMA (1<<4) +#define SYS_CTRL_AP_ENABLE_AXI_ALWAYS (1<<5) +#define SYS_CTRL_AP_ENABLE_AXI_CONNECT (1<<6) +#define SYS_CTRL_AP_ENABLE_AXI_VPU (1<<7) +#define SYS_CTRL_AP_ENABLE_APB0_IRQ (1<<8) +#define SYS_CTRL_AP_ENABLE_CLK_AXI(n) (((n)&0x1FF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXI_MASK (0x1FF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXI_SHIFT (0) + +//Clk_AXI_Disable +#define SYS_CTRL_AP_DISABLE_AHB0_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB0_CONF (1<<1) +#define SYS_CTRL_AP_DISABLE_AXI_VOC (1<<2) +#define SYS_CTRL_AP_DISABLE_AXI_VOC2 (1<<3) +#define SYS_CTRL_AP_DISABLE_AXI_DMA (1<<4) +#define SYS_CTRL_AP_DISABLE_AXI_ALWAYS (1<<5) +#define SYS_CTRL_AP_DISABLE_AXI_CONNECT (1<<6) +#define SYS_CTRL_AP_DISABLE_AXI_VPU (1<<7) +#define SYS_CTRL_AP_DISABLE_APB0_IRQ (1<<8) +#define SYS_CTRL_AP_DISABLE_CLK_AXI(n) (((n)&0x1FF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXI_MASK (0x1FF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXI_SHIFT (0) + +//Clk_AXIDIV2_Mode +#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_MANUAL (1<<0) + +//Clk_AXIDIV2_Enable +#define SYS_CTRL_AP_ENABLE_AXIDIV2_IMEM (1<<0) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_ALWAYS (1<<1) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_CONNECT (1<<2) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_VPU (1<<3) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2(n) (((n)&15)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_MASK (15<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_SHIFT (0) + +//Clk_AXIDIV2_Disable +#define SYS_CTRL_AP_DISABLE_AXIDIV2_IMEM (1<<0) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_ALWAYS (1<<1) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_CONNECT (1<<2) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_VPU (1<<3) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2(n) (((n)&15)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_MASK (15<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_SHIFT (0) + +//Clk_GCG_Mode +#define SYS_CTRL_AP_MODE_GCG_APB_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_GCG_APB_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_GCG_GOUDA_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_GCG_CAMERA_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_GCG_CAMERA2_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_GCG_CAMERA2_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_CLK_GCG(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_MODE_CLK_GCG_MASK (0xF<<0) +#define SYS_CTRL_AP_MODE_CLK_GCG_SHIFT (0) + +//Clk_GCG_Enable +#define SYS_CTRL_AP_ENABLE_GCG_APB_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_GCG_GOUDA (1<<1) +#define SYS_CTRL_AP_ENABLE_GCG_CAMERA (1<<2) +#define SYS_CTRL_AP_ENABLE_GCG_CAMERA2 (1<<3) +#define SYS_CTRL_AP_ENABLE_GCG_ALWAYS (1<<4) +#define SYS_CTRL_AP_ENABLE_GCG_CONNECT (1<<5) +#define SYS_CTRL_AP_ENABLE_GCG_GOUDA_AW (1<<6) +#define SYS_CTRL_AP_ENABLE_GCG_GOUDA_DPI (1<<7) +#define SYS_CTRL_AP_ENABLE_CLK_GCG(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_GCG_MASK (0xFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_GCG_SHIFT (0) + +//Clk_GCG_Disable +#define SYS_CTRL_AP_DISABLE_GCG_APB_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_GCG_GOUDA (1<<1) +#define SYS_CTRL_AP_DISABLE_GCG_CAMERA (1<<2) +#define SYS_CTRL_AP_DISABLE_GCG_CAMERA2 (1<<3) +#define SYS_CTRL_AP_DISABLE_GCG_ALWAYS (1<<4) +#define SYS_CTRL_AP_DISABLE_GCG_CONNECT (1<<5) +#define SYS_CTRL_AP_DISABLE_GCG_GOUDA_AW (1<<6) +#define SYS_CTRL_AP_DISABLE_GCG_GOUDA_DPI (1<<7) +#define SYS_CTRL_AP_DISABLE_CLK_GCG(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_GCG_MASK (0xFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_GCG_SHIFT (0) + +//Clk_AHB1_Mode +#define SYS_CTRL_AP_MODE_CLK_AHB1_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_AHB1_MANUAL (1<<0) + +//Clk_AHB1_Enable +#define SYS_CTRL_AP_ENABLE_AHB1_USBC (1<<0) +#define SYS_CTRL_AP_ENABLE_AHB1_ALWAYS (1<<1) +#define SYS_CTRL_AP_ENABLE_AHB1_SPIFLASH (1<<2) +#define SYS_CTRL_AP_ENABLE_AHB1_EMAC (1<<3) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1_MASK (0xF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1_SHIFT (0) + +//Clk_AHB1_Disable +#define SYS_CTRL_AP_DISABLE_AHB1_USBC (1<<0) +#define SYS_CTRL_AP_DISABLE_AHB1_ALWAYS (1<<1) +#define SYS_CTRL_AP_DISABLE_AHB1_SPIFLASH (1<<2) +#define SYS_CTRL_AP_DISABLE_AHB1_EMAC (1<<3) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1_MASK (0xF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1_SHIFT (0) + +//Clk_APB1_Mode +#define SYS_CTRL_AP_MODE_APB1_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APB1_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB1_AIF_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB1_AIF_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APB1_AIF2_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APB1_AIF2_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APB1D_OSC_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APB1D_OSC_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_APB1D_OSC2_AUTOMATIC (0<<9) +#define SYS_CTRL_AP_MODE_APB1D_OSC2_MANUAL (1<<9) +#define SYS_CTRL_AP_MODE_APB1D_OSC3_AUTOMATIC (0<<10) +#define SYS_CTRL_AP_MODE_APB1D_OSC3_MANUAL (1<<10) +#define SYS_CTRL_AP_MODE_APB1D_PWM_AUTOMATIC (0<<11) +#define SYS_CTRL_AP_MODE_APB1D_PWM_MANUAL (1<<11) +#define SYS_CTRL_AP_MODE_CLK_APB1(n) (((n)&0xFFF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APB1_MASK (0xFFF<<0) +#define SYS_CTRL_AP_MODE_CLK_APB1_SHIFT (0) + +//Clk_APB1_Enable +#define SYS_CTRL_AP_ENABLE_APB1_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB1_AIF (1<<1) +#define SYS_CTRL_AP_ENABLE_APB1_AIF2 (1<<2) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC (1<<3) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH0 (1<<4) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH1 (1<<5) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH2 (1<<6) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH3 (1<<7) +#define SYS_CTRL_AP_ENABLE_APB1D_OSC (1<<8) +#define SYS_CTRL_AP_ENABLE_APB1D_OSC2 (1<<9) +#define SYS_CTRL_AP_ENABLE_APB1D_OSC3 (1<<10) +#define SYS_CTRL_AP_ENABLE_APB1D_PWM (1<<11) +#define SYS_CTRL_AP_ENABLE_APB1_ALWAYS (1<<12) +#define SYS_CTRL_AP_ENABLE_APB1_DAPLITE (1<<13) +#define SYS_CTRL_AP_ENABLE_APB1_TIMER (1<<14) +#define SYS_CTRL_AP_ENABLE_APB1_GPIO (1<<15) +#define SYS_CTRL_AP_ENABLE_CLK_APB1(n) (((n)&0xFFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB1_MASK (0xFFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB1_SHIFT (0) + +//Clk_APB1_Disable +#define SYS_CTRL_AP_DISABLE_APB1_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB1_AIF (1<<1) +#define SYS_CTRL_AP_DISABLE_APB1_AIF2 (1<<2) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC (1<<3) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH0 (1<<4) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH1 (1<<5) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH2 (1<<6) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH3 (1<<7) +#define SYS_CTRL_AP_DISABLE_APB1D_OSC (1<<8) +#define SYS_CTRL_AP_DISABLE_APB1D_OSC2 (1<<9) +#define SYS_CTRL_AP_DISABLE_APB1D_OSC3 (1<<10) +#define SYS_CTRL_AP_DISABLE_APB1D_PWM (1<<11) +#define SYS_CTRL_AP_DISABLE_APB1_ALWAYS (1<<12) +#define SYS_CTRL_AP_DISABLE_APB1_DAPLITE (1<<13) +#define SYS_CTRL_AP_DISABLE_APB1_TIMER (1<<14) +#define SYS_CTRL_AP_DISABLE_APB1_GPIO (1<<15) +#define SYS_CTRL_AP_DISABLE_CLK_APB1(n) (((n)&0xFFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB1_MASK (0xFFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB1_SHIFT (0) + +//Clk_APB2_Mode +#define SYS_CTRL_AP_MODE_APB2_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APB2_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB2_IFC_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB2_IFC_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_AUTOMATIC (0<<9) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_MANUAL (1<<9) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH8_AUTOMATIC (0<<10) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH8_MANUAL (1<<10) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH9_AUTOMATIC (0<<11) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH9_MANUAL (1<<11) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH10_AUTOMATIC (0<<12) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH10_MANUAL (1<<12) +#define SYS_CTRL_AP_MODE_APB2_UART1_AUTOMATIC (0<<13) +#define SYS_CTRL_AP_MODE_APB2_UART1_MANUAL (1<<13) +#define SYS_CTRL_AP_MODE_APB2_UART2_AUTOMATIC (0<<14) +#define SYS_CTRL_AP_MODE_APB2_UART2_MANUAL (1<<14) +#define SYS_CTRL_AP_MODE_APB2_UART3_AUTOMATIC (0<<15) +#define SYS_CTRL_AP_MODE_APB2_UART3_MANUAL (1<<15) +#define SYS_CTRL_AP_MODE_APB2_SPI1_AUTOMATIC (0<<16) +#define SYS_CTRL_AP_MODE_APB2_SPI1_MANUAL (1<<16) +#define SYS_CTRL_AP_MODE_APB2_SPI2_AUTOMATIC (0<<17) +#define SYS_CTRL_AP_MODE_APB2_SPI2_MANUAL (1<<17) +#define SYS_CTRL_AP_MODE_APB2_SPI3_AUTOMATIC (0<<18) +#define SYS_CTRL_AP_MODE_APB2_SPI3_MANUAL (1<<18) +#define SYS_CTRL_AP_MODE_APB2_SDMMC1_AUTOMATIC (0<<19) +#define SYS_CTRL_AP_MODE_APB2_SDMMC1_MANUAL (1<<19) +#define SYS_CTRL_AP_MODE_APB2_SDMMC2_AUTOMATIC (0<<20) +#define SYS_CTRL_AP_MODE_APB2_SDMMC2_MANUAL (1<<20) +#define SYS_CTRL_AP_MODE_APB2_SDMMC3_AUTOMATIC (0<<21) +#define SYS_CTRL_AP_MODE_APB2_SDMMC3_MANUAL (1<<21) +#define SYS_CTRL_AP_MODE_APB2_I2C1_AUTOMATIC (0<<22) +#define SYS_CTRL_AP_MODE_APB2_I2C1_MANUAL (1<<22) +#define SYS_CTRL_AP_MODE_APB2_I2C2_AUTOMATIC (0<<23) +#define SYS_CTRL_AP_MODE_APB2_I2C2_MANUAL (1<<23) +#define SYS_CTRL_AP_MODE_APB2_I2C3_AUTOMATIC (0<<24) +#define SYS_CTRL_AP_MODE_APB2_I2C3_MANUAL (1<<24) +#define SYS_CTRL_AP_MODE_CLK_APB2(n) (((n)&0x1FFFFFF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APB2_MASK (0x1FFFFFF<<0) +#define SYS_CTRL_AP_MODE_CLK_APB2_SHIFT (0) + +//Clk_APB2_Enable +#define SYS_CTRL_AP_ENABLE_APB2_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB2_IFC (1<<1) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH0 (1<<2) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH1 (1<<3) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH2 (1<<4) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH3 (1<<5) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH4 (1<<6) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH5 (1<<7) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH6 (1<<8) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH7 (1<<9) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH8 (1<<10) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH9 (1<<11) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH10 (1<<12) +#define SYS_CTRL_AP_ENABLE_APB2_UART1 (1<<13) +#define SYS_CTRL_AP_ENABLE_APB2_UART2 (1<<14) +#define SYS_CTRL_AP_ENABLE_APB2_UART3 (1<<15) +#define SYS_CTRL_AP_ENABLE_APB2_SPI1 (1<<16) +#define SYS_CTRL_AP_ENABLE_APB2_SPI2 (1<<17) +#define SYS_CTRL_AP_ENABLE_APB2_SPI3 (1<<18) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC1 (1<<19) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC2 (1<<20) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC3 (1<<21) +#define SYS_CTRL_AP_ENABLE_APB2_I2C1 (1<<22) +#define SYS_CTRL_AP_ENABLE_APB2_I2C2 (1<<23) +#define SYS_CTRL_AP_ENABLE_APB2_I2C3 (1<<24) +#define SYS_CTRL_AP_ENABLE_APB2_ALWAYS (1<<25) +#define SYS_CTRL_AP_ENABLE_APB2_NANDFLASH (1<<26) +#define SYS_CTRL_AP_ENABLE_CLK_APB2(n) (((n)&0x7FFFFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB2_MASK (0x7FFFFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB2_SHIFT (0) + +//Clk_APB2_Disable +#define SYS_CTRL_AP_DISABLE_APB2_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB2_IFC (1<<1) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH0 (1<<2) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH1 (1<<3) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH2 (1<<4) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH3 (1<<5) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH4 (1<<6) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH5 (1<<7) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH6 (1<<8) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH7 (1<<9) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH8 (1<<10) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH9 (1<<11) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH10 (1<<12) +#define SYS_CTRL_AP_DISABLE_APB2_UART1 (1<<13) +#define SYS_CTRL_AP_DISABLE_APB2_UART2 (1<<14) +#define SYS_CTRL_AP_DISABLE_APB2_UART3 (1<<15) +#define SYS_CTRL_AP_DISABLE_APB2_SPI1 (1<<16) +#define SYS_CTRL_AP_DISABLE_APB2_SPI2 (1<<17) +#define SYS_CTRL_AP_DISABLE_APB2_SPI3 (1<<18) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC1 (1<<19) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC2 (1<<20) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC3 (1<<21) +#define SYS_CTRL_AP_DISABLE_APB2_I2C1 (1<<22) +#define SYS_CTRL_AP_DISABLE_APB2_I2C2 (1<<23) +#define SYS_CTRL_AP_DISABLE_APB2_I2C3 (1<<24) +#define SYS_CTRL_AP_DISABLE_APB2_ALWAYS (1<<25) +#define SYS_CTRL_AP_DISABLE_APB2_NANDFLASH (1<<26) +#define SYS_CTRL_AP_DISABLE_CLK_APB2(n) (((n)&0x7FFFFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB2_MASK (0x7FFFFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB2_SHIFT (0) + +//Clk_MEM_Mode +#define SYS_CTRL_AP_MODE_CLK_MEM_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_MEM_MANUAL (1<<0) + +//Clk_MEM_Enable +#define SYS_CTRL_AP_ENABLE_MEM_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_MEM_DMC (1<<1) +#define SYS_CTRL_AP_ENABLE_MEM_DDRPHY_P (1<<2) +#define SYS_CTRL_AP_ENABLE_MEM_CONNECT (1<<3) +#define SYS_CTRL_AP_ENABLE_CLK_MEM(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_MEM_MASK (0xF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_MEM_SHIFT (0) + +//Clk_MEM_Disable +#define SYS_CTRL_AP_DISABLE_MEM_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_MEM_DMC (1<<1) +#define SYS_CTRL_AP_DISABLE_MEM_DDRPHY_P (1<<2) +#define SYS_CTRL_AP_DISABLE_MEM_CONNECT (1<<3) +#define SYS_CTRL_AP_DISABLE_CLK_MEM(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_MEM_MASK (0xF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_MEM_SHIFT (0) + +//Clk_APO_Mode +#define SYS_CTRL_AP_MODE_APOC_BCK_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APOC_BCK_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APOC_BCK2_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APOC_BCK2_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APOC_UART1_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APOC_UART1_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APOC_UART2_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APOC_UART2_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APOC_UART3_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APOC_UART3_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APOC_VOC_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APOC_VOC_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APOC_VOC2_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APOC_VOC2_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_CLK_APO(n) (((n)&01FF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APO_MASK (0x1FF<<0) +#define SYS_CTRL_AP_MODE_CLK_APO_SHIFT (0) + +//Clk_APO_Enable +#define SYS_CTRL_AP_ENABLE_APOC_BCK (1<<0) +#define SYS_CTRL_AP_ENABLE_APOC_BCK2 (1<<1) +#define SYS_CTRL_AP_ENABLE_APOC_UART1 (1<<2) +#define SYS_CTRL_AP_ENABLE_APOC_UART2 (1<<3) +#define SYS_CTRL_AP_ENABLE_APOC_UART3 (1<<4) +#define SYS_CTRL_AP_ENABLE_APOC_VOC_CORE (1<<5) +#define SYS_CTRL_AP_ENABLE_APOC_VOC2_CORE (1<<6) +#define SYS_CTRL_AP_ENABLE_APOC_VOC (1<<7) +#define SYS_CTRL_AP_ENABLE_APOC_VOC2 (1<<8) +#define SYS_CTRL_AP_ENABLE_APOC_VOC_ALWAYS (1<<9) +#define SYS_CTRL_AP_ENABLE_APOC_VOC2_ALWAYS (1<<10) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY_N (1<<11) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XP (1<<12) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XN (1<<13) +#define SYS_CTRL_AP_ENABLE_APOC_VPU (1<<14) +#define SYS_CTRL_AP_ENABLE_APOC_GPU (1<<15) +#define SYS_CTRL_AP_ENABLE_APOC_USBPHY (1<<16) +#define SYS_CTRL_AP_ENABLE_APOC_CSI (1<<17) +#define SYS_CTRL_AP_ENABLE_APOC_CSI2 (1<<18) +#define SYS_CTRL_AP_ENABLE_APOC_DSI (1<<19) +#define SYS_CTRL_AP_ENABLE_APOC_GPIO (1<<20) +#define SYS_CTRL_AP_ENABLE_APOC_SPIFLASH (1<<21) +#define SYS_CTRL_AP_ENABLE_APOC_PIX (1<<22) +#define SYS_CTRL_AP_ENABLE_APOC_PIX2 (1<<23) +#define SYS_CTRL_AP_ENABLE_APOC_PDGB (1<<24) +#define SYS_CTRL_AP_ENABLE_CLK_APO(n) (((n)&0x1FFFFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APO_MASK (0x1FFFFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APO_SHIFT (0) + +//Clk_APO_Disable +#define SYS_CTRL_AP_DISABLE_APOC_BCK (1<<0) +#define SYS_CTRL_AP_DISABLE_APOC_BCK2 (1<<1) +#define SYS_CTRL_AP_DISABLE_APOC_UART1 (1<<2) +#define SYS_CTRL_AP_DISABLE_APOC_UART2 (1<<3) +#define SYS_CTRL_AP_DISABLE_APOC_UART3 (1<<4) +#define SYS_CTRL_AP_DISABLE_APOC_VOC_CORE (1<<5) +#define SYS_CTRL_AP_DISABLE_APOC_VOC2_CORE (1<<6) +#define SYS_CTRL_AP_DISABLE_APOC_VOC (1<<7) +#define SYS_CTRL_AP_DISABLE_APOC_VOC2 (1<<8) +#define SYS_CTRL_AP_DISABLE_APOC_VOC_ALWAYS (1<<9) +#define SYS_CTRL_AP_DISABLE_APOC_VOC2_ALWAYS (1<<10) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY_N (1<<11) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XP (1<<12) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XN (1<<13) +#define SYS_CTRL_AP_DISABLE_APOC_VPU (1<<14) +#define SYS_CTRL_AP_DISABLE_APOC_GPU (1<<15) +#define SYS_CTRL_AP_DISABLE_APOC_USBPHY (1<<16) +#define SYS_CTRL_AP_DISABLE_APOC_CSI (1<<17) +#define SYS_CTRL_AP_DISABLE_APOC_CSI2 (1<<18) +#define SYS_CTRL_AP_DISABLE_APOC_DSI (1<<19) +#define SYS_CTRL_AP_DISABLE_APOC_GPIO (1<<20) +#define SYS_CTRL_AP_DISABLE_APOC_SPIFLASH (1<<21) +#define SYS_CTRL_AP_DISABLE_APOC_PIX (1<<22) +#define SYS_CTRL_AP_DISABLE_APOC_PIX2 (1<<23) +#define SYS_CTRL_AP_DISABLE_APOC_PDGB (1<<24) +#define SYS_CTRL_AP_DISABLE_CLK_APO(n) (((n)&0x1FFFFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APO_MASK (0x1FFFFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APO_SHIFT (0) + +//Cfg_Clk_AP_CPU +#define SYS_CTRL_AP_AP_CPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_CPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_BUS_DIV_SEL(n) (((n)&3)<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_MASK (3<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_SHIFT (16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV2 (0<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV3 (1<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV4 (2<<16) +#define SYS_CTRL_AP_DBG_CLKDIV_SEL(n) (((n)&15)<<20) +#define SYS_CTRL_AP_DBG_CLKDIV_DIV_SEL_MASK (15<<20) +#define SYS_CTRL_AP_DBG_CLKDIV_SEL_SHIFT (20) +#define SYS_CTRL_AP_AP_CPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_AXI +#define SYS_CTRL_AP_AP_AXI_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_AXI_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_AXI_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_AXI_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_GCG +#define SYS_CTRL_AP_AP_GCG_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_GCG_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_GCG_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_GCG_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_AHB1 +#define SYS_CTRL_AP_AP_AHB1_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_AHB1_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_AHB1_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_APB1 +#define SYS_CTRL_AP_AP_APB1_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_APB1_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_APB1_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_APB1_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_APB2 +#define SYS_CTRL_AP_AP_APB2_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_APB2_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_APB2_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_APB2_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_MEM +#define SYS_CTRL_AP_AP_MEM_SRC_DIV2 (1<<12) + +//Cfg_Clk_AP_GPU +#define SYS_CTRL_AP_AP_GPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_GPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_GPU_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_GPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_VPU +#define SYS_CTRL_AP_AP_VPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_VPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_VPU_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_VPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_VOC +#define SYS_CTRL_AP_AP_VOC_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_SFLSH +#define SYS_CTRL_AP_AP_SFLSH_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_SFLSH_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_SFLSH_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_Uart +#define SYS_CTRL_AP_UART_DIVIDER(n) (((n)&0x3FF)<<0) +#define SYS_CTRL_AP_UART_DIVIDER_MASK (0x3FF<<0) +#define SYS_CTRL_AP_UART_DIVIDER_SHIFT (0) +#define SYS_CTRL_AP_UART_SEL_PLL_SLOW (0<<12) +#define SYS_CTRL_AP_UART_SEL_PLL_PLL (1<<12) + +//L2cc_Ctrl +#define SYS_CTRL_AP_ARQOS_L2CC_1_M(n) (((n)&15)<<0) +#define SYS_CTRL_AP_ARQOS_L2CC_1_M_MASK (15<<0) +#define SYS_CTRL_AP_ARQOS_L2CC_1_M_SHIFT (0) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M(n) (((n)&15)<<4) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M_MASK (15<<4) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M_SHIFT (4) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<8) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_MASK (15<<8) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_SHIFT (8) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<12) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_MASK (15<<12) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_SHIFT (12) +#define SYS_CTRL_AP_ARAP_L2CC_1_M (1<<16) +#define SYS_CTRL_AP_AWAP_L2CC_1_M (1<<17) +#define SYS_CTRL_AP_ARAP_MODEM_MEM_AHBS_M (1<<18) +#define SYS_CTRL_AP_AWAP_MODEM_MEM_AHBS_M (1<<19) +#define SYS_CTRL_AP_ARAP_MERGE1M (1<<20) +#define SYS_CTRL_AP_AWAP_MERGE1M (1<<21) +#define SYS_CTRL_AP_ARAP_MERGE2M (1<<22) +#define SYS_CTRL_AP_AWAP_MERGE2M (1<<23) +#define SYS_CTRL_AP_RESERVE1(n) (((n)&0xFF)<<24) +#define SYS_CTRL_AP_RESERVE1_MASK (0xFF<<24) +#define SYS_CTRL_AP_RESERVE1_SHIFT (24) + +//Spi_Ctrl +#define SYS_CTRL_AP_LIMITED_EN_SPI1 (1<<0) +#define SYS_CTRL_AP_LPSEN_SPI1 (1<<1) +#define SYS_CTRL_AP_LIMITED_EN_SPI2 (1<<2) +#define SYS_CTRL_AP_LPSEN_SPI2 (1<<3) +#define SYS_CTRL_AP_LIMITED_EN_SPI3 (1<<4) +#define SYS_CTRL_AP_LPSEN_SPI3 (1<<5) +#define SYS_CTRL_AP_FBUSWID_NFSC (1<<6) +#define SYS_CTRL_AP_RESERVE3 (1<<7) +#define SYS_CTRL_AP_DMC_CFG(n) (((n)&0x3FF)<<8) +#define SYS_CTRL_AP_DMC_CFG_MASK (0x3FF<<8) +#define SYS_CTRL_AP_DMC_CFG_SHIFT (8) +#define SYS_CTRL_AP_RESERVE2(n) (((n)&0x3FFF)<<18) +#define SYS_CTRL_AP_RESERVE2_MASK (0x3FFF<<18) +#define SYS_CTRL_AP_RESERVE2_SHIFT (18) + +//Memory_Margin +#define SYS_CTRL_AP_EMAW_VOC(n) (((n)&3)<<0) +#define SYS_CTRL_AP_EMAW_VOC_MASK (3<<0) +#define SYS_CTRL_AP_EMAW_VOC_SHIFT (0) +#define SYS_CTRL_AP_EMA_VOC(n) (((n)&7)<<2) +#define SYS_CTRL_AP_EMA_VOC_MASK (7<<2) +#define SYS_CTRL_AP_EMA_VOC_SHIFT (2) +#define SYS_CTRL_AP_EMAW_VPU(n) (((n)&3)<<5) +#define SYS_CTRL_AP_EMAW_VPU_MASK (3<<5) +#define SYS_CTRL_AP_EMAW_VPU_SHIFT (5) +#define SYS_CTRL_AP_EMA_VPU(n) (((n)&7)<<7) +#define SYS_CTRL_AP_EMA_VPU_MASK (7<<7) +#define SYS_CTRL_AP_EMA_VPU_SHIFT (7) +#define SYS_CTRL_AP_EMAW_GPU(n) (((n)&3)<<10) +#define SYS_CTRL_AP_EMAW_GPU_MASK (3<<10) +#define SYS_CTRL_AP_EMAW_GPU_SHIFT (10) +#define SYS_CTRL_AP_EMA_GPU(n) (((n)&7)<<12) +#define SYS_CTRL_AP_EMA_GPU_MASK (7<<12) +#define SYS_CTRL_AP_EMA_GPU_SHIFT (12) +#define SYS_CTRL_AP_EMAW_GOUDA(n) (((n)&3)<<15) +#define SYS_CTRL_AP_EMAW_GOUDA_MASK (3<<15) +#define SYS_CTRL_AP_EMAW_GOUDA_SHIFT (15) +#define SYS_CTRL_AP_EMA_GOUDA(n) (((n)&7)<<17) +#define SYS_CTRL_AP_EMA_GOUDA_MASK (7<<17) +#define SYS_CTRL_AP_EMA_GOUDA_SHIFT (17) +#define SYS_CTRL_AP_EMAW_IMEM(n) (((n)&3)<<20) +#define SYS_CTRL_AP_EMAW_IMEM_MASK (3<<20) +#define SYS_CTRL_AP_EMAW_IMEM_SHIFT (20) +#define SYS_CTRL_AP_EMA_IMEM(n) (((n)&7)<<22) +#define SYS_CTRL_AP_EMA_IMEM_MASK (7<<22) +#define SYS_CTRL_AP_EMA_IMEM_SHIFT (22) +#define SYS_CTRL_AP_EMAW_USB(n) (((n)&3)<<25) +#define SYS_CTRL_AP_EMAW_USB_MASK (3<<25) +#define SYS_CTRL_AP_EMAW_USB_SHIFT (25) +#define SYS_CTRL_AP_EMA_USB(n) (((n)&7)<<27) +#define SYS_CTRL_AP_EMA_USB_MASK (7<<27) +#define SYS_CTRL_AP_EMA_USB_SHIFT (27) + +//Memory_Margin2 +#define SYS_CTRL_AP_EMAW_NFSC(n) (((n)&3)<<0) +#define SYS_CTRL_AP_EMAW_NFSC_MASK (3<<0) +#define SYS_CTRL_AP_EMAW_NFSC_SHIFT (0) +#define SYS_CTRL_AP_EMA_NFSC(n) (((n)&7)<<2) +#define SYS_CTRL_AP_EMA_NFSC_MASK (7<<2) +#define SYS_CTRL_AP_EMA_NFSC_SHIFT (2) +#define SYS_CTRL_AP_EMA_VPUROM(n) (((n)&7)<<5) +#define SYS_CTRL_AP_EMA_VPUROM_MASK (7<<5) +#define SYS_CTRL_AP_EMA_VPUROM_SHIFT (5) +#define SYS_CTRL_AP_EMA_IMEMROM(n) (((n)&7)<<8) +#define SYS_CTRL_AP_EMA_IMEMROM_MASK (7<<8) +#define SYS_CTRL_AP_EMA_IMEMROM_SHIFT (8) +#define SYS_CTRL_AP_KEN_VPUROM (1<<11) +#define SYS_CTRL_AP_PGEN_VPUROM (1<<12) +#define SYS_CTRL_AP_KEN_IMEMROM (1<<13) +#define SYS_CTRL_AP_PGEN_IMEMROM (1<<14) + +//Memory_Observe +#define SYS_CTRL_AP_MEM_OBSERVE(n) (((n)&0xFFFFFFFF)<<0) + +//Cfg_Clk_AP_VOC2 +#define SYS_CTRL_AP_AP_VOC2_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_VOC2_FREQ_MASK (31 << 0) +#define SYS_CTRL_AP_AP_VOC2_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_VOC2_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_VOC2_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_EMMC +#define SYS_CTRL_AP_EMMC_DATA_STB_DLY(n) (((n)&31)<<0) +#define SYS_CTRL_AP_EMMC_DATA_STB_DLY_MASK (31 << 0) +#define SYS_CTRL_AP_EMMC_DATA_STB_DLY_SHIFT 0 +#define SYS_CTRL_AP_EMMC_CLK_DLY(n) (((n)&31)<<8) +#define SYS_CTRL_AP_EMMC_CLK_DLY_MASK (31 << 8) +#define SYS_CTRL_AP_EMMC_CLK_DLY_SHIFT 8 +#define SYS_CTRL_AP_EMMC_CLK_POL (1<<13) + +//Test_Pulse +#define SYS_CTRL_AP_PULSE_COUNTER(n) (((n)&0xFFFFFFFF)<<0) + +//Cfg_Reserve +#define SYS_CTRL_AP_RESERVE(n) (((n)&0xFFFFFFFF)<<0) + +#endif diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810h.h b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810h.h new file mode 100644 index 0000000000..ab7ba4c951 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810h.h @@ -0,0 +1,1578 @@ +#ifndef _REG_SYSCTRL_H_ +#define _REG_SYSCTRL_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= + +// ============================================================================ +// AP_CPU_ID_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// CPU IDs + CPU0 = 0x00000000, + CPU1 = 0x00000001 +} AP_CPU_ID_T; + + +// ============================================================================ +// CPU_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP CPU side System clocks + CPU_CORE = 0x00000000, +/// the following don't have an auto enable + CPU_DUMMY = 0x00000001 +} CPU_CLKS_T; + +#define NB_CPU_CLK_AEN (1) +#define NB_CPU_CLK_EN (2) +#define NB_CPU_CLK (2) + +// ============================================================================ +// AXI_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXI side System clocks: AXI and AHB0 and APB0 + AHB0_CONF = 0x00000000, + APB0_CONF = 0x00000001, + AXI_VOC = 0x00000002, + AXI_DMA = 0x00000003, +/// the following don't have an auto enable + AXI_ALWAYS = 0x00000004, + AXI_CONNECT = 0x00000005, + APB0_IRQ = 0x00000006 +} AXI_CLKS_T; + +#define NB_AXI_CLK_AEN (4) +#define NB_AXI_CLK_EN (7) +#define NB_AXI_CLK (7) + +// ============================================================================ +// AXIDIV2_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXIdiv2 side System clocks + AXIDIV2_IMEM = 0x00000000, +/// the following don't have an auto enable + AXIDIV2_ALWAYS = 0x00000001, + AXIDIV2_CONNECT = 0x00000002, + AXIDIV2_VPU = 0x00000003 +} AXIDIV2_CLKS_T; + +#define NB_AXIDIV2_CLK_AEN (1) +#define NB_AXIDIV2_CLK_EN (4) +#define NB_AXIDIV2_CLK (4) + +// ============================================================================ +// GCG_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GCG side System clocks + GCG_APB_CONF = 0x00000000, + GCG_GOUDA = 0x00000001, + GCG_CAMERA = 0x00000002, +/// the following don't have an auto enable + GCG_ALWAYS = 0x00000003, + GCG_CONNECT = 0x00000004 +} GCG_CLKS_T; + +#define NB_GCG_CLK_AEN (3) +#define NB_GCG_CLK_EN (5) +#define NB_GCG_CLK (5) + +// ============================================================================ +// AHB1_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AHB1 side System clocks + AHB1_USBC = 0x00000000, +/// the following don't have an auto enable + AHB1_ALWAYS = 0x00000001, + AHB1_SPIFLASH = 0x00000002 +} AHB1_CLKS_T; + +#define NB_AHB1_CLK_AEN (1) +#define NB_AHB1_CLK_EN (3) +#define NB_AHB1_CLK (3) + +// ============================================================================ +// APB1_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB1 side System clocks + APB1_CONF = 0x00000000, + APB1_AIF = 0x00000001, + APB1_AUIFC = 0x00000002, + APB1_AUIFC_CH0 = 0x00000003, + APB1_AUIFC_CH1 = 0x00000004, + APB1_I2C1 = 0x00000005, + APB1_I2C2 = 0x00000006, + APB1_I2C3 = 0x00000007, +/// AP APB1 side divided clock (either divided by module or by clock_ctrl) + APB1D_OSC = 0x00000008, + APB1D_PWM = 0x00000009, +/// the following don't have an auto enable + APB1_ALWAYS = 0x0000000A, + APB1_DAPLITE = 0x0000000B, + APB1_TIMER = 0x0000000C, + APB1_GPIO = 0x0000000D +} APB1_CLKS_T; + +#define NB_APB1_CLK_AEN (10) +#define NB_APB1_CLK_EN (14) +#define NB_APB1_CLK (14) + +// ============================================================================ +// APB2_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB2 side System clocks + APB2_CONF = 0x00000000, + APB2_IFC = 0x00000001, + APB2_IFC_CH0 = 0x00000002, + APB2_IFC_CH1 = 0x00000003, + APB2_IFC_CH2 = 0x00000004, + APB2_IFC_CH3 = 0x00000005, + APB2_IFC_CH4 = 0x00000006, + APB2_IFC_CH5 = 0x00000007, + APB2_IFC_CH6 = 0x00000008, + APB2_IFC_CH7 = 0x00000009, + APB2_UART1 = 0x0000000A, + APB2_UART2 = 0x0000000B, + APB2_UART3 = 0x0000000C, + APB2_SPI1 = 0x0000000D, + APB2_SPI2 = 0x0000000E, + APB2_SPI3 = 0x0000000F, + APB2_SDMMC1 = 0x00000010, + APB2_SDMMC2 = 0x00000011, + APB2_SDMMC3 = 0x00000012, +/// the following don't have an auto enable + APB2_ALWAYS = 0x00000013, + APB2_NANDFLASH = 0x00000014 +} APB2_CLKS_T; + +#define NB_APB2_CLK_AEN (19) +#define NB_APB2_CLK_EN (21) +#define NB_APB2_CLK (21) + +// ============================================================================ +// MEM_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP MEM side System clocks + MEM_CONF = 0x00000000, +/// the following don't have an auto enable + MEM_DMC = 0x00000001, + MEM_GPU = 0x00000002, + MEM_VPU = 0x00000003, + MEM_DDRPHY_P = 0x00000004, + MEM_CONNECT = 0x00000005 +} MEM_CLKS_T; + +#define NB_MEM_CLK_AEN (1) +#define NB_MEM_CLK_EN (6) +#define NB_MEM_CLK (6) + +// ============================================================================ +// APO_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP side Other clocks +/// clocks with auto enble + APOC_VPU = 0x00000000, + APOC_BCK = 0x00000001, + APOC_UART1 = 0x00000002, + APOC_UART2 = 0x00000003, + APOC_UART3 = 0x00000004, + APOC_VOC_CORE = 0x00000005, + APOC_VOC = 0x00000006, +/// the following don't have an auto enable + APOC_VOC_ALWAYS = 0x00000007, + APOC_DDRPHY_N = 0x00000008, + APOC_DDRPHY2XP = 0x00000009, + APOC_DDRPHY2XN = 0x0000000A, + APOC_GPU = 0x0000000B, + APOC_USBPHY = 0x0000000C, + APOC_CSI = 0x0000000D, + APOC_DSI = 0x0000000E, + APOC_GPIO = 0x0000000F, + APOC_SPIFLASH = 0x00000010, + APOC_PIX = 0x00000011, + APOC_PDGB = 0x00000012 +} APO_CLKS_T; + +#define NB_CLK_VOC_AEN_SYNC (5) +#define NB_CLK_VOC_CORE (6) +#define NB_APO_CLK_AEN (7) +#define NB_CLK_VOC_END (8) +#define NB_APO_CLK_EN (19) +#define NB_APO_CLK (19) + +// ============================================================================ +// CPU_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP CPU side resets + CPU_RST_CORE = 0x00000000, + CPU_RST_SYS = 0x00000001 +} CPU_RESETS_T; + +#define NB_CPU_RST (2) + +// ============================================================================ +// AXI_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXI side resets: AXI and AHB0 and APB0 + AXI_RST_VOC = 0x00000000, + AXI_RST_DMA = 0x00000001, + AXI_RST_SYS = 0x00000002, + AXI_RST_CONNECT = 0x00000003, + AHB0_RST_GPU = 0x00000004, + APB0_RST_VPU = 0x00000005, + APB0_RST_IRQ = 0x00000006 +} AXI_RESETS_T; + +#define NB_AXI_RST (7) + +// ============================================================================ +// AXIDIV2_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXIDIV2 side resets + AXIDIV2_RST_IMEM = 0x00000000, + AXIDIV2_RST_SYS = 0x00000001, + AXIDIV2_RST_VPU = 0x00000002 +} AXIDIV2_RESETS_T; + +#define NB_AXIDIV2_RST (3) + +// ============================================================================ +// GCG_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GCG side resets + GCG_RST_SYS = 0x00000000, + GCG_RST_GOUDA = 0x00000001, + GCG_RST_CAMERA = 0x00000002 +} GCG_RESETS_T; + +#define NB_GCG_RST (3) + +// ============================================================================ +// AHB1_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AHB1 side resets + AHB1_RST_SYS = 0x00000000, + AHB1_RST_USBC = 0x00000001, + AHB1_RST_SPIFLASH = 0x00000002 +} AHB1_RESETS_T; + +#define NB_AHB1_RST (3) + +// ============================================================================ +// APB1_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB1 side resets + APB1_RST_SYS = 0x00000000, + APB1_RST_TIMER = 0x00000001, + APB1_RST_KEYPAD = 0x00000002, + APB1_RST_GPIO = 0x00000003, + APB1_RST_PWM = 0x00000004, + APB1_RST_AIF = 0x00000005, + APB1_RST_AUIFC = 0x00000006, + APB1_RST_I2C1 = 0x00000007, + APB1_RST_I2C2 = 0x00000008, + APB1_RST_I2C3 = 0x00000009, + APB1_RST_COM_REGS = 0x0000000A, + APB1_RST_DMC = 0x0000000B, + APB1_RST_DDRPHY_P = 0x0000000C, + APB1_RST_BB2G_XCPU = 0x0000000D, + APB1_RST_BB2G_BCPU = 0x0000000E, + APB1_RST_BB2G_AHBC = 0x0000000F, + APB1_RST_BB2G_DMA = 0x00000010, + APB1_RST_BB2G_A2A = 0x00000011, + APB1_RST_BB2G_XIFC = 0x00000012, + APB1_RST_BB2G_BIFC = 0x00000013, + APB1_RST_BB2G_BAHBC = 0x00000014, + APB1_RST_BB2G_MEM_BRIDGE = 0x00000015 +} APB1_RESETS_T; + +#define NB_APB1_RST (22) + +// ============================================================================ +// APB2_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB2 side resets + APB2_RST_SYS = 0x00000000, + APB2_RST_IFC = 0x00000001, + APB2_RST_UART1 = 0x00000002, + APB2_RST_UART2 = 0x00000003, + APB2_RST_UART3 = 0x00000004, + APB2_RST_SPI1 = 0x00000005, + APB2_RST_SPI2 = 0x00000006, + APB2_RST_SPI3 = 0x00000007, + APB2_RST_SDMMC1 = 0x00000008, + APB2_RST_SDMMC2 = 0x00000009, + APB2_RST_SDMMC3 = 0x0000000A, + APB2_RST_NANDFLASH = 0x0000000B +} APB2_RESETS_T; + +#define NB_APB2_RST (12) + +// ============================================================================ +// MEM_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP MEM side resets + MEM_RST_SYS = 0x00000000, + MEM_RST_GPU = 0x00000001, + MEM_RST_VPU = 0x00000002, + MEM_RST_DMC = 0x00000003, + MEM_RST_DDRPHY_P = 0x00000004 +} MEM_RESETS_T; + +#define NB_MEM_RST (5) + +// ============================================================================ +// AP_OTHERS_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP Reset Other : resync on corresponding clock other + AP_RSTO_VOC = 0x00000000, + AP_RSTO_DDRPHY_N = 0x00000001, + AP_RSTO_DDRPHY2XP = 0x00000002, + AP_RSTO_DDRPHY2XN = 0x00000003, + AP_RSTO_GPU = 0x00000004, + AP_RSTO_VPU = 0x00000005, + AP_RSTO_BCK = 0x00000006, + AP_RSTO_UART1 = 0x00000007, + AP_RSTO_UART2 = 0x00000008, + AP_RSTO_UART3 = 0x00000009, + AP_RSTO_GPIO = 0x0000000A, + AP_RSTO_TIMER = 0x0000000B, + AP_RSTO_USBC = 0x0000000C, + AP_RSTO_DSI = 0x0000000D, + AP_RSTO_SPIFLASH = 0x0000000E, + AP_RSTO_TCK = 0x0000000F, + AP_RSTO_PDBG_XTAL = 0x00000010 +} AP_OTHERS_RESETS_T; + +#define NB_AP_RSTO (17) +/// For REG_DBG protect lock/unlock value +#define AP_CTRL_PROTECT_LOCK (0XA50000) +#define AP_CTRL_PROTECT_UNLOCK (0XA50001) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// SYS_CTRL_AP_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + /// <strong>This register is used to Lock and Unlock the protected registers.</strong> + REG32 REG_DBG; //0x00000000 + /// Register protected by Write_Unlocked_H. + REG32 Cfg_Pll_Ctrl[4]; //0x00000004 + /// This register is protected. + REG32 Sel_Clock; //0x00000014 + REG32 Reset_Cause; //0x00000018 + /// This register is protected. + REG32 CPU_Rst_Set; //0x0000001C + REG32 CPU_Rst_Clr; //0x00000020 + /// This register is protected. + REG32 AXI_Rst_Set; //0x00000024 + REG32 AXI_Rst_Clr; //0x00000028 + /// This register is protected. + REG32 AXIDIV2_Rst_Set; //0x0000002C + REG32 AXIDIV2_Rst_Clr; //0x00000030 + /// This register is protected. + REG32 GCG_Rst_Set; //0x00000034 + REG32 GCG_Rst_Clr; //0x00000038 + /// This register is protected. + REG32 AHB1_Rst_Set; //0x0000003C + REG32 AHB1_Rst_Clr; //0x00000040 + /// This register is protected. + REG32 APB1_Rst_Set; //0x00000044 + REG32 APB1_Rst_Clr; //0x00000048 + /// This register is protected. + REG32 APB2_Rst_Set; //0x0000004C + REG32 APB2_Rst_Clr; //0x00000050 + /// This register is protected. + REG32 MEM_Rst_Set; //0x00000054 + REG32 MEM_Rst_Clr; //0x00000058 + REG32 Clk_CPU_Mode; //0x0000005C + REG32 Clk_CPU_Enable; //0x00000060 + /// This register is protected. + REG32 Clk_CPU_Disable; //0x00000064 + REG32 Clk_AXI_Mode; //0x00000068 + REG32 Clk_AXI_Enable; //0x0000006C + /// This register is protected. + REG32 Clk_AXI_Disable; //0x00000070 + REG32 Clk_AXIDIV2_Mode; //0x00000074 + REG32 Clk_AXIDIV2_Enable; //0x00000078 + /// This register is protected. + REG32 Clk_AXIDIV2_Disable; //0x0000007C + REG32 Clk_GCG_Mode; //0x00000080 + REG32 Clk_GCG_Enable; //0x00000084 + /// This register is protected. + REG32 Clk_GCG_Disable; //0x00000088 + REG32 Clk_AHB1_Mode; //0x0000008C + REG32 Clk_AHB1_Enable; //0x00000090 + /// This register is protected. + REG32 Clk_AHB1_Disable; //0x00000094 + REG32 Clk_APB1_Mode; //0x00000098 + REG32 Clk_APB1_Enable; //0x0000009C + /// This register is protected. + REG32 Clk_APB1_Disable; //0x000000A0 + REG32 Clk_APB2_Mode; //0x000000A4 + REG32 Clk_APB2_Enable; //0x000000A8 + /// This register is protected. + REG32 Clk_APB2_Disable; //0x000000AC + REG32 Clk_MEM_Mode; //0x000000B0 + REG32 Clk_MEM_Enable; //0x000000B4 + /// This register is protected. + REG32 Clk_MEM_Disable; //0x000000B8 + REG32 Clk_APO_Mode; //0x000000BC + REG32 Clk_APO_Enable; //0x000000C0 + /// This register is protected. + REG32 Clk_APO_Disable; //0x000000C4 + REG32 Cfg_Clk_AP_CPU; //0x000000C8 + REG32 Cfg_Clk_AP_AXI; //0x000000CC + REG32 Cfg_Clk_AP_GCG; //0x000000D0 + REG32 Cfg_Clk_AP_AHB1; //0x000000D4 + REG32 Cfg_Clk_AP_APB1; //0x000000D8 + REG32 Cfg_Clk_AP_APB2; //0x000000DC + REG32 Cfg_Clk_AP_MEM; //0x000000E0 + REG32 Cfg_Clk_AP_GPU; //0x000000E4 + REG32 Cfg_Clk_AP_VPU; //0x000000E8 + REG32 Cfg_Clk_AP_VOC; //0x000000EC + REG32 Cfg_Clk_AP_SFLSH; //0x000000F0 + REG32 Cfg_Clk_Uart[3]; //0x000000F4 + REG32 L2cc_Ctrl; //0x00000100 + REG32 Spi_Ctrl; //0x00000104 + REG32 Memory_Margin; //0x00000108 + REG32 Memory_Margin2; //0x0000010C + REG32 Memory_Observe; //0x00000110 + REG32 Cfg_Clk_AP_VOC2; //0x00000114 + REG32 Cfg_Clk_EMMC; //0x00000118 + REG32 Test_Pulse; //0x0000011C + REG32 Reserved_00000114[49]; //0x00000120 + /// This register is reserved. + REG32 Cfg_Cpu_Reserve0; //0x000001E4 + REG32 Cfg_Cpu_Reserve1; //0x000001E8 + REG32 Cfg_Cpu_Reserve2; //0x000001EC + REG32 Cfg_Cpu_Reserve3; //0x000001F0 + REG32 Cfg_Cpu_Reserve4; //0x000001F4 + REG32 Cfg_Cpu_Reserve5; //0x000001F8 + REG32 Cfg_Reserve; //0x000001FC +} HWP_SYS_CTRL_AP_T; + +#define hwp_sysCtrlAp ((HWP_SYS_CTRL_AP_T*)(RDA_SYSCTRL_BASE)) + + +//REG_DBG +#define SYS_CTRL_AP_SCRATCH(n) (((n)&0xFFFF)<<0) +#define SYS_CTRL_AP_WRITE_UNLOCK_STATUS (1<<30) +#define SYS_CTRL_AP_WRITE_UNLOCK (1<<31) + +//Cfg_Pll_Ctrl +#define SYS_CTRL_AP_AP_PLL_ENABLE (1<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_MASK (1<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_SHIFT (0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN (0<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE (1<<0) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET (1<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK (1<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_SHIFT (4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET (0<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET (1<<4) +#define SYS_CTRL_AP_AP_PLL_BYPASS (1<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_MASK (1<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_SHIFT (8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_PASS (0<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_BYPASS (1<<8) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_MASK (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_SHIFT (12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_DISABLE (0<<12) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(n) (((n)&31)<<16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_MASK (31<<16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_SHIFT (16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(n) (((n)&31)<<24) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_MASK (31<<24) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_SHIFT (24) +#define SYS_CTRL_AP_PLL_AP_CFG(n) (((n)&0x1F1F1111)<<0) +#define SYS_CTRL_AP_PLL_AP_CFG_MASK (0x1F1F1111<<0) +#define SYS_CTRL_AP_PLL_AP_CFG_SHIFT (0) + +//Sel_Clock +#define SYS_CTRL_AP_SLOW_SEL_RF_OSCILLATOR (1<<0) +#define SYS_CTRL_AP_SLOW_SEL_RF_RF (0<<0) +#define SYS_CTRL_AP_TIMER_SEL_FAST_SLOW (1<<1) +#define SYS_CTRL_AP_TIMER_SEL_FAST_FAST (0<<1) +#define SYS_CTRL_AP_TIMER2_SEL_FAST_SLOW (1<<2) +#define SYS_CTRL_AP_TIMER2_SEL_FAST_FAST (0<<2) +#define SYS_CTRL_AP_TIMER3_SEL_FAST_SLOW (1<<3) +#define SYS_CTRL_AP_TIMER3_SEL_FAST_FAST (0<<3) +#define SYS_CTRL_AP_CPU_SEL_FAST_SLOW (1<<4) +#define SYS_CTRL_AP_CPU_SEL_FAST_FAST (0<<4) +#define SYS_CTRL_AP_BUS_SEL_FAST_SLOW (1<<5) +#define SYS_CTRL_AP_BUS_SEL_FAST_FAST (0<<5) +#define SYS_CTRL_AP_RF_DETECTED_OK (1<<8) +#define SYS_CTRL_AP_RF_DETECTED_NO (0<<8) +#define SYS_CTRL_AP_RF_DETECT_BYPASS (1<<9) +#define SYS_CTRL_AP_RF_DETECT_RESET (1<<10) +#define SYS_CTRL_AP_RF_SELECTED_L (1<<11) +#define SYS_CTRL_AP_PLL_LOCKED_CPU (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_MASK (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_SHIFT (12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_NOT_LOCKED (0<<12) +#define SYS_CTRL_AP_PLL_LOCKED_BUS (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_MASK (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_SHIFT (13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_NOT_LOCKED (0<<13) +#define SYS_CTRL_AP_PLL_LOCKED_MEM (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_MASK (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_SHIFT (14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_NOT_LOCKED (0<<14) +#define SYS_CTRL_AP_PLL_LOCKED_USB (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_MASK (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_SHIFT (15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_NOT_LOCKED (0<<15) +#define SYS_CTRL_AP_PLL_BYPASS_LOCK_CPU (1<<20) +#define SYS_CTRL_AP_PLL_BYPASS_LOCK_BUS (1<<21) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L (1<<30) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_MASK (1<<30) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_SHIFT (30) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L (1<<31) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_MASK (1<<31) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_SHIFT (31) + +//Reset_Cause +#define SYS_CTRL_AP_WATCHDOG_RESET_HAPPENED (1<<0) +#define SYS_CTRL_AP_WATCHDOG_RESET_NO (0<<0) +#define SYS_CTRL_AP_GLOBALSOFT_RESET_HAPPENED (1<<4) +#define SYS_CTRL_AP_GLOBALSOFT_RESET_NO (0<<4) +#define SYS_CTRL_AP_HOSTDEBUG_RESET_HAPPENED (1<<5) +#define SYS_CTRL_AP_HOSTDEBUG_RESET_NO (0<<5) +#define SYS_CTRL_AP_ALARMCAUSE_HAPPENED (1<<6) +#define SYS_CTRL_AP_ALARMCAUSE_NO (0<<6) +#define SYS_CTRL_AP_BOOT_MODE(n) (((n)&0xFFFF)<<8) +#define SYS_CTRL_AP_BOOT_MODE_MASK (0xFFFF<<8) +#define SYS_CTRL_AP_BOOT_MODE_SHIFT (8) +#define SYS_CTRL_AP_SW_BOOT_MODE(n) (((n)&0x7F)<<24) +#define SYS_CTRL_AP_SW_BOOT_MODE_MASK (0x7F<<24) +#define SYS_CTRL_AP_SW_BOOT_MODE_SHIFT (24) +#define SYS_CTRL_AP_FONCTIONAL_TEST_MODE (1<<31) + +//CPU_Rst_Set +#define SYS_CTRL_AP_SET_CPU_RST_CORE (1<<0) +#define SYS_CTRL_AP_SET_CPU_RST_CORE1 (1<<1) +#define SYS_CTRL_AP_SET_CPU_RST_CORE2 (1<<2) +#define SYS_CTRL_AP_SET_CPU_RST_CORE3 (1<<3) +#define SYS_CTRL_AP_SET_CPU_RST_L2 (1<<4) +#define SYS_CTRL_AP_SET_CPU_RST_SYS (1<<5) +#define SYS_CTRL_AP_SOFT_RST (1<<31) +#define SYS_CTRL_AP_SET_CPU_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_SET_CPU_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_SET_CPU_RST_SHIFT (0) + +//CPU_Rst_Clr +#define SYS_CTRL_AP_CLR_CPU_RST_CORE (1<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_CORE1 (1<<1) +#define SYS_CTRL_AP_CLR_CPU_RST_CORE2 (1<<2) +#define SYS_CTRL_AP_CLR_CPU_RST_CORE3 (1<<3) +#define SYS_CTRL_AP_CLR_CPU_RST_L2 (1<<4) +#define SYS_CTRL_AP_CLR_CPU_RST_SYS (1<<5) +#define SYS_CTRL_AP_CLR_CPU_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_SHIFT (0) + +//AXI_Rst_Set +#define SYS_CTRL_AP_SET_AXI_RST_VOC (1<<0) +#define SYS_CTRL_AP_SET_AXI_RST_VOC2 (1<<1) +#define SYS_CTRL_AP_SET_AXI_RST_DMA (1<<2) +#define SYS_CTRL_AP_SET_AXI_RST_SYS (1<<3) +#define SYS_CTRL_AP_SET_AXI_RST_CONNECT (1<<4) +#define SYS_CTRL_AP_SET_APB0_RST_GPU (1<<5) +#define SYS_CTRL_AP_SET_APB0_RST_VPU (1<<6) +#define SYS_CTRL_AP_SET_APB0_RST_IRQ (1<<7) +#define SYS_CTRL_AP_SET_AXI_RST(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_SET_AXI_RST_MASK (0xFF<<0) +#define SYS_CTRL_AP_SET_AXI_RST_SHIFT (0) + +//AXI_Rst_Clr +#define SYS_CTRL_AP_CLR_AXI_RST_VOC (1<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_VOC2 (1<<1) +#define SYS_CTRL_AP_CLR_AXI_RST_DMA (1<<2) +#define SYS_CTRL_AP_CLR_AXI_RST_SYS (1<<3) +#define SYS_CTRL_AP_CLR_AXI_RST_CONNECT (1<<4) +#define SYS_CTRL_AP_CLR_APB0_RST_GPU (1<<5) +#define SYS_CTRL_AP_CLR_APB0_RST_VPU (1<<6) +#define SYS_CTRL_AP_CLR_APB0_RST_IRQ (1<<7) +#define SYS_CTRL_AP_CLR_AXI_RST(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_MASK (0xFF<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_SHIFT (0) + +//AXIDIV2_Rst_Set +#define SYS_CTRL_AP_SET_AXIDIV2_RST_IMEM (1<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_SYS (1<<1) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_VPU (1<<2) +#define SYS_CTRL_AP_SET_AXIDIV2_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_MASK (7<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_SHIFT (0) + +//AXIDIV2_Rst_Clr +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_IMEM (1<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SYS (1<<1) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_VPU (1<<2) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_MASK (7<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SHIFT (0) + +//GCG_Rst_Set +#define SYS_CTRL_AP_SET_GCG_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_GCG_RST_GOUDA (1<<1) +#define SYS_CTRL_AP_SET_GCG_RST_CAMERA (1<<2) +#define SYS_CTRL_AP_SET_GCG_RST_CAMERA2 (1<<3) +#define SYS_CTRL_AP_SET_GCG_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_SET_GCG_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_SET_GCG_RST_SHIFT (0) + +//GCG_Rst_Clr +#define SYS_CTRL_AP_CLR_GCG_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_GOUDA (1<<1) +#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA (1<<2) +#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA2 (1<<3) +#define SYS_CTRL_AP_CLR_GCG_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_SHIFT (0) + +//AHB1_Rst_Set +#define SYS_CTRL_AP_SET_AHB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_USBC (1<<1) +#define SYS_CTRL_AP_SET_AHB1_RST_SPIFLASH (1<<2) +#define SYS_CTRL_AP_SET_AHB1_RST_EMAC (1<<3) +#define SYS_CTRL_AP_SET_AHB1_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_SHIFT (0) + +//AHB1_Rst_Clr +#define SYS_CTRL_AP_CLR_AHB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_USBC (1<<1) +#define SYS_CTRL_AP_CLR_AHB1_RST_SPIFLASH (1<<2) +#define SYS_CTRL_AP_CLR_AHB1_RST_EMAC (1<<3) +#define SYS_CTRL_AP_CLR_AHB1_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_SHIFT (0) + +//APB1_Rst_Set +#define SYS_CTRL_AP_SET_APB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_APB1_RST_TIMER (1<<1) +#define SYS_CTRL_AP_SET_APB1_RST_KEYPAD (1<<2) +#define SYS_CTRL_AP_SET_APB1_RST_GPIO (1<<3) +#define SYS_CTRL_AP_SET_APB1_RST_PWM (1<<4) +#define SYS_CTRL_AP_SET_APB1_RST_AIF (1<<5) +#define SYS_CTRL_AP_SET_APB1_RST_AIF2 (1<<6) +#define SYS_CTRL_AP_SET_APB1_RST_AUIFC (1<<7) +#define SYS_CTRL_AP_SET_APB1_RST_COM_REGS (1<<8) +#define SYS_CTRL_AP_SET_APB1_RST_DMC (1<<9) +#define SYS_CTRL_AP_SET_APB1_RST_DDRPHY_P (1<<10) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XCPU (1<<11) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BCPU (1<<12) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_AHBC (1<<13) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_DMA (1<<14) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_A2A (1<<15) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XIFC (1<<16) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BIFC (1<<17) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BAHBC (1<<18) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_MEM_BRIDGE (1<<19) +#define SYS_CTRL_AP_SET_APB1_RST(n) (((n)&0xFFFFF)<<0) +#define SYS_CTRL_AP_SET_APB1_RST_MASK (0xFFFFF<<0) +#define SYS_CTRL_AP_SET_APB1_RST_SHIFT (0) + +//APB1_Rst_Clr +#define SYS_CTRL_AP_CLR_APB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_TIMER (1<<1) +#define SYS_CTRL_AP_CLR_APB1_RST_KEYPAD (1<<2) +#define SYS_CTRL_AP_CLR_APB1_RST_GPIO (1<<3) +#define SYS_CTRL_AP_CLR_APB1_RST_PWM (1<<4) +#define SYS_CTRL_AP_CLR_APB1_RST_AIF (1<<5) +#define SYS_CTRL_AP_CLR_APB1_RST_AIF2 (1<<6) +#define SYS_CTRL_AP_CLR_APB1_RST_AUIFC (1<<7) +#define SYS_CTRL_AP_CLR_APB1_RST_COM_REGS (1<<8) +#define SYS_CTRL_AP_CLR_APB1_RST_DMC (1<<9) +#define SYS_CTRL_AP_CLR_APB1_RST_DDRPHY_P (1<<10) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XCPU (1<<11) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BCPU (1<<12) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_AHBC (1<<13) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_DMA (1<<14) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_A2A (1<<15) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XIFC (1<<16) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BIFC (1<<17) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BAHBC (1<<18) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_MEM_BRIDGE (1<<19) +#define SYS_CTRL_AP_CLR_APB1_RST(n) (((n)&0xFFFFF)<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_MASK (0xFFFFF<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_SHIFT (0) + +//APB2_Rst_Set +#define SYS_CTRL_AP_SET_APB2_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_APB2_RST_IFC (1<<1) +#define SYS_CTRL_AP_SET_APB2_RST_UART1 (1<<2) +#define SYS_CTRL_AP_SET_APB2_RST_UART2 (1<<3) +#define SYS_CTRL_AP_SET_APB2_RST_UART3 (1<<4) +#define SYS_CTRL_AP_SET_APB2_RST_SPI1 (1<<5) +#define SYS_CTRL_AP_SET_APB2_RST_SPI2 (1<<6) +#define SYS_CTRL_AP_SET_APB2_RST_SPI3 (1<<7) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC1 (1<<8) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC2 (1<<9) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC3 (1<<10) +#define SYS_CTRL_AP_SET_APB2_RST_NANDFLASH (1<<11) +#define SYS_CTRL_AP_SET_APB2_RST_I2C1 (1<<12) +#define SYS_CTRL_AP_SET_APB2_RST_I2C2 (1<<13) +#define SYS_CTRL_AP_SET_APB2_RST_I2C3 (1<<14) +#define SYS_CTRL_AP_SET_APB2_RST(n) (((n)&0x7FFF)<<0) +#define SYS_CTRL_AP_SET_APB2_RST_MASK (0x7FFF<<0) +#define SYS_CTRL_AP_SET_APB2_RST_SHIFT (0) + +//APB2_Rst_Clr +#define SYS_CTRL_AP_CLR_APB2_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_IFC (1<<1) +#define SYS_CTRL_AP_CLR_APB2_RST_UART1 (1<<2) +#define SYS_CTRL_AP_CLR_APB2_RST_UART2 (1<<3) +#define SYS_CTRL_AP_CLR_APB2_RST_UART3 (1<<4) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI1 (1<<5) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI2 (1<<6) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI3 (1<<7) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC1 (1<<8) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC2 (1<<9) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC3 (1<<10) +#define SYS_CTRL_AP_CLR_APB2_RST_NANDFLASH (1<<11) +#define SYS_CTRL_AP_CLR_APB2_RST_I2C1 (1<<12) +#define SYS_CTRL_AP_CLR_APB2_RST_I2C2 (1<<13) +#define SYS_CTRL_AP_CLR_APB2_RST_I2C3 (1<<14) +#define SYS_CTRL_AP_CLR_APB2_RST(n) (((n)&0x7FFF)<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_MASK (0x7FFF<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_SHIFT (0) + +//MEM_Rst_Set +#define SYS_CTRL_AP_SET_MEM_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_MEM_RST_DMC (1<<1) +#define SYS_CTRL_AP_SET_MEM_RST_DDRPHY_P (1<<2) +#define SYS_CTRL_AP_SET_MEM_RST(n) (((n)&0x7)<<0) +#define SYS_CTRL_AP_SET_MEM_RST_MASK (0x7<<0) +#define SYS_CTRL_AP_SET_MEM_RST_SHIFT (0) + +//MEM_Rst_Clr +#define SYS_CTRL_AP_CLR_MEM_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_DMC (1<<1) +#define SYS_CTRL_AP_CLR_MEM_RST_DDRPHY_P (1<<2) +#define SYS_CTRL_AP_CLR_MEM_RST(n) (((n)&0x7)<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_MASK (0x7<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_SHIFT (0) + +//Clk_CPU_Mode +#define SYS_CTRL_AP_MODE_CLK_CPU_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_CPU_MANUAL (1<<0) + +//Clk_CPU_Enable +#define SYS_CTRL_AP_ENABLE_CPU_CORE (1<<0) +#define SYS_CTRL_AP_ENABLE_CPU_DUMMY (1<<1) +#define SYS_CTRL_AP_ENABLE_CLK_CPU(n) (((n)&3)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_CPU_MASK (3<<0) +#define SYS_CTRL_AP_ENABLE_CLK_CPU_SHIFT (0) + +//Clk_CPU_Disable +#define SYS_CTRL_AP_DISABLE_CPU_CORE (1<<0) +#define SYS_CTRL_AP_DISABLE_CPU_DUMMY (1<<1) +#define SYS_CTRL_AP_DISABLE_CLK_CPU(n) (((n)&3)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_CPU_MASK (3<<0) +#define SYS_CTRL_AP_DISABLE_CLK_CPU_SHIFT (0) + +//Clk_AXI_Mode +#define SYS_CTRL_AP_MODE_AHB0_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_AHB0_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB0_CONF_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB0_CONF_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_AXI_VOC_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_AXI_VOC_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_AXI_VOC2_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_AXI_VOC2_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_AXI_DMA_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_AXI_DMA_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_CLK_AXI(n) (((n)&0x1F)<<0) +#define SYS_CTRL_AP_MODE_CLK_AXI_MASK (0x1F<<0) +#define SYS_CTRL_AP_MODE_CLK_AXI_SHIFT (0) + +//Clk_AXI_Enable +#define SYS_CTRL_AP_ENABLE_AHB0_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB0_CONF (1<<1) +#define SYS_CTRL_AP_ENABLE_AXI_VOC (1<<2) +#define SYS_CTRL_AP_ENABLE_AXI_VOC2 (1<<3) +#define SYS_CTRL_AP_ENABLE_AXI_DMA (1<<4) +#define SYS_CTRL_AP_ENABLE_AXI_ALWAYS (1<<5) +#define SYS_CTRL_AP_ENABLE_AXI_CONNECT (1<<6) +#define SYS_CTRL_AP_ENABLE_AXI_VPU (1<<7) +#define SYS_CTRL_AP_ENABLE_APB0_IRQ (1<<8) +#define SYS_CTRL_AP_ENABLE_CLK_AXI(n) (((n)&0x1FF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXI_MASK (0x1FF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXI_SHIFT (0) + +//Clk_AXI_Disable +#define SYS_CTRL_AP_DISABLE_AHB0_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB0_CONF (1<<1) +#define SYS_CTRL_AP_DISABLE_AXI_VOC (1<<2) +#define SYS_CTRL_AP_DISABLE_AXI_VOC2 (1<<3) +#define SYS_CTRL_AP_DISABLE_AXI_DMA (1<<4) +#define SYS_CTRL_AP_DISABLE_AXI_ALWAYS (1<<5) +#define SYS_CTRL_AP_DISABLE_AXI_CONNECT (1<<6) +#define SYS_CTRL_AP_DISABLE_AXI_VPU (1<<7) +#define SYS_CTRL_AP_DISABLE_APB0_IRQ (1<<8) +#define SYS_CTRL_AP_DISABLE_CLK_AXI(n) (((n)&0x1FF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXI_MASK (0x1FF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXI_SHIFT (0) + +//Clk_AXIDIV2_Mode +#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_MANUAL (1<<0) + +//Clk_AXIDIV2_Enable +#define SYS_CTRL_AP_ENABLE_AXIDIV2_IMEM (1<<0) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_ALWAYS (1<<1) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_CONNECT (1<<2) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_VPU (1<<3) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2(n) (((n)&15)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_MASK (15<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_SHIFT (0) + +//Clk_AXIDIV2_Disable +#define SYS_CTRL_AP_DISABLE_AXIDIV2_IMEM (1<<0) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_ALWAYS (1<<1) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_CONNECT (1<<2) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_VPU (1<<3) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2(n) (((n)&15)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_MASK (15<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_SHIFT (0) + +//Clk_GCG_Mode +#define SYS_CTRL_AP_MODE_GCG_APB_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_GCG_APB_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_GCG_GOUDA_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_GCG_CAMERA_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_GCG_CAMERA2_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_GCG_CAMERA2_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_CLK_GCG(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_MODE_CLK_GCG_MASK (0xF<<0) +#define SYS_CTRL_AP_MODE_CLK_GCG_SHIFT (0) + +//Clk_GCG_Enable +#define SYS_CTRL_AP_ENABLE_GCG_APB_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_GCG_GOUDA (1<<1) +#define SYS_CTRL_AP_ENABLE_GCG_CAMERA (1<<2) +#define SYS_CTRL_AP_ENABLE_GCG_CAMERA2 (1<<3) +#define SYS_CTRL_AP_ENABLE_GCG_ALWAYS (1<<4) +#define SYS_CTRL_AP_ENABLE_GCG_CONNECT (1<<5) +#define SYS_CTRL_AP_ENABLE_GCG_GOUDA_AW (1<<6) +#define SYS_CTRL_AP_ENABLE_GCG_GOUDA_DPI (1<<7) +#define SYS_CTRL_AP_ENABLE_CLK_GCG(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_GCG_MASK (0xFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_GCG_SHIFT (0) + +//Clk_GCG_Disable +#define SYS_CTRL_AP_DISABLE_GCG_APB_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_GCG_GOUDA (1<<1) +#define SYS_CTRL_AP_DISABLE_GCG_CAMERA (1<<2) +#define SYS_CTRL_AP_DISABLE_GCG_CAMERA2 (1<<3) +#define SYS_CTRL_AP_DISABLE_GCG_ALWAYS (1<<4) +#define SYS_CTRL_AP_DISABLE_GCG_CONNECT (1<<5) +#define SYS_CTRL_AP_DISABLE_GCG_GOUDA_AW (1<<6) +#define SYS_CTRL_AP_DISABLE_GCG_GOUDA_DPI (1<<7) +#define SYS_CTRL_AP_DISABLE_CLK_GCG(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_GCG_MASK (0xFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_GCG_SHIFT (0) + +//Clk_AHB1_Mode +#define SYS_CTRL_AP_MODE_CLK_AHB1_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_AHB1_MANUAL (1<<0) + +//Clk_AHB1_Enable +#define SYS_CTRL_AP_ENABLE_AHB1_USBC (1<<0) +#define SYS_CTRL_AP_ENABLE_AHB1_ALWAYS (1<<1) +#define SYS_CTRL_AP_ENABLE_AHB1_SPIFLASH (1<<2) +#define SYS_CTRL_AP_ENABLE_AHB1_EMAC (1<<3) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1_MASK (0xF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1_SHIFT (0) + +//Clk_AHB1_Disable +#define SYS_CTRL_AP_DISABLE_AHB1_USBC (1<<0) +#define SYS_CTRL_AP_DISABLE_AHB1_ALWAYS (1<<1) +#define SYS_CTRL_AP_DISABLE_AHB1_SPIFLASH (1<<2) +#define SYS_CTRL_AP_DISABLE_AHB1_EMAC (1<<3) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1_MASK (0xF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1_SHIFT (0) + +//Clk_APB1_Mode +#define SYS_CTRL_AP_MODE_APB1_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APB1_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB1_AIF_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB1_AIF_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APB1_AIF2_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APB1_AIF2_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APB1D_OSC_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APB1D_OSC_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_APB1D_OSC2_AUTOMATIC (0<<9) +#define SYS_CTRL_AP_MODE_APB1D_OSC2_MANUAL (1<<9) +#define SYS_CTRL_AP_MODE_APB1D_OSC3_AUTOMATIC (0<<10) +#define SYS_CTRL_AP_MODE_APB1D_OSC3_MANUAL (1<<10) +#define SYS_CTRL_AP_MODE_APB1D_PWM_AUTOMATIC (0<<11) +#define SYS_CTRL_AP_MODE_APB1D_PWM_MANUAL (1<<11) +#define SYS_CTRL_AP_MODE_CLK_APB1(n) (((n)&0xFFF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APB1_MASK (0xFFF<<0) +#define SYS_CTRL_AP_MODE_CLK_APB1_SHIFT (0) + +//Clk_APB1_Enable +#define SYS_CTRL_AP_ENABLE_APB1_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB1_AIF (1<<1) +#define SYS_CTRL_AP_ENABLE_APB1_AIF2 (1<<2) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC (1<<3) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH0 (1<<4) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH1 (1<<5) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH2 (1<<6) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH3 (1<<7) +#define SYS_CTRL_AP_ENABLE_APB1D_OSC (1<<8) +#define SYS_CTRL_AP_ENABLE_APB1D_OSC2 (1<<9) +#define SYS_CTRL_AP_ENABLE_APB1D_OSC3 (1<<10) +#define SYS_CTRL_AP_ENABLE_APB1D_PWM (1<<11) +#define SYS_CTRL_AP_ENABLE_APB1_ALWAYS (1<<12) +#define SYS_CTRL_AP_ENABLE_APB1_DAPLITE (1<<13) +#define SYS_CTRL_AP_ENABLE_APB1_TIMER (1<<14) +#define SYS_CTRL_AP_ENABLE_APB1_GPIO (1<<15) +#define SYS_CTRL_AP_ENABLE_CLK_APB1(n) (((n)&0xFFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB1_MASK (0xFFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB1_SHIFT (0) + +//Clk_APB1_Disable +#define SYS_CTRL_AP_DISABLE_APB1_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB1_AIF (1<<1) +#define SYS_CTRL_AP_DISABLE_APB1_AIF2 (1<<2) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC (1<<3) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH0 (1<<4) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH1 (1<<5) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH2 (1<<6) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH3 (1<<7) +#define SYS_CTRL_AP_DISABLE_APB1D_OSC (1<<8) +#define SYS_CTRL_AP_DISABLE_APB1D_OSC2 (1<<9) +#define SYS_CTRL_AP_DISABLE_APB1D_OSC3 (1<<10) +#define SYS_CTRL_AP_DISABLE_APB1D_PWM (1<<11) +#define SYS_CTRL_AP_DISABLE_APB1_ALWAYS (1<<12) +#define SYS_CTRL_AP_DISABLE_APB1_DAPLITE (1<<13) +#define SYS_CTRL_AP_DISABLE_APB1_TIMER (1<<14) +#define SYS_CTRL_AP_DISABLE_APB1_GPIO (1<<15) +#define SYS_CTRL_AP_DISABLE_CLK_APB1(n) (((n)&0xFFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB1_MASK (0xFFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB1_SHIFT (0) + +//Clk_APB2_Mode +#define SYS_CTRL_AP_MODE_APB2_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APB2_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB2_IFC_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB2_IFC_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_AUTOMATIC (0<<9) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_MANUAL (1<<9) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH8_AUTOMATIC (0<<10) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH8_MANUAL (1<<10) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH9_AUTOMATIC (0<<11) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH9_MANUAL (1<<11) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH10_AUTOMATIC (0<<12) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH10_MANUAL (1<<12) +#define SYS_CTRL_AP_MODE_APB2_UART1_AUTOMATIC (0<<13) +#define SYS_CTRL_AP_MODE_APB2_UART1_MANUAL (1<<13) +#define SYS_CTRL_AP_MODE_APB2_UART2_AUTOMATIC (0<<14) +#define SYS_CTRL_AP_MODE_APB2_UART2_MANUAL (1<<14) +#define SYS_CTRL_AP_MODE_APB2_UART3_AUTOMATIC (0<<15) +#define SYS_CTRL_AP_MODE_APB2_UART3_MANUAL (1<<15) +#define SYS_CTRL_AP_MODE_APB2_SPI1_AUTOMATIC (0<<16) +#define SYS_CTRL_AP_MODE_APB2_SPI1_MANUAL (1<<16) +#define SYS_CTRL_AP_MODE_APB2_SPI2_AUTOMATIC (0<<17) +#define SYS_CTRL_AP_MODE_APB2_SPI2_MANUAL (1<<17) +#define SYS_CTRL_AP_MODE_APB2_SPI3_AUTOMATIC (0<<18) +#define SYS_CTRL_AP_MODE_APB2_SPI3_MANUAL (1<<18) +#define SYS_CTRL_AP_MODE_APB2_SDMMC1_AUTOMATIC (0<<19) +#define SYS_CTRL_AP_MODE_APB2_SDMMC1_MANUAL (1<<19) +#define SYS_CTRL_AP_MODE_APB2_SDMMC2_AUTOMATIC (0<<20) +#define SYS_CTRL_AP_MODE_APB2_SDMMC2_MANUAL (1<<20) +#define SYS_CTRL_AP_MODE_APB2_SDMMC3_AUTOMATIC (0<<21) +#define SYS_CTRL_AP_MODE_APB2_SDMMC3_MANUAL (1<<21) +#define SYS_CTRL_AP_MODE_APB2_I2C1_AUTOMATIC (0<<22) +#define SYS_CTRL_AP_MODE_APB2_I2C1_MANUAL (1<<22) +#define SYS_CTRL_AP_MODE_APB2_I2C2_AUTOMATIC (0<<23) +#define SYS_CTRL_AP_MODE_APB2_I2C2_MANUAL (1<<23) +#define SYS_CTRL_AP_MODE_APB2_I2C3_AUTOMATIC (0<<24) +#define SYS_CTRL_AP_MODE_APB2_I2C3_MANUAL (1<<24) +#define SYS_CTRL_AP_MODE_CLK_APB2(n) (((n)&0x1FFFFFF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APB2_MASK (0x1FFFFFF<<0) +#define SYS_CTRL_AP_MODE_CLK_APB2_SHIFT (0) + +//Clk_APB2_Enable +#define SYS_CTRL_AP_ENABLE_APB2_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB2_IFC (1<<1) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH0 (1<<2) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH1 (1<<3) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH2 (1<<4) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH3 (1<<5) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH4 (1<<6) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH5 (1<<7) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH6 (1<<8) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH7 (1<<9) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH8 (1<<10) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH9 (1<<11) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH10 (1<<12) +#define SYS_CTRL_AP_ENABLE_APB2_UART1 (1<<13) +#define SYS_CTRL_AP_ENABLE_APB2_UART2 (1<<14) +#define SYS_CTRL_AP_ENABLE_APB2_UART3 (1<<15) +#define SYS_CTRL_AP_ENABLE_APB2_SPI1 (1<<16) +#define SYS_CTRL_AP_ENABLE_APB2_SPI2 (1<<17) +#define SYS_CTRL_AP_ENABLE_APB2_SPI3 (1<<18) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC1 (1<<19) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC2 (1<<20) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC3 (1<<21) +#define SYS_CTRL_AP_ENABLE_APB2_I2C1 (1<<22) +#define SYS_CTRL_AP_ENABLE_APB2_I2C2 (1<<23) +#define SYS_CTRL_AP_ENABLE_APB2_I2C3 (1<<24) +#define SYS_CTRL_AP_ENABLE_APB2_ALWAYS (1<<25) +#define SYS_CTRL_AP_ENABLE_APB2_NANDFLASH (1<<26) +#define SYS_CTRL_AP_ENABLE_CLK_APB2(n) (((n)&0x7FFFFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB2_MASK (0x7FFFFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB2_SHIFT (0) + +//Clk_APB2_Disable +#define SYS_CTRL_AP_DISABLE_APB2_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB2_IFC (1<<1) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH0 (1<<2) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH1 (1<<3) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH2 (1<<4) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH3 (1<<5) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH4 (1<<6) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH5 (1<<7) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH6 (1<<8) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH7 (1<<9) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH8 (1<<10) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH9 (1<<11) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH10 (1<<12) +#define SYS_CTRL_AP_DISABLE_APB2_UART1 (1<<13) +#define SYS_CTRL_AP_DISABLE_APB2_UART2 (1<<14) +#define SYS_CTRL_AP_DISABLE_APB2_UART3 (1<<15) +#define SYS_CTRL_AP_DISABLE_APB2_SPI1 (1<<16) +#define SYS_CTRL_AP_DISABLE_APB2_SPI2 (1<<17) +#define SYS_CTRL_AP_DISABLE_APB2_SPI3 (1<<18) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC1 (1<<19) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC2 (1<<20) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC3 (1<<21) +#define SYS_CTRL_AP_DISABLE_APB2_I2C1 (1<<22) +#define SYS_CTRL_AP_DISABLE_APB2_I2C2 (1<<23) +#define SYS_CTRL_AP_DISABLE_APB2_I2C3 (1<<24) +#define SYS_CTRL_AP_DISABLE_APB2_ALWAYS (1<<25) +#define SYS_CTRL_AP_DISABLE_APB2_NANDFLASH (1<<26) +#define SYS_CTRL_AP_DISABLE_CLK_APB2(n) (((n)&0x7FFFFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB2_MASK (0x7FFFFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB2_SHIFT (0) + +//Clk_MEM_Mode +#define SYS_CTRL_AP_MODE_CLK_MEM_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_MEM_MANUAL (1<<0) + +//Clk_MEM_Enable +#define SYS_CTRL_AP_ENABLE_MEM_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_MEM_DMC (1<<1) +#define SYS_CTRL_AP_ENABLE_MEM_DDRPHY_P (1<<2) +#define SYS_CTRL_AP_ENABLE_MEM_CONNECT (1<<3) +#define SYS_CTRL_AP_ENABLE_CLK_MEM(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_MEM_MASK (0xF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_MEM_SHIFT (0) + +//Clk_MEM_Disable +#define SYS_CTRL_AP_DISABLE_MEM_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_MEM_DMC (1<<1) +#define SYS_CTRL_AP_DISABLE_MEM_DDRPHY_P (1<<2) +#define SYS_CTRL_AP_DISABLE_MEM_CONNECT (1<<3) +#define SYS_CTRL_AP_DISABLE_CLK_MEM(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_MEM_MASK (0xF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_MEM_SHIFT (0) + +//Clk_APO_Mode +#define SYS_CTRL_AP_MODE_APOC_BCK_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APOC_BCK_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APOC_BCK2_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APOC_BCK2_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APOC_UART1_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APOC_UART1_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APOC_UART2_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APOC_UART2_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APOC_UART3_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APOC_UART3_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APOC_VOC_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APOC_VOC_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APOC_VOC2_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APOC_VOC2_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_CLK_APO(n) (((n)&01FF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APO_MASK (0x1FF<<0) +#define SYS_CTRL_AP_MODE_CLK_APO_SHIFT (0) + +//Clk_APO_Enable +#define SYS_CTRL_AP_ENABLE_APOC_BCK (1<<0) +#define SYS_CTRL_AP_ENABLE_APOC_BCK2 (1<<1) +#define SYS_CTRL_AP_ENABLE_APOC_UART1 (1<<2) +#define SYS_CTRL_AP_ENABLE_APOC_UART2 (1<<3) +#define SYS_CTRL_AP_ENABLE_APOC_UART3 (1<<4) +#define SYS_CTRL_AP_ENABLE_APOC_VOC_CORE (1<<5) +#define SYS_CTRL_AP_ENABLE_APOC_VOC2_CORE (1<<6) +#define SYS_CTRL_AP_ENABLE_APOC_VOC (1<<7) +#define SYS_CTRL_AP_ENABLE_APOC_VOC2 (1<<8) +#define SYS_CTRL_AP_ENABLE_APOC_VOC_ALWAYS (1<<9) +#define SYS_CTRL_AP_ENABLE_APOC_VOC2_ALWAYS (1<<10) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY_N (1<<11) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XP (1<<12) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XN (1<<13) +#define SYS_CTRL_AP_ENABLE_APOC_VPU (1<<14) +#define SYS_CTRL_AP_ENABLE_APOC_GPU (1<<15) +#define SYS_CTRL_AP_ENABLE_APOC_USBPHY (1<<16) +#define SYS_CTRL_AP_ENABLE_APOC_CSI (1<<17) +#define SYS_CTRL_AP_ENABLE_APOC_CSI2 (1<<18) +#define SYS_CTRL_AP_ENABLE_APOC_DSI (1<<19) +#define SYS_CTRL_AP_ENABLE_APOC_GPIO (1<<20) +#define SYS_CTRL_AP_ENABLE_APOC_SPIFLASH (1<<21) +#define SYS_CTRL_AP_ENABLE_APOC_PIX (1<<22) +#define SYS_CTRL_AP_ENABLE_APOC_PIX2 (1<<23) +#define SYS_CTRL_AP_ENABLE_APOC_PDGB (1<<24) +#define SYS_CTRL_AP_ENABLE_CLK_APO(n) (((n)&0x1FFFFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APO_MASK (0x1FFFFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APO_SHIFT (0) + +//Clk_APO_Disable +#define SYS_CTRL_AP_DISABLE_APOC_BCK (1<<0) +#define SYS_CTRL_AP_DISABLE_APOC_BCK2 (1<<1) +#define SYS_CTRL_AP_DISABLE_APOC_UART1 (1<<2) +#define SYS_CTRL_AP_DISABLE_APOC_UART2 (1<<3) +#define SYS_CTRL_AP_DISABLE_APOC_UART3 (1<<4) +#define SYS_CTRL_AP_DISABLE_APOC_VOC_CORE (1<<5) +#define SYS_CTRL_AP_DISABLE_APOC_VOC2_CORE (1<<6) +#define SYS_CTRL_AP_DISABLE_APOC_VOC (1<<7) +#define SYS_CTRL_AP_DISABLE_APOC_VOC2 (1<<8) +#define SYS_CTRL_AP_DISABLE_APOC_VOC_ALWAYS (1<<9) +#define SYS_CTRL_AP_DISABLE_APOC_VOC2_ALWAYS (1<<10) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY_N (1<<11) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XP (1<<12) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XN (1<<13) +#define SYS_CTRL_AP_DISABLE_APOC_VPU (1<<14) +#define SYS_CTRL_AP_DISABLE_APOC_GPU (1<<15) +#define SYS_CTRL_AP_DISABLE_APOC_USBPHY (1<<16) +#define SYS_CTRL_AP_DISABLE_APOC_CSI (1<<17) +#define SYS_CTRL_AP_DISABLE_APOC_CSI2 (1<<18) +#define SYS_CTRL_AP_DISABLE_APOC_DSI (1<<19) +#define SYS_CTRL_AP_DISABLE_APOC_GPIO (1<<20) +#define SYS_CTRL_AP_DISABLE_APOC_SPIFLASH (1<<21) +#define SYS_CTRL_AP_DISABLE_APOC_PIX (1<<22) +#define SYS_CTRL_AP_DISABLE_APOC_PIX2 (1<<23) +#define SYS_CTRL_AP_DISABLE_APOC_PDGB (1<<24) +#define SYS_CTRL_AP_DISABLE_CLK_APO(n) (((n)&0x1FFFFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APO_MASK (0x1FFFFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APO_SHIFT (0) + +//Cfg_Clk_AP_CPU +#define SYS_CTRL_AP_AP_CPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_CPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_BUS_DIV_SEL(n) (((n)&3)<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_MASK (3<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_SHIFT (16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV2 (0<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV3 (1<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV4 (2<<16) +#define SYS_CTRL_AP_DBG_CLKDIV_SEL(n) (((n)&15)<<20) +#define SYS_CTRL_AP_DBG_CLKDIV_DIV_SEL_MASK (15<<20) +#define SYS_CTRL_AP_DBG_CLKDIV_SEL_SHIFT (20) +#define SYS_CTRL_AP_AP_CPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_AXI +#define SYS_CTRL_AP_AP_AXI_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_AXI_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_AXI_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_AXI_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_GCG +#define SYS_CTRL_AP_AP_GCG_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_GCG_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_GCG_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_GCG_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_AHB1 +#define SYS_CTRL_AP_AP_AHB1_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_AHB1_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_AHB1_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_APB1 +#define SYS_CTRL_AP_AP_APB1_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_APB1_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_APB1_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_APB1_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_APB2 +#define SYS_CTRL_AP_AP_APB2_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_APB2_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_APB2_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_APB2_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_MEM +#define SYS_CTRL_AP_AP_MEM_SRC_DIV2 (1<<12) + +//Cfg_Clk_AP_GPU +#define SYS_CTRL_AP_AP_GPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_GPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_GPU_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_GPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_VPU +#define SYS_CTRL_AP_AP_VPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_VPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_VPU_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_VPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_VOC +#define SYS_CTRL_AP_AP_VOC_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_SFLSH +#define SYS_CTRL_AP_AP_SFLSH_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_SFLSH_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_SFLSH_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_Uart +#define SYS_CTRL_AP_UART_DIVIDER(n) (((n)&0x3FF)<<0) +#define SYS_CTRL_AP_UART_DIVIDER_MASK (0x3FF<<0) +#define SYS_CTRL_AP_UART_DIVIDER_SHIFT (0) +#define SYS_CTRL_AP_UART_SEL_PLL_SLOW (0<<12) +#define SYS_CTRL_AP_UART_SEL_PLL_PLL (1<<12) + +//L2cc_Ctrl +#define SYS_CTRL_AP_ARQOS_L2CC_1_M(n) (((n)&15)<<0) +#define SYS_CTRL_AP_ARQOS_L2CC_1_M_MASK (15<<0) +#define SYS_CTRL_AP_ARQOS_L2CC_1_M_SHIFT (0) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M(n) (((n)&15)<<4) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M_MASK (15<<4) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M_SHIFT (4) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<8) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_MASK (15<<8) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_SHIFT (8) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<12) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_MASK (15<<12) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_SHIFT (12) +#define SYS_CTRL_AP_ARAP_L2CC_1_M (1<<16) +#define SYS_CTRL_AP_AWAP_L2CC_1_M (1<<17) +#define SYS_CTRL_AP_ARAP_MODEM_MEM_AHBS_M (1<<18) +#define SYS_CTRL_AP_AWAP_MODEM_MEM_AHBS_M (1<<19) +#define SYS_CTRL_AP_ARAP_MERGE1M (1<<20) +#define SYS_CTRL_AP_AWAP_MERGE1M (1<<21) +#define SYS_CTRL_AP_ARAP_MERGE2M (1<<22) +#define SYS_CTRL_AP_AWAP_MERGE2M (1<<23) +#define SYS_CTRL_AP_RESERVE1(n) (((n)&0xFF)<<24) +#define SYS_CTRL_AP_RESERVE1_MASK (0xFF<<24) +#define SYS_CTRL_AP_RESERVE1_SHIFT (24) + +//Spi_Ctrl +#define SYS_CTRL_AP_LIMITED_EN_SPI1 (1<<0) +#define SYS_CTRL_AP_LPSEN_SPI1 (1<<1) +#define SYS_CTRL_AP_LIMITED_EN_SPI2 (1<<2) +#define SYS_CTRL_AP_LPSEN_SPI2 (1<<3) +#define SYS_CTRL_AP_LIMITED_EN_SPI3 (1<<4) +#define SYS_CTRL_AP_LPSEN_SPI3 (1<<5) +#define SYS_CTRL_AP_FBUSWID_NFSC (1<<6) +#define SYS_CTRL_AP_RESERVE3 (1<<7) +#define SYS_CTRL_AP_DMC_CFG(n) (((n)&0x3FF)<<8) +#define SYS_CTRL_AP_DMC_CFG_MASK (0x3FF<<8) +#define SYS_CTRL_AP_DMC_CFG_SHIFT (8) +#define SYS_CTRL_AP_RESERVE2(n) (((n)&0x3FFF)<<18) +#define SYS_CTRL_AP_RESERVE2_MASK (0x3FFF<<18) +#define SYS_CTRL_AP_RESERVE2_SHIFT (18) + +//Memory_Margin +#define SYS_CTRL_AP_EMAW_VOC(n) (((n)&3)<<0) +#define SYS_CTRL_AP_EMAW_VOC_MASK (3<<0) +#define SYS_CTRL_AP_EMAW_VOC_SHIFT (0) +#define SYS_CTRL_AP_EMA_VOC(n) (((n)&7)<<2) +#define SYS_CTRL_AP_EMA_VOC_MASK (7<<2) +#define SYS_CTRL_AP_EMA_VOC_SHIFT (2) +#define SYS_CTRL_AP_EMAW_VPU(n) (((n)&3)<<5) +#define SYS_CTRL_AP_EMAW_VPU_MASK (3<<5) +#define SYS_CTRL_AP_EMAW_VPU_SHIFT (5) +#define SYS_CTRL_AP_EMA_VPU(n) (((n)&7)<<7) +#define SYS_CTRL_AP_EMA_VPU_MASK (7<<7) +#define SYS_CTRL_AP_EMA_VPU_SHIFT (7) +#define SYS_CTRL_AP_EMAW_GPU(n) (((n)&3)<<10) +#define SYS_CTRL_AP_EMAW_GPU_MASK (3<<10) +#define SYS_CTRL_AP_EMAW_GPU_SHIFT (10) +#define SYS_CTRL_AP_EMA_GPU(n) (((n)&7)<<12) +#define SYS_CTRL_AP_EMA_GPU_MASK (7<<12) +#define SYS_CTRL_AP_EMA_GPU_SHIFT (12) +#define SYS_CTRL_AP_EMAW_GOUDA(n) (((n)&3)<<15) +#define SYS_CTRL_AP_EMAW_GOUDA_MASK (3<<15) +#define SYS_CTRL_AP_EMAW_GOUDA_SHIFT (15) +#define SYS_CTRL_AP_EMA_GOUDA(n) (((n)&7)<<17) +#define SYS_CTRL_AP_EMA_GOUDA_MASK (7<<17) +#define SYS_CTRL_AP_EMA_GOUDA_SHIFT (17) +#define SYS_CTRL_AP_EMAW_IMEM(n) (((n)&3)<<20) +#define SYS_CTRL_AP_EMAW_IMEM_MASK (3<<20) +#define SYS_CTRL_AP_EMAW_IMEM_SHIFT (20) +#define SYS_CTRL_AP_EMA_IMEM(n) (((n)&7)<<22) +#define SYS_CTRL_AP_EMA_IMEM_MASK (7<<22) +#define SYS_CTRL_AP_EMA_IMEM_SHIFT (22) +#define SYS_CTRL_AP_EMAW_USB(n) (((n)&3)<<25) +#define SYS_CTRL_AP_EMAW_USB_MASK (3<<25) +#define SYS_CTRL_AP_EMAW_USB_SHIFT (25) +#define SYS_CTRL_AP_EMA_USB(n) (((n)&7)<<27) +#define SYS_CTRL_AP_EMA_USB_MASK (7<<27) +#define SYS_CTRL_AP_EMA_USB_SHIFT (27) + +//Memory_Margin2 +#define SYS_CTRL_AP_EMAW_NFSC(n) (((n)&3)<<0) +#define SYS_CTRL_AP_EMAW_NFSC_MASK (3<<0) +#define SYS_CTRL_AP_EMAW_NFSC_SHIFT (0) +#define SYS_CTRL_AP_EMA_NFSC(n) (((n)&7)<<2) +#define SYS_CTRL_AP_EMA_NFSC_MASK (7<<2) +#define SYS_CTRL_AP_EMA_NFSC_SHIFT (2) +#define SYS_CTRL_AP_EMA_VPUROM(n) (((n)&7)<<5) +#define SYS_CTRL_AP_EMA_VPUROM_MASK (7<<5) +#define SYS_CTRL_AP_EMA_VPUROM_SHIFT (5) +#define SYS_CTRL_AP_EMA_IMEMROM(n) (((n)&7)<<8) +#define SYS_CTRL_AP_EMA_IMEMROM_MASK (7<<8) +#define SYS_CTRL_AP_EMA_IMEMROM_SHIFT (8) +#define SYS_CTRL_AP_KEN_VPUROM (1<<11) +#define SYS_CTRL_AP_PGEN_VPUROM (1<<12) +#define SYS_CTRL_AP_KEN_IMEMROM (1<<13) +#define SYS_CTRL_AP_PGEN_IMEMROM (1<<14) + +//Memory_Observe +#define SYS_CTRL_AP_MEM_OBSERVE(n) (((n)&0xFFFFFFFF)<<0) + +//Cfg_Clk_AP_VOC2 +#define SYS_CTRL_AP_AP_VOC2_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_VOC2_FREQ_MASK (31 << 0) +#define SYS_CTRL_AP_AP_VOC2_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_VOC2_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_VOC2_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_EMMC +#define SYS_CTRL_AP_EMMC_DATA_STB_DLY(n) (((n)&31)<<0) +#define SYS_CTRL_AP_EMMC_DATA_STB_DLY_MASK (31 << 0) +#define SYS_CTRL_AP_EMMC_DATA_STB_DLY_SHIFT 0 +#define SYS_CTRL_AP_EMMC_CLK_DLY(n) (((n)&31)<<8) +#define SYS_CTRL_AP_EMMC_CLK_DLY_MASK (31 << 8) +#define SYS_CTRL_AP_EMMC_CLK_DLY_SHIFT 8 +#define SYS_CTRL_AP_EMMC_CLK_POL (1<<13) + +//Test_Pulse +#define SYS_CTRL_AP_PULSE_COUNTER(n) (((n)&0xFFFFFFFF)<<0) + +//Cfg_Reserve +#define SYS_CTRL_AP_RESERVE(n) (((n)&0xFFFFFFFF)<<0) + +#endif diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8820.h b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8820.h new file mode 100644 index 0000000000..ab7ba4c951 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8820.h @@ -0,0 +1,1578 @@ +#ifndef _REG_SYSCTRL_H_ +#define _REG_SYSCTRL_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= + +// ============================================================================ +// AP_CPU_ID_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// CPU IDs + CPU0 = 0x00000000, + CPU1 = 0x00000001 +} AP_CPU_ID_T; + + +// ============================================================================ +// CPU_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP CPU side System clocks + CPU_CORE = 0x00000000, +/// the following don't have an auto enable + CPU_DUMMY = 0x00000001 +} CPU_CLKS_T; + +#define NB_CPU_CLK_AEN (1) +#define NB_CPU_CLK_EN (2) +#define NB_CPU_CLK (2) + +// ============================================================================ +// AXI_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXI side System clocks: AXI and AHB0 and APB0 + AHB0_CONF = 0x00000000, + APB0_CONF = 0x00000001, + AXI_VOC = 0x00000002, + AXI_DMA = 0x00000003, +/// the following don't have an auto enable + AXI_ALWAYS = 0x00000004, + AXI_CONNECT = 0x00000005, + APB0_IRQ = 0x00000006 +} AXI_CLKS_T; + +#define NB_AXI_CLK_AEN (4) +#define NB_AXI_CLK_EN (7) +#define NB_AXI_CLK (7) + +// ============================================================================ +// AXIDIV2_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXIdiv2 side System clocks + AXIDIV2_IMEM = 0x00000000, +/// the following don't have an auto enable + AXIDIV2_ALWAYS = 0x00000001, + AXIDIV2_CONNECT = 0x00000002, + AXIDIV2_VPU = 0x00000003 +} AXIDIV2_CLKS_T; + +#define NB_AXIDIV2_CLK_AEN (1) +#define NB_AXIDIV2_CLK_EN (4) +#define NB_AXIDIV2_CLK (4) + +// ============================================================================ +// GCG_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GCG side System clocks + GCG_APB_CONF = 0x00000000, + GCG_GOUDA = 0x00000001, + GCG_CAMERA = 0x00000002, +/// the following don't have an auto enable + GCG_ALWAYS = 0x00000003, + GCG_CONNECT = 0x00000004 +} GCG_CLKS_T; + +#define NB_GCG_CLK_AEN (3) +#define NB_GCG_CLK_EN (5) +#define NB_GCG_CLK (5) + +// ============================================================================ +// AHB1_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AHB1 side System clocks + AHB1_USBC = 0x00000000, +/// the following don't have an auto enable + AHB1_ALWAYS = 0x00000001, + AHB1_SPIFLASH = 0x00000002 +} AHB1_CLKS_T; + +#define NB_AHB1_CLK_AEN (1) +#define NB_AHB1_CLK_EN (3) +#define NB_AHB1_CLK (3) + +// ============================================================================ +// APB1_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB1 side System clocks + APB1_CONF = 0x00000000, + APB1_AIF = 0x00000001, + APB1_AUIFC = 0x00000002, + APB1_AUIFC_CH0 = 0x00000003, + APB1_AUIFC_CH1 = 0x00000004, + APB1_I2C1 = 0x00000005, + APB1_I2C2 = 0x00000006, + APB1_I2C3 = 0x00000007, +/// AP APB1 side divided clock (either divided by module or by clock_ctrl) + APB1D_OSC = 0x00000008, + APB1D_PWM = 0x00000009, +/// the following don't have an auto enable + APB1_ALWAYS = 0x0000000A, + APB1_DAPLITE = 0x0000000B, + APB1_TIMER = 0x0000000C, + APB1_GPIO = 0x0000000D +} APB1_CLKS_T; + +#define NB_APB1_CLK_AEN (10) +#define NB_APB1_CLK_EN (14) +#define NB_APB1_CLK (14) + +// ============================================================================ +// APB2_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB2 side System clocks + APB2_CONF = 0x00000000, + APB2_IFC = 0x00000001, + APB2_IFC_CH0 = 0x00000002, + APB2_IFC_CH1 = 0x00000003, + APB2_IFC_CH2 = 0x00000004, + APB2_IFC_CH3 = 0x00000005, + APB2_IFC_CH4 = 0x00000006, + APB2_IFC_CH5 = 0x00000007, + APB2_IFC_CH6 = 0x00000008, + APB2_IFC_CH7 = 0x00000009, + APB2_UART1 = 0x0000000A, + APB2_UART2 = 0x0000000B, + APB2_UART3 = 0x0000000C, + APB2_SPI1 = 0x0000000D, + APB2_SPI2 = 0x0000000E, + APB2_SPI3 = 0x0000000F, + APB2_SDMMC1 = 0x00000010, + APB2_SDMMC2 = 0x00000011, + APB2_SDMMC3 = 0x00000012, +/// the following don't have an auto enable + APB2_ALWAYS = 0x00000013, + APB2_NANDFLASH = 0x00000014 +} APB2_CLKS_T; + +#define NB_APB2_CLK_AEN (19) +#define NB_APB2_CLK_EN (21) +#define NB_APB2_CLK (21) + +// ============================================================================ +// MEM_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP MEM side System clocks + MEM_CONF = 0x00000000, +/// the following don't have an auto enable + MEM_DMC = 0x00000001, + MEM_GPU = 0x00000002, + MEM_VPU = 0x00000003, + MEM_DDRPHY_P = 0x00000004, + MEM_CONNECT = 0x00000005 +} MEM_CLKS_T; + +#define NB_MEM_CLK_AEN (1) +#define NB_MEM_CLK_EN (6) +#define NB_MEM_CLK (6) + +// ============================================================================ +// APO_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP side Other clocks +/// clocks with auto enble + APOC_VPU = 0x00000000, + APOC_BCK = 0x00000001, + APOC_UART1 = 0x00000002, + APOC_UART2 = 0x00000003, + APOC_UART3 = 0x00000004, + APOC_VOC_CORE = 0x00000005, + APOC_VOC = 0x00000006, +/// the following don't have an auto enable + APOC_VOC_ALWAYS = 0x00000007, + APOC_DDRPHY_N = 0x00000008, + APOC_DDRPHY2XP = 0x00000009, + APOC_DDRPHY2XN = 0x0000000A, + APOC_GPU = 0x0000000B, + APOC_USBPHY = 0x0000000C, + APOC_CSI = 0x0000000D, + APOC_DSI = 0x0000000E, + APOC_GPIO = 0x0000000F, + APOC_SPIFLASH = 0x00000010, + APOC_PIX = 0x00000011, + APOC_PDGB = 0x00000012 +} APO_CLKS_T; + +#define NB_CLK_VOC_AEN_SYNC (5) +#define NB_CLK_VOC_CORE (6) +#define NB_APO_CLK_AEN (7) +#define NB_CLK_VOC_END (8) +#define NB_APO_CLK_EN (19) +#define NB_APO_CLK (19) + +// ============================================================================ +// CPU_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP CPU side resets + CPU_RST_CORE = 0x00000000, + CPU_RST_SYS = 0x00000001 +} CPU_RESETS_T; + +#define NB_CPU_RST (2) + +// ============================================================================ +// AXI_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXI side resets: AXI and AHB0 and APB0 + AXI_RST_VOC = 0x00000000, + AXI_RST_DMA = 0x00000001, + AXI_RST_SYS = 0x00000002, + AXI_RST_CONNECT = 0x00000003, + AHB0_RST_GPU = 0x00000004, + APB0_RST_VPU = 0x00000005, + APB0_RST_IRQ = 0x00000006 +} AXI_RESETS_T; + +#define NB_AXI_RST (7) + +// ============================================================================ +// AXIDIV2_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXIDIV2 side resets + AXIDIV2_RST_IMEM = 0x00000000, + AXIDIV2_RST_SYS = 0x00000001, + AXIDIV2_RST_VPU = 0x00000002 +} AXIDIV2_RESETS_T; + +#define NB_AXIDIV2_RST (3) + +// ============================================================================ +// GCG_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GCG side resets + GCG_RST_SYS = 0x00000000, + GCG_RST_GOUDA = 0x00000001, + GCG_RST_CAMERA = 0x00000002 +} GCG_RESETS_T; + +#define NB_GCG_RST (3) + +// ============================================================================ +// AHB1_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AHB1 side resets + AHB1_RST_SYS = 0x00000000, + AHB1_RST_USBC = 0x00000001, + AHB1_RST_SPIFLASH = 0x00000002 +} AHB1_RESETS_T; + +#define NB_AHB1_RST (3) + +// ============================================================================ +// APB1_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB1 side resets + APB1_RST_SYS = 0x00000000, + APB1_RST_TIMER = 0x00000001, + APB1_RST_KEYPAD = 0x00000002, + APB1_RST_GPIO = 0x00000003, + APB1_RST_PWM = 0x00000004, + APB1_RST_AIF = 0x00000005, + APB1_RST_AUIFC = 0x00000006, + APB1_RST_I2C1 = 0x00000007, + APB1_RST_I2C2 = 0x00000008, + APB1_RST_I2C3 = 0x00000009, + APB1_RST_COM_REGS = 0x0000000A, + APB1_RST_DMC = 0x0000000B, + APB1_RST_DDRPHY_P = 0x0000000C, + APB1_RST_BB2G_XCPU = 0x0000000D, + APB1_RST_BB2G_BCPU = 0x0000000E, + APB1_RST_BB2G_AHBC = 0x0000000F, + APB1_RST_BB2G_DMA = 0x00000010, + APB1_RST_BB2G_A2A = 0x00000011, + APB1_RST_BB2G_XIFC = 0x00000012, + APB1_RST_BB2G_BIFC = 0x00000013, + APB1_RST_BB2G_BAHBC = 0x00000014, + APB1_RST_BB2G_MEM_BRIDGE = 0x00000015 +} APB1_RESETS_T; + +#define NB_APB1_RST (22) + +// ============================================================================ +// APB2_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB2 side resets + APB2_RST_SYS = 0x00000000, + APB2_RST_IFC = 0x00000001, + APB2_RST_UART1 = 0x00000002, + APB2_RST_UART2 = 0x00000003, + APB2_RST_UART3 = 0x00000004, + APB2_RST_SPI1 = 0x00000005, + APB2_RST_SPI2 = 0x00000006, + APB2_RST_SPI3 = 0x00000007, + APB2_RST_SDMMC1 = 0x00000008, + APB2_RST_SDMMC2 = 0x00000009, + APB2_RST_SDMMC3 = 0x0000000A, + APB2_RST_NANDFLASH = 0x0000000B +} APB2_RESETS_T; + +#define NB_APB2_RST (12) + +// ============================================================================ +// MEM_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP MEM side resets + MEM_RST_SYS = 0x00000000, + MEM_RST_GPU = 0x00000001, + MEM_RST_VPU = 0x00000002, + MEM_RST_DMC = 0x00000003, + MEM_RST_DDRPHY_P = 0x00000004 +} MEM_RESETS_T; + +#define NB_MEM_RST (5) + +// ============================================================================ +// AP_OTHERS_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP Reset Other : resync on corresponding clock other + AP_RSTO_VOC = 0x00000000, + AP_RSTO_DDRPHY_N = 0x00000001, + AP_RSTO_DDRPHY2XP = 0x00000002, + AP_RSTO_DDRPHY2XN = 0x00000003, + AP_RSTO_GPU = 0x00000004, + AP_RSTO_VPU = 0x00000005, + AP_RSTO_BCK = 0x00000006, + AP_RSTO_UART1 = 0x00000007, + AP_RSTO_UART2 = 0x00000008, + AP_RSTO_UART3 = 0x00000009, + AP_RSTO_GPIO = 0x0000000A, + AP_RSTO_TIMER = 0x0000000B, + AP_RSTO_USBC = 0x0000000C, + AP_RSTO_DSI = 0x0000000D, + AP_RSTO_SPIFLASH = 0x0000000E, + AP_RSTO_TCK = 0x0000000F, + AP_RSTO_PDBG_XTAL = 0x00000010 +} AP_OTHERS_RESETS_T; + +#define NB_AP_RSTO (17) +/// For REG_DBG protect lock/unlock value +#define AP_CTRL_PROTECT_LOCK (0XA50000) +#define AP_CTRL_PROTECT_UNLOCK (0XA50001) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// SYS_CTRL_AP_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + /// <strong>This register is used to Lock and Unlock the protected registers.</strong> + REG32 REG_DBG; //0x00000000 + /// Register protected by Write_Unlocked_H. + REG32 Cfg_Pll_Ctrl[4]; //0x00000004 + /// This register is protected. + REG32 Sel_Clock; //0x00000014 + REG32 Reset_Cause; //0x00000018 + /// This register is protected. + REG32 CPU_Rst_Set; //0x0000001C + REG32 CPU_Rst_Clr; //0x00000020 + /// This register is protected. + REG32 AXI_Rst_Set; //0x00000024 + REG32 AXI_Rst_Clr; //0x00000028 + /// This register is protected. + REG32 AXIDIV2_Rst_Set; //0x0000002C + REG32 AXIDIV2_Rst_Clr; //0x00000030 + /// This register is protected. + REG32 GCG_Rst_Set; //0x00000034 + REG32 GCG_Rst_Clr; //0x00000038 + /// This register is protected. + REG32 AHB1_Rst_Set; //0x0000003C + REG32 AHB1_Rst_Clr; //0x00000040 + /// This register is protected. + REG32 APB1_Rst_Set; //0x00000044 + REG32 APB1_Rst_Clr; //0x00000048 + /// This register is protected. + REG32 APB2_Rst_Set; //0x0000004C + REG32 APB2_Rst_Clr; //0x00000050 + /// This register is protected. + REG32 MEM_Rst_Set; //0x00000054 + REG32 MEM_Rst_Clr; //0x00000058 + REG32 Clk_CPU_Mode; //0x0000005C + REG32 Clk_CPU_Enable; //0x00000060 + /// This register is protected. + REG32 Clk_CPU_Disable; //0x00000064 + REG32 Clk_AXI_Mode; //0x00000068 + REG32 Clk_AXI_Enable; //0x0000006C + /// This register is protected. + REG32 Clk_AXI_Disable; //0x00000070 + REG32 Clk_AXIDIV2_Mode; //0x00000074 + REG32 Clk_AXIDIV2_Enable; //0x00000078 + /// This register is protected. + REG32 Clk_AXIDIV2_Disable; //0x0000007C + REG32 Clk_GCG_Mode; //0x00000080 + REG32 Clk_GCG_Enable; //0x00000084 + /// This register is protected. + REG32 Clk_GCG_Disable; //0x00000088 + REG32 Clk_AHB1_Mode; //0x0000008C + REG32 Clk_AHB1_Enable; //0x00000090 + /// This register is protected. + REG32 Clk_AHB1_Disable; //0x00000094 + REG32 Clk_APB1_Mode; //0x00000098 + REG32 Clk_APB1_Enable; //0x0000009C + /// This register is protected. + REG32 Clk_APB1_Disable; //0x000000A0 + REG32 Clk_APB2_Mode; //0x000000A4 + REG32 Clk_APB2_Enable; //0x000000A8 + /// This register is protected. + REG32 Clk_APB2_Disable; //0x000000AC + REG32 Clk_MEM_Mode; //0x000000B0 + REG32 Clk_MEM_Enable; //0x000000B4 + /// This register is protected. + REG32 Clk_MEM_Disable; //0x000000B8 + REG32 Clk_APO_Mode; //0x000000BC + REG32 Clk_APO_Enable; //0x000000C0 + /// This register is protected. + REG32 Clk_APO_Disable; //0x000000C4 + REG32 Cfg_Clk_AP_CPU; //0x000000C8 + REG32 Cfg_Clk_AP_AXI; //0x000000CC + REG32 Cfg_Clk_AP_GCG; //0x000000D0 + REG32 Cfg_Clk_AP_AHB1; //0x000000D4 + REG32 Cfg_Clk_AP_APB1; //0x000000D8 + REG32 Cfg_Clk_AP_APB2; //0x000000DC + REG32 Cfg_Clk_AP_MEM; //0x000000E0 + REG32 Cfg_Clk_AP_GPU; //0x000000E4 + REG32 Cfg_Clk_AP_VPU; //0x000000E8 + REG32 Cfg_Clk_AP_VOC; //0x000000EC + REG32 Cfg_Clk_AP_SFLSH; //0x000000F0 + REG32 Cfg_Clk_Uart[3]; //0x000000F4 + REG32 L2cc_Ctrl; //0x00000100 + REG32 Spi_Ctrl; //0x00000104 + REG32 Memory_Margin; //0x00000108 + REG32 Memory_Margin2; //0x0000010C + REG32 Memory_Observe; //0x00000110 + REG32 Cfg_Clk_AP_VOC2; //0x00000114 + REG32 Cfg_Clk_EMMC; //0x00000118 + REG32 Test_Pulse; //0x0000011C + REG32 Reserved_00000114[49]; //0x00000120 + /// This register is reserved. + REG32 Cfg_Cpu_Reserve0; //0x000001E4 + REG32 Cfg_Cpu_Reserve1; //0x000001E8 + REG32 Cfg_Cpu_Reserve2; //0x000001EC + REG32 Cfg_Cpu_Reserve3; //0x000001F0 + REG32 Cfg_Cpu_Reserve4; //0x000001F4 + REG32 Cfg_Cpu_Reserve5; //0x000001F8 + REG32 Cfg_Reserve; //0x000001FC +} HWP_SYS_CTRL_AP_T; + +#define hwp_sysCtrlAp ((HWP_SYS_CTRL_AP_T*)(RDA_SYSCTRL_BASE)) + + +//REG_DBG +#define SYS_CTRL_AP_SCRATCH(n) (((n)&0xFFFF)<<0) +#define SYS_CTRL_AP_WRITE_UNLOCK_STATUS (1<<30) +#define SYS_CTRL_AP_WRITE_UNLOCK (1<<31) + +//Cfg_Pll_Ctrl +#define SYS_CTRL_AP_AP_PLL_ENABLE (1<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_MASK (1<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_SHIFT (0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN (0<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE (1<<0) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET (1<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK (1<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_SHIFT (4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET (0<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET (1<<4) +#define SYS_CTRL_AP_AP_PLL_BYPASS (1<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_MASK (1<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_SHIFT (8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_PASS (0<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_BYPASS (1<<8) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_MASK (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_SHIFT (12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_DISABLE (0<<12) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(n) (((n)&31)<<16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_MASK (31<<16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_SHIFT (16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(n) (((n)&31)<<24) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_MASK (31<<24) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_SHIFT (24) +#define SYS_CTRL_AP_PLL_AP_CFG(n) (((n)&0x1F1F1111)<<0) +#define SYS_CTRL_AP_PLL_AP_CFG_MASK (0x1F1F1111<<0) +#define SYS_CTRL_AP_PLL_AP_CFG_SHIFT (0) + +//Sel_Clock +#define SYS_CTRL_AP_SLOW_SEL_RF_OSCILLATOR (1<<0) +#define SYS_CTRL_AP_SLOW_SEL_RF_RF (0<<0) +#define SYS_CTRL_AP_TIMER_SEL_FAST_SLOW (1<<1) +#define SYS_CTRL_AP_TIMER_SEL_FAST_FAST (0<<1) +#define SYS_CTRL_AP_TIMER2_SEL_FAST_SLOW (1<<2) +#define SYS_CTRL_AP_TIMER2_SEL_FAST_FAST (0<<2) +#define SYS_CTRL_AP_TIMER3_SEL_FAST_SLOW (1<<3) +#define SYS_CTRL_AP_TIMER3_SEL_FAST_FAST (0<<3) +#define SYS_CTRL_AP_CPU_SEL_FAST_SLOW (1<<4) +#define SYS_CTRL_AP_CPU_SEL_FAST_FAST (0<<4) +#define SYS_CTRL_AP_BUS_SEL_FAST_SLOW (1<<5) +#define SYS_CTRL_AP_BUS_SEL_FAST_FAST (0<<5) +#define SYS_CTRL_AP_RF_DETECTED_OK (1<<8) +#define SYS_CTRL_AP_RF_DETECTED_NO (0<<8) +#define SYS_CTRL_AP_RF_DETECT_BYPASS (1<<9) +#define SYS_CTRL_AP_RF_DETECT_RESET (1<<10) +#define SYS_CTRL_AP_RF_SELECTED_L (1<<11) +#define SYS_CTRL_AP_PLL_LOCKED_CPU (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_MASK (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_SHIFT (12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_NOT_LOCKED (0<<12) +#define SYS_CTRL_AP_PLL_LOCKED_BUS (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_MASK (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_SHIFT (13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_NOT_LOCKED (0<<13) +#define SYS_CTRL_AP_PLL_LOCKED_MEM (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_MASK (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_SHIFT (14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_NOT_LOCKED (0<<14) +#define SYS_CTRL_AP_PLL_LOCKED_USB (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_MASK (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_SHIFT (15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_NOT_LOCKED (0<<15) +#define SYS_CTRL_AP_PLL_BYPASS_LOCK_CPU (1<<20) +#define SYS_CTRL_AP_PLL_BYPASS_LOCK_BUS (1<<21) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L (1<<30) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_MASK (1<<30) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_SHIFT (30) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L (1<<31) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_MASK (1<<31) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_SHIFT (31) + +//Reset_Cause +#define SYS_CTRL_AP_WATCHDOG_RESET_HAPPENED (1<<0) +#define SYS_CTRL_AP_WATCHDOG_RESET_NO (0<<0) +#define SYS_CTRL_AP_GLOBALSOFT_RESET_HAPPENED (1<<4) +#define SYS_CTRL_AP_GLOBALSOFT_RESET_NO (0<<4) +#define SYS_CTRL_AP_HOSTDEBUG_RESET_HAPPENED (1<<5) +#define SYS_CTRL_AP_HOSTDEBUG_RESET_NO (0<<5) +#define SYS_CTRL_AP_ALARMCAUSE_HAPPENED (1<<6) +#define SYS_CTRL_AP_ALARMCAUSE_NO (0<<6) +#define SYS_CTRL_AP_BOOT_MODE(n) (((n)&0xFFFF)<<8) +#define SYS_CTRL_AP_BOOT_MODE_MASK (0xFFFF<<8) +#define SYS_CTRL_AP_BOOT_MODE_SHIFT (8) +#define SYS_CTRL_AP_SW_BOOT_MODE(n) (((n)&0x7F)<<24) +#define SYS_CTRL_AP_SW_BOOT_MODE_MASK (0x7F<<24) +#define SYS_CTRL_AP_SW_BOOT_MODE_SHIFT (24) +#define SYS_CTRL_AP_FONCTIONAL_TEST_MODE (1<<31) + +//CPU_Rst_Set +#define SYS_CTRL_AP_SET_CPU_RST_CORE (1<<0) +#define SYS_CTRL_AP_SET_CPU_RST_CORE1 (1<<1) +#define SYS_CTRL_AP_SET_CPU_RST_CORE2 (1<<2) +#define SYS_CTRL_AP_SET_CPU_RST_CORE3 (1<<3) +#define SYS_CTRL_AP_SET_CPU_RST_L2 (1<<4) +#define SYS_CTRL_AP_SET_CPU_RST_SYS (1<<5) +#define SYS_CTRL_AP_SOFT_RST (1<<31) +#define SYS_CTRL_AP_SET_CPU_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_SET_CPU_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_SET_CPU_RST_SHIFT (0) + +//CPU_Rst_Clr +#define SYS_CTRL_AP_CLR_CPU_RST_CORE (1<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_CORE1 (1<<1) +#define SYS_CTRL_AP_CLR_CPU_RST_CORE2 (1<<2) +#define SYS_CTRL_AP_CLR_CPU_RST_CORE3 (1<<3) +#define SYS_CTRL_AP_CLR_CPU_RST_L2 (1<<4) +#define SYS_CTRL_AP_CLR_CPU_RST_SYS (1<<5) +#define SYS_CTRL_AP_CLR_CPU_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_SHIFT (0) + +//AXI_Rst_Set +#define SYS_CTRL_AP_SET_AXI_RST_VOC (1<<0) +#define SYS_CTRL_AP_SET_AXI_RST_VOC2 (1<<1) +#define SYS_CTRL_AP_SET_AXI_RST_DMA (1<<2) +#define SYS_CTRL_AP_SET_AXI_RST_SYS (1<<3) +#define SYS_CTRL_AP_SET_AXI_RST_CONNECT (1<<4) +#define SYS_CTRL_AP_SET_APB0_RST_GPU (1<<5) +#define SYS_CTRL_AP_SET_APB0_RST_VPU (1<<6) +#define SYS_CTRL_AP_SET_APB0_RST_IRQ (1<<7) +#define SYS_CTRL_AP_SET_AXI_RST(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_SET_AXI_RST_MASK (0xFF<<0) +#define SYS_CTRL_AP_SET_AXI_RST_SHIFT (0) + +//AXI_Rst_Clr +#define SYS_CTRL_AP_CLR_AXI_RST_VOC (1<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_VOC2 (1<<1) +#define SYS_CTRL_AP_CLR_AXI_RST_DMA (1<<2) +#define SYS_CTRL_AP_CLR_AXI_RST_SYS (1<<3) +#define SYS_CTRL_AP_CLR_AXI_RST_CONNECT (1<<4) +#define SYS_CTRL_AP_CLR_APB0_RST_GPU (1<<5) +#define SYS_CTRL_AP_CLR_APB0_RST_VPU (1<<6) +#define SYS_CTRL_AP_CLR_APB0_RST_IRQ (1<<7) +#define SYS_CTRL_AP_CLR_AXI_RST(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_MASK (0xFF<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_SHIFT (0) + +//AXIDIV2_Rst_Set +#define SYS_CTRL_AP_SET_AXIDIV2_RST_IMEM (1<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_SYS (1<<1) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_VPU (1<<2) +#define SYS_CTRL_AP_SET_AXIDIV2_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_MASK (7<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_SHIFT (0) + +//AXIDIV2_Rst_Clr +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_IMEM (1<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SYS (1<<1) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_VPU (1<<2) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_MASK (7<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SHIFT (0) + +//GCG_Rst_Set +#define SYS_CTRL_AP_SET_GCG_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_GCG_RST_GOUDA (1<<1) +#define SYS_CTRL_AP_SET_GCG_RST_CAMERA (1<<2) +#define SYS_CTRL_AP_SET_GCG_RST_CAMERA2 (1<<3) +#define SYS_CTRL_AP_SET_GCG_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_SET_GCG_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_SET_GCG_RST_SHIFT (0) + +//GCG_Rst_Clr +#define SYS_CTRL_AP_CLR_GCG_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_GOUDA (1<<1) +#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA (1<<2) +#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA2 (1<<3) +#define SYS_CTRL_AP_CLR_GCG_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_SHIFT (0) + +//AHB1_Rst_Set +#define SYS_CTRL_AP_SET_AHB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_USBC (1<<1) +#define SYS_CTRL_AP_SET_AHB1_RST_SPIFLASH (1<<2) +#define SYS_CTRL_AP_SET_AHB1_RST_EMAC (1<<3) +#define SYS_CTRL_AP_SET_AHB1_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_SHIFT (0) + +//AHB1_Rst_Clr +#define SYS_CTRL_AP_CLR_AHB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_USBC (1<<1) +#define SYS_CTRL_AP_CLR_AHB1_RST_SPIFLASH (1<<2) +#define SYS_CTRL_AP_CLR_AHB1_RST_EMAC (1<<3) +#define SYS_CTRL_AP_CLR_AHB1_RST(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_MASK (0xF<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_SHIFT (0) + +//APB1_Rst_Set +#define SYS_CTRL_AP_SET_APB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_APB1_RST_TIMER (1<<1) +#define SYS_CTRL_AP_SET_APB1_RST_KEYPAD (1<<2) +#define SYS_CTRL_AP_SET_APB1_RST_GPIO (1<<3) +#define SYS_CTRL_AP_SET_APB1_RST_PWM (1<<4) +#define SYS_CTRL_AP_SET_APB1_RST_AIF (1<<5) +#define SYS_CTRL_AP_SET_APB1_RST_AIF2 (1<<6) +#define SYS_CTRL_AP_SET_APB1_RST_AUIFC (1<<7) +#define SYS_CTRL_AP_SET_APB1_RST_COM_REGS (1<<8) +#define SYS_CTRL_AP_SET_APB1_RST_DMC (1<<9) +#define SYS_CTRL_AP_SET_APB1_RST_DDRPHY_P (1<<10) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XCPU (1<<11) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BCPU (1<<12) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_AHBC (1<<13) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_DMA (1<<14) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_A2A (1<<15) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XIFC (1<<16) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BIFC (1<<17) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BAHBC (1<<18) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_MEM_BRIDGE (1<<19) +#define SYS_CTRL_AP_SET_APB1_RST(n) (((n)&0xFFFFF)<<0) +#define SYS_CTRL_AP_SET_APB1_RST_MASK (0xFFFFF<<0) +#define SYS_CTRL_AP_SET_APB1_RST_SHIFT (0) + +//APB1_Rst_Clr +#define SYS_CTRL_AP_CLR_APB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_TIMER (1<<1) +#define SYS_CTRL_AP_CLR_APB1_RST_KEYPAD (1<<2) +#define SYS_CTRL_AP_CLR_APB1_RST_GPIO (1<<3) +#define SYS_CTRL_AP_CLR_APB1_RST_PWM (1<<4) +#define SYS_CTRL_AP_CLR_APB1_RST_AIF (1<<5) +#define SYS_CTRL_AP_CLR_APB1_RST_AIF2 (1<<6) +#define SYS_CTRL_AP_CLR_APB1_RST_AUIFC (1<<7) +#define SYS_CTRL_AP_CLR_APB1_RST_COM_REGS (1<<8) +#define SYS_CTRL_AP_CLR_APB1_RST_DMC (1<<9) +#define SYS_CTRL_AP_CLR_APB1_RST_DDRPHY_P (1<<10) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XCPU (1<<11) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BCPU (1<<12) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_AHBC (1<<13) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_DMA (1<<14) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_A2A (1<<15) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XIFC (1<<16) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BIFC (1<<17) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BAHBC (1<<18) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_MEM_BRIDGE (1<<19) +#define SYS_CTRL_AP_CLR_APB1_RST(n) (((n)&0xFFFFF)<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_MASK (0xFFFFF<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_SHIFT (0) + +//APB2_Rst_Set +#define SYS_CTRL_AP_SET_APB2_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_APB2_RST_IFC (1<<1) +#define SYS_CTRL_AP_SET_APB2_RST_UART1 (1<<2) +#define SYS_CTRL_AP_SET_APB2_RST_UART2 (1<<3) +#define SYS_CTRL_AP_SET_APB2_RST_UART3 (1<<4) +#define SYS_CTRL_AP_SET_APB2_RST_SPI1 (1<<5) +#define SYS_CTRL_AP_SET_APB2_RST_SPI2 (1<<6) +#define SYS_CTRL_AP_SET_APB2_RST_SPI3 (1<<7) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC1 (1<<8) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC2 (1<<9) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC3 (1<<10) +#define SYS_CTRL_AP_SET_APB2_RST_NANDFLASH (1<<11) +#define SYS_CTRL_AP_SET_APB2_RST_I2C1 (1<<12) +#define SYS_CTRL_AP_SET_APB2_RST_I2C2 (1<<13) +#define SYS_CTRL_AP_SET_APB2_RST_I2C3 (1<<14) +#define SYS_CTRL_AP_SET_APB2_RST(n) (((n)&0x7FFF)<<0) +#define SYS_CTRL_AP_SET_APB2_RST_MASK (0x7FFF<<0) +#define SYS_CTRL_AP_SET_APB2_RST_SHIFT (0) + +//APB2_Rst_Clr +#define SYS_CTRL_AP_CLR_APB2_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_IFC (1<<1) +#define SYS_CTRL_AP_CLR_APB2_RST_UART1 (1<<2) +#define SYS_CTRL_AP_CLR_APB2_RST_UART2 (1<<3) +#define SYS_CTRL_AP_CLR_APB2_RST_UART3 (1<<4) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI1 (1<<5) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI2 (1<<6) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI3 (1<<7) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC1 (1<<8) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC2 (1<<9) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC3 (1<<10) +#define SYS_CTRL_AP_CLR_APB2_RST_NANDFLASH (1<<11) +#define SYS_CTRL_AP_CLR_APB2_RST_I2C1 (1<<12) +#define SYS_CTRL_AP_CLR_APB2_RST_I2C2 (1<<13) +#define SYS_CTRL_AP_CLR_APB2_RST_I2C3 (1<<14) +#define SYS_CTRL_AP_CLR_APB2_RST(n) (((n)&0x7FFF)<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_MASK (0x7FFF<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_SHIFT (0) + +//MEM_Rst_Set +#define SYS_CTRL_AP_SET_MEM_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_MEM_RST_DMC (1<<1) +#define SYS_CTRL_AP_SET_MEM_RST_DDRPHY_P (1<<2) +#define SYS_CTRL_AP_SET_MEM_RST(n) (((n)&0x7)<<0) +#define SYS_CTRL_AP_SET_MEM_RST_MASK (0x7<<0) +#define SYS_CTRL_AP_SET_MEM_RST_SHIFT (0) + +//MEM_Rst_Clr +#define SYS_CTRL_AP_CLR_MEM_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_DMC (1<<1) +#define SYS_CTRL_AP_CLR_MEM_RST_DDRPHY_P (1<<2) +#define SYS_CTRL_AP_CLR_MEM_RST(n) (((n)&0x7)<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_MASK (0x7<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_SHIFT (0) + +//Clk_CPU_Mode +#define SYS_CTRL_AP_MODE_CLK_CPU_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_CPU_MANUAL (1<<0) + +//Clk_CPU_Enable +#define SYS_CTRL_AP_ENABLE_CPU_CORE (1<<0) +#define SYS_CTRL_AP_ENABLE_CPU_DUMMY (1<<1) +#define SYS_CTRL_AP_ENABLE_CLK_CPU(n) (((n)&3)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_CPU_MASK (3<<0) +#define SYS_CTRL_AP_ENABLE_CLK_CPU_SHIFT (0) + +//Clk_CPU_Disable +#define SYS_CTRL_AP_DISABLE_CPU_CORE (1<<0) +#define SYS_CTRL_AP_DISABLE_CPU_DUMMY (1<<1) +#define SYS_CTRL_AP_DISABLE_CLK_CPU(n) (((n)&3)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_CPU_MASK (3<<0) +#define SYS_CTRL_AP_DISABLE_CLK_CPU_SHIFT (0) + +//Clk_AXI_Mode +#define SYS_CTRL_AP_MODE_AHB0_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_AHB0_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB0_CONF_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB0_CONF_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_AXI_VOC_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_AXI_VOC_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_AXI_VOC2_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_AXI_VOC2_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_AXI_DMA_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_AXI_DMA_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_CLK_AXI(n) (((n)&0x1F)<<0) +#define SYS_CTRL_AP_MODE_CLK_AXI_MASK (0x1F<<0) +#define SYS_CTRL_AP_MODE_CLK_AXI_SHIFT (0) + +//Clk_AXI_Enable +#define SYS_CTRL_AP_ENABLE_AHB0_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB0_CONF (1<<1) +#define SYS_CTRL_AP_ENABLE_AXI_VOC (1<<2) +#define SYS_CTRL_AP_ENABLE_AXI_VOC2 (1<<3) +#define SYS_CTRL_AP_ENABLE_AXI_DMA (1<<4) +#define SYS_CTRL_AP_ENABLE_AXI_ALWAYS (1<<5) +#define SYS_CTRL_AP_ENABLE_AXI_CONNECT (1<<6) +#define SYS_CTRL_AP_ENABLE_AXI_VPU (1<<7) +#define SYS_CTRL_AP_ENABLE_APB0_IRQ (1<<8) +#define SYS_CTRL_AP_ENABLE_CLK_AXI(n) (((n)&0x1FF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXI_MASK (0x1FF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXI_SHIFT (0) + +//Clk_AXI_Disable +#define SYS_CTRL_AP_DISABLE_AHB0_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB0_CONF (1<<1) +#define SYS_CTRL_AP_DISABLE_AXI_VOC (1<<2) +#define SYS_CTRL_AP_DISABLE_AXI_VOC2 (1<<3) +#define SYS_CTRL_AP_DISABLE_AXI_DMA (1<<4) +#define SYS_CTRL_AP_DISABLE_AXI_ALWAYS (1<<5) +#define SYS_CTRL_AP_DISABLE_AXI_CONNECT (1<<6) +#define SYS_CTRL_AP_DISABLE_AXI_VPU (1<<7) +#define SYS_CTRL_AP_DISABLE_APB0_IRQ (1<<8) +#define SYS_CTRL_AP_DISABLE_CLK_AXI(n) (((n)&0x1FF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXI_MASK (0x1FF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXI_SHIFT (0) + +//Clk_AXIDIV2_Mode +#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_MANUAL (1<<0) + +//Clk_AXIDIV2_Enable +#define SYS_CTRL_AP_ENABLE_AXIDIV2_IMEM (1<<0) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_ALWAYS (1<<1) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_CONNECT (1<<2) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_VPU (1<<3) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2(n) (((n)&15)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_MASK (15<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_SHIFT (0) + +//Clk_AXIDIV2_Disable +#define SYS_CTRL_AP_DISABLE_AXIDIV2_IMEM (1<<0) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_ALWAYS (1<<1) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_CONNECT (1<<2) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_VPU (1<<3) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2(n) (((n)&15)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_MASK (15<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_SHIFT (0) + +//Clk_GCG_Mode +#define SYS_CTRL_AP_MODE_GCG_APB_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_GCG_APB_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_GCG_GOUDA_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_GCG_CAMERA_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_GCG_CAMERA2_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_GCG_CAMERA2_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_CLK_GCG(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_MODE_CLK_GCG_MASK (0xF<<0) +#define SYS_CTRL_AP_MODE_CLK_GCG_SHIFT (0) + +//Clk_GCG_Enable +#define SYS_CTRL_AP_ENABLE_GCG_APB_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_GCG_GOUDA (1<<1) +#define SYS_CTRL_AP_ENABLE_GCG_CAMERA (1<<2) +#define SYS_CTRL_AP_ENABLE_GCG_CAMERA2 (1<<3) +#define SYS_CTRL_AP_ENABLE_GCG_ALWAYS (1<<4) +#define SYS_CTRL_AP_ENABLE_GCG_CONNECT (1<<5) +#define SYS_CTRL_AP_ENABLE_GCG_GOUDA_AW (1<<6) +#define SYS_CTRL_AP_ENABLE_GCG_GOUDA_DPI (1<<7) +#define SYS_CTRL_AP_ENABLE_CLK_GCG(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_GCG_MASK (0xFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_GCG_SHIFT (0) + +//Clk_GCG_Disable +#define SYS_CTRL_AP_DISABLE_GCG_APB_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_GCG_GOUDA (1<<1) +#define SYS_CTRL_AP_DISABLE_GCG_CAMERA (1<<2) +#define SYS_CTRL_AP_DISABLE_GCG_CAMERA2 (1<<3) +#define SYS_CTRL_AP_DISABLE_GCG_ALWAYS (1<<4) +#define SYS_CTRL_AP_DISABLE_GCG_CONNECT (1<<5) +#define SYS_CTRL_AP_DISABLE_GCG_GOUDA_AW (1<<6) +#define SYS_CTRL_AP_DISABLE_GCG_GOUDA_DPI (1<<7) +#define SYS_CTRL_AP_DISABLE_CLK_GCG(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_GCG_MASK (0xFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_GCG_SHIFT (0) + +//Clk_AHB1_Mode +#define SYS_CTRL_AP_MODE_CLK_AHB1_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_AHB1_MANUAL (1<<0) + +//Clk_AHB1_Enable +#define SYS_CTRL_AP_ENABLE_AHB1_USBC (1<<0) +#define SYS_CTRL_AP_ENABLE_AHB1_ALWAYS (1<<1) +#define SYS_CTRL_AP_ENABLE_AHB1_SPIFLASH (1<<2) +#define SYS_CTRL_AP_ENABLE_AHB1_EMAC (1<<3) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1_MASK (0xF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1_SHIFT (0) + +//Clk_AHB1_Disable +#define SYS_CTRL_AP_DISABLE_AHB1_USBC (1<<0) +#define SYS_CTRL_AP_DISABLE_AHB1_ALWAYS (1<<1) +#define SYS_CTRL_AP_DISABLE_AHB1_SPIFLASH (1<<2) +#define SYS_CTRL_AP_DISABLE_AHB1_EMAC (1<<3) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1_MASK (0xF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1_SHIFT (0) + +//Clk_APB1_Mode +#define SYS_CTRL_AP_MODE_APB1_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APB1_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB1_AIF_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB1_AIF_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APB1_AIF2_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APB1_AIF2_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APB1D_OSC_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APB1D_OSC_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_APB1D_OSC2_AUTOMATIC (0<<9) +#define SYS_CTRL_AP_MODE_APB1D_OSC2_MANUAL (1<<9) +#define SYS_CTRL_AP_MODE_APB1D_OSC3_AUTOMATIC (0<<10) +#define SYS_CTRL_AP_MODE_APB1D_OSC3_MANUAL (1<<10) +#define SYS_CTRL_AP_MODE_APB1D_PWM_AUTOMATIC (0<<11) +#define SYS_CTRL_AP_MODE_APB1D_PWM_MANUAL (1<<11) +#define SYS_CTRL_AP_MODE_CLK_APB1(n) (((n)&0xFFF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APB1_MASK (0xFFF<<0) +#define SYS_CTRL_AP_MODE_CLK_APB1_SHIFT (0) + +//Clk_APB1_Enable +#define SYS_CTRL_AP_ENABLE_APB1_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB1_AIF (1<<1) +#define SYS_CTRL_AP_ENABLE_APB1_AIF2 (1<<2) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC (1<<3) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH0 (1<<4) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH1 (1<<5) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH2 (1<<6) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH3 (1<<7) +#define SYS_CTRL_AP_ENABLE_APB1D_OSC (1<<8) +#define SYS_CTRL_AP_ENABLE_APB1D_OSC2 (1<<9) +#define SYS_CTRL_AP_ENABLE_APB1D_OSC3 (1<<10) +#define SYS_CTRL_AP_ENABLE_APB1D_PWM (1<<11) +#define SYS_CTRL_AP_ENABLE_APB1_ALWAYS (1<<12) +#define SYS_CTRL_AP_ENABLE_APB1_DAPLITE (1<<13) +#define SYS_CTRL_AP_ENABLE_APB1_TIMER (1<<14) +#define SYS_CTRL_AP_ENABLE_APB1_GPIO (1<<15) +#define SYS_CTRL_AP_ENABLE_CLK_APB1(n) (((n)&0xFFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB1_MASK (0xFFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB1_SHIFT (0) + +//Clk_APB1_Disable +#define SYS_CTRL_AP_DISABLE_APB1_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB1_AIF (1<<1) +#define SYS_CTRL_AP_DISABLE_APB1_AIF2 (1<<2) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC (1<<3) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH0 (1<<4) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH1 (1<<5) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH2 (1<<6) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH3 (1<<7) +#define SYS_CTRL_AP_DISABLE_APB1D_OSC (1<<8) +#define SYS_CTRL_AP_DISABLE_APB1D_OSC2 (1<<9) +#define SYS_CTRL_AP_DISABLE_APB1D_OSC3 (1<<10) +#define SYS_CTRL_AP_DISABLE_APB1D_PWM (1<<11) +#define SYS_CTRL_AP_DISABLE_APB1_ALWAYS (1<<12) +#define SYS_CTRL_AP_DISABLE_APB1_DAPLITE (1<<13) +#define SYS_CTRL_AP_DISABLE_APB1_TIMER (1<<14) +#define SYS_CTRL_AP_DISABLE_APB1_GPIO (1<<15) +#define SYS_CTRL_AP_DISABLE_CLK_APB1(n) (((n)&0xFFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB1_MASK (0xFFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB1_SHIFT (0) + +//Clk_APB2_Mode +#define SYS_CTRL_AP_MODE_APB2_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APB2_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB2_IFC_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB2_IFC_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_AUTOMATIC (0<<9) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_MANUAL (1<<9) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH8_AUTOMATIC (0<<10) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH8_MANUAL (1<<10) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH9_AUTOMATIC (0<<11) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH9_MANUAL (1<<11) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH10_AUTOMATIC (0<<12) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH10_MANUAL (1<<12) +#define SYS_CTRL_AP_MODE_APB2_UART1_AUTOMATIC (0<<13) +#define SYS_CTRL_AP_MODE_APB2_UART1_MANUAL (1<<13) +#define SYS_CTRL_AP_MODE_APB2_UART2_AUTOMATIC (0<<14) +#define SYS_CTRL_AP_MODE_APB2_UART2_MANUAL (1<<14) +#define SYS_CTRL_AP_MODE_APB2_UART3_AUTOMATIC (0<<15) +#define SYS_CTRL_AP_MODE_APB2_UART3_MANUAL (1<<15) +#define SYS_CTRL_AP_MODE_APB2_SPI1_AUTOMATIC (0<<16) +#define SYS_CTRL_AP_MODE_APB2_SPI1_MANUAL (1<<16) +#define SYS_CTRL_AP_MODE_APB2_SPI2_AUTOMATIC (0<<17) +#define SYS_CTRL_AP_MODE_APB2_SPI2_MANUAL (1<<17) +#define SYS_CTRL_AP_MODE_APB2_SPI3_AUTOMATIC (0<<18) +#define SYS_CTRL_AP_MODE_APB2_SPI3_MANUAL (1<<18) +#define SYS_CTRL_AP_MODE_APB2_SDMMC1_AUTOMATIC (0<<19) +#define SYS_CTRL_AP_MODE_APB2_SDMMC1_MANUAL (1<<19) +#define SYS_CTRL_AP_MODE_APB2_SDMMC2_AUTOMATIC (0<<20) +#define SYS_CTRL_AP_MODE_APB2_SDMMC2_MANUAL (1<<20) +#define SYS_CTRL_AP_MODE_APB2_SDMMC3_AUTOMATIC (0<<21) +#define SYS_CTRL_AP_MODE_APB2_SDMMC3_MANUAL (1<<21) +#define SYS_CTRL_AP_MODE_APB2_I2C1_AUTOMATIC (0<<22) +#define SYS_CTRL_AP_MODE_APB2_I2C1_MANUAL (1<<22) +#define SYS_CTRL_AP_MODE_APB2_I2C2_AUTOMATIC (0<<23) +#define SYS_CTRL_AP_MODE_APB2_I2C2_MANUAL (1<<23) +#define SYS_CTRL_AP_MODE_APB2_I2C3_AUTOMATIC (0<<24) +#define SYS_CTRL_AP_MODE_APB2_I2C3_MANUAL (1<<24) +#define SYS_CTRL_AP_MODE_CLK_APB2(n) (((n)&0x1FFFFFF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APB2_MASK (0x1FFFFFF<<0) +#define SYS_CTRL_AP_MODE_CLK_APB2_SHIFT (0) + +//Clk_APB2_Enable +#define SYS_CTRL_AP_ENABLE_APB2_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB2_IFC (1<<1) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH0 (1<<2) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH1 (1<<3) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH2 (1<<4) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH3 (1<<5) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH4 (1<<6) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH5 (1<<7) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH6 (1<<8) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH7 (1<<9) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH8 (1<<10) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH9 (1<<11) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH10 (1<<12) +#define SYS_CTRL_AP_ENABLE_APB2_UART1 (1<<13) +#define SYS_CTRL_AP_ENABLE_APB2_UART2 (1<<14) +#define SYS_CTRL_AP_ENABLE_APB2_UART3 (1<<15) +#define SYS_CTRL_AP_ENABLE_APB2_SPI1 (1<<16) +#define SYS_CTRL_AP_ENABLE_APB2_SPI2 (1<<17) +#define SYS_CTRL_AP_ENABLE_APB2_SPI3 (1<<18) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC1 (1<<19) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC2 (1<<20) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC3 (1<<21) +#define SYS_CTRL_AP_ENABLE_APB2_I2C1 (1<<22) +#define SYS_CTRL_AP_ENABLE_APB2_I2C2 (1<<23) +#define SYS_CTRL_AP_ENABLE_APB2_I2C3 (1<<24) +#define SYS_CTRL_AP_ENABLE_APB2_ALWAYS (1<<25) +#define SYS_CTRL_AP_ENABLE_APB2_NANDFLASH (1<<26) +#define SYS_CTRL_AP_ENABLE_CLK_APB2(n) (((n)&0x7FFFFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB2_MASK (0x7FFFFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB2_SHIFT (0) + +//Clk_APB2_Disable +#define SYS_CTRL_AP_DISABLE_APB2_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB2_IFC (1<<1) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH0 (1<<2) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH1 (1<<3) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH2 (1<<4) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH3 (1<<5) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH4 (1<<6) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH5 (1<<7) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH6 (1<<8) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH7 (1<<9) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH8 (1<<10) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH9 (1<<11) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH10 (1<<12) +#define SYS_CTRL_AP_DISABLE_APB2_UART1 (1<<13) +#define SYS_CTRL_AP_DISABLE_APB2_UART2 (1<<14) +#define SYS_CTRL_AP_DISABLE_APB2_UART3 (1<<15) +#define SYS_CTRL_AP_DISABLE_APB2_SPI1 (1<<16) +#define SYS_CTRL_AP_DISABLE_APB2_SPI2 (1<<17) +#define SYS_CTRL_AP_DISABLE_APB2_SPI3 (1<<18) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC1 (1<<19) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC2 (1<<20) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC3 (1<<21) +#define SYS_CTRL_AP_DISABLE_APB2_I2C1 (1<<22) +#define SYS_CTRL_AP_DISABLE_APB2_I2C2 (1<<23) +#define SYS_CTRL_AP_DISABLE_APB2_I2C3 (1<<24) +#define SYS_CTRL_AP_DISABLE_APB2_ALWAYS (1<<25) +#define SYS_CTRL_AP_DISABLE_APB2_NANDFLASH (1<<26) +#define SYS_CTRL_AP_DISABLE_CLK_APB2(n) (((n)&0x7FFFFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB2_MASK (0x7FFFFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB2_SHIFT (0) + +//Clk_MEM_Mode +#define SYS_CTRL_AP_MODE_CLK_MEM_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_MEM_MANUAL (1<<0) + +//Clk_MEM_Enable +#define SYS_CTRL_AP_ENABLE_MEM_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_MEM_DMC (1<<1) +#define SYS_CTRL_AP_ENABLE_MEM_DDRPHY_P (1<<2) +#define SYS_CTRL_AP_ENABLE_MEM_CONNECT (1<<3) +#define SYS_CTRL_AP_ENABLE_CLK_MEM(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_MEM_MASK (0xF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_MEM_SHIFT (0) + +//Clk_MEM_Disable +#define SYS_CTRL_AP_DISABLE_MEM_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_MEM_DMC (1<<1) +#define SYS_CTRL_AP_DISABLE_MEM_DDRPHY_P (1<<2) +#define SYS_CTRL_AP_DISABLE_MEM_CONNECT (1<<3) +#define SYS_CTRL_AP_DISABLE_CLK_MEM(n) (((n)&0xF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_MEM_MASK (0xF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_MEM_SHIFT (0) + +//Clk_APO_Mode +#define SYS_CTRL_AP_MODE_APOC_BCK_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APOC_BCK_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APOC_BCK2_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APOC_BCK2_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APOC_UART1_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APOC_UART1_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APOC_UART2_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APOC_UART2_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APOC_UART3_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APOC_UART3_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APOC_VOC_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APOC_VOC_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APOC_VOC2_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APOC_VOC2_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_CLK_APO(n) (((n)&01FF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APO_MASK (0x1FF<<0) +#define SYS_CTRL_AP_MODE_CLK_APO_SHIFT (0) + +//Clk_APO_Enable +#define SYS_CTRL_AP_ENABLE_APOC_BCK (1<<0) +#define SYS_CTRL_AP_ENABLE_APOC_BCK2 (1<<1) +#define SYS_CTRL_AP_ENABLE_APOC_UART1 (1<<2) +#define SYS_CTRL_AP_ENABLE_APOC_UART2 (1<<3) +#define SYS_CTRL_AP_ENABLE_APOC_UART3 (1<<4) +#define SYS_CTRL_AP_ENABLE_APOC_VOC_CORE (1<<5) +#define SYS_CTRL_AP_ENABLE_APOC_VOC2_CORE (1<<6) +#define SYS_CTRL_AP_ENABLE_APOC_VOC (1<<7) +#define SYS_CTRL_AP_ENABLE_APOC_VOC2 (1<<8) +#define SYS_CTRL_AP_ENABLE_APOC_VOC_ALWAYS (1<<9) +#define SYS_CTRL_AP_ENABLE_APOC_VOC2_ALWAYS (1<<10) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY_N (1<<11) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XP (1<<12) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XN (1<<13) +#define SYS_CTRL_AP_ENABLE_APOC_VPU (1<<14) +#define SYS_CTRL_AP_ENABLE_APOC_GPU (1<<15) +#define SYS_CTRL_AP_ENABLE_APOC_USBPHY (1<<16) +#define SYS_CTRL_AP_ENABLE_APOC_CSI (1<<17) +#define SYS_CTRL_AP_ENABLE_APOC_CSI2 (1<<18) +#define SYS_CTRL_AP_ENABLE_APOC_DSI (1<<19) +#define SYS_CTRL_AP_ENABLE_APOC_GPIO (1<<20) +#define SYS_CTRL_AP_ENABLE_APOC_SPIFLASH (1<<21) +#define SYS_CTRL_AP_ENABLE_APOC_PIX (1<<22) +#define SYS_CTRL_AP_ENABLE_APOC_PIX2 (1<<23) +#define SYS_CTRL_AP_ENABLE_APOC_PDGB (1<<24) +#define SYS_CTRL_AP_ENABLE_CLK_APO(n) (((n)&0x1FFFFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APO_MASK (0x1FFFFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APO_SHIFT (0) + +//Clk_APO_Disable +#define SYS_CTRL_AP_DISABLE_APOC_BCK (1<<0) +#define SYS_CTRL_AP_DISABLE_APOC_BCK2 (1<<1) +#define SYS_CTRL_AP_DISABLE_APOC_UART1 (1<<2) +#define SYS_CTRL_AP_DISABLE_APOC_UART2 (1<<3) +#define SYS_CTRL_AP_DISABLE_APOC_UART3 (1<<4) +#define SYS_CTRL_AP_DISABLE_APOC_VOC_CORE (1<<5) +#define SYS_CTRL_AP_DISABLE_APOC_VOC2_CORE (1<<6) +#define SYS_CTRL_AP_DISABLE_APOC_VOC (1<<7) +#define SYS_CTRL_AP_DISABLE_APOC_VOC2 (1<<8) +#define SYS_CTRL_AP_DISABLE_APOC_VOC_ALWAYS (1<<9) +#define SYS_CTRL_AP_DISABLE_APOC_VOC2_ALWAYS (1<<10) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY_N (1<<11) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XP (1<<12) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XN (1<<13) +#define SYS_CTRL_AP_DISABLE_APOC_VPU (1<<14) +#define SYS_CTRL_AP_DISABLE_APOC_GPU (1<<15) +#define SYS_CTRL_AP_DISABLE_APOC_USBPHY (1<<16) +#define SYS_CTRL_AP_DISABLE_APOC_CSI (1<<17) +#define SYS_CTRL_AP_DISABLE_APOC_CSI2 (1<<18) +#define SYS_CTRL_AP_DISABLE_APOC_DSI (1<<19) +#define SYS_CTRL_AP_DISABLE_APOC_GPIO (1<<20) +#define SYS_CTRL_AP_DISABLE_APOC_SPIFLASH (1<<21) +#define SYS_CTRL_AP_DISABLE_APOC_PIX (1<<22) +#define SYS_CTRL_AP_DISABLE_APOC_PIX2 (1<<23) +#define SYS_CTRL_AP_DISABLE_APOC_PDGB (1<<24) +#define SYS_CTRL_AP_DISABLE_CLK_APO(n) (((n)&0x1FFFFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APO_MASK (0x1FFFFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APO_SHIFT (0) + +//Cfg_Clk_AP_CPU +#define SYS_CTRL_AP_AP_CPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_CPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_BUS_DIV_SEL(n) (((n)&3)<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_MASK (3<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_SHIFT (16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV2 (0<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV3 (1<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV4 (2<<16) +#define SYS_CTRL_AP_DBG_CLKDIV_SEL(n) (((n)&15)<<20) +#define SYS_CTRL_AP_DBG_CLKDIV_DIV_SEL_MASK (15<<20) +#define SYS_CTRL_AP_DBG_CLKDIV_SEL_SHIFT (20) +#define SYS_CTRL_AP_AP_CPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_AXI +#define SYS_CTRL_AP_AP_AXI_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_AXI_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_AXI_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_AXI_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_GCG +#define SYS_CTRL_AP_AP_GCG_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_GCG_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_GCG_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_GCG_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_AHB1 +#define SYS_CTRL_AP_AP_AHB1_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_AHB1_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_AHB1_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_APB1 +#define SYS_CTRL_AP_AP_APB1_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_APB1_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_APB1_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_APB1_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_APB2 +#define SYS_CTRL_AP_AP_APB2_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_APB2_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_APB2_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_APB2_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_MEM +#define SYS_CTRL_AP_AP_MEM_SRC_DIV2 (1<<12) + +//Cfg_Clk_AP_GPU +#define SYS_CTRL_AP_AP_GPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_GPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_GPU_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_GPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_VPU +#define SYS_CTRL_AP_AP_VPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_VPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_VPU_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_VPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_VOC +#define SYS_CTRL_AP_AP_VOC_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_SFLSH +#define SYS_CTRL_AP_AP_SFLSH_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_SFLSH_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_SFLSH_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_Uart +#define SYS_CTRL_AP_UART_DIVIDER(n) (((n)&0x3FF)<<0) +#define SYS_CTRL_AP_UART_DIVIDER_MASK (0x3FF<<0) +#define SYS_CTRL_AP_UART_DIVIDER_SHIFT (0) +#define SYS_CTRL_AP_UART_SEL_PLL_SLOW (0<<12) +#define SYS_CTRL_AP_UART_SEL_PLL_PLL (1<<12) + +//L2cc_Ctrl +#define SYS_CTRL_AP_ARQOS_L2CC_1_M(n) (((n)&15)<<0) +#define SYS_CTRL_AP_ARQOS_L2CC_1_M_MASK (15<<0) +#define SYS_CTRL_AP_ARQOS_L2CC_1_M_SHIFT (0) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M(n) (((n)&15)<<4) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M_MASK (15<<4) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M_SHIFT (4) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<8) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_MASK (15<<8) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_SHIFT (8) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<12) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_MASK (15<<12) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_SHIFT (12) +#define SYS_CTRL_AP_ARAP_L2CC_1_M (1<<16) +#define SYS_CTRL_AP_AWAP_L2CC_1_M (1<<17) +#define SYS_CTRL_AP_ARAP_MODEM_MEM_AHBS_M (1<<18) +#define SYS_CTRL_AP_AWAP_MODEM_MEM_AHBS_M (1<<19) +#define SYS_CTRL_AP_ARAP_MERGE1M (1<<20) +#define SYS_CTRL_AP_AWAP_MERGE1M (1<<21) +#define SYS_CTRL_AP_ARAP_MERGE2M (1<<22) +#define SYS_CTRL_AP_AWAP_MERGE2M (1<<23) +#define SYS_CTRL_AP_RESERVE1(n) (((n)&0xFF)<<24) +#define SYS_CTRL_AP_RESERVE1_MASK (0xFF<<24) +#define SYS_CTRL_AP_RESERVE1_SHIFT (24) + +//Spi_Ctrl +#define SYS_CTRL_AP_LIMITED_EN_SPI1 (1<<0) +#define SYS_CTRL_AP_LPSEN_SPI1 (1<<1) +#define SYS_CTRL_AP_LIMITED_EN_SPI2 (1<<2) +#define SYS_CTRL_AP_LPSEN_SPI2 (1<<3) +#define SYS_CTRL_AP_LIMITED_EN_SPI3 (1<<4) +#define SYS_CTRL_AP_LPSEN_SPI3 (1<<5) +#define SYS_CTRL_AP_FBUSWID_NFSC (1<<6) +#define SYS_CTRL_AP_RESERVE3 (1<<7) +#define SYS_CTRL_AP_DMC_CFG(n) (((n)&0x3FF)<<8) +#define SYS_CTRL_AP_DMC_CFG_MASK (0x3FF<<8) +#define SYS_CTRL_AP_DMC_CFG_SHIFT (8) +#define SYS_CTRL_AP_RESERVE2(n) (((n)&0x3FFF)<<18) +#define SYS_CTRL_AP_RESERVE2_MASK (0x3FFF<<18) +#define SYS_CTRL_AP_RESERVE2_SHIFT (18) + +//Memory_Margin +#define SYS_CTRL_AP_EMAW_VOC(n) (((n)&3)<<0) +#define SYS_CTRL_AP_EMAW_VOC_MASK (3<<0) +#define SYS_CTRL_AP_EMAW_VOC_SHIFT (0) +#define SYS_CTRL_AP_EMA_VOC(n) (((n)&7)<<2) +#define SYS_CTRL_AP_EMA_VOC_MASK (7<<2) +#define SYS_CTRL_AP_EMA_VOC_SHIFT (2) +#define SYS_CTRL_AP_EMAW_VPU(n) (((n)&3)<<5) +#define SYS_CTRL_AP_EMAW_VPU_MASK (3<<5) +#define SYS_CTRL_AP_EMAW_VPU_SHIFT (5) +#define SYS_CTRL_AP_EMA_VPU(n) (((n)&7)<<7) +#define SYS_CTRL_AP_EMA_VPU_MASK (7<<7) +#define SYS_CTRL_AP_EMA_VPU_SHIFT (7) +#define SYS_CTRL_AP_EMAW_GPU(n) (((n)&3)<<10) +#define SYS_CTRL_AP_EMAW_GPU_MASK (3<<10) +#define SYS_CTRL_AP_EMAW_GPU_SHIFT (10) +#define SYS_CTRL_AP_EMA_GPU(n) (((n)&7)<<12) +#define SYS_CTRL_AP_EMA_GPU_MASK (7<<12) +#define SYS_CTRL_AP_EMA_GPU_SHIFT (12) +#define SYS_CTRL_AP_EMAW_GOUDA(n) (((n)&3)<<15) +#define SYS_CTRL_AP_EMAW_GOUDA_MASK (3<<15) +#define SYS_CTRL_AP_EMAW_GOUDA_SHIFT (15) +#define SYS_CTRL_AP_EMA_GOUDA(n) (((n)&7)<<17) +#define SYS_CTRL_AP_EMA_GOUDA_MASK (7<<17) +#define SYS_CTRL_AP_EMA_GOUDA_SHIFT (17) +#define SYS_CTRL_AP_EMAW_IMEM(n) (((n)&3)<<20) +#define SYS_CTRL_AP_EMAW_IMEM_MASK (3<<20) +#define SYS_CTRL_AP_EMAW_IMEM_SHIFT (20) +#define SYS_CTRL_AP_EMA_IMEM(n) (((n)&7)<<22) +#define SYS_CTRL_AP_EMA_IMEM_MASK (7<<22) +#define SYS_CTRL_AP_EMA_IMEM_SHIFT (22) +#define SYS_CTRL_AP_EMAW_USB(n) (((n)&3)<<25) +#define SYS_CTRL_AP_EMAW_USB_MASK (3<<25) +#define SYS_CTRL_AP_EMAW_USB_SHIFT (25) +#define SYS_CTRL_AP_EMA_USB(n) (((n)&7)<<27) +#define SYS_CTRL_AP_EMA_USB_MASK (7<<27) +#define SYS_CTRL_AP_EMA_USB_SHIFT (27) + +//Memory_Margin2 +#define SYS_CTRL_AP_EMAW_NFSC(n) (((n)&3)<<0) +#define SYS_CTRL_AP_EMAW_NFSC_MASK (3<<0) +#define SYS_CTRL_AP_EMAW_NFSC_SHIFT (0) +#define SYS_CTRL_AP_EMA_NFSC(n) (((n)&7)<<2) +#define SYS_CTRL_AP_EMA_NFSC_MASK (7<<2) +#define SYS_CTRL_AP_EMA_NFSC_SHIFT (2) +#define SYS_CTRL_AP_EMA_VPUROM(n) (((n)&7)<<5) +#define SYS_CTRL_AP_EMA_VPUROM_MASK (7<<5) +#define SYS_CTRL_AP_EMA_VPUROM_SHIFT (5) +#define SYS_CTRL_AP_EMA_IMEMROM(n) (((n)&7)<<8) +#define SYS_CTRL_AP_EMA_IMEMROM_MASK (7<<8) +#define SYS_CTRL_AP_EMA_IMEMROM_SHIFT (8) +#define SYS_CTRL_AP_KEN_VPUROM (1<<11) +#define SYS_CTRL_AP_PGEN_VPUROM (1<<12) +#define SYS_CTRL_AP_KEN_IMEMROM (1<<13) +#define SYS_CTRL_AP_PGEN_IMEMROM (1<<14) + +//Memory_Observe +#define SYS_CTRL_AP_MEM_OBSERVE(n) (((n)&0xFFFFFFFF)<<0) + +//Cfg_Clk_AP_VOC2 +#define SYS_CTRL_AP_AP_VOC2_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_VOC2_FREQ_MASK (31 << 0) +#define SYS_CTRL_AP_AP_VOC2_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_VOC2_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_VOC2_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_EMMC +#define SYS_CTRL_AP_EMMC_DATA_STB_DLY(n) (((n)&31)<<0) +#define SYS_CTRL_AP_EMMC_DATA_STB_DLY_MASK (31 << 0) +#define SYS_CTRL_AP_EMMC_DATA_STB_DLY_SHIFT 0 +#define SYS_CTRL_AP_EMMC_CLK_DLY(n) (((n)&31)<<8) +#define SYS_CTRL_AP_EMMC_CLK_DLY_MASK (31 << 8) +#define SYS_CTRL_AP_EMMC_CLK_DLY_SHIFT 8 +#define SYS_CTRL_AP_EMMC_CLK_POL (1<<13) + +//Test_Pulse +#define SYS_CTRL_AP_PULSE_COUNTER(n) (((n)&0xFFFFFFFF)<<0) + +//Cfg_Reserve +#define SYS_CTRL_AP_RESERVE(n) (((n)&0xFFFFFFFF)<<0) + +#endif diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8850.h b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8850.h new file mode 100644 index 0000000000..6b0169fc89 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8850.h @@ -0,0 +1,1540 @@ +#ifndef _REG_SYSCTRL_H_
+#define _REG_SYSCTRL_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+// MACROS
+// =============================================================================
+
+// ============================================================================
+// AP_CPU_ID_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// CPU IDs
+ CPU0 = 0x00000000,
+ CPU1 = 0x00000001
+} AP_CPU_ID_T;
+
+
+// ============================================================================
+// CPU_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP CPU side System clocks
+ CPU_CORE = 0x00000000,
+/// the following don't have an auto enable
+ CPU_DUMMY = 0x00000001
+} CPU_CLKS_T;
+
+#define NB_CPU_CLK_AEN (1)
+#define NB_CPU_CLK_EN (2)
+#define NB_CPU_CLK (2)
+
+// ============================================================================
+// AXI_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP AXI side System clocks: AXI and AHB0 and APB0
+ AHB0_CONF = 0x00000000,
+ APB0_CONF = 0x00000001,
+ AXI_VOC = 0x00000002,
+ AXI_VOC2 = 0x00000003,
+ AXI_DMA = 0x00000004,
+/// the following don't have an auto enable
+ AXI_ALWAYS = 0x00000005,
+ AXI_CONNECT = 0x00000006,
+ APB0_IRQ = 0x00000007
+} AXI_CLKS_T;
+
+#define NB_AXI_CLK_AEN (5)
+#define NB_AXI_CLK_EN (8)
+#define NB_AXI_CLK (8)
+
+// ============================================================================
+// AXIDIV2_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP AXIdiv2 side System clocks
+ AXIDIV2_IMEM = 0x00000000,
+/// the following don't have an auto enable
+ AXIDIV2_ALWAYS = 0x00000001,
+ AXIDIV2_CONNECT = 0x00000002,
+ AXIDIV2_VPU = 0x00000003
+} AXIDIV2_CLKS_T;
+
+#define NB_AXIDIV2_CLK_AEN (1)
+#define NB_AXIDIV2_CLK_EN (4)
+#define NB_AXIDIV2_CLK (4)
+
+// ============================================================================
+// GCG_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GCG side System clocks
+ GCG_APB_CONF = 0x00000000,
+ GCG_GOUDA = 0x00000001,
+ GCG_CAMERA = 0x00000002,
+/// the following don't have an auto enable
+ GCG_ALWAYS = 0x00000003,
+ GCG_CONNECT = 0x00000004
+} GCG_CLKS_T;
+
+#define NB_GCG_CLK_AEN (3)
+#define NB_GCG_CLK_EN (5)
+#define NB_GCG_CLK (5)
+
+// ============================================================================
+// AHB1_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP AHB1 side System clocks
+ AHB1_USBC = 0x00000000,
+/// the following don't have an auto enable
+ AHB1_ALWAYS = 0x00000001,
+ AHB1_SPIFLASH = 0x00000002
+} AHB1_CLKS_T;
+
+#define NB_AHB1_CLK_AEN (1)
+#define NB_AHB1_CLK_EN (3)
+#define NB_AHB1_CLK (3)
+
+// ============================================================================
+// APB1_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP APB1 side System clocks
+ APB1_CONF = 0x00000000,
+ APB1_AIF = 0x00000001,
+ APB1_AIF2 = 0x00000002,
+ APB1_AUIFC = 0x00000003,
+ APB1_AUIFC_CH0 = 0x00000004,
+ APB1_AUIFC_CH1 = 0x00000005,
+ APB1_AUIFC_CH2 = 0x00000006,
+ APB1_AUIFC_CH3 = 0x00000007,
+ APB1_I2C1 = 0x00000008,
+ APB1_I2C2 = 0x00000009,
+ APB1_I2C3 = 0x0000000A,
+/// AP APB1 side divided clock (either divided by module or by clock_ctrl)
+ APB1D_OSC = 0x0000000B,
+ APB1D_PWM = 0x0000000C,
+/// the following don't have an auto enable
+ APB1_ALWAYS = 0x0000000D,
+ APB1_DAPLITE = 0x0000000E,
+ APB1_TIMER = 0x0000000F,
+ APB1_GPIO = 0x00000010
+} APB1_CLKS_T;
+
+#define NB_APB1_CLK_AEN (13)
+#define NB_APB1_CLK_EN (17)
+#define NB_APB1_CLK (17)
+
+// ============================================================================
+// APB2_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP APB2 side System clocks
+ APB2_CONF = 0x00000000,
+ APB2_IFC = 0x00000001,
+ APB2_IFC_CH0 = 0x00000002,
+ APB2_IFC_CH1 = 0x00000003,
+ APB2_IFC_CH2 = 0x00000004,
+ APB2_IFC_CH3 = 0x00000005,
+ APB2_IFC_CH4 = 0x00000006,
+ APB2_IFC_CH5 = 0x00000007,
+ APB2_IFC_CH6 = 0x00000008,
+ APB2_IFC_CH7 = 0x00000009,
+ APB2_UART1 = 0x0000000A,
+ APB2_UART2 = 0x0000000B,
+ APB2_UART3 = 0x0000000C,
+ APB2_SPI1 = 0x0000000D,
+ APB2_SPI2 = 0x0000000E,
+ APB2_SPI3 = 0x0000000F,
+ APB2_SDMMC1 = 0x00000010,
+ APB2_SDMMC2 = 0x00000011,
+ APB2_SDMMC3 = 0x00000012,
+/// the following don't have an auto enable
+ APB2_ALWAYS = 0x00000013,
+ APB2_NANDFLASH = 0x00000014
+} APB2_CLKS_T;
+
+#define NB_APB2_CLK_AEN (19)
+#define NB_APB2_CLK_EN (21)
+#define NB_APB2_CLK (21)
+
+// ============================================================================
+// MEM_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP MEM side System clocks
+ MEM_CONF = 0x00000000,
+/// the following don't have an auto enable
+ MEM_DMC = 0x00000001,
+ MEM_GPU = 0x00000002,
+ MEM_VPU = 0x00000003,
+ MEM_DDRPHY_P = 0x00000004,
+ MEM_CONNECT = 0x00000005
+} MEM_CLKS_T;
+
+#define NB_MEM_CLK_AEN (1)
+#define NB_MEM_CLK_EN (6)
+#define NB_MEM_CLK (6)
+
+// ============================================================================
+// APO_CLKS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP side Other clocks
+/// clocks with auto enble
+ APOC_VPU = 0x00000000,
+ APOC_BCK = 0x00000001,
+ APOC_BCK2 = 0x00000002,
+ APOC_UART1 = 0x00000003,
+ APOC_UART2 = 0x00000004,
+ APOC_UART3 = 0x00000005,
+ APOC_VOC_CORE = 0x00000006,
+ APOC_VOC2_CORE = 0x00000007,
+ APOC_VOC = 0x00000008,
+ APOC_VOC2 = 0x00000009,
+/// the following don't have an auto enable
+ APOC_VOC_ALWAYS = 0x0000000A,
+ APOC_VOC2_ALWAYS = 0x0000000B,
+ APOC_DDRPHY_N = 0x0000000C,
+ APOC_DDRPHY2XP = 0x0000000D,
+ APOC_DDRPHY2XN = 0x0000000E,
+ APOC_GPU = 0x0000000F,
+ APOC_USBPHY = 0x00000010,
+ APOC_CSI = 0x00000011,
+ APOC_DSI = 0x00000012,
+ APOC_GPIO = 0x00000013,
+ APOC_SPIFLASH = 0x00000014,
+ APOC_PIX = 0x00000015,
+ APOC_PDGB = 0x00000016
+} APO_CLKS_T;
+
+#define NB_CLK_VOC_AEN_SYNC (6)
+#define NB_CLK_VOC_CORE (8)
+#define NB_APO_CLK_AEN (10)
+#define NB_CLK_VOC_END (12)
+#define NB_APO_CLK_EN (23)
+#define NB_APO_CLK (23)
+
+// ============================================================================
+// CPU_RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP CPU side resets
+ CPU_RST_CORE = 0x00000000,
+ CPU_RST_SYS = 0x00000001
+} CPU_RESETS_T;
+
+#define NB_CPU_RST (2)
+
+// ============================================================================
+// AXI_RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP AXI side resets: AXI and AHB0 and APB0
+ AXI_RST_VOC = 0x00000000,
+ AXI_RST_VOC2 = 0x00000001,
+ AXI_RST_DMA = 0x00000002,
+ AXI_RST_SYS = 0x00000003,
+ AXI_RST_CONNECT = 0x00000004,
+ AHB0_RST_GPU = 0x00000005,
+ APB0_RST_VPU = 0x00000006,
+ APB0_RST_IRQ = 0x00000007
+} AXI_RESETS_T;
+
+#define NB_AXI_RST (8)
+
+// ============================================================================
+// AXIDIV2_RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP AXIDIV2 side resets
+ AXIDIV2_RST_IMEM = 0x00000000,
+ AXIDIV2_RST_SYS = 0x00000001,
+ AXIDIV2_RST_VPU = 0x00000002
+} AXIDIV2_RESETS_T;
+
+#define NB_AXIDIV2_RST (3)
+
+// ============================================================================
+// GCG_RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GCG side resets
+ GCG_RST_SYS = 0x00000000,
+ GCG_RST_GOUDA = 0x00000001,
+ GCG_RST_CAMERA = 0x00000002
+} GCG_RESETS_T;
+
+#define NB_GCG_RST (3)
+
+// ============================================================================
+// AHB1_RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP AHB1 side resets
+ AHB1_RST_SYS = 0x00000000,
+ AHB1_RST_USBC = 0x00000001,
+ AHB1_RST_SPIFLASH = 0x00000002
+} AHB1_RESETS_T;
+
+#define NB_AHB1_RST (3)
+
+// ============================================================================
+// APB1_RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP APB1 side resets
+ APB1_RST_SYS = 0x00000000,
+ APB1_RST_TIMER = 0x00000001,
+ APB1_RST_KEYPAD = 0x00000002,
+ APB1_RST_GPIO = 0x00000003,
+ APB1_RST_PWM = 0x00000004,
+ APB1_RST_AIF = 0x00000005,
+ APB1_RST_AIF2 = 0x00000006,
+ APB1_RST_AUIFC = 0x00000007,
+ APB1_RST_I2C1 = 0x00000008,
+ APB1_RST_I2C2 = 0x00000009,
+ APB1_RST_I2C3 = 0x0000000A,
+ APB1_RST_COM_REGS = 0x0000000B,
+ APB1_RST_DMC = 0x0000000C,
+ APB1_RST_DDRPHY_P = 0x0000000D,
+ APB1_RST_BB2G_XCPU = 0x0000000E,
+ APB1_RST_BB2G_BCPU = 0x0000000F,
+ APB1_RST_BB2G_AHBC = 0x00000010,
+ APB1_RST_BB2G_DMA = 0x00000011,
+ APB1_RST_BB2G_A2A = 0x00000012,
+ APB1_RST_BB2G_XIFC = 0x00000013,
+ APB1_RST_BB2G_BIFC = 0x00000014,
+ APB1_RST_BB2G_BAHBC = 0x00000015,
+ APB1_RST_BB2G_MEM_BRIDGE = 0x00000016
+} APB1_RESETS_T;
+
+#define NB_APB1_RST (23)
+
+// ============================================================================
+// APB2_RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP APB2 side resets
+ APB2_RST_SYS = 0x00000000,
+ APB2_RST_IFC = 0x00000001,
+ APB2_RST_UART1 = 0x00000002,
+ APB2_RST_UART2 = 0x00000003,
+ APB2_RST_UART3 = 0x00000004,
+ APB2_RST_SPI1 = 0x00000005,
+ APB2_RST_SPI2 = 0x00000006,
+ APB2_RST_SPI3 = 0x00000007,
+ APB2_RST_SDMMC1 = 0x00000008,
+ APB2_RST_SDMMC2 = 0x00000009,
+ APB2_RST_SDMMC3 = 0x0000000A,
+ APB2_RST_NANDFLASH = 0x0000000B
+} APB2_RESETS_T;
+
+#define NB_APB2_RST (12)
+
+// ============================================================================
+// MEM_RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP MEM side resets
+ MEM_RST_SYS = 0x00000000,
+ MEM_RST_GPU = 0x00000001,
+ MEM_RST_VPU = 0x00000002,
+ MEM_RST_DMC = 0x00000003,
+ MEM_RST_DDRPHY_P = 0x00000004
+} MEM_RESETS_T;
+
+#define NB_MEM_RST (5)
+
+// ============================================================================
+// AP_OTHERS_RESETS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP Reset Other : resync on corresponding clock other
+ AP_RSTO_VOC = 0x00000000,
+ AP_RSTO_VOC2 = 0x00000001,
+ AP_RSTO_DDRPHY_N = 0x00000002,
+ AP_RSTO_DDRPHY2XP = 0x00000003,
+ AP_RSTO_DDRPHY2XN = 0x00000004,
+ AP_RSTO_GPU = 0x00000005,
+ AP_RSTO_VPU = 0x00000006,
+ AP_RSTO_BCK = 0x00000007,
+ AP_RSTO_BCK2 = 0x00000008,
+ AP_RSTO_UART1 = 0x00000009,
+ AP_RSTO_UART2 = 0x0000000A,
+ AP_RSTO_UART3 = 0x0000000B,
+ AP_RSTO_GPIO = 0x0000000C,
+ AP_RSTO_TIMER = 0x0000000D,
+ AP_RSTO_USBC = 0x0000000E,
+ AP_RSTO_DSI = 0x0000000F,
+ AP_RSTO_SPIFLASH = 0x00000010,
+ AP_RSTO_TCK = 0x00000011,
+ AP_RSTO_PDBG_XTAL = 0x00000012
+} AP_OTHERS_RESETS_T;
+
+#define NB_AP_RSTO (19)
+/// For REG_DBG protect lock/unlock value
+#define AP_CTRL_PROTECT_LOCK (0XA50000)
+#define AP_CTRL_PROTECT_UNLOCK (0XA50001)
+
+// =============================================================================
+// TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_CTRL_AP_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef volatile struct
+{
+ /// <strong>This register is used to Lock and Unlock the protected registers.</strong>
+ REG32 REG_DBG; //0x00000000
+ /// Register protected by Write_Unlocked_H.
+ REG32 Cfg_Pll_Ctrl[4]; //0x00000004
+ /// This register is protected.
+ REG32 Sel_Clock; //0x00000014
+ REG32 Reset_Cause; //0x00000018
+ /// This register is protected.
+ REG32 CPU_Rst_Set; //0x0000001C
+ REG32 CPU_Rst_Clr; //0x00000020
+ /// This register is protected.
+ REG32 AXI_Rst_Set; //0x00000024
+ REG32 AXI_Rst_Clr; //0x00000028
+ /// This register is protected.
+ REG32 AXIDIV2_Rst_Set; //0x0000002C
+ REG32 AXIDIV2_Rst_Clr; //0x00000030
+ /// This register is protected.
+ REG32 GCG_Rst_Set; //0x00000034
+ REG32 GCG_Rst_Clr; //0x00000038
+ /// This register is protected.
+ REG32 AHB1_Rst_Set; //0x0000003C
+ REG32 AHB1_Rst_Clr; //0x00000040
+ /// This register is protected.
+ REG32 APB1_Rst_Set; //0x00000044
+ REG32 APB1_Rst_Clr; //0x00000048
+ /// This register is protected.
+ REG32 APB2_Rst_Set; //0x0000004C
+ REG32 APB2_Rst_Clr; //0x00000050
+ /// This register is protected.
+ REG32 MEM_Rst_Set; //0x00000054
+ REG32 MEM_Rst_Clr; //0x00000058
+ REG32 Clk_CPU_Mode; //0x0000005C
+ REG32 Clk_CPU_Enable; //0x00000060
+ /// This register is protected.
+ REG32 Clk_CPU_Disable; //0x00000064
+ REG32 Clk_AXI_Mode; //0x00000068
+ REG32 Clk_AXI_Enable; //0x0000006C
+ /// This register is protected.
+ REG32 Clk_AXI_Disable; //0x00000070
+ REG32 Clk_AXIDIV2_Mode; //0x00000074
+ REG32 Clk_AXIDIV2_Enable; //0x00000078
+ /// This register is protected.
+ REG32 Clk_AXIDIV2_Disable; //0x0000007C
+ REG32 Clk_GCG_Mode; //0x00000080
+ REG32 Clk_GCG_Enable; //0x00000084
+ /// This register is protected.
+ REG32 Clk_GCG_Disable; //0x00000088
+ REG32 Clk_AHB1_Mode; //0x0000008C
+ REG32 Clk_AHB1_Enable; //0x00000090
+ /// This register is protected.
+ REG32 Clk_AHB1_Disable; //0x00000094
+ REG32 Clk_APB1_Mode; //0x00000098
+ REG32 Clk_APB1_Enable; //0x0000009C
+ /// This register is protected.
+ REG32 Clk_APB1_Disable; //0x000000A0
+ REG32 Clk_APB2_Mode; //0x000000A4
+ REG32 Clk_APB2_Enable; //0x000000A8
+ /// This register is protected.
+ REG32 Clk_APB2_Disable; //0x000000AC
+ REG32 Clk_MEM_Mode; //0x000000B0
+ REG32 Clk_MEM_Enable; //0x000000B4
+ /// This register is protected.
+ REG32 Clk_MEM_Disable; //0x000000B8
+ REG32 Clk_APO_Mode; //0x000000BC
+ REG32 Clk_APO_Enable; //0x000000C0
+ /// This register is protected.
+ REG32 Clk_APO_Disable; //0x000000C4
+ REG32 Cfg_Clk_AP_CPU; //0x000000C8
+ REG32 Cfg_Clk_AP_AXI; //0x000000CC
+ REG32 Cfg_Clk_AP_GCG; //0x000000D0
+ REG32 Cfg_Clk_AP_AHB1; //0x000000D4
+ REG32 Cfg_Clk_AP_APB1; //0x000000D8
+ REG32 Cfg_Clk_AP_APB2; //0x000000DC
+ REG32 Cfg_Clk_AP_MEM; //0x000000E0
+ REG32 Cfg_Clk_AP_GPU; //0x000000E4
+ REG32 Cfg_Clk_AP_VPU; //0x000000E8
+ REG32 Cfg_Clk_AP_VOC; //0x000000EC
+ REG32 Cfg_Clk_AP_SFLSH; //0x000000F0
+ REG32 Cfg_Clk_Uart[3]; //0x000000F4
+ REG32 L2cc_Ctrl; //0x00000100
+ REG32 Spi_Ctrl; //0x00000104
+ REG32 Memory_Margin; //0x00000108
+ REG32 Memory_Margin2; //0x0000010C
+ REG32 Memory_Observe; //0x00000110
+ REG32 Cfg_Clk_AP_VOC2; //0x00000114
+ REG32 Reserved_00000118[57]; //0x00000118
+ /// This register is reserved.
+ REG32 Cfg_Reserve; //0x000001FC
+} HWP_SYS_CTRL_AP_T;
+
+#define hwp_sysCtrlAp ((HWP_SYS_CTRL_AP_T*)(RDA_SYSCTRL_BASE))
+
+
+//REG_DBG
+#define SYS_CTRL_AP_SCRATCH(n) (((n)&0xFFFF)<<0)
+#define SYS_CTRL_AP_WRITE_UNLOCK_STATUS (1<<30)
+#define SYS_CTRL_AP_WRITE_UNLOCK (1<<31)
+
+//Cfg_Pll_Ctrl
+#define SYS_CTRL_AP_AP_PLL_ENABLE (1<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_MASK (1<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_SHIFT (0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET (1<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_AP_AP_PLL_BYPASS (1<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_MASK (1<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_SHIFT (8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_PASS (0<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(n) (((n)&31)<<16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_MASK (31<<16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_SHIFT (16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(n) (((n)&31)<<24)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_MASK (31<<24)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_SHIFT (24)
+#define SYS_CTRL_AP_PLL_AP_CFG(n) (((n)&0x1F1F1111)<<0)
+#define SYS_CTRL_AP_PLL_AP_CFG_MASK (0x1F1F1111<<0)
+#define SYS_CTRL_AP_PLL_AP_CFG_SHIFT (0)
+
+//Sel_Clock
+#define SYS_CTRL_AP_SLOW_SEL_RF_OSCILLATOR (1<<0)
+#define SYS_CTRL_AP_SLOW_SEL_RF_RF (0<<0)
+#define SYS_CTRL_AP_CPU_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_AP_CPU_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_AP_BUS_SEL_FAST_SLOW (1<<5)
+#define SYS_CTRL_AP_BUS_SEL_FAST_FAST (0<<5)
+#define SYS_CTRL_AP_TIMER_SEL_FAST_SLOW (1<<7)
+#define SYS_CTRL_AP_TIMER_SEL_FAST_FAST (0<<7)
+#define SYS_CTRL_AP_RF_DETECTED_OK (1<<8)
+#define SYS_CTRL_AP_RF_DETECTED_NO (0<<8)
+#define SYS_CTRL_AP_RF_DETECT_BYPASS (1<<9)
+#define SYS_CTRL_AP_RF_DETECT_RESET (1<<10)
+#define SYS_CTRL_AP_RF_SELECTED_L (1<<11)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_MASK (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_SHIFT (12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_NOT_LOCKED (0<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_MASK (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_SHIFT (13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_NOT_LOCKED (0<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_MASK (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_SHIFT (14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_NOT_LOCKED (0<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_USB (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_MASK (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_SHIFT (15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_NOT_LOCKED (0<<15)
+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_CPU (1<<20)
+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_BUS (1<<21)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L (1<<30)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_MASK (1<<30)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_SHIFT (30)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L (1<<31)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_MASK (1<<31)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_SHIFT (31)
+
+//Reset_Cause
+#define SYS_CTRL_AP_WATCHDOG_RESET_HAPPENED (1<<0)
+#define SYS_CTRL_AP_WATCHDOG_RESET_NO (0<<0)
+#define SYS_CTRL_AP_GLOBALSOFT_RESET_HAPPENED (1<<4)
+#define SYS_CTRL_AP_GLOBALSOFT_RESET_NO (0<<4)
+#define SYS_CTRL_AP_HOSTDEBUG_RESET_HAPPENED (1<<5)
+#define SYS_CTRL_AP_HOSTDEBUG_RESET_NO (0<<5)
+#define SYS_CTRL_AP_ALARMCAUSE_HAPPENED (1<<6)
+#define SYS_CTRL_AP_ALARMCAUSE_NO (0<<6)
+#define SYS_CTRL_AP_BOOT_MODE(n) (((n)&0xFFFF)<<8)
+#define SYS_CTRL_AP_BOOT_MODE_MASK (0xFFFF<<8)
+#define SYS_CTRL_AP_BOOT_MODE_SHIFT (8)
+#define SYS_CTRL_AP_SW_BOOT_MODE(n) (((n)&0x7F)<<24)
+#define SYS_CTRL_AP_SW_BOOT_MODE_MASK (0x7F<<24)
+#define SYS_CTRL_AP_SW_BOOT_MODE_SHIFT (24)
+#define SYS_CTRL_AP_FONCTIONAL_TEST_MODE (1<<31)
+
+//CPU_Rst_Set
+#define SYS_CTRL_AP_SET_CPU_RST_CORE (1<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_SYS (1<<1)
+#define SYS_CTRL_AP_SOFT_RST (1<<31)
+#define SYS_CTRL_AP_SET_CPU_RST(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_MASK (3<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_SHIFT (0)
+
+//CPU_Rst_Clr
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE (1<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_SYS (1<<1)
+#define SYS_CTRL_AP_CLR_CPU_RST(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_MASK (3<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_SHIFT (0)
+
+//AXI_Rst_Set
+#define SYS_CTRL_AP_SET_AXI_RST_VOC (1<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_VOC2 (1<<1)
+#define SYS_CTRL_AP_SET_AXI_RST_DMA (1<<2)
+#define SYS_CTRL_AP_SET_AXI_RST_SYS (1<<3)
+#define SYS_CTRL_AP_SET_AXI_RST_CONNECT (1<<4)
+#define SYS_CTRL_AP_SET_AHB0_RST_GPU (1<<5)
+#define SYS_CTRL_AP_SET_APB0_RST_VPU (1<<6)
+#define SYS_CTRL_AP_SET_APB0_RST_IRQ (1<<7)
+#define SYS_CTRL_AP_SET_AXI_RST(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_MASK (0xFF<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_SHIFT (0)
+
+//AXI_Rst_Clr
+#define SYS_CTRL_AP_CLR_AXI_RST_VOC (1<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_VOC2 (1<<1)
+#define SYS_CTRL_AP_CLR_AXI_RST_DMA (1<<2)
+#define SYS_CTRL_AP_CLR_AXI_RST_SYS (1<<3)
+#define SYS_CTRL_AP_CLR_AXI_RST_CONNECT (1<<4)
+#define SYS_CTRL_AP_CLR_AHB0_RST_GPU (1<<5)
+#define SYS_CTRL_AP_CLR_APB0_RST_VPU (1<<6)
+#define SYS_CTRL_AP_CLR_APB0_RST_IRQ (1<<7)
+#define SYS_CTRL_AP_CLR_AXI_RST(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_MASK (0xFF<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_SHIFT (0)
+
+//AXIDIV2_Rst_Set
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_IMEM (1<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SYS (1<<1)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_VPU (1<<2)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_MASK (7<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SHIFT (0)
+
+//AXIDIV2_Rst_Clr
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_IMEM (1<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SYS (1<<1)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_VPU (1<<2)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_MASK (7<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SHIFT (0)
+
+//GCG_Rst_Set
+#define SYS_CTRL_AP_SET_GCG_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_GOUDA (1<<1)
+#define SYS_CTRL_AP_SET_GCG_RST_CAMERA (1<<2)
+#define SYS_CTRL_AP_SET_GCG_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_MASK (7<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_SHIFT (0)
+
+//GCG_Rst_Clr
+#define SYS_CTRL_AP_CLR_GCG_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_GOUDA (1<<1)
+#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA (1<<2)
+#define SYS_CTRL_AP_CLR_GCG_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_MASK (7<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_SHIFT (0)
+
+//AHB1_Rst_Set
+#define SYS_CTRL_AP_SET_AHB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_USBC (1<<1)
+#define SYS_CTRL_AP_SET_AHB1_RST_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_SET_AHB1_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_MASK (7<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_SHIFT (0)
+
+//AHB1_Rst_Clr
+#define SYS_CTRL_AP_CLR_AHB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_USBC (1<<1)
+#define SYS_CTRL_AP_CLR_AHB1_RST_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_CLR_AHB1_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_MASK (7<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_SHIFT (0)
+
+//APB1_Rst_Set
+#define SYS_CTRL_AP_SET_APB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_TIMER (1<<1)
+#define SYS_CTRL_AP_SET_APB1_RST_KEYPAD (1<<2)
+#define SYS_CTRL_AP_SET_APB1_RST_GPIO (1<<3)
+#define SYS_CTRL_AP_SET_APB1_RST_PWM (1<<4)
+#define SYS_CTRL_AP_SET_APB1_RST_AIF (1<<5)
+#define SYS_CTRL_AP_SET_APB1_RST_AIF2 (1<<6)
+#define SYS_CTRL_AP_SET_APB1_RST_AUIFC (1<<7)
+#define SYS_CTRL_AP_SET_APB1_RST_I2C1 (1<<8)
+#define SYS_CTRL_AP_SET_APB1_RST_I2C2 (1<<9)
+#define SYS_CTRL_AP_SET_APB1_RST_I2C3 (1<<10)
+#define SYS_CTRL_AP_SET_APB1_RST_COM_REGS (1<<11)
+#define SYS_CTRL_AP_SET_APB1_RST_DMC (1<<12)
+#define SYS_CTRL_AP_SET_APB1_RST_DDRPHY_P (1<<13)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XCPU (1<<14)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BCPU (1<<15)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_AHBC (1<<16)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_DMA (1<<17)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_A2A (1<<18)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XIFC (1<<19)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BIFC (1<<20)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BAHBC (1<<21)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_MEM_BRIDGE (1<<22)
+#define SYS_CTRL_AP_SET_APB1_RST(n) (((n)&0x7FFFFF)<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_MASK (0x7FFFFF<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_SHIFT (0)
+
+//APB1_Rst_Clr
+#define SYS_CTRL_AP_CLR_APB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_TIMER (1<<1)
+#define SYS_CTRL_AP_CLR_APB1_RST_KEYPAD (1<<2)
+#define SYS_CTRL_AP_CLR_APB1_RST_GPIO (1<<3)
+#define SYS_CTRL_AP_CLR_APB1_RST_PWM (1<<4)
+#define SYS_CTRL_AP_CLR_APB1_RST_AIF (1<<5)
+#define SYS_CTRL_AP_CLR_APB1_RST_AIF2 (1<<6)
+#define SYS_CTRL_AP_CLR_APB1_RST_AUIFC (1<<7)
+#define SYS_CTRL_AP_CLR_APB1_RST_I2C1 (1<<8)
+#define SYS_CTRL_AP_CLR_APB1_RST_I2C2 (1<<9)
+#define SYS_CTRL_AP_CLR_APB1_RST_I2C3 (1<<10)
+#define SYS_CTRL_AP_CLR_APB1_RST_COM_REGS (1<<11)
+#define SYS_CTRL_AP_CLR_APB1_RST_DMC (1<<12)
+#define SYS_CTRL_AP_CLR_APB1_RST_DDRPHY_P (1<<13)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XCPU (1<<14)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BCPU (1<<15)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_AHBC (1<<16)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_DMA (1<<17)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_A2A (1<<18)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XIFC (1<<19)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BIFC (1<<20)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BAHBC (1<<21)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_MEM_BRIDGE (1<<22)
+#define SYS_CTRL_AP_CLR_APB1_RST(n) (((n)&0x7FFFFF)<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_MASK (0x7FFFFF<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_SHIFT (0)
+
+//APB2_Rst_Set
+#define SYS_CTRL_AP_SET_APB2_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_IFC (1<<1)
+#define SYS_CTRL_AP_SET_APB2_RST_UART1 (1<<2)
+#define SYS_CTRL_AP_SET_APB2_RST_UART2 (1<<3)
+#define SYS_CTRL_AP_SET_APB2_RST_UART3 (1<<4)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI1 (1<<5)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI2 (1<<6)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI3 (1<<7)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC1 (1<<8)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC2 (1<<9)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC3 (1<<10)
+#define SYS_CTRL_AP_SET_APB2_RST_NANDFLASH (1<<11)
+#define SYS_CTRL_AP_SET_APB2_RST(n) (((n)&0xFFF)<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_MASK (0xFFF<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_SHIFT (0)
+
+//APB2_Rst_Clr
+#define SYS_CTRL_AP_CLR_APB2_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_IFC (1<<1)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART1 (1<<2)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART2 (1<<3)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART3 (1<<4)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI1 (1<<5)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI2 (1<<6)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI3 (1<<7)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC1 (1<<8)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC2 (1<<9)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC3 (1<<10)
+#define SYS_CTRL_AP_CLR_APB2_RST_NANDFLASH (1<<11)
+#define SYS_CTRL_AP_CLR_APB2_RST(n) (((n)&0xFFF)<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_MASK (0xFFF<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_SHIFT (0)
+
+//MEM_Rst_Set
+#define SYS_CTRL_AP_SET_MEM_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_GPU (1<<1)
+#define SYS_CTRL_AP_SET_MEM_RST_VPU (1<<2)
+#define SYS_CTRL_AP_SET_MEM_RST_DMC (1<<3)
+#define SYS_CTRL_AP_SET_MEM_RST_DDRPHY_P (1<<4)
+#define SYS_CTRL_AP_SET_MEM_RST(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_MASK (31<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_SHIFT (0)
+
+//MEM_Rst_Clr
+#define SYS_CTRL_AP_CLR_MEM_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_GPU (1<<1)
+#define SYS_CTRL_AP_CLR_MEM_RST_VPU (1<<2)
+#define SYS_CTRL_AP_CLR_MEM_RST_DMC (1<<3)
+#define SYS_CTRL_AP_CLR_MEM_RST_DDRPHY_P (1<<4)
+#define SYS_CTRL_AP_CLR_MEM_RST(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_MASK (31<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_SHIFT (0)
+
+//Clk_CPU_Mode
+#define SYS_CTRL_AP_MODE_CLK_CPU_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_CPU_MANUAL (1<<0)
+
+//Clk_CPU_Enable
+#define SYS_CTRL_AP_ENABLE_CPU_CORE (1<<0)
+#define SYS_CTRL_AP_ENABLE_CPU_DUMMY (1<<1)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU_MASK (3<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU_SHIFT (0)
+
+//Clk_CPU_Disable
+#define SYS_CTRL_AP_DISABLE_CPU_CORE (1<<0)
+#define SYS_CTRL_AP_DISABLE_CPU_DUMMY (1<<1)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU_MASK (3<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU_SHIFT (0)
+
+//Clk_AXI_Mode
+#define SYS_CTRL_AP_MODE_AHB0_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_AHB0_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB0_CONF_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB0_CONF_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_AXI_VOC_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_AXI_VOC_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_AXI_VOC2_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_AXI_VOC2_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_AXI_DMA_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_AXI_DMA_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_CLK_AXI(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXI_MASK (31<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXI_SHIFT (0)
+
+//Clk_AXI_Enable
+#define SYS_CTRL_AP_ENABLE_AHB0_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB0_CONF (1<<1)
+#define SYS_CTRL_AP_ENABLE_AXI_VOC (1<<2)
+#define SYS_CTRL_AP_ENABLE_AXI_VOC2 (1<<3)
+#define SYS_CTRL_AP_ENABLE_AXI_DMA (1<<4)
+#define SYS_CTRL_AP_ENABLE_AXI_ALWAYS (1<<5)
+#define SYS_CTRL_AP_ENABLE_AXI_CONNECT (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB0_IRQ (1<<7)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI_MASK (0xFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI_SHIFT (0)
+
+//Clk_AXI_Disable
+#define SYS_CTRL_AP_DISABLE_AHB0_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB0_CONF (1<<1)
+#define SYS_CTRL_AP_DISABLE_AXI_VOC (1<<2)
+#define SYS_CTRL_AP_DISABLE_AXI_VOC2 (1<<3)
+#define SYS_CTRL_AP_DISABLE_AXI_DMA (1<<4)
+#define SYS_CTRL_AP_DISABLE_AXI_ALWAYS (1<<5)
+#define SYS_CTRL_AP_DISABLE_AXI_CONNECT (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB0_IRQ (1<<7)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI_MASK (0xFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI_SHIFT (0)
+
+//Clk_AXIDIV2_Mode
+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_MANUAL (1<<0)
+
+//Clk_AXIDIV2_Enable
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_IMEM (1<<0)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_ALWAYS (1<<1)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_CONNECT (1<<2)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_VPU (1<<3)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_MASK (15<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_SHIFT (0)
+
+//Clk_AXIDIV2_Disable
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_IMEM (1<<0)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_ALWAYS (1<<1)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_CONNECT (1<<2)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_VPU (1<<3)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_MASK (15<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_SHIFT (0)
+
+//Clk_GCG_Mode
+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_GCG_GOUDA_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_CLK_GCG(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_MODE_CLK_GCG_MASK (7<<0)
+#define SYS_CTRL_AP_MODE_CLK_GCG_SHIFT (0)
+
+//Clk_GCG_Enable
+#define SYS_CTRL_AP_ENABLE_GCG_APB_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_GCG_GOUDA (1<<1)
+#define SYS_CTRL_AP_ENABLE_GCG_CAMERA (1<<2)
+#define SYS_CTRL_AP_ENABLE_GCG_ALWAYS (1<<3)
+#define SYS_CTRL_AP_ENABLE_GCG_CONNECT (1<<4)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG_MASK (31<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG_SHIFT (0)
+
+//Clk_GCG_Disable
+#define SYS_CTRL_AP_DISABLE_GCG_APB_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_GCG_GOUDA (1<<1)
+#define SYS_CTRL_AP_DISABLE_GCG_CAMERA (1<<2)
+#define SYS_CTRL_AP_DISABLE_GCG_ALWAYS (1<<3)
+#define SYS_CTRL_AP_DISABLE_GCG_CONNECT (1<<4)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG_MASK (31<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG_SHIFT (0)
+
+//Clk_AHB1_Mode
+#define SYS_CTRL_AP_MODE_CLK_AHB1_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_AHB1_MANUAL (1<<0)
+
+//Clk_AHB1_Enable
+#define SYS_CTRL_AP_ENABLE_AHB1_USBC (1<<0)
+#define SYS_CTRL_AP_ENABLE_AHB1_ALWAYS (1<<1)
+#define SYS_CTRL_AP_ENABLE_AHB1_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_MASK (7<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_SHIFT (0)
+
+//Clk_AHB1_Disable
+#define SYS_CTRL_AP_DISABLE_AHB1_USBC (1<<0)
+#define SYS_CTRL_AP_DISABLE_AHB1_ALWAYS (1<<1)
+#define SYS_CTRL_AP_DISABLE_AHB1_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_MASK (7<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_SHIFT (0)
+
+//Clk_APB1_Mode
+#define SYS_CTRL_AP_MODE_APB1_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APB1_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB1_AIF_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB1_AIF_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APB1_AIF2_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APB1_AIF2_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APB1_I2C1_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APB1_I2C1_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APB1_I2C2_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APB1_I2C2_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_APB1_I2C3_AUTOMATIC (0<<10)
+#define SYS_CTRL_AP_MODE_APB1_I2C3_MANUAL (1<<10)
+#define SYS_CTRL_AP_MODE_APB1D_OSC_AUTOMATIC (0<<11)
+#define SYS_CTRL_AP_MODE_APB1D_OSC_MANUAL (1<<11)
+#define SYS_CTRL_AP_MODE_APB1D_PWM_AUTOMATIC (0<<12)
+#define SYS_CTRL_AP_MODE_APB1D_PWM_MANUAL (1<<12)
+#define SYS_CTRL_AP_MODE_CLK_APB1(n) (((n)&0x1FFF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB1_MASK (0x1FFF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB1_SHIFT (0)
+
+//Clk_APB1_Enable
+#define SYS_CTRL_AP_ENABLE_APB1_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB1_AIF (1<<1)
+#define SYS_CTRL_AP_ENABLE_APB1_AIF2 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC (1<<3)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH0 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH1 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH2 (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH3 (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB1_I2C1 (1<<8)
+#define SYS_CTRL_AP_ENABLE_APB1_I2C2 (1<<9)
+#define SYS_CTRL_AP_ENABLE_APB1_I2C3 (1<<10)
+#define SYS_CTRL_AP_ENABLE_APB1D_OSC (1<<11)
+#define SYS_CTRL_AP_ENABLE_APB1D_PWM (1<<12)
+#define SYS_CTRL_AP_ENABLE_APB1_ALWAYS (1<<13)
+#define SYS_CTRL_AP_ENABLE_APB1_DAPLITE (1<<14)
+#define SYS_CTRL_AP_ENABLE_APB1_TIMER (1<<15)
+#define SYS_CTRL_AP_ENABLE_APB1_GPIO (1<<16)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1(n) (((n)&0x1FFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1_MASK (0x1FFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1_SHIFT (0)
+
+//Clk_APB1_Disable
+#define SYS_CTRL_AP_DISABLE_APB1_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB1_AIF (1<<1)
+#define SYS_CTRL_AP_DISABLE_APB1_AIF2 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC (1<<3)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH0 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH1 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH2 (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH3 (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB1_I2C1 (1<<8)
+#define SYS_CTRL_AP_DISABLE_APB1_I2C2 (1<<9)
+#define SYS_CTRL_AP_DISABLE_APB1_I2C3 (1<<10)
+#define SYS_CTRL_AP_DISABLE_APB1D_OSC (1<<11)
+#define SYS_CTRL_AP_DISABLE_APB1D_PWM (1<<12)
+#define SYS_CTRL_AP_DISABLE_APB1_ALWAYS (1<<13)
+#define SYS_CTRL_AP_DISABLE_APB1_DAPLITE (1<<14)
+#define SYS_CTRL_AP_DISABLE_APB1_TIMER (1<<15)
+#define SYS_CTRL_AP_DISABLE_APB1_GPIO (1<<16)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1(n) (((n)&0x1FFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1_MASK (0x1FFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1_SHIFT (0)
+
+//Clk_APB2_Mode
+#define SYS_CTRL_AP_MODE_APB2_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APB2_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB2_IFC_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB2_IFC_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_APB2_UART1_AUTOMATIC (0<<10)
+#define SYS_CTRL_AP_MODE_APB2_UART1_MANUAL (1<<10)
+#define SYS_CTRL_AP_MODE_APB2_UART2_AUTOMATIC (0<<11)
+#define SYS_CTRL_AP_MODE_APB2_UART2_MANUAL (1<<11)
+#define SYS_CTRL_AP_MODE_APB2_UART3_AUTOMATIC (0<<12)
+#define SYS_CTRL_AP_MODE_APB2_UART3_MANUAL (1<<12)
+#define SYS_CTRL_AP_MODE_APB2_SPI1_AUTOMATIC (0<<13)
+#define SYS_CTRL_AP_MODE_APB2_SPI1_MANUAL (1<<13)
+#define SYS_CTRL_AP_MODE_APB2_SPI2_AUTOMATIC (0<<14)
+#define SYS_CTRL_AP_MODE_APB2_SPI2_MANUAL (1<<14)
+#define SYS_CTRL_AP_MODE_APB2_SPI3_AUTOMATIC (0<<15)
+#define SYS_CTRL_AP_MODE_APB2_SPI3_MANUAL (1<<15)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_AUTOMATIC (0<<16)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_MANUAL (1<<16)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_AUTOMATIC (0<<17)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_MANUAL (1<<17)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_AUTOMATIC (0<<18)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_MANUAL (1<<18)
+#define SYS_CTRL_AP_MODE_CLK_APB2(n) (((n)&0x7FFFF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB2_MASK (0x7FFFF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB2_SHIFT (0)
+
+//Clk_APB2_Enable
+#define SYS_CTRL_AP_ENABLE_APB2_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC (1<<1)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH0 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH1 (1<<3)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH2 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH3 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH4 (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH5 (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH6 (1<<8)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH7 (1<<9)
+#define SYS_CTRL_AP_ENABLE_APB2_UART1 (1<<10)
+#define SYS_CTRL_AP_ENABLE_APB2_UART2 (1<<11)
+#define SYS_CTRL_AP_ENABLE_APB2_UART3 (1<<12)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI1 (1<<13)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI2 (1<<14)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI3 (1<<15)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC1 (1<<16)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC2 (1<<17)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC3 (1<<18)
+#define SYS_CTRL_AP_ENABLE_APB2_ALWAYS (1<<19)
+#define SYS_CTRL_AP_ENABLE_APB2_NANDFLASH (1<<20)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2(n) (((n)&0x1FFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2_MASK (0x1FFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2_SHIFT (0)
+
+//Clk_APB2_Disable
+#define SYS_CTRL_AP_DISABLE_APB2_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC (1<<1)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH0 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH1 (1<<3)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH2 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH3 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH4 (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH5 (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH6 (1<<8)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH7 (1<<9)
+#define SYS_CTRL_AP_DISABLE_APB2_UART1 (1<<10)
+#define SYS_CTRL_AP_DISABLE_APB2_UART2 (1<<11)
+#define SYS_CTRL_AP_DISABLE_APB2_UART3 (1<<12)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI1 (1<<13)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI2 (1<<14)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI3 (1<<15)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC1 (1<<16)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC2 (1<<17)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC3 (1<<18)
+#define SYS_CTRL_AP_DISABLE_APB2_ALWAYS (1<<19)
+#define SYS_CTRL_AP_DISABLE_APB2_NANDFLASH (1<<20)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2(n) (((n)&0x1FFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2_MASK (0x1FFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2_SHIFT (0)
+
+//Clk_MEM_Mode
+#define SYS_CTRL_AP_MODE_CLK_MEM_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_MEM_MANUAL (1<<0)
+
+//Clk_MEM_Enable
+#define SYS_CTRL_AP_ENABLE_MEM_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_MEM_DMC (1<<1)
+#define SYS_CTRL_AP_ENABLE_MEM_GPU (1<<2)
+#define SYS_CTRL_AP_ENABLE_MEM_VPU (1<<3)
+#define SYS_CTRL_AP_ENABLE_MEM_DDRPHY_P (1<<4)
+#define SYS_CTRL_AP_ENABLE_MEM_CONNECT (1<<5)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM(n) (((n)&0x3F)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM_MASK (0x3F<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM_SHIFT (0)
+
+//Clk_MEM_Disable
+#define SYS_CTRL_AP_DISABLE_MEM_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_MEM_DMC (1<<1)
+#define SYS_CTRL_AP_DISABLE_MEM_GPU (1<<2)
+#define SYS_CTRL_AP_DISABLE_MEM_VPU (1<<3)
+#define SYS_CTRL_AP_DISABLE_MEM_DDRPHY_P (1<<4)
+#define SYS_CTRL_AP_DISABLE_MEM_CONNECT (1<<5)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM(n) (((n)&0x3F)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM_MASK (0x3F<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM_SHIFT (0)
+
+//Clk_APO_Mode
+#define SYS_CTRL_AP_MODE_APOC_VPU_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APOC_VPU_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APOC_BCK_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APOC_BCK_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APOC_BCK2_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APOC_BCK2_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APOC_UART1_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APOC_UART1_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APOC_UART2_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APOC_UART2_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APOC_UART3_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APOC_UART3_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APOC_VOC_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APOC_VOC_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_CLK_APO(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APO_MASK (0x3FF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APO_SHIFT (0)
+
+//Clk_APO_Enable
+#define SYS_CTRL_AP_ENABLE_APOC_VPU (1<<0)
+#define SYS_CTRL_AP_ENABLE_APOC_BCK (1<<1)
+#define SYS_CTRL_AP_ENABLE_APOC_BCK2 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APOC_UART1 (1<<3)
+#define SYS_CTRL_AP_ENABLE_APOC_UART2 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APOC_UART3 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC_CORE (1<<6)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2_CORE (1<<7)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC (1<<8)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2 (1<<9)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC_ALWAYS (1<<10)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2_ALWAYS (1<<11)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY_N (1<<12)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XP (1<<13)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XN (1<<14)
+#define SYS_CTRL_AP_ENABLE_APOC_GPU (1<<15)
+#define SYS_CTRL_AP_ENABLE_APOC_USBPHY (1<<16)
+#define SYS_CTRL_AP_ENABLE_APOC_CSI (1<<17)
+#define SYS_CTRL_AP_ENABLE_APOC_DSI (1<<18)
+#define SYS_CTRL_AP_ENABLE_APOC_GPIO (1<<19)
+#define SYS_CTRL_AP_ENABLE_APOC_SPIFLASH (1<<20)
+#define SYS_CTRL_AP_ENABLE_APOC_PIX (1<<21)
+#define SYS_CTRL_AP_ENABLE_APOC_PDGB (1<<22)
+#define SYS_CTRL_AP_ENABLE_CLK_APO(n) (((n)&0x7FFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APO_MASK (0x7FFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APO_SHIFT (0)
+
+//Clk_APO_Disable
+#define SYS_CTRL_AP_DISABLE_APOC_VPU (1<<0)
+#define SYS_CTRL_AP_DISABLE_APOC_BCK (1<<1)
+#define SYS_CTRL_AP_DISABLE_APOC_BCK2 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APOC_UART1 (1<<3)
+#define SYS_CTRL_AP_DISABLE_APOC_UART2 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APOC_UART3 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC_CORE (1<<6)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2_CORE (1<<7)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC (1<<8)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2 (1<<9)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC_ALWAYS (1<<10)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2_ALWAYS (1<<11)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY_N (1<<12)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XP (1<<13)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XN (1<<14)
+#define SYS_CTRL_AP_DISABLE_APOC_GPU (1<<15)
+#define SYS_CTRL_AP_DISABLE_APOC_USBPHY (1<<16)
+#define SYS_CTRL_AP_DISABLE_APOC_CSI (1<<17)
+#define SYS_CTRL_AP_DISABLE_APOC_DSI (1<<18)
+#define SYS_CTRL_AP_DISABLE_APOC_GPIO (1<<19)
+#define SYS_CTRL_AP_DISABLE_APOC_SPIFLASH (1<<20)
+#define SYS_CTRL_AP_DISABLE_APOC_PIX (1<<21)
+#define SYS_CTRL_AP_DISABLE_APOC_PDGB (1<<22)
+#define SYS_CTRL_AP_DISABLE_CLK_APO(n) (((n)&0x7FFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APO_MASK (0x7FFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APO_SHIFT (0)
+
+//Cfg_Clk_AP_CPU
+#define SYS_CTRL_AP_AP_CPU_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_BUS_DIV_SEL(n) (((n)&3)<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_MASK (3<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_SHIFT (16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV2 (0<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV3 (1<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV4 (2<<16)
+#define SYS_CTRL_AP_AP_CPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_AXI
+#define SYS_CTRL_AP_AP_AXI_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_AXI_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_AXI_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_GCG
+#define SYS_CTRL_AP_AP_GCG_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_GCG_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_GCG_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_AHB1
+#define SYS_CTRL_AP_AP_AHB1_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_AHB1_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_AHB1_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_APB1
+#define SYS_CTRL_AP_AP_APB1_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_APB1_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_APB1_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_APB2
+#define SYS_CTRL_AP_AP_APB2_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_APB2_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_APB2_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_MEM
+#define SYS_CTRL_AP_AP_MEM_SRC_DIV2 (1<<12)
+
+//Cfg_Clk_AP_GPU
+#define SYS_CTRL_AP_AP_GPU_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_GPU_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_GPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_VPU
+#define SYS_CTRL_AP_AP_VPU_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_VPU_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_VPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_VOC
+#define SYS_CTRL_AP_AP_VOC_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_SFLSH
+#define SYS_CTRL_AP_AP_SFLSH_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_SFLSH_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_SFLSH_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_Uart
+#define SYS_CTRL_AP_UART_DIVIDER(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_AP_UART_DIVIDER_MASK (0x3FF<<0)
+#define SYS_CTRL_AP_UART_DIVIDER_SHIFT (0)
+#define SYS_CTRL_AP_UART_SEL_PLL_SLOW (0<<12)
+#define SYS_CTRL_AP_UART_SEL_PLL_PLL (1<<12)
+
+//L2cc_Ctrl
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_MASK (15<<0)
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_SHIFT (0)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M(n) (((n)&15)<<4)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_MASK (15<<4)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_SHIFT (4)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<8)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_MASK (15<<8)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_SHIFT (8)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<12)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_MASK (15<<12)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_SHIFT (12)
+#define SYS_CTRL_AP_ARAP_L2CC_1_M (1<<16)
+#define SYS_CTRL_AP_AWAP_L2CC_1_M (1<<17)
+#define SYS_CTRL_AP_ARAP_MODEM_MEM_AHBS_M (1<<18)
+#define SYS_CTRL_AP_AWAP_MODEM_MEM_AHBS_M (1<<19)
+#define SYS_CTRL_AP_ARAP_MERGE1M (1<<20)
+#define SYS_CTRL_AP_AWAP_MERGE1M (1<<21)
+#define SYS_CTRL_AP_ARAP_MERGE2M (1<<22)
+#define SYS_CTRL_AP_AWAP_MERGE2M (1<<23)
+#define SYS_CTRL_AP_RESERVE1(n) (((n)&0xFF)<<24)
+#define SYS_CTRL_AP_RESERVE1_MASK (0xFF<<24)
+#define SYS_CTRL_AP_RESERVE1_SHIFT (24)
+
+//Spi_Ctrl
+#define SYS_CTRL_AP_LIMITED_EN_SPI1 (1<<0)
+#define SYS_CTRL_AP_LPSEN_SPI1 (1<<1)
+#define SYS_CTRL_AP_LIMITED_EN_SPI2 (1<<2)
+#define SYS_CTRL_AP_LPSEN_SPI2 (1<<3)
+#define SYS_CTRL_AP_LIMITED_EN_SPI3 (1<<4)
+#define SYS_CTRL_AP_LPSEN_SPI3 (1<<5)
+#define SYS_CTRL_AP_FBUSWID_NFSC (1<<6)
+#define SYS_CTRL_AP_RESERVE3 (1<<7)
+#define SYS_CTRL_AP_DMC_CFG(n) (((n)&0x3FF)<<8)
+#define SYS_CTRL_AP_DMC_CFG_MASK (0x3FF<<8)
+#define SYS_CTRL_AP_DMC_CFG_SHIFT (8)
+#define SYS_CTRL_AP_RESERVE2(n) (((n)&0x3FFF)<<18)
+#define SYS_CTRL_AP_RESERVE2_MASK (0x3FFF<<18)
+#define SYS_CTRL_AP_RESERVE2_SHIFT (18)
+
+//Memory_Margin
+#define SYS_CTRL_AP_EMAW_VOC(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_EMAW_VOC_MASK (3<<0)
+#define SYS_CTRL_AP_EMAW_VOC_SHIFT (0)
+#define SYS_CTRL_AP_EMA_VOC(n) (((n)&7)<<2)
+#define SYS_CTRL_AP_EMA_VOC_MASK (7<<2)
+#define SYS_CTRL_AP_EMA_VOC_SHIFT (2)
+#define SYS_CTRL_AP_EMAW_VPU(n) (((n)&3)<<5)
+#define SYS_CTRL_AP_EMAW_VPU_MASK (3<<5)
+#define SYS_CTRL_AP_EMAW_VPU_SHIFT (5)
+#define SYS_CTRL_AP_EMA_VPU(n) (((n)&7)<<7)
+#define SYS_CTRL_AP_EMA_VPU_MASK (7<<7)
+#define SYS_CTRL_AP_EMA_VPU_SHIFT (7)
+#define SYS_CTRL_AP_EMAW_GPU(n) (((n)&3)<<10)
+#define SYS_CTRL_AP_EMAW_GPU_MASK (3<<10)
+#define SYS_CTRL_AP_EMAW_GPU_SHIFT (10)
+#define SYS_CTRL_AP_EMA_GPU(n) (((n)&7)<<12)
+#define SYS_CTRL_AP_EMA_GPU_MASK (7<<12)
+#define SYS_CTRL_AP_EMA_GPU_SHIFT (12)
+#define SYS_CTRL_AP_EMAW_GOUDA(n) (((n)&3)<<15)
+#define SYS_CTRL_AP_EMAW_GOUDA_MASK (3<<15)
+#define SYS_CTRL_AP_EMAW_GOUDA_SHIFT (15)
+#define SYS_CTRL_AP_EMA_GOUDA(n) (((n)&7)<<17)
+#define SYS_CTRL_AP_EMA_GOUDA_MASK (7<<17)
+#define SYS_CTRL_AP_EMA_GOUDA_SHIFT (17)
+#define SYS_CTRL_AP_EMAW_IMEM(n) (((n)&3)<<20)
+#define SYS_CTRL_AP_EMAW_IMEM_MASK (3<<20)
+#define SYS_CTRL_AP_EMAW_IMEM_SHIFT (20)
+#define SYS_CTRL_AP_EMA_IMEM(n) (((n)&7)<<22)
+#define SYS_CTRL_AP_EMA_IMEM_MASK (7<<22)
+#define SYS_CTRL_AP_EMA_IMEM_SHIFT (22)
+#define SYS_CTRL_AP_EMAW_USB(n) (((n)&3)<<25)
+#define SYS_CTRL_AP_EMAW_USB_MASK (3<<25)
+#define SYS_CTRL_AP_EMAW_USB_SHIFT (25)
+#define SYS_CTRL_AP_EMA_USB(n) (((n)&7)<<27)
+#define SYS_CTRL_AP_EMA_USB_MASK (7<<27)
+#define SYS_CTRL_AP_EMA_USB_SHIFT (27)
+
+//Memory_Margin2
+#define SYS_CTRL_AP_EMAW_NFSC(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_EMAW_NFSC_MASK (3<<0)
+#define SYS_CTRL_AP_EMAW_NFSC_SHIFT (0)
+#define SYS_CTRL_AP_EMA_NFSC(n) (((n)&7)<<2)
+#define SYS_CTRL_AP_EMA_NFSC_MASK (7<<2)
+#define SYS_CTRL_AP_EMA_NFSC_SHIFT (2)
+#define SYS_CTRL_AP_EMA_VPUROM(n) (((n)&7)<<5)
+#define SYS_CTRL_AP_EMA_VPUROM_MASK (7<<5)
+#define SYS_CTRL_AP_EMA_VPUROM_SHIFT (5)
+#define SYS_CTRL_AP_EMA_IMEMROM(n) (((n)&7)<<8)
+#define SYS_CTRL_AP_EMA_IMEMROM_MASK (7<<8)
+#define SYS_CTRL_AP_EMA_IMEMROM_SHIFT (8)
+#define SYS_CTRL_AP_KEN_VPUROM (1<<11)
+#define SYS_CTRL_AP_PGEN_VPUROM (1<<12)
+#define SYS_CTRL_AP_KEN_IMEMROM (1<<13)
+#define SYS_CTRL_AP_PGEN_IMEMROM (1<<14)
+
+//Memory_Observe
+#define SYS_CTRL_AP_MEM_OBSERVE(n) (((n)&0xFFFFFFFF)<<0)
+
+//Cfg_Clk_AP_VOC2
+//#define SYS_CTRL_AP_AP_VOC_FREQ(n) (((n)&31)<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0)
+//#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12)
+//#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Reserve
+#define SYS_CTRL_AP_RESERVE(n) (((n)&0x3FFFFFFF)<<0)
+#define SYS_CTRL_AP_AUIFC_CH0_IRQ_MASK (1<<30)
+#define SYS_CTRL_AP_AUIFC_CH1_IRQ_MASK (1<<31)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8850e.h b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8850e.h new file mode 100644 index 0000000000..9ae0041a35 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8850e.h @@ -0,0 +1,1540 @@ +#ifndef _REG_SYSCTRL_H_ +#define _REG_SYSCTRL_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= + +// ============================================================================ +// AP_CPU_ID_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// CPU IDs + CPU0 = 0x00000000, + CPU1 = 0x00000001 +} AP_CPU_ID_T; + + +// ============================================================================ +// CPU_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP CPU side System clocks + CPU_CORE = 0x00000000, +/// the following don't have an auto enable + CPU_DUMMY = 0x00000001 +} CPU_CLKS_T; + +#define NB_CPU_CLK_AEN (1) +#define NB_CPU_CLK_EN (2) +#define NB_CPU_CLK (2) + +// ============================================================================ +// AXI_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXI side System clocks: AXI and AHB0 and APB0 + AHB0_CONF = 0x00000000, + APB0_CONF = 0x00000001, + AXI_VOC = 0x00000002, + AXI_VOC2 = 0x00000003, + AXI_DMA = 0x00000004, +/// the following don't have an auto enable + AXI_ALWAYS = 0x00000005, + AXI_CONNECT = 0x00000006, + APB0_IRQ = 0x00000007 +} AXI_CLKS_T; + +#define NB_AXI_CLK_AEN (5) +#define NB_AXI_CLK_EN (8) +#define NB_AXI_CLK (8) + +// ============================================================================ +// AXIDIV2_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXIdiv2 side System clocks + AXIDIV2_IMEM = 0x00000000, +/// the following don't have an auto enable + AXIDIV2_ALWAYS = 0x00000001, + AXIDIV2_CONNECT = 0x00000002, + AXIDIV2_VPU = 0x00000003 +} AXIDIV2_CLKS_T; + +#define NB_AXIDIV2_CLK_AEN (1) +#define NB_AXIDIV2_CLK_EN (4) +#define NB_AXIDIV2_CLK (4) + +// ============================================================================ +// GCG_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GCG side System clocks + GCG_APB_CONF = 0x00000000, + GCG_GOUDA = 0x00000001, + GCG_CAMERA = 0x00000002, +/// the following don't have an auto enable + GCG_ALWAYS = 0x00000003, + GCG_CONNECT = 0x00000004 +} GCG_CLKS_T; + +#define NB_GCG_CLK_AEN (3) +#define NB_GCG_CLK_EN (5) +#define NB_GCG_CLK (5) + +// ============================================================================ +// AHB1_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AHB1 side System clocks + AHB1_USBC = 0x00000000, +/// the following don't have an auto enable + AHB1_ALWAYS = 0x00000001, + AHB1_SPIFLASH = 0x00000002 +} AHB1_CLKS_T; + +#define NB_AHB1_CLK_AEN (1) +#define NB_AHB1_CLK_EN (3) +#define NB_AHB1_CLK (3) + +// ============================================================================ +// APB1_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB1 side System clocks + APB1_CONF = 0x00000000, + APB1_AIF = 0x00000001, + APB1_AIF2 = 0x00000002, + APB1_AUIFC = 0x00000003, + APB1_AUIFC_CH0 = 0x00000004, + APB1_AUIFC_CH1 = 0x00000005, + APB1_AUIFC_CH2 = 0x00000006, + APB1_AUIFC_CH3 = 0x00000007, + APB1_I2C1 = 0x00000008, + APB1_I2C2 = 0x00000009, + APB1_I2C3 = 0x0000000A, +/// AP APB1 side divided clock (either divided by module or by clock_ctrl) + APB1D_OSC = 0x0000000B, + APB1D_PWM = 0x0000000C, +/// the following don't have an auto enable + APB1_ALWAYS = 0x0000000D, + APB1_DAPLITE = 0x0000000E, + APB1_TIMER = 0x0000000F, + APB1_GPIO = 0x00000010 +} APB1_CLKS_T; + +#define NB_APB1_CLK_AEN (13) +#define NB_APB1_CLK_EN (17) +#define NB_APB1_CLK (17) + +// ============================================================================ +// APB2_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB2 side System clocks + APB2_CONF = 0x00000000, + APB2_IFC = 0x00000001, + APB2_IFC_CH0 = 0x00000002, + APB2_IFC_CH1 = 0x00000003, + APB2_IFC_CH2 = 0x00000004, + APB2_IFC_CH3 = 0x00000005, + APB2_IFC_CH4 = 0x00000006, + APB2_IFC_CH5 = 0x00000007, + APB2_IFC_CH6 = 0x00000008, + APB2_IFC_CH7 = 0x00000009, + APB2_UART1 = 0x0000000A, + APB2_UART2 = 0x0000000B, + APB2_UART3 = 0x0000000C, + APB2_SPI1 = 0x0000000D, + APB2_SPI2 = 0x0000000E, + APB2_SPI3 = 0x0000000F, + APB2_SDMMC1 = 0x00000010, + APB2_SDMMC2 = 0x00000011, + APB2_SDMMC3 = 0x00000012, +/// the following don't have an auto enable + APB2_ALWAYS = 0x00000013, + APB2_NANDFLASH = 0x00000014 +} APB2_CLKS_T; + +#define NB_APB2_CLK_AEN (19) +#define NB_APB2_CLK_EN (21) +#define NB_APB2_CLK (21) + +// ============================================================================ +// MEM_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP MEM side System clocks + MEM_CONF = 0x00000000, +/// the following don't have an auto enable + MEM_DMC = 0x00000001, + MEM_GPU = 0x00000002, + MEM_VPU = 0x00000003, + MEM_DDRPHY_P = 0x00000004, + MEM_CONNECT = 0x00000005 +} MEM_CLKS_T; + +#define NB_MEM_CLK_AEN (1) +#define NB_MEM_CLK_EN (6) +#define NB_MEM_CLK (6) + +// ============================================================================ +// APO_CLKS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP side Other clocks +/// clocks with auto enble + APOC_VPU = 0x00000000, + APOC_BCK = 0x00000001, + APOC_BCK2 = 0x00000002, + APOC_UART1 = 0x00000003, + APOC_UART2 = 0x00000004, + APOC_UART3 = 0x00000005, + APOC_VOC_CORE = 0x00000006, + APOC_VOC2_CORE = 0x00000007, + APOC_VOC = 0x00000008, + APOC_VOC2 = 0x00000009, +/// the following don't have an auto enable + APOC_VOC_ALWAYS = 0x0000000A, + APOC_VOC2_ALWAYS = 0x0000000B, + APOC_DDRPHY_N = 0x0000000C, + APOC_DDRPHY2XP = 0x0000000D, + APOC_DDRPHY2XN = 0x0000000E, + APOC_GPU = 0x0000000F, + APOC_USBPHY = 0x00000010, + APOC_CSI = 0x00000011, + APOC_DSI = 0x00000012, + APOC_GPIO = 0x00000013, + APOC_SPIFLASH = 0x00000014, + APOC_PIX = 0x00000015, + APOC_PDGB = 0x00000016 +} APO_CLKS_T; + +#define NB_CLK_VOC_AEN_SYNC (6) +#define NB_CLK_VOC_CORE (8) +#define NB_APO_CLK_AEN (10) +#define NB_CLK_VOC_END (12) +#define NB_APO_CLK_EN (23) +#define NB_APO_CLK (23) + +// ============================================================================ +// CPU_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP CPU side resets + CPU_RST_CORE = 0x00000000, + CPU_RST_SYS = 0x00000001 +} CPU_RESETS_T; + +#define NB_CPU_RST (2) + +// ============================================================================ +// AXI_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXI side resets: AXI and AHB0 and APB0 + AXI_RST_VOC = 0x00000000, + AXI_RST_VOC2 = 0x00000001, + AXI_RST_DMA = 0x00000002, + AXI_RST_SYS = 0x00000003, + AXI_RST_CONNECT = 0x00000004, + AHB0_RST_GPU = 0x00000005, + APB0_RST_VPU = 0x00000006, + APB0_RST_IRQ = 0x00000007 +} AXI_RESETS_T; + +#define NB_AXI_RST (8) + +// ============================================================================ +// AXIDIV2_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AXIDIV2 side resets + AXIDIV2_RST_IMEM = 0x00000000, + AXIDIV2_RST_SYS = 0x00000001, + AXIDIV2_RST_VPU = 0x00000002 +} AXIDIV2_RESETS_T; + +#define NB_AXIDIV2_RST (3) + +// ============================================================================ +// GCG_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP GCG side resets + GCG_RST_SYS = 0x00000000, + GCG_RST_GOUDA = 0x00000001, + GCG_RST_CAMERA = 0x00000002 +} GCG_RESETS_T; + +#define NB_GCG_RST (3) + +// ============================================================================ +// AHB1_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP AHB1 side resets + AHB1_RST_SYS = 0x00000000, + AHB1_RST_USBC = 0x00000001, + AHB1_RST_SPIFLASH = 0x00000002 +} AHB1_RESETS_T; + +#define NB_AHB1_RST (3) + +// ============================================================================ +// APB1_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB1 side resets + APB1_RST_SYS = 0x00000000, + APB1_RST_TIMER = 0x00000001, + APB1_RST_KEYPAD = 0x00000002, + APB1_RST_GPIO = 0x00000003, + APB1_RST_PWM = 0x00000004, + APB1_RST_AIF = 0x00000005, + APB1_RST_AIF2 = 0x00000006, + APB1_RST_AUIFC = 0x00000007, + APB1_RST_I2C1 = 0x00000008, + APB1_RST_I2C2 = 0x00000009, + APB1_RST_I2C3 = 0x0000000A, + APB1_RST_COM_REGS = 0x0000000B, + APB1_RST_DMC = 0x0000000C, + APB1_RST_DDRPHY_P = 0x0000000D, + APB1_RST_BB2G_XCPU = 0x0000000E, + APB1_RST_BB2G_BCPU = 0x0000000F, + APB1_RST_BB2G_AHBC = 0x00000010, + APB1_RST_BB2G_DMA = 0x00000011, + APB1_RST_BB2G_A2A = 0x00000012, + APB1_RST_BB2G_XIFC = 0x00000013, + APB1_RST_BB2G_BIFC = 0x00000014, + APB1_RST_BB2G_BAHBC = 0x00000015, + APB1_RST_BB2G_MEM_BRIDGE = 0x00000016 +} APB1_RESETS_T; + +#define NB_APB1_RST (23) + +// ============================================================================ +// APB2_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP APB2 side resets + APB2_RST_SYS = 0x00000000, + APB2_RST_IFC = 0x00000001, + APB2_RST_UART1 = 0x00000002, + APB2_RST_UART2 = 0x00000003, + APB2_RST_UART3 = 0x00000004, + APB2_RST_SPI1 = 0x00000005, + APB2_RST_SPI2 = 0x00000006, + APB2_RST_SPI3 = 0x00000007, + APB2_RST_SDMMC1 = 0x00000008, + APB2_RST_SDMMC2 = 0x00000009, + APB2_RST_SDMMC3 = 0x0000000A, + APB2_RST_NANDFLASH = 0x0000000B +} APB2_RESETS_T; + +#define NB_APB2_RST (12) + +// ============================================================================ +// MEM_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP MEM side resets + MEM_RST_SYS = 0x00000000, + MEM_RST_GPU = 0x00000001, + MEM_RST_VPU = 0x00000002, + MEM_RST_DMC = 0x00000003, + MEM_RST_DDRPHY_P = 0x00000004 +} MEM_RESETS_T; + +#define NB_MEM_RST (5) + +// ============================================================================ +// AP_OTHERS_RESETS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef enum +{ +/// AP Reset Other : resync on corresponding clock other + AP_RSTO_VOC = 0x00000000, + AP_RSTO_VOC2 = 0x00000001, + AP_RSTO_DDRPHY_N = 0x00000002, + AP_RSTO_DDRPHY2XP = 0x00000003, + AP_RSTO_DDRPHY2XN = 0x00000004, + AP_RSTO_GPU = 0x00000005, + AP_RSTO_VPU = 0x00000006, + AP_RSTO_BCK = 0x00000007, + AP_RSTO_BCK2 = 0x00000008, + AP_RSTO_UART1 = 0x00000009, + AP_RSTO_UART2 = 0x0000000A, + AP_RSTO_UART3 = 0x0000000B, + AP_RSTO_GPIO = 0x0000000C, + AP_RSTO_TIMER = 0x0000000D, + AP_RSTO_USBC = 0x0000000E, + AP_RSTO_DSI = 0x0000000F, + AP_RSTO_SPIFLASH = 0x00000010, + AP_RSTO_TCK = 0x00000011, + AP_RSTO_PDBG_XTAL = 0x00000012 +} AP_OTHERS_RESETS_T; + +#define NB_AP_RSTO (19) +/// For REG_DBG protect lock/unlock value +#define AP_CTRL_PROTECT_LOCK (0XA50000) +#define AP_CTRL_PROTECT_UNLOCK (0XA50001) + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// SYS_CTRL_AP_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + /// <strong>This register is used to Lock and Unlock the protected registers.</strong> + REG32 REG_DBG; //0x00000000 + /// Register protected by Write_Unlocked_H. + REG32 Cfg_Pll_Ctrl[4]; //0x00000004 + /// This register is protected. + REG32 Sel_Clock; //0x00000014 + REG32 Reset_Cause; //0x00000018 + /// This register is protected. + REG32 CPU_Rst_Set; //0x0000001C + REG32 CPU_Rst_Clr; //0x00000020 + /// This register is protected. + REG32 AXI_Rst_Set; //0x00000024 + REG32 AXI_Rst_Clr; //0x00000028 + /// This register is protected. + REG32 AXIDIV2_Rst_Set; //0x0000002C + REG32 AXIDIV2_Rst_Clr; //0x00000030 + /// This register is protected. + REG32 GCG_Rst_Set; //0x00000034 + REG32 GCG_Rst_Clr; //0x00000038 + /// This register is protected. + REG32 AHB1_Rst_Set; //0x0000003C + REG32 AHB1_Rst_Clr; //0x00000040 + /// This register is protected. + REG32 APB1_Rst_Set; //0x00000044 + REG32 APB1_Rst_Clr; //0x00000048 + /// This register is protected. + REG32 APB2_Rst_Set; //0x0000004C + REG32 APB2_Rst_Clr; //0x00000050 + /// This register is protected. + REG32 MEM_Rst_Set; //0x00000054 + REG32 MEM_Rst_Clr; //0x00000058 + REG32 Clk_CPU_Mode; //0x0000005C + REG32 Clk_CPU_Enable; //0x00000060 + /// This register is protected. + REG32 Clk_CPU_Disable; //0x00000064 + REG32 Clk_AXI_Mode; //0x00000068 + REG32 Clk_AXI_Enable; //0x0000006C + /// This register is protected. + REG32 Clk_AXI_Disable; //0x00000070 + REG32 Clk_AXIDIV2_Mode; //0x00000074 + REG32 Clk_AXIDIV2_Enable; //0x00000078 + /// This register is protected. + REG32 Clk_AXIDIV2_Disable; //0x0000007C + REG32 Clk_GCG_Mode; //0x00000080 + REG32 Clk_GCG_Enable; //0x00000084 + /// This register is protected. + REG32 Clk_GCG_Disable; //0x00000088 + REG32 Clk_AHB1_Mode; //0x0000008C + REG32 Clk_AHB1_Enable; //0x00000090 + /// This register is protected. + REG32 Clk_AHB1_Disable; //0x00000094 + REG32 Clk_APB1_Mode; //0x00000098 + REG32 Clk_APB1_Enable; //0x0000009C + /// This register is protected. + REG32 Clk_APB1_Disable; //0x000000A0 + REG32 Clk_APB2_Mode; //0x000000A4 + REG32 Clk_APB2_Enable; //0x000000A8 + /// This register is protected. + REG32 Clk_APB2_Disable; //0x000000AC + REG32 Clk_MEM_Mode; //0x000000B0 + REG32 Clk_MEM_Enable; //0x000000B4 + /// This register is protected. + REG32 Clk_MEM_Disable; //0x000000B8 + REG32 Clk_APO_Mode; //0x000000BC + REG32 Clk_APO_Enable; //0x000000C0 + /// This register is protected. + REG32 Clk_APO_Disable; //0x000000C4 + REG32 Cfg_Clk_AP_CPU; //0x000000C8 + REG32 Cfg_Clk_AP_AXI; //0x000000CC + REG32 Cfg_Clk_AP_GCG; //0x000000D0 + REG32 Cfg_Clk_AP_AHB1; //0x000000D4 + REG32 Cfg_Clk_AP_APB1; //0x000000D8 + REG32 Cfg_Clk_AP_APB2; //0x000000DC + REG32 Cfg_Clk_AP_MEM; //0x000000E0 + REG32 Cfg_Clk_AP_GPU; //0x000000E4 + REG32 Cfg_Clk_AP_VPU; //0x000000E8 + REG32 Cfg_Clk_AP_VOC; //0x000000EC + REG32 Cfg_Clk_AP_SFLSH; //0x000000F0 + REG32 Cfg_Clk_Uart[3]; //0x000000F4 + REG32 L2cc_Ctrl; //0x00000100 + REG32 Spi_Ctrl; //0x00000104 + REG32 Memory_Margin; //0x00000108 + REG32 Memory_Margin2; //0x0000010C + REG32 Memory_Observe; //0x00000110 + REG32 Cfg_Clk_AP_VOC2; //0x00000114 + REG32 Reserved_00000118[57]; //0x00000118 + /// This register is reserved. + REG32 Cfg_Reserve; //0x000001FC +} HWP_SYS_CTRL_AP_T; + +#define hwp_sysCtrlAp ((HWP_SYS_CTRL_AP_T*)(RDA_SYSCTRL_BASE)) + + +//REG_DBG +#define SYS_CTRL_AP_SCRATCH(n) (((n)&0xFFFF)<<0) +#define SYS_CTRL_AP_WRITE_UNLOCK_STATUS (1<<30) +#define SYS_CTRL_AP_WRITE_UNLOCK (1<<31) + +//Cfg_Pll_Ctrl +#define SYS_CTRL_AP_AP_PLL_ENABLE (1<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_MASK (1<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_SHIFT (0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN (0<<0) +#define SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE (1<<0) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET (1<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK (1<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_SHIFT (4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET (0<<4) +#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET (1<<4) +#define SYS_CTRL_AP_AP_PLL_BYPASS (1<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_MASK (1<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_SHIFT (8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_PASS (0<<8) +#define SYS_CTRL_AP_AP_PLL_BYPASS_BYPASS (1<<8) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_MASK (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_SHIFT (12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE (1<<12) +#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_DISABLE (0<<12) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(n) (((n)&31)<<16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_MASK (31<<16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_SHIFT (16) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(n) (((n)&31)<<24) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_MASK (31<<24) +#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_SHIFT (24) +#define SYS_CTRL_AP_PLL_AP_CFG(n) (((n)&0x1F1F1111)<<0) +#define SYS_CTRL_AP_PLL_AP_CFG_MASK (0x1F1F1111<<0) +#define SYS_CTRL_AP_PLL_AP_CFG_SHIFT (0) + +//Sel_Clock +#define SYS_CTRL_AP_SLOW_SEL_RF_OSCILLATOR (1<<0) +#define SYS_CTRL_AP_SLOW_SEL_RF_RF (0<<0) +#define SYS_CTRL_AP_CPU_SEL_FAST_SLOW (1<<4) +#define SYS_CTRL_AP_CPU_SEL_FAST_FAST (0<<4) +#define SYS_CTRL_AP_BUS_SEL_FAST_SLOW (1<<5) +#define SYS_CTRL_AP_BUS_SEL_FAST_FAST (0<<5) +#define SYS_CTRL_AP_TIMER_SEL_FAST_SLOW (1<<7) +#define SYS_CTRL_AP_TIMER_SEL_FAST_FAST (0<<7) +#define SYS_CTRL_AP_RF_DETECTED_OK (1<<8) +#define SYS_CTRL_AP_RF_DETECTED_NO (0<<8) +#define SYS_CTRL_AP_RF_DETECT_BYPASS (1<<9) +#define SYS_CTRL_AP_RF_DETECT_RESET (1<<10) +#define SYS_CTRL_AP_RF_SELECTED_L (1<<11) +#define SYS_CTRL_AP_PLL_LOCKED_CPU (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_MASK (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_SHIFT (12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED (1<<12) +#define SYS_CTRL_AP_PLL_LOCKED_CPU_NOT_LOCKED (0<<12) +#define SYS_CTRL_AP_PLL_LOCKED_BUS (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_MASK (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_SHIFT (13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED (1<<13) +#define SYS_CTRL_AP_PLL_LOCKED_BUS_NOT_LOCKED (0<<13) +#define SYS_CTRL_AP_PLL_LOCKED_MEM (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_MASK (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_SHIFT (14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED (1<<14) +#define SYS_CTRL_AP_PLL_LOCKED_MEM_NOT_LOCKED (0<<14) +#define SYS_CTRL_AP_PLL_LOCKED_USB (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_MASK (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_SHIFT (15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED (1<<15) +#define SYS_CTRL_AP_PLL_LOCKED_USB_NOT_LOCKED (0<<15) +#define SYS_CTRL_AP_PLL_BYPASS_LOCK_CPU (1<<20) +#define SYS_CTRL_AP_PLL_BYPASS_LOCK_BUS (1<<21) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L (1<<30) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_MASK (1<<30) +#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_SHIFT (30) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L (1<<31) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_MASK (1<<31) +#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_SHIFT (31) + +//Reset_Cause +#define SYS_CTRL_AP_WATCHDOG_RESET_HAPPENED (1<<0) +#define SYS_CTRL_AP_WATCHDOG_RESET_NO (0<<0) +#define SYS_CTRL_AP_GLOBALSOFT_RESET_HAPPENED (1<<4) +#define SYS_CTRL_AP_GLOBALSOFT_RESET_NO (0<<4) +#define SYS_CTRL_AP_HOSTDEBUG_RESET_HAPPENED (1<<5) +#define SYS_CTRL_AP_HOSTDEBUG_RESET_NO (0<<5) +#define SYS_CTRL_AP_ALARMCAUSE_HAPPENED (1<<6) +#define SYS_CTRL_AP_ALARMCAUSE_NO (0<<6) +#define SYS_CTRL_AP_BOOT_MODE(n) (((n)&0xFFFF)<<8) +#define SYS_CTRL_AP_BOOT_MODE_MASK (0xFFFF<<8) +#define SYS_CTRL_AP_BOOT_MODE_SHIFT (8) +#define SYS_CTRL_AP_SW_BOOT_MODE(n) (((n)&0x7F)<<24) +#define SYS_CTRL_AP_SW_BOOT_MODE_MASK (0x7F<<24) +#define SYS_CTRL_AP_SW_BOOT_MODE_SHIFT (24) +#define SYS_CTRL_AP_FONCTIONAL_TEST_MODE (1<<31) + +//CPU_Rst_Set +#define SYS_CTRL_AP_SET_CPU_RST_CORE (1<<0) +#define SYS_CTRL_AP_SET_CPU_RST_SYS (1<<1) +#define SYS_CTRL_AP_SOFT_RST (1<<31) +#define SYS_CTRL_AP_SET_CPU_RST(n) (((n)&3)<<0) +#define SYS_CTRL_AP_SET_CPU_RST_MASK (3<<0) +#define SYS_CTRL_AP_SET_CPU_RST_SHIFT (0) + +//CPU_Rst_Clr +#define SYS_CTRL_AP_CLR_CPU_RST_CORE (1<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_SYS (1<<1) +#define SYS_CTRL_AP_CLR_CPU_RST(n) (((n)&3)<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_MASK (3<<0) +#define SYS_CTRL_AP_CLR_CPU_RST_SHIFT (0) + +//AXI_Rst_Set +#define SYS_CTRL_AP_SET_AXI_RST_VOC (1<<0) +#define SYS_CTRL_AP_SET_AXI_RST_VOC2 (1<<1) +#define SYS_CTRL_AP_SET_AXI_RST_DMA (1<<2) +#define SYS_CTRL_AP_SET_AXI_RST_SYS (1<<3) +#define SYS_CTRL_AP_SET_AXI_RST_CONNECT (1<<4) +#define SYS_CTRL_AP_SET_AHB0_RST_GPU (1<<5) +#define SYS_CTRL_AP_SET_APB0_RST_VPU (1<<6) +#define SYS_CTRL_AP_SET_APB0_RST_IRQ (1<<7) +#define SYS_CTRL_AP_SET_AXI_RST(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_SET_AXI_RST_MASK (0xFF<<0) +#define SYS_CTRL_AP_SET_AXI_RST_SHIFT (0) + +//AXI_Rst_Clr +#define SYS_CTRL_AP_CLR_AXI_RST_VOC (1<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_VOC2 (1<<1) +#define SYS_CTRL_AP_CLR_AXI_RST_DMA (1<<2) +#define SYS_CTRL_AP_CLR_AXI_RST_SYS (1<<3) +#define SYS_CTRL_AP_CLR_AXI_RST_CONNECT (1<<4) +#define SYS_CTRL_AP_CLR_AHB0_RST_GPU (1<<5) +#define SYS_CTRL_AP_CLR_APB0_RST_VPU (1<<6) +#define SYS_CTRL_AP_CLR_APB0_RST_IRQ (1<<7) +#define SYS_CTRL_AP_CLR_AXI_RST(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_MASK (0xFF<<0) +#define SYS_CTRL_AP_CLR_AXI_RST_SHIFT (0) + +//AXIDIV2_Rst_Set +#define SYS_CTRL_AP_SET_AXIDIV2_RST_IMEM (1<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_SYS (1<<1) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_VPU (1<<2) +#define SYS_CTRL_AP_SET_AXIDIV2_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_MASK (7<<0) +#define SYS_CTRL_AP_SET_AXIDIV2_RST_SHIFT (0) + +//AXIDIV2_Rst_Clr +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_IMEM (1<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SYS (1<<1) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_VPU (1<<2) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_MASK (7<<0) +#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SHIFT (0) + +//GCG_Rst_Set +#define SYS_CTRL_AP_SET_GCG_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_GCG_RST_GOUDA (1<<1) +#define SYS_CTRL_AP_SET_GCG_RST_CAMERA (1<<2) +#define SYS_CTRL_AP_SET_GCG_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_SET_GCG_RST_MASK (7<<0) +#define SYS_CTRL_AP_SET_GCG_RST_SHIFT (0) + +//GCG_Rst_Clr +#define SYS_CTRL_AP_CLR_GCG_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_GOUDA (1<<1) +#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA (1<<2) +#define SYS_CTRL_AP_CLR_GCG_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_MASK (7<<0) +#define SYS_CTRL_AP_CLR_GCG_RST_SHIFT (0) + +//AHB1_Rst_Set +#define SYS_CTRL_AP_SET_AHB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_USBC (1<<1) +#define SYS_CTRL_AP_SET_AHB1_RST_SPIFLASH (1<<2) +#define SYS_CTRL_AP_SET_AHB1_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_MASK (7<<0) +#define SYS_CTRL_AP_SET_AHB1_RST_SHIFT (0) + +//AHB1_Rst_Clr +#define SYS_CTRL_AP_CLR_AHB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_USBC (1<<1) +#define SYS_CTRL_AP_CLR_AHB1_RST_SPIFLASH (1<<2) +#define SYS_CTRL_AP_CLR_AHB1_RST(n) (((n)&7)<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_MASK (7<<0) +#define SYS_CTRL_AP_CLR_AHB1_RST_SHIFT (0) + +//APB1_Rst_Set +#define SYS_CTRL_AP_SET_APB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_APB1_RST_TIMER (1<<1) +#define SYS_CTRL_AP_SET_APB1_RST_KEYPAD (1<<2) +#define SYS_CTRL_AP_SET_APB1_RST_GPIO (1<<3) +#define SYS_CTRL_AP_SET_APB1_RST_PWM (1<<4) +#define SYS_CTRL_AP_SET_APB1_RST_AIF (1<<5) +#define SYS_CTRL_AP_SET_APB1_RST_AIF2 (1<<6) +#define SYS_CTRL_AP_SET_APB1_RST_AUIFC (1<<7) +#define SYS_CTRL_AP_SET_APB1_RST_I2C1 (1<<8) +#define SYS_CTRL_AP_SET_APB1_RST_I2C2 (1<<9) +#define SYS_CTRL_AP_SET_APB1_RST_I2C3 (1<<10) +#define SYS_CTRL_AP_SET_APB1_RST_COM_REGS (1<<11) +#define SYS_CTRL_AP_SET_APB1_RST_DMC (1<<12) +#define SYS_CTRL_AP_SET_APB1_RST_DDRPHY_P (1<<13) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XCPU (1<<14) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BCPU (1<<15) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_AHBC (1<<16) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_DMA (1<<17) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_A2A (1<<18) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XIFC (1<<19) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BIFC (1<<20) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BAHBC (1<<21) +#define SYS_CTRL_AP_SET_APB1_RST_BB2G_MEM_BRIDGE (1<<22) +#define SYS_CTRL_AP_SET_APB1_RST(n) (((n)&0x7FFFFF)<<0) +#define SYS_CTRL_AP_SET_APB1_RST_MASK (0x7FFFFF<<0) +#define SYS_CTRL_AP_SET_APB1_RST_SHIFT (0) + +//APB1_Rst_Clr +#define SYS_CTRL_AP_CLR_APB1_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_TIMER (1<<1) +#define SYS_CTRL_AP_CLR_APB1_RST_KEYPAD (1<<2) +#define SYS_CTRL_AP_CLR_APB1_RST_GPIO (1<<3) +#define SYS_CTRL_AP_CLR_APB1_RST_PWM (1<<4) +#define SYS_CTRL_AP_CLR_APB1_RST_AIF (1<<5) +#define SYS_CTRL_AP_CLR_APB1_RST_AIF2 (1<<6) +#define SYS_CTRL_AP_CLR_APB1_RST_AUIFC (1<<7) +#define SYS_CTRL_AP_CLR_APB1_RST_I2C1 (1<<8) +#define SYS_CTRL_AP_CLR_APB1_RST_I2C2 (1<<9) +#define SYS_CTRL_AP_CLR_APB1_RST_I2C3 (1<<10) +#define SYS_CTRL_AP_CLR_APB1_RST_COM_REGS (1<<11) +#define SYS_CTRL_AP_CLR_APB1_RST_DMC (1<<12) +#define SYS_CTRL_AP_CLR_APB1_RST_DDRPHY_P (1<<13) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XCPU (1<<14) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BCPU (1<<15) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_AHBC (1<<16) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_DMA (1<<17) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_A2A (1<<18) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XIFC (1<<19) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BIFC (1<<20) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BAHBC (1<<21) +#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_MEM_BRIDGE (1<<22) +#define SYS_CTRL_AP_CLR_APB1_RST(n) (((n)&0x7FFFFF)<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_MASK (0x7FFFFF<<0) +#define SYS_CTRL_AP_CLR_APB1_RST_SHIFT (0) + +//APB2_Rst_Set +#define SYS_CTRL_AP_SET_APB2_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_APB2_RST_IFC (1<<1) +#define SYS_CTRL_AP_SET_APB2_RST_UART1 (1<<2) +#define SYS_CTRL_AP_SET_APB2_RST_UART2 (1<<3) +#define SYS_CTRL_AP_SET_APB2_RST_UART3 (1<<4) +#define SYS_CTRL_AP_SET_APB2_RST_SPI1 (1<<5) +#define SYS_CTRL_AP_SET_APB2_RST_SPI2 (1<<6) +#define SYS_CTRL_AP_SET_APB2_RST_SPI3 (1<<7) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC1 (1<<8) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC2 (1<<9) +#define SYS_CTRL_AP_SET_APB2_RST_SDMMC3 (1<<10) +#define SYS_CTRL_AP_SET_APB2_RST_NANDFLASH (1<<11) +#define SYS_CTRL_AP_SET_APB2_RST(n) (((n)&0xFFF)<<0) +#define SYS_CTRL_AP_SET_APB2_RST_MASK (0xFFF<<0) +#define SYS_CTRL_AP_SET_APB2_RST_SHIFT (0) + +//APB2_Rst_Clr +#define SYS_CTRL_AP_CLR_APB2_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_IFC (1<<1) +#define SYS_CTRL_AP_CLR_APB2_RST_UART1 (1<<2) +#define SYS_CTRL_AP_CLR_APB2_RST_UART2 (1<<3) +#define SYS_CTRL_AP_CLR_APB2_RST_UART3 (1<<4) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI1 (1<<5) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI2 (1<<6) +#define SYS_CTRL_AP_CLR_APB2_RST_SPI3 (1<<7) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC1 (1<<8) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC2 (1<<9) +#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC3 (1<<10) +#define SYS_CTRL_AP_CLR_APB2_RST_NANDFLASH (1<<11) +#define SYS_CTRL_AP_CLR_APB2_RST(n) (((n)&0xFFF)<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_MASK (0xFFF<<0) +#define SYS_CTRL_AP_CLR_APB2_RST_SHIFT (0) + +//MEM_Rst_Set +#define SYS_CTRL_AP_SET_MEM_RST_SYS (1<<0) +#define SYS_CTRL_AP_SET_MEM_RST_GPU (1<<1) +#define SYS_CTRL_AP_SET_MEM_RST_VPU (1<<2) +#define SYS_CTRL_AP_SET_MEM_RST_DMC (1<<3) +#define SYS_CTRL_AP_SET_MEM_RST_DDRPHY_P (1<<4) +#define SYS_CTRL_AP_SET_MEM_RST(n) (((n)&31)<<0) +#define SYS_CTRL_AP_SET_MEM_RST_MASK (31<<0) +#define SYS_CTRL_AP_SET_MEM_RST_SHIFT (0) + +//MEM_Rst_Clr +#define SYS_CTRL_AP_CLR_MEM_RST_SYS (1<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_GPU (1<<1) +#define SYS_CTRL_AP_CLR_MEM_RST_VPU (1<<2) +#define SYS_CTRL_AP_CLR_MEM_RST_DMC (1<<3) +#define SYS_CTRL_AP_CLR_MEM_RST_DDRPHY_P (1<<4) +#define SYS_CTRL_AP_CLR_MEM_RST(n) (((n)&31)<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_MASK (31<<0) +#define SYS_CTRL_AP_CLR_MEM_RST_SHIFT (0) + +//Clk_CPU_Mode +#define SYS_CTRL_AP_MODE_CLK_CPU_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_CPU_MANUAL (1<<0) + +//Clk_CPU_Enable +#define SYS_CTRL_AP_ENABLE_CPU_CORE (1<<0) +#define SYS_CTRL_AP_ENABLE_CPU_DUMMY (1<<1) +#define SYS_CTRL_AP_ENABLE_CLK_CPU(n) (((n)&3)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_CPU_MASK (3<<0) +#define SYS_CTRL_AP_ENABLE_CLK_CPU_SHIFT (0) + +//Clk_CPU_Disable +#define SYS_CTRL_AP_DISABLE_CPU_CORE (1<<0) +#define SYS_CTRL_AP_DISABLE_CPU_DUMMY (1<<1) +#define SYS_CTRL_AP_DISABLE_CLK_CPU(n) (((n)&3)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_CPU_MASK (3<<0) +#define SYS_CTRL_AP_DISABLE_CLK_CPU_SHIFT (0) + +//Clk_AXI_Mode +#define SYS_CTRL_AP_MODE_AHB0_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_AHB0_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB0_CONF_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB0_CONF_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_AXI_VOC_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_AXI_VOC_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_AXI_VOC2_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_AXI_VOC2_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_AXI_DMA_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_AXI_DMA_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_CLK_AXI(n) (((n)&31)<<0) +#define SYS_CTRL_AP_MODE_CLK_AXI_MASK (31<<0) +#define SYS_CTRL_AP_MODE_CLK_AXI_SHIFT (0) + +//Clk_AXI_Enable +#define SYS_CTRL_AP_ENABLE_AHB0_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB0_CONF (1<<1) +#define SYS_CTRL_AP_ENABLE_AXI_VOC (1<<2) +#define SYS_CTRL_AP_ENABLE_AXI_VOC2 (1<<3) +#define SYS_CTRL_AP_ENABLE_AXI_DMA (1<<4) +#define SYS_CTRL_AP_ENABLE_AXI_ALWAYS (1<<5) +#define SYS_CTRL_AP_ENABLE_AXI_CONNECT (1<<6) +#define SYS_CTRL_AP_ENABLE_APB0_IRQ (1<<7) +#define SYS_CTRL_AP_ENABLE_CLK_AXI(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXI_MASK (0xFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXI_SHIFT (0) + +//Clk_AXI_Disable +#define SYS_CTRL_AP_DISABLE_AHB0_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB0_CONF (1<<1) +#define SYS_CTRL_AP_DISABLE_AXI_VOC (1<<2) +#define SYS_CTRL_AP_DISABLE_AXI_VOC2 (1<<3) +#define SYS_CTRL_AP_DISABLE_AXI_DMA (1<<4) +#define SYS_CTRL_AP_DISABLE_AXI_ALWAYS (1<<5) +#define SYS_CTRL_AP_DISABLE_AXI_CONNECT (1<<6) +#define SYS_CTRL_AP_DISABLE_APB0_IRQ (1<<7) +#define SYS_CTRL_AP_DISABLE_CLK_AXI(n) (((n)&0xFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXI_MASK (0xFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXI_SHIFT (0) + +//Clk_AXIDIV2_Mode +#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_MANUAL (1<<0) + +//Clk_AXIDIV2_Enable +#define SYS_CTRL_AP_ENABLE_AXIDIV2_IMEM (1<<0) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_ALWAYS (1<<1) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_CONNECT (1<<2) +#define SYS_CTRL_AP_ENABLE_AXIDIV2_VPU (1<<3) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2(n) (((n)&15)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_MASK (15<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_SHIFT (0) + +//Clk_AXIDIV2_Disable +#define SYS_CTRL_AP_DISABLE_AXIDIV2_IMEM (1<<0) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_ALWAYS (1<<1) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_CONNECT (1<<2) +#define SYS_CTRL_AP_DISABLE_AXIDIV2_VPU (1<<3) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2(n) (((n)&15)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_MASK (15<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_SHIFT (0) + +//Clk_GCG_Mode +#define SYS_CTRL_AP_MODE_GCG_APB_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_GCG_APB_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_GCG_GOUDA_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_GCG_CAMERA_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_CLK_GCG(n) (((n)&7)<<0) +#define SYS_CTRL_AP_MODE_CLK_GCG_MASK (7<<0) +#define SYS_CTRL_AP_MODE_CLK_GCG_SHIFT (0) + +//Clk_GCG_Enable +#define SYS_CTRL_AP_ENABLE_GCG_APB_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_GCG_GOUDA (1<<1) +#define SYS_CTRL_AP_ENABLE_GCG_CAMERA (1<<2) +#define SYS_CTRL_AP_ENABLE_GCG_ALWAYS (1<<3) +#define SYS_CTRL_AP_ENABLE_GCG_CONNECT (1<<4) +#define SYS_CTRL_AP_ENABLE_CLK_GCG(n) (((n)&31)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_GCG_MASK (31<<0) +#define SYS_CTRL_AP_ENABLE_CLK_GCG_SHIFT (0) + +//Clk_GCG_Disable +#define SYS_CTRL_AP_DISABLE_GCG_APB_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_GCG_GOUDA (1<<1) +#define SYS_CTRL_AP_DISABLE_GCG_CAMERA (1<<2) +#define SYS_CTRL_AP_DISABLE_GCG_ALWAYS (1<<3) +#define SYS_CTRL_AP_DISABLE_GCG_CONNECT (1<<4) +#define SYS_CTRL_AP_DISABLE_CLK_GCG(n) (((n)&31)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_GCG_MASK (31<<0) +#define SYS_CTRL_AP_DISABLE_CLK_GCG_SHIFT (0) + +//Clk_AHB1_Mode +#define SYS_CTRL_AP_MODE_CLK_AHB1_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_AHB1_MANUAL (1<<0) + +//Clk_AHB1_Enable +#define SYS_CTRL_AP_ENABLE_AHB1_USBC (1<<0) +#define SYS_CTRL_AP_ENABLE_AHB1_ALWAYS (1<<1) +#define SYS_CTRL_AP_ENABLE_AHB1_SPIFLASH (1<<2) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1(n) (((n)&7)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1_MASK (7<<0) +#define SYS_CTRL_AP_ENABLE_CLK_AHB1_SHIFT (0) + +//Clk_AHB1_Disable +#define SYS_CTRL_AP_DISABLE_AHB1_USBC (1<<0) +#define SYS_CTRL_AP_DISABLE_AHB1_ALWAYS (1<<1) +#define SYS_CTRL_AP_DISABLE_AHB1_SPIFLASH (1<<2) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1(n) (((n)&7)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1_MASK (7<<0) +#define SYS_CTRL_AP_DISABLE_CLK_AHB1_SHIFT (0) + +//Clk_APB1_Mode +#define SYS_CTRL_AP_MODE_APB1_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APB1_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB1_AIF_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB1_AIF_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APB1_AIF2_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APB1_AIF2_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APB1_I2C1_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APB1_I2C1_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_APB1_I2C2_AUTOMATIC (0<<9) +#define SYS_CTRL_AP_MODE_APB1_I2C2_MANUAL (1<<9) +#define SYS_CTRL_AP_MODE_APB1_I2C3_AUTOMATIC (0<<10) +#define SYS_CTRL_AP_MODE_APB1_I2C3_MANUAL (1<<10) +#define SYS_CTRL_AP_MODE_APB1D_OSC_AUTOMATIC (0<<11) +#define SYS_CTRL_AP_MODE_APB1D_OSC_MANUAL (1<<11) +#define SYS_CTRL_AP_MODE_APB1D_PWM_AUTOMATIC (0<<12) +#define SYS_CTRL_AP_MODE_APB1D_PWM_MANUAL (1<<12) +#define SYS_CTRL_AP_MODE_CLK_APB1(n) (((n)&0x1FFF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APB1_MASK (0x1FFF<<0) +#define SYS_CTRL_AP_MODE_CLK_APB1_SHIFT (0) + +//Clk_APB1_Enable +#define SYS_CTRL_AP_ENABLE_APB1_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB1_AIF (1<<1) +#define SYS_CTRL_AP_ENABLE_APB1_AIF2 (1<<2) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC (1<<3) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH0 (1<<4) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH1 (1<<5) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH2 (1<<6) +#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH3 (1<<7) +#define SYS_CTRL_AP_ENABLE_APB1_I2C1 (1<<8) +#define SYS_CTRL_AP_ENABLE_APB1_I2C2 (1<<9) +#define SYS_CTRL_AP_ENABLE_APB1_I2C3 (1<<10) +#define SYS_CTRL_AP_ENABLE_APB1D_OSC (1<<11) +#define SYS_CTRL_AP_ENABLE_APB1D_PWM (1<<12) +#define SYS_CTRL_AP_ENABLE_APB1_ALWAYS (1<<13) +#define SYS_CTRL_AP_ENABLE_APB1_DAPLITE (1<<14) +#define SYS_CTRL_AP_ENABLE_APB1_TIMER (1<<15) +#define SYS_CTRL_AP_ENABLE_APB1_GPIO (1<<16) +#define SYS_CTRL_AP_ENABLE_CLK_APB1(n) (((n)&0x1FFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB1_MASK (0x1FFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB1_SHIFT (0) + +//Clk_APB1_Disable +#define SYS_CTRL_AP_DISABLE_APB1_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB1_AIF (1<<1) +#define SYS_CTRL_AP_DISABLE_APB1_AIF2 (1<<2) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC (1<<3) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH0 (1<<4) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH1 (1<<5) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH2 (1<<6) +#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH3 (1<<7) +#define SYS_CTRL_AP_DISABLE_APB1_I2C1 (1<<8) +#define SYS_CTRL_AP_DISABLE_APB1_I2C2 (1<<9) +#define SYS_CTRL_AP_DISABLE_APB1_I2C3 (1<<10) +#define SYS_CTRL_AP_DISABLE_APB1D_OSC (1<<11) +#define SYS_CTRL_AP_DISABLE_APB1D_PWM (1<<12) +#define SYS_CTRL_AP_DISABLE_APB1_ALWAYS (1<<13) +#define SYS_CTRL_AP_DISABLE_APB1_DAPLITE (1<<14) +#define SYS_CTRL_AP_DISABLE_APB1_TIMER (1<<15) +#define SYS_CTRL_AP_DISABLE_APB1_GPIO (1<<16) +#define SYS_CTRL_AP_DISABLE_CLK_APB1(n) (((n)&0x1FFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB1_MASK (0x1FFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB1_SHIFT (0) + +//Clk_APB2_Mode +#define SYS_CTRL_AP_MODE_APB2_CONF_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APB2_CONF_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APB2_IFC_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APB2_IFC_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_AUTOMATIC (0<<9) +#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_MANUAL (1<<9) +#define SYS_CTRL_AP_MODE_APB2_UART1_AUTOMATIC (0<<10) +#define SYS_CTRL_AP_MODE_APB2_UART1_MANUAL (1<<10) +#define SYS_CTRL_AP_MODE_APB2_UART2_AUTOMATIC (0<<11) +#define SYS_CTRL_AP_MODE_APB2_UART2_MANUAL (1<<11) +#define SYS_CTRL_AP_MODE_APB2_UART3_AUTOMATIC (0<<12) +#define SYS_CTRL_AP_MODE_APB2_UART3_MANUAL (1<<12) +#define SYS_CTRL_AP_MODE_APB2_SPI1_AUTOMATIC (0<<13) +#define SYS_CTRL_AP_MODE_APB2_SPI1_MANUAL (1<<13) +#define SYS_CTRL_AP_MODE_APB2_SPI2_AUTOMATIC (0<<14) +#define SYS_CTRL_AP_MODE_APB2_SPI2_MANUAL (1<<14) +#define SYS_CTRL_AP_MODE_APB2_SPI3_AUTOMATIC (0<<15) +#define SYS_CTRL_AP_MODE_APB2_SPI3_MANUAL (1<<15) +#define SYS_CTRL_AP_MODE_APB2_SDMMC1_AUTOMATIC (0<<16) +#define SYS_CTRL_AP_MODE_APB2_SDMMC1_MANUAL (1<<16) +#define SYS_CTRL_AP_MODE_APB2_SDMMC2_AUTOMATIC (0<<17) +#define SYS_CTRL_AP_MODE_APB2_SDMMC2_MANUAL (1<<17) +#define SYS_CTRL_AP_MODE_APB2_SDMMC3_AUTOMATIC (0<<18) +#define SYS_CTRL_AP_MODE_APB2_SDMMC3_MANUAL (1<<18) +#define SYS_CTRL_AP_MODE_CLK_APB2(n) (((n)&0x7FFFF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APB2_MASK (0x7FFFF<<0) +#define SYS_CTRL_AP_MODE_CLK_APB2_SHIFT (0) + +//Clk_APB2_Enable +#define SYS_CTRL_AP_ENABLE_APB2_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_APB2_IFC (1<<1) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH0 (1<<2) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH1 (1<<3) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH2 (1<<4) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH3 (1<<5) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH4 (1<<6) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH5 (1<<7) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH6 (1<<8) +#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH7 (1<<9) +#define SYS_CTRL_AP_ENABLE_APB2_UART1 (1<<10) +#define SYS_CTRL_AP_ENABLE_APB2_UART2 (1<<11) +#define SYS_CTRL_AP_ENABLE_APB2_UART3 (1<<12) +#define SYS_CTRL_AP_ENABLE_APB2_SPI1 (1<<13) +#define SYS_CTRL_AP_ENABLE_APB2_SPI2 (1<<14) +#define SYS_CTRL_AP_ENABLE_APB2_SPI3 (1<<15) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC1 (1<<16) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC2 (1<<17) +#define SYS_CTRL_AP_ENABLE_APB2_SDMMC3 (1<<18) +#define SYS_CTRL_AP_ENABLE_APB2_ALWAYS (1<<19) +#define SYS_CTRL_AP_ENABLE_APB2_NANDFLASH (1<<20) +#define SYS_CTRL_AP_ENABLE_CLK_APB2(n) (((n)&0x1FFFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB2_MASK (0x1FFFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APB2_SHIFT (0) + +//Clk_APB2_Disable +#define SYS_CTRL_AP_DISABLE_APB2_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_APB2_IFC (1<<1) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH0 (1<<2) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH1 (1<<3) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH2 (1<<4) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH3 (1<<5) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH4 (1<<6) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH5 (1<<7) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH6 (1<<8) +#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH7 (1<<9) +#define SYS_CTRL_AP_DISABLE_APB2_UART1 (1<<10) +#define SYS_CTRL_AP_DISABLE_APB2_UART2 (1<<11) +#define SYS_CTRL_AP_DISABLE_APB2_UART3 (1<<12) +#define SYS_CTRL_AP_DISABLE_APB2_SPI1 (1<<13) +#define SYS_CTRL_AP_DISABLE_APB2_SPI2 (1<<14) +#define SYS_CTRL_AP_DISABLE_APB2_SPI3 (1<<15) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC1 (1<<16) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC2 (1<<17) +#define SYS_CTRL_AP_DISABLE_APB2_SDMMC3 (1<<18) +#define SYS_CTRL_AP_DISABLE_APB2_ALWAYS (1<<19) +#define SYS_CTRL_AP_DISABLE_APB2_NANDFLASH (1<<20) +#define SYS_CTRL_AP_DISABLE_CLK_APB2(n) (((n)&0x1FFFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB2_MASK (0x1FFFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APB2_SHIFT (0) + +//Clk_MEM_Mode +#define SYS_CTRL_AP_MODE_CLK_MEM_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_CLK_MEM_MANUAL (1<<0) + +//Clk_MEM_Enable +#define SYS_CTRL_AP_ENABLE_MEM_CONF (1<<0) +#define SYS_CTRL_AP_ENABLE_MEM_DMC (1<<1) +#define SYS_CTRL_AP_ENABLE_MEM_GPU (1<<2) +#define SYS_CTRL_AP_ENABLE_MEM_VPU (1<<3) +#define SYS_CTRL_AP_ENABLE_MEM_DDRPHY_P (1<<4) +#define SYS_CTRL_AP_ENABLE_MEM_CONNECT (1<<5) +#define SYS_CTRL_AP_ENABLE_CLK_MEM(n) (((n)&0x3F)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_MEM_MASK (0x3F<<0) +#define SYS_CTRL_AP_ENABLE_CLK_MEM_SHIFT (0) + +//Clk_MEM_Disable +#define SYS_CTRL_AP_DISABLE_MEM_CONF (1<<0) +#define SYS_CTRL_AP_DISABLE_MEM_DMC (1<<1) +#define SYS_CTRL_AP_DISABLE_MEM_GPU (1<<2) +#define SYS_CTRL_AP_DISABLE_MEM_VPU (1<<3) +#define SYS_CTRL_AP_DISABLE_MEM_DDRPHY_P (1<<4) +#define SYS_CTRL_AP_DISABLE_MEM_CONNECT (1<<5) +#define SYS_CTRL_AP_DISABLE_CLK_MEM(n) (((n)&0x3F)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_MEM_MASK (0x3F<<0) +#define SYS_CTRL_AP_DISABLE_CLK_MEM_SHIFT (0) + +//Clk_APO_Mode +#define SYS_CTRL_AP_MODE_APOC_VPU_AUTOMATIC (0<<0) +#define SYS_CTRL_AP_MODE_APOC_VPU_MANUAL (1<<0) +#define SYS_CTRL_AP_MODE_APOC_BCK_AUTOMATIC (0<<1) +#define SYS_CTRL_AP_MODE_APOC_BCK_MANUAL (1<<1) +#define SYS_CTRL_AP_MODE_APOC_BCK2_AUTOMATIC (0<<2) +#define SYS_CTRL_AP_MODE_APOC_BCK2_MANUAL (1<<2) +#define SYS_CTRL_AP_MODE_APOC_UART1_AUTOMATIC (0<<3) +#define SYS_CTRL_AP_MODE_APOC_UART1_MANUAL (1<<3) +#define SYS_CTRL_AP_MODE_APOC_UART2_AUTOMATIC (0<<4) +#define SYS_CTRL_AP_MODE_APOC_UART2_MANUAL (1<<4) +#define SYS_CTRL_AP_MODE_APOC_UART3_AUTOMATIC (0<<5) +#define SYS_CTRL_AP_MODE_APOC_UART3_MANUAL (1<<5) +#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_AUTOMATIC (0<<6) +#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_MANUAL (1<<6) +#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_AUTOMATIC (0<<7) +#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_MANUAL (1<<7) +#define SYS_CTRL_AP_MODE_APOC_VOC_AUTOMATIC (0<<8) +#define SYS_CTRL_AP_MODE_APOC_VOC_MANUAL (1<<8) +#define SYS_CTRL_AP_MODE_APOC_VOC2_AUTOMATIC (0<<9) +#define SYS_CTRL_AP_MODE_APOC_VOC2_MANUAL (1<<9) +#define SYS_CTRL_AP_MODE_CLK_APO(n) (((n)&0x3FF)<<0) +#define SYS_CTRL_AP_MODE_CLK_APO_MASK (0x3FF<<0) +#define SYS_CTRL_AP_MODE_CLK_APO_SHIFT (0) + +//Clk_APO_Enable +#define SYS_CTRL_AP_ENABLE_APOC_VPU (1<<0) +#define SYS_CTRL_AP_ENABLE_APOC_BCK (1<<1) +#define SYS_CTRL_AP_ENABLE_APOC_BCK2 (1<<2) +#define SYS_CTRL_AP_ENABLE_APOC_UART1 (1<<3) +#define SYS_CTRL_AP_ENABLE_APOC_UART2 (1<<4) +#define SYS_CTRL_AP_ENABLE_APOC_UART3 (1<<5) +#define SYS_CTRL_AP_ENABLE_APOC_VOC_CORE (1<<6) +#define SYS_CTRL_AP_ENABLE_APOC_VOC2_CORE (1<<7) +#define SYS_CTRL_AP_ENABLE_APOC_VOC (1<<8) +#define SYS_CTRL_AP_ENABLE_APOC_VOC2 (1<<9) +#define SYS_CTRL_AP_ENABLE_APOC_VOC_ALWAYS (1<<10) +#define SYS_CTRL_AP_ENABLE_APOC_VOC2_ALWAYS (1<<11) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY_N (1<<12) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XP (1<<13) +#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XN (1<<14) +#define SYS_CTRL_AP_ENABLE_APOC_GPU (1<<15) +#define SYS_CTRL_AP_ENABLE_APOC_USBPHY (1<<16) +#define SYS_CTRL_AP_ENABLE_APOC_CSI (1<<17) +#define SYS_CTRL_AP_ENABLE_APOC_DSI (1<<18) +#define SYS_CTRL_AP_ENABLE_APOC_GPIO (1<<19) +#define SYS_CTRL_AP_ENABLE_APOC_SPIFLASH (1<<20) +#define SYS_CTRL_AP_ENABLE_APOC_PIX (1<<21) +#define SYS_CTRL_AP_ENABLE_APOC_PDGB (1<<22) +#define SYS_CTRL_AP_ENABLE_CLK_APO(n) (((n)&0x7FFFFF)<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APO_MASK (0x7FFFFF<<0) +#define SYS_CTRL_AP_ENABLE_CLK_APO_SHIFT (0) + +//Clk_APO_Disable +#define SYS_CTRL_AP_DISABLE_APOC_VPU (1<<0) +#define SYS_CTRL_AP_DISABLE_APOC_BCK (1<<1) +#define SYS_CTRL_AP_DISABLE_APOC_BCK2 (1<<2) +#define SYS_CTRL_AP_DISABLE_APOC_UART1 (1<<3) +#define SYS_CTRL_AP_DISABLE_APOC_UART2 (1<<4) +#define SYS_CTRL_AP_DISABLE_APOC_UART3 (1<<5) +#define SYS_CTRL_AP_DISABLE_APOC_VOC_CORE (1<<6) +#define SYS_CTRL_AP_DISABLE_APOC_VOC2_CORE (1<<7) +#define SYS_CTRL_AP_DISABLE_APOC_VOC (1<<8) +#define SYS_CTRL_AP_DISABLE_APOC_VOC2 (1<<9) +#define SYS_CTRL_AP_DISABLE_APOC_VOC_ALWAYS (1<<10) +#define SYS_CTRL_AP_DISABLE_APOC_VOC2_ALWAYS (1<<11) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY_N (1<<12) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XP (1<<13) +#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XN (1<<14) +#define SYS_CTRL_AP_DISABLE_APOC_GPU (1<<15) +#define SYS_CTRL_AP_DISABLE_APOC_USBPHY (1<<16) +#define SYS_CTRL_AP_DISABLE_APOC_CSI (1<<17) +#define SYS_CTRL_AP_DISABLE_APOC_DSI (1<<18) +#define SYS_CTRL_AP_DISABLE_APOC_GPIO (1<<19) +#define SYS_CTRL_AP_DISABLE_APOC_SPIFLASH (1<<20) +#define SYS_CTRL_AP_DISABLE_APOC_PIX (1<<21) +#define SYS_CTRL_AP_DISABLE_APOC_PDGB (1<<22) +#define SYS_CTRL_AP_DISABLE_CLK_APO(n) (((n)&0x7FFFFF)<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APO_MASK (0x7FFFFF<<0) +#define SYS_CTRL_AP_DISABLE_CLK_APO_SHIFT (0) + +//Cfg_Clk_AP_CPU +#define SYS_CTRL_AP_AP_CPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_CPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_CPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_BUS_DIV_SEL(n) (((n)&3)<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_MASK (3<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_SHIFT (16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV2 (0<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV3 (1<<16) +#define SYS_CTRL_AP_BUS_DIV_SEL_DIV4 (2<<16) +#define SYS_CTRL_AP_AP_CPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_AXI +#define SYS_CTRL_AP_AP_AXI_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_AXI_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_AXI_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_AXI_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_AXI_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_GCG +#define SYS_CTRL_AP_AP_GCG_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_GCG_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_GCG_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_GCG_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_GCG_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_AHB1 +#define SYS_CTRL_AP_AP_AHB1_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_AHB1_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_AHB1_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_AHB1_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_APB1 +#define SYS_CTRL_AP_AP_APB1_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_APB1_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_APB1_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_APB1_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_APB1_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_APB2 +#define SYS_CTRL_AP_AP_APB2_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_APB2_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_APB2_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_APB2_SRC_SEL (1<<12) +#define SYS_CTRL_AP_AP_APB2_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_MEM +#define SYS_CTRL_AP_AP_MEM_SRC_DIV2 (1<<12) + +//Cfg_Clk_AP_GPU +#define SYS_CTRL_AP_AP_GPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_GPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_GPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_GPU_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_GPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_VPU +#define SYS_CTRL_AP_AP_VPU_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_VPU_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_VPU_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_VPU_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_VPU_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_VOC +#define SYS_CTRL_AP_AP_VOC_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_AP_SFLSH +#define SYS_CTRL_AP_AP_SFLSH_FREQ(n) (((n)&31)<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_MASK (31<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_SHIFT (0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_19M (6<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_20M (7<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_300M (26<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_340M (27<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_400M (28<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_480M (29<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_600M (30<<0) +#define SYS_CTRL_AP_AP_SFLSH_FREQ_1_2G (31<<0) +#define SYS_CTRL_AP_AP_SFLSH_SRC_DIV2 (1<<12) +#define SYS_CTRL_AP_AP_SFLSH_REQ_DIV_UPDATE (1<<31) + +//Cfg_Clk_Uart +#define SYS_CTRL_AP_UART_DIVIDER(n) (((n)&0x3FF)<<0) +#define SYS_CTRL_AP_UART_DIVIDER_MASK (0x3FF<<0) +#define SYS_CTRL_AP_UART_DIVIDER_SHIFT (0) +#define SYS_CTRL_AP_UART_SEL_PLL_SLOW (0<<12) +#define SYS_CTRL_AP_UART_SEL_PLL_PLL (1<<12) + +//L2cc_Ctrl +#define SYS_CTRL_AP_ARQOS_L2CC_1_M(n) (((n)&15)<<0) +#define SYS_CTRL_AP_ARQOS_L2CC_1_M_MASK (15<<0) +#define SYS_CTRL_AP_ARQOS_L2CC_1_M_SHIFT (0) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M(n) (((n)&15)<<4) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M_MASK (15<<4) +#define SYS_CTRL_AP_AWQOS_L2CC_1_M_SHIFT (4) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<8) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_MASK (15<<8) +#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_SHIFT (8) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<12) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_MASK (15<<12) +#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_SHIFT (12) +#define SYS_CTRL_AP_ARAP_L2CC_1_M (1<<16) +#define SYS_CTRL_AP_AWAP_L2CC_1_M (1<<17) +#define SYS_CTRL_AP_ARAP_MODEM_MEM_AHBS_M (1<<18) +#define SYS_CTRL_AP_AWAP_MODEM_MEM_AHBS_M (1<<19) +#define SYS_CTRL_AP_ARAP_MERGE1M (1<<20) +#define SYS_CTRL_AP_AWAP_MERGE1M (1<<21) +#define SYS_CTRL_AP_ARAP_MERGE2M (1<<22) +#define SYS_CTRL_AP_AWAP_MERGE2M (1<<23) +#define SYS_CTRL_AP_RESERVE1(n) (((n)&0xFF)<<24) +#define SYS_CTRL_AP_RESERVE1_MASK (0xFF<<24) +#define SYS_CTRL_AP_RESERVE1_SHIFT (24) + +//Spi_Ctrl +#define SYS_CTRL_AP_LIMITED_EN_SPI1 (1<<0) +#define SYS_CTRL_AP_LPSEN_SPI1 (1<<1) +#define SYS_CTRL_AP_LIMITED_EN_SPI2 (1<<2) +#define SYS_CTRL_AP_LPSEN_SPI2 (1<<3) +#define SYS_CTRL_AP_LIMITED_EN_SPI3 (1<<4) +#define SYS_CTRL_AP_LPSEN_SPI3 (1<<5) +#define SYS_CTRL_AP_FBUSWID_NFSC (1<<6) +#define SYS_CTRL_AP_RESERVE3 (1<<7) +#define SYS_CTRL_AP_DMC_CFG(n) (((n)&0x3FF)<<8) +#define SYS_CTRL_AP_DMC_CFG_MASK (0x3FF<<8) +#define SYS_CTRL_AP_DMC_CFG_SHIFT (8) +#define SYS_CTRL_AP_RESERVE2(n) (((n)&0x3FFF)<<18) +#define SYS_CTRL_AP_RESERVE2_MASK (0x3FFF<<18) +#define SYS_CTRL_AP_RESERVE2_SHIFT (18) + +//Memory_Margin +#define SYS_CTRL_AP_EMAW_VOC(n) (((n)&3)<<0) +#define SYS_CTRL_AP_EMAW_VOC_MASK (3<<0) +#define SYS_CTRL_AP_EMAW_VOC_SHIFT (0) +#define SYS_CTRL_AP_EMA_VOC(n) (((n)&7)<<2) +#define SYS_CTRL_AP_EMA_VOC_MASK (7<<2) +#define SYS_CTRL_AP_EMA_VOC_SHIFT (2) +#define SYS_CTRL_AP_EMAW_VPU(n) (((n)&3)<<5) +#define SYS_CTRL_AP_EMAW_VPU_MASK (3<<5) +#define SYS_CTRL_AP_EMAW_VPU_SHIFT (5) +#define SYS_CTRL_AP_EMA_VPU(n) (((n)&7)<<7) +#define SYS_CTRL_AP_EMA_VPU_MASK (7<<7) +#define SYS_CTRL_AP_EMA_VPU_SHIFT (7) +#define SYS_CTRL_AP_EMAW_GPU(n) (((n)&3)<<10) +#define SYS_CTRL_AP_EMAW_GPU_MASK (3<<10) +#define SYS_CTRL_AP_EMAW_GPU_SHIFT (10) +#define SYS_CTRL_AP_EMA_GPU(n) (((n)&7)<<12) +#define SYS_CTRL_AP_EMA_GPU_MASK (7<<12) +#define SYS_CTRL_AP_EMA_GPU_SHIFT (12) +#define SYS_CTRL_AP_EMAW_GOUDA(n) (((n)&3)<<15) +#define SYS_CTRL_AP_EMAW_GOUDA_MASK (3<<15) +#define SYS_CTRL_AP_EMAW_GOUDA_SHIFT (15) +#define SYS_CTRL_AP_EMA_GOUDA(n) (((n)&7)<<17) +#define SYS_CTRL_AP_EMA_GOUDA_MASK (7<<17) +#define SYS_CTRL_AP_EMA_GOUDA_SHIFT (17) +#define SYS_CTRL_AP_EMAW_IMEM(n) (((n)&3)<<20) +#define SYS_CTRL_AP_EMAW_IMEM_MASK (3<<20) +#define SYS_CTRL_AP_EMAW_IMEM_SHIFT (20) +#define SYS_CTRL_AP_EMA_IMEM(n) (((n)&7)<<22) +#define SYS_CTRL_AP_EMA_IMEM_MASK (7<<22) +#define SYS_CTRL_AP_EMA_IMEM_SHIFT (22) +#define SYS_CTRL_AP_EMAW_USB(n) (((n)&3)<<25) +#define SYS_CTRL_AP_EMAW_USB_MASK (3<<25) +#define SYS_CTRL_AP_EMAW_USB_SHIFT (25) +#define SYS_CTRL_AP_EMA_USB(n) (((n)&7)<<27) +#define SYS_CTRL_AP_EMA_USB_MASK (7<<27) +#define SYS_CTRL_AP_EMA_USB_SHIFT (27) + +//Memory_Margin2 +#define SYS_CTRL_AP_EMAW_NFSC(n) (((n)&3)<<0) +#define SYS_CTRL_AP_EMAW_NFSC_MASK (3<<0) +#define SYS_CTRL_AP_EMAW_NFSC_SHIFT (0) +#define SYS_CTRL_AP_EMA_NFSC(n) (((n)&7)<<2) +#define SYS_CTRL_AP_EMA_NFSC_MASK (7<<2) +#define SYS_CTRL_AP_EMA_NFSC_SHIFT (2) +#define SYS_CTRL_AP_EMA_VPUROM(n) (((n)&7)<<5) +#define SYS_CTRL_AP_EMA_VPUROM_MASK (7<<5) +#define SYS_CTRL_AP_EMA_VPUROM_SHIFT (5) +#define SYS_CTRL_AP_EMA_IMEMROM(n) (((n)&7)<<8) +#define SYS_CTRL_AP_EMA_IMEMROM_MASK (7<<8) +#define SYS_CTRL_AP_EMA_IMEMROM_SHIFT (8) +#define SYS_CTRL_AP_KEN_VPUROM (1<<11) +#define SYS_CTRL_AP_PGEN_VPUROM (1<<12) +#define SYS_CTRL_AP_KEN_IMEMROM (1<<13) +#define SYS_CTRL_AP_PGEN_IMEMROM (1<<14) + +//Memory_Observe +#define SYS_CTRL_AP_MEM_OBSERVE(n) (((n)&0xFFFFFFFF)<<0) + +//Cfg_Clk_AP_VOC2 +//#define SYS_CTRL_AP_AP_VOC_FREQ(n) (((n)&31)<<0) +//#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0) +//#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0) +//#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0) +//#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0) +//#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0) +//#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0) +//#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0) +//#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0) +//#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0) +//#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0) +//#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12) +//#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31) + +//Cfg_Reserve +#define SYS_CTRL_AP_RESERVE(n) (((n)&0x3FFFFFFF)<<0) +#define SYS_CTRL_AP_AUIFC_CH0_IRQ_MASK (1<<30) +#define SYS_CTRL_AP_AUIFC_CH1_IRQ_MASK (1<<31) + + + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/reg_timer.h b/arch/arm/include/asm/arch-rda/reg_timer.h new file mode 100644 index 0000000000..80a4021caa --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_timer.h @@ -0,0 +1,112 @@ +#ifndef _REG_TIMER_H_ +#define _REG_TIMER_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +// ============================================================================= +// MACROS +// ============================================================================= +#define NB_INTERVAL (1) +#define INT_TIMER_NB_BITS (56) +#define HW_TIMER_NB_BITS (64) + +// ============================================================================ +// TIMER_AP_T +// ----------------------------------------------------------------------------- +typedef volatile struct +{ + REG32 OSTimer_LoadVal_L; //0x00000000 + REG32 OSTimer_Ctrl; //0x00000004 + REG32 OSTimer_CurVal_L; //0x00000008 + REG32 OSTimer_CurVal_H; //0x0000000C + REG32 OSTimer_LockVal_L; //0x00000010 + REG32 OSTimer_LockVal_H; //0x00000014 + REG32 HWTimer_Ctrl; //0x00000018 + REG32 HWTimer_CurVal_L; //0x0000001C + REG32 HWTimer_CurVal_H; //0x00000020 + REG32 HWTimer_LockVal_L; //0x00000024 + REG32 HWTimer_LockVal_H; //0x00000028 + REG32 Timer_Irq_Mask_Set; //0x0000002C + REG32 Timer_Irq_Mask_Clr; //0x00000030 + REG32 Timer_Irq_Clr; //0x00000034 + REG32 Timer_Irq_Cause; //0x00000038 +} HWP_TIMER_AP_T; + +#define hwp_apTimer ((HWP_TIMER_AP_T*)(RDA_TIMER_BASE)) + +//OSTimer_LoadVal_L +#define TIMER_AP_OS_LOADVAL_L(n) (((n)&0xFFFFFFFF)<<0) + +//OSTimer_Ctrl +#define TIMER_AP_OS_LOADVAL_H(n) (((n)&0xFFFFFF)<<0) +#define TIMER_AP_OS_LOADVAL_H_MASK (0xFFFFFF<<0) +#define TIMER_AP_OS_LOADVAL_H_SHIFT (0) +#define TIMER_AP_ENABLE (1<<24) +#define TIMER_AP_ENABLED (1<<25) +#define TIMER_AP_CLEARED (1<<26) +#define TIMER_AP_REPEAT (1<<28) +#define TIMER_AP_WRAP (1<<29) +#define TIMER_AP_LOAD (1<<30) + +//OSTimer_CurVal_L +#define TIMER_AP_OS_CURVAL_L(n) (((n)&0xFFFFFFFF)<<0) + +//OSTimer_CurVal_H +#define TIMER_AP_OS_CURVAL_H(n) (((n)&0xFFFFFF)<<0) +#define TIMER_AP_OS_CURVAL_H_MASK (0xFFFFFF<<0) +#define TIMER_AP_OS_CURVAL_H_SHIFT (0) + +//OSTimer_LockVal_L +#define TIMER_AP_OS_LOCKVAL_L(n) (((n)&0xFFFFFFFF)<<0) +#define TIMER_AP_OS_LOCKVAL_L_MASK (0xFFFFFFFF<<0) +#define TIMER_AP_OS_LOCKVAL_L_SHIFT (0) + +//OSTimer_LockVal_H +#define TIMER_AP_OS_LOCKVAL_H(n) (((n)&0xFFFFFF)<<0) +#define TIMER_AP_OS_LOCKVAL_H_MASK (0xFFFFFF<<0) +#define TIMER_AP_OS_LOCKVAL_H_SHIFT (0) + +//HWTimer_Ctrl +#define TIMER_AP_INTERVAL_EN (1<<8) +#define TIMER_AP_INTERVAL(n) (((n)&3)<<0) + +//HWTimer_CurVal_L +#define TIMER_AP_HW_CURVAL_L(n) (((n)&0xFFFFFFFF)<<0) + +//HWTimer_CurVal_H +#define TIMER_AP_HW_CURVAL_H(n) (((n)&0xFFFFFFFF)<<0) + +//HWTimer_LockVal_L +#define TIMER_AP_HW_LOCKVAL_L(n) (((n)&0xFFFFFFFF)<<0) + +//HWTimer_LockVal_H +#define TIMER_AP_HW_LOCKVAL_H(n) (((n)&0xFFFFFFFF)<<0) + +//Timer_Irq_Mask_Set +#define TIMER_AP_OSTIMER_MASK (1<<0) +#define TIMER_AP_HWTIMER_WRAP_MASK (1<<1) +#define TIMER_AP_HWTIMER_ITV_MASK (1<<2) + +//Timer_Irq_Mask_Clr +//#define TIMER_AP_OSTIMER_MASK (1<<0) +//#define TIMER_AP_HWTIMER_WRAP_MASK (1<<1) +//#define TIMER_AP_HWTIMER_ITV_MASK (1<<2) + +//Timer_Irq_Clr +#define TIMER_AP_OSTIMER_CLR (1<<0) +#define TIMER_AP_HWTIMER_WRAP_CLR (1<<1) +#define TIMER_AP_HWTIMER_ITV_CLR (1<<2) + +//Timer_Irq_Cause +#define TIMER_AP_OSTIMER_CAUSE (1<<0) +#define TIMER_AP_HWTIMER_WRAP_CAUSE (1<<1) +#define TIMER_AP_HWTIMER_ITV_CAUSE (1<<2) +#define TIMER_AP_OSTIMER_STATUS (1<<16) +#define TIMER_AP_HWTIMER_WRAP_STATUS (1<<17) +#define TIMER_AP_HWTIMER_ITV_STATUS (1<<18) +#define TIMER_AP_OTHER_TIMS_IRQ(n) (((n)&3)<<1) +#define TIMER_AP_OTHER_TIMS_IRQ_MASK (3<<1) +#define TIMER_AP_OTHER_TIMS_IRQ_SHIFT (1) + +#endif /* _REG_TIMER_H_ */ diff --git a/arch/arm/include/asm/arch-rda/reg_uart.h b/arch/arm/include/asm/arch-rda/reg_uart.h new file mode 100644 index 0000000000..f3d5a7fdd0 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_uart.h @@ -0,0 +1,478 @@ +#ifndef _REG_UART_H_ +#define _REG_UART_H_ + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + +#define UART_RX_FIFO_SIZE (32) +#define UART_TX_FIFO_SIZE (16) +#define NB_RX_FIFO_BITS (5) +#define NB_TX_FIFO_BITS (4) + +typedef volatile struct +{ + REG32 ctrl; //0x00000000 + REG32 status; //0x00000004 + REG32 rxtx_buffer; //0x00000008 + REG32 irq_mask; //0x0000000C + REG32 irq_cause; //0x00000010 + REG32 triggers; //0x00000014 + REG32 CMD_Set; //0x00000018 + REG32 CMD_Clr; //0x0000001C +} HWP_UART_T; + +#define hwp_uart1 ((HWP_UART_T*)(RDA_UART1_BASE)) +#define hwp_uart2 ((HWP_UART_T*)(RDA_UART2_BASE)) +#define hwp_uart3 ((HWP_UART_T*)(RDA_UART3_BASE)) +#define hwp_uart hwp_uart3 + +//ctrl +#define UART_ENABLE (1<<0) +#define UART_ENABLE_DISABLE (0<<0) +#define UART_ENABLE_ENABLE (1<<0) +#define UART_DATA_BITS (1<<1) +#define UART_DATA_BITS_7_BITS (0<<1) +#define UART_DATA_BITS_8_BITS (1<<1) +#define UART_TX_STOP_BITS (1<<2) +#define UART_TX_STOP_BITS_1_BIT (0<<2) +#define UART_TX_STOP_BITS_2_BITS (1<<2) +#define UART_PARITY_ENABLE (1<<3) +#define UART_PARITY_ENABLE_NO (0<<3) +#define UART_PARITY_ENABLE_YES (1<<3) +#define UART_PARITY_SELECT(n) (((n)&3)<<4) +#define UART_PARITY_SELECT_ODD (0<<4) +#define UART_PARITY_SELECT_EVEN (1<<4) +#define UART_PARITY_SELECT_SPACE (2<<4) +#define UART_PARITY_SELECT_MARK (3<<4) +#define UART_DIVISOR_MODE (1<<20) +#define UART_IRDA_ENABLE (1<<21) +#define UART_DMA_MODE (1<<22) +#define UART_DMA_MODE_DISABLE (0<<22) +#define UART_DMA_MODE_ENABLE (1<<22) +#define UART_AUTO_FLOW_CONTROL (1<<23) +#define UART_AUTO_FLOW_CONTROL_ENABLE (1<<23) +#define UART_AUTO_FLOW_CONTROL_DISABLE (0<<23) +#define UART_LOOP_BACK_MODE (1<<24) +#define UART_RX_LOCK_ERR (1<<25) +#define UART_RX_BREAK_LENGTH(n) (((n)&15)<<28) + +//status +#define UART_RX_FIFO_LEVEL(n) (((n)&0x3F)<<0) +#define UART_RX_FIFO_LEVEL_MASK (0x3F<<0) +#define UART_RX_FIFO_LEVEL_SHIFT (0) +#define UART_TX_FIFO_SPACE(n) (((n)&31)<<8) +#define UART_TX_FIFO_SPACE_MASK (31<<8) +#define UART_TX_FIFO_SPACE_SHIFT (8) +#define UART_TX_ACTIVE (1<<14) +#define UART_RX_ACTIVE (1<<15) +#define UART_RX_OVERFLOW_ERR (1<<16) +#define UART_TX_OVERFLOW_ERR (1<<17) +#define UART_RX_PARITY_ERR (1<<18) +#define UART_RX_FRAMING_ERR (1<<19) +#define UART_RX_BREAK_INT (1<<20) +#define UART_DCTS (1<<24) +#define UART_CTS (1<<25) +#define UART_DTR (1<<28) +#define UART_CLK_ENABLED (1<<31) + +//rxtx_buffer +#define UART_RX_DATA(n) (((n)&0xFF)<<0) +#define UART_TX_DATA(n) (((n)&0xFF)<<0) + +//irq_mask +#define UART_TX_MODEM_STATUS (1<<0) +#define UART_RX_DATA_AVAILABLE (1<<1) +#define UART_TX_DATA_NEEDED (1<<2) +#define UART_RX_TIMEOUT (1<<3) +#define UART_RX_LINE_ERR (1<<4) +#define UART_TX_DMA_DONE (1<<5) +#define UART_RX_DMA_DONE (1<<6) +#define UART_RX_DMA_TIMEOUT (1<<7) +#define UART_DTR_RISE (1<<8) +#define UART_DTR_FALL (1<<9) + +//irq_cause +//#define UART_TX_MODEM_STATUS (1<<0) +//#define UART_RX_DATA_AVAILABLE (1<<1) +//#define UART_TX_DATA_NEEDED (1<<2) +//#define UART_RX_TIMEOUT (1<<3) +//#define UART_RX_LINE_ERR (1<<4) +//#define UART_TX_DMA_DONE (1<<5) +//#define UART_RX_DMA_DONE (1<<6) +//#define UART_RX_DMA_TIMEOUT (1<<7) +//#define UART_DTR_RISE (1<<8) +//#define UART_DTR_FALL (1<<9) +#define UART_TX_MODEM_STATUS_U (1<<16) +#define UART_RX_DATA_AVAILABLE_U (1<<17) +#define UART_TX_DATA_NEEDED_U (1<<18) +#define UART_RX_TIMEOUT_U (1<<19) +#define UART_RX_LINE_ERR_U (1<<20) +#define UART_TX_DMA_DONE_U (1<<21) +#define UART_RX_DMA_DONE_U (1<<22) +#define UART_RX_DMA_TIMEOUT_U (1<<23) +#define UART_DTR_RISE_U (1<<24) +#define UART_DTR_FALL_U (1<<25) + +//triggers +#define UART_RX_TRIGGER(n) (((n)&31)<<0) +#define UART_TX_TRIGGER(n) (((n)&15)<<8) +#define UART_AFC_LEVEL(n) (((n)&31)<<16) + +//CMD_Set +#define UART_RI (1<<0) +#define UART_DCD (1<<1) +#define UART_DSR (1<<2) +#define UART_TX_BREAK_CONTROL (1<<3) +#define UART_TX_FINISH_N_WAIT (1<<4) +#define UART_RTS (1<<5) +#define UART_RX_FIFO_RESET (1<<6) +#define UART_TX_FIFO_RESET (1<<7) + +//CMD_Clr +//#define UART_RI (1<<0) +//#define UART_DCD (1<<1) +//#define UART_DSR (1<<2) +//#define UART_TX_BREAK_CONTROL (1<<3) +//#define UART_TX_FINISH_N_WAIT (1<<4) +//#define UART_RTS (1<<5) + +#define CHIP_STD_UART_QTY 2 + +// ============================================================================= +// MACROS +// ============================================================================= + +// ============================================================================ +// HAL_UART_DATA_BITS_T +// ----------------------------------------------------------------------------- +/// UART data length +// ============================================================================= +typedef enum +{ +/// Data is 7 bits + HAL_UART_7_DATA_BITS = 0x00000000, +/// Data is 8 bits + HAL_UART_8_DATA_BITS = 0x00000001, + HAL_UART_DATA_BITS_QTY = 0x00000002 +} HAL_UART_DATA_BITS_T; + + +// ============================================================================ +// HAL_UART_STOP_BITS_QTY_T +// ----------------------------------------------------------------------------- +/// Number of stop bits +// ============================================================================= +typedef enum +{ +/// There is 1 stop bit + HAL_UART_1_STOP_BIT = 0x00000000, +/// There are 2 stop bits + HAL_UART_2_STOP_BITS = 0x00000001, + HAL_UART_STOP_BITS_QTY = 0x00000002 +} HAL_UART_STOP_BITS_QTY_T; + + +// ============================================================================ +// HAL_UART_PARITY_CFG_T +// ----------------------------------------------------------------------------- +/// Data parity control selection If enabled, a parity check can be performed +// ============================================================================= +typedef enum +{ +/// No parity check + HAL_UART_NO_PARITY = 0x00000000, +/// Parity check is odd + HAL_UART_ODD_PARITY = 0x00000001, +/// Parity check is even + HAL_UART_EVEN_PARITY = 0x00000002, +/// Parity check is always 0 (space) + HAL_UART_SPACE_PARITY = 0x00000003, +/// Parity check is always 1 (mark) + HAL_UART_MARK_PARITY = 0x00000004, + HAL_UART_PARITY_QTY = 0x00000005 +} HAL_UART_PARITY_CFG_T; + + +// ============================================================================ +// HAL_UART_RX_TRIGGER_CFG_T +// ----------------------------------------------------------------------------- +/// Reception FIFO trigger (or treshold) level The Uarts can be configured to generate +/// an interrupt when the reception FIFO is above a configurable threshold (Rx FIFO +/// trigger +// ============================================================================= +typedef enum +{ +/// One data received in the Rx FIFO + HAL_UART_RX_TRIG_1 = 0x00000000, +/// 1/4 of the Rx FIFO is full + HAL_UART_RX_TRIG_QUARTER = 0x00000001, +/// 1/2 of the Rx FIFO is full + HAL_UART_RX_TRIG_HALF = 0x00000002, +/// Rx FIFO is almost full + HAL_UART_RX_TRIG_NEARFULL = 0x00000003, + HAL_UART_RX_TRIG_QTY = 0x00000004 +} HAL_UART_RX_TRIGGER_CFG_T; + + +// ============================================================================ +// HAL_UART_TX_TRIGGER_CFG_T +// ----------------------------------------------------------------------------- +/// Tranmission FIFO trigger (or treshold) level. The Uarts can be configured to +/// generate an interrupt when the emission FIFO is below a configurable threshold +/// (Tx FIFO trigger +// ============================================================================= +typedef enum +{ +/// Tx FIFO empty + HAL_UART_TX_TRIG_EMPTY = 0x00000000, +/// Less than 1/4 of the Tx FIFO left to send + HAL_UART_TX_TRIG_QUARTER = 0x00000001, +/// Less than 1/2 of the Tx FIFO left to send + HAL_UART_TX_TRIG_HALF = 0x00000002, +/// Less thant 3/4 of the Tx FIFO left to send + HAL_UART_TX_TRIG_3QUARTER = 0x00000003, + HAL_UART_TX_TRIG_QTY = 0x00000004 +} HAL_UART_TX_TRIGGER_CFG_T; + + +// ============================================================================ +// HAL_UART_AFC_MODE_T +// ----------------------------------------------------------------------------- +/// Auto Flow Control. Controls the Rx Fifo level at which the Uart_RTS Auto Flow +/// Control will be set inactive high (see UART Operation for more details on AFC). +/// The Uart_RTS Auto Flow Control will be set inactive high when quantity of data +/// in Rx Fifo &gt; AFC Level +// ============================================================================= +typedef enum +{ +/// RTS inactive with 1 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_1 = 0x00000000, +/// RTS inactive with 2 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_2 = 0x00000001, +/// RTS inactive with 3 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_3 = 0x00000002, +/// RTS inactive with 4 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_4 = 0x00000003, +/// RTS inactive with 5 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_5 = 0x00000004, +/// RTS inactive with 6 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_6 = 0x00000005, +/// RTS inactive with 7 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_7 = 0x00000006, +/// RTS inactive with 8 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_8 = 0x00000007, +/// RTS inactive with 9 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_9 = 0x00000008, +/// RTS inactive with 10 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_10 = 0x00000009, +/// RTS inactive with 11 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_11 = 0x0000000A, +/// RTS inactive with 12 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_12 = 0x0000000B, +/// RTS inactive with 13 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_13 = 0x0000000C, +/// RTS inactive with 14 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_14 = 0x0000000D, +/// RTS inactive with 15 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_15 = 0x0000000E, +/// RTS inactive with 16 data in the Rx FIFO + HAL_UART_AFC_MODE_RX_TRIG_16 = 0x0000000F, +/// Hardware flow control is disabled. \n &lt;B&gt; NEVER USE THIS MODE &lt;/B&gt; + HAL_UART_AFC_MODE_DISABLE = 0x00000010, + HAL_UART_AFC_MODE_QTY = 0x00000011, +/// AFC mode is loopback \n When set, data on the Uart_Tx line is held high, while +/// the serial output is looped back to the serial input line, internally. + HAL_UART_AFC_LOOP_BACK = 0x00000020 +} HAL_UART_AFC_MODE_T; + + +// ============================================================================ +// HAL_UART_IRDA_MODE_T +// ----------------------------------------------------------------------------- +/// IrDA protocole enabling IrDA SIR mode is available, and can be activated when +/// the user open the Uart +// ============================================================================= +typedef enum +{ +/// IrDA mode disabled + HAL_UART_IRDA_MODE_DISABLE = 0x00000000, +/// IrDA mode enabled + HAL_UART_IRDA_MODE_ENABLE = 0x00000001, + HAL_UART_IRDA_MODE_QTY = 0x00000002 +} HAL_UART_IRDA_MODE_T; + + +// ============================================================================ +// HAL_UART_BAUD_RATE_T +// ----------------------------------------------------------------------------- +/// Baudrate available with the modifiable system clock UARTs are able to run at +/// a wide selection of baud rates. This must be configured at the UART opening +// ============================================================================= +typedef enum +{ +/// 2.4 KBaud (Serial and IrDA) + HAL_UART_BAUD_RATE_2400 = 0x00000960, +/// 4.8 KBaud (Serial and IrDA) + HAL_UART_BAUD_RATE_4800 = 0x000012C0, +/// 9.6 KBaud (Serial and IrDA) + HAL_UART_BAUD_RATE_9600 = 0x00002580, +/// 14.4 KBaud (Serial and IrDA) + HAL_UART_BAUD_RATE_14400 = 0x00003840, +/// 19.2 KBaud (Serial and IrDA) + HAL_UART_BAUD_RATE_19200 = 0x00004B00, +/// 28.8 KBaud (Serial and IrDA) + HAL_UART_BAUD_RATE_28800 = 0x00007080, +/// 33.6 KBaud (Serial and IrDA) + HAL_UART_BAUD_RATE_33600 = 0x00008340, +/// 38.4 KBaud (Serial and IrDA) + HAL_UART_BAUD_RATE_38400 = 0x00009600, +/// 57.6 KBaud (Serial and IrDA) + HAL_UART_BAUD_RATE_57600 = 0x0000E100, +/// 115.2 KBaud (Serial and IrDA) + HAL_UART_BAUD_RATE_115200 = 0x0001C200, +/// 230.4 KBaud (Available only in serial mode) + HAL_UART_BAUD_RATE_230400 = 0x00038400, +/// 460.8 KBaud (Available only in serial mode) + HAL_UART_BAUD_RATE_460800 = 0x00070800, +/// 921.6 KBaud (Available only in serial mode) + HAL_UART_BAUD_RATE_921600 = 0x000E1000, +/// 1843.2 KBaud (Available only in serial mode) + HAL_UART_BAUD_RATE_1843200 = 0x001C2000, + HAL_UART_BAUD_RATE_QTY = 0x001C2001 +} HAL_UART_BAUD_RATE_T; + + +// ============================================================================ +// HAL_UART_TRANSFERT_MODE_T +// ----------------------------------------------------------------------------- +/// Data transfert mode: via DMA or direct. To allow for an easy use of the Uart +/// modules, a non blocking hardware abstraction layer interface is provided +// ============================================================================= +typedef enum +{ +/// Direct polling: The application sends/receives the data directly to/from the +/// hardware module. The number of bytes actually sent/received is returned. No IRQ +/// is generated. + HAL_UART_TRANSFERT_MODE_DIRECT_POLLING = 0x00000000, +/// Direct Irq: The application sends/receives the data directly to/from the hardware +/// module. The number of bytes actually sent/received is returned.An irq can be +/// generated when the Tx/Rx FIFO reaches the pre-programmed level. + HAL_UART_TRANSFERT_MODE_DIRECT_IRQ = 0x00000001, +/// DMA polling: The application sends/receives the data through a DMA to the hardware +/// module. When no DMA channel is available, the function returns 0. No byte is +/// sent. When a DMA resource is available, the function returns the number of bytes +/// to send. They will all be sent. A function allows to check if the previous DMA +/// transfer is finished. No new DMA transfer for the same Uart and in the same direction +/// is allowed until the previous transfer is finished. + HAL_UART_TRANSFERT_MODE_DMA_POLLING = 0x00000002, +/// The application sends/receives the data through a DMA to the hardware module. +/// When no DMA channel is available, the function returns 0. No byte is sent. When +/// a DMA resource is available, the function returns the number of bytes to send. +/// They will all be sent. An Irq is generated when the current transfer is finished. +/// No new DMA transfer for the same Uart and in the same direction is allowed until +/// the previous transfer is finished. + HAL_UART_TRANSFERT_MODE_DMA_IRQ = 0x00000003, +/// The transfert is off. + HAL_UART_TRANSFERT_MODE_OFF = 0x00000004, + HAL_UART_TRANSFERT_MODE_QTY = 0x00000005 +} HAL_UART_TRANSFERT_MODE_T; + + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// HAL_UART_CFG_T +// ----------------------------------------------------------------------------- +/// UART Configuration Structure This structure defines the Uart behavior +// ============================================================================= +typedef struct +{ + /// Data format + HAL_UART_DATA_BITS_T data; //0x00000000 + /// Number of stop bits + HAL_UART_STOP_BITS_QTY_T stop; //0x00000004 + /// Parity check + HAL_UART_PARITY_CFG_T parity; //0x00000008 + /// Trigger for the Rx FIFO + HAL_UART_RX_TRIGGER_CFG_T rx_trigger; //0x0000000C + /// Trigger for the Tx FIFO + HAL_UART_TX_TRIGGER_CFG_T tx_trigger; //0x00000010 + /// Hardware Flow control + HAL_UART_AFC_MODE_T afc; //0x00000014 + /// IrDA mode + HAL_UART_IRDA_MODE_T irda; //0x00000018 + /// Baud Rate + HAL_UART_BAUD_RATE_T rate; //0x0000001C + /// Reception transfer mode + HAL_UART_TRANSFERT_MODE_T rx_mode; //0x00000020 + /// Transmission transfer mode + HAL_UART_TRANSFERT_MODE_T tx_mode; //0x00000024 +} HAL_UART_CFG_T; //Size : 0x28 + + + +// ============================================================================ +// HAL_UART_IRQ_STATUS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef struct +{ + u32 txModemStatus:1; + u32 rxDataAvailable:1; + u32 txDataNeeded:1; + u32 rxTimeout:1; + u32 rxLineErr:1; + u32 txDmaDone:1; + u32 rxDmaDone:1; + u32 rxDmaTimeout:1; +} HAL_UART_IRQ_STATUS_T; +//unused +#define HAL_UART_IRQ_STATUS_TXMODEMSTATUS (1<<0) +#define HAL_UART_IRQ_STATUS_RXDATAAVAILABLE (1<<1) +#define HAL_UART_IRQ_STATUS_TXDATANEEDED (1<<2) +#define HAL_UART_IRQ_STATUS_RXTIMEOUT (1<<3) +#define HAL_UART_IRQ_STATUS_RXLINEERR (1<<4) +#define HAL_UART_IRQ_STATUS_TXDMADONE (1<<5) +#define HAL_UART_IRQ_STATUS_RXDMADONE (1<<6) +#define HAL_UART_IRQ_STATUS_RXDMATIMEOUT (1<<7) + + + +// ============================================================================ +// HAL_UART_ERROR_STATUS_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef struct +{ + u32 _:4; + u32 rxOvflErr:1; + u32 txOvflErr:1; + u32 rxParityErr:1; + u32 rxFramingErr:1; + u32 rxBreakInt:1; +} HAL_UART_ERROR_STATUS_T; +//unused +#define HAL_UART_ERROR_STATUS__(n) (((n)&15)<<0) +#define HAL_UART_ERROR_STATUS_RXOVFLERR (1<<4) +#define HAL_UART_ERROR_STATUS_TXOVFLERR (1<<5) +#define HAL_UART_ERROR_STATUS_RXPARITYERR (1<<6) +#define HAL_UART_ERROR_STATUS_RXFRAMINGERR (1<<7) +#define HAL_UART_ERROR_STATUS_RXBREAKINT (1<<8) + + +/// Uart 0 is the trace uart and is unavailable for this driver +/// The numbering starts at 1 for consistency. +/// The HAL_UART_QTY value is defined as the number of UARTS +/// avalaible for the chip on which the driver is running, and +/// can therefore be used for consistency checks +typedef enum { + HAL_UART_1 = 0x00000001, + HAL_UART_2 = 0x00000002, + HAL_UART_QTY = CHIP_STD_UART_QTY+1 +} HAL_UART_ID_T; + +#endif /* _REG_UART_H_ */ diff --git a/arch/arm/include/asm/arch-rda/reg_xcpu.h b/arch/arm/include/asm/arch-rda/reg_xcpu.h new file mode 100644 index 0000000000..166fbaff89 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/reg_xcpu.h @@ -0,0 +1,314 @@ +//============================================================================== +// +// Copyright (C) 2012-2013, RDA Microelectronics. +// All Rights Reserved +// +// This source code is the property of RDA Microelectronics and is +// confidential. Any modification, distribution, reproduction or +// exploitation of any content of this file is totally forbidden, +// except with the written permission of RDA Microelectronics. +// +//============================================================================== +// +// THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML. +// +// !!! PLEASE DO NOT EDIT !!! +// +// $HeadURL$ +// $Author$ +// $Date$ +// $Revision$ +// +//============================================================================== +// +/// @file +// +//============================================================================== + +#ifndef _XCPU_H_ +#define _XCPU_H_ + +#ifdef CT_ASM +#error "You are trying to use in an assembly code the normal H description of 'xcpu'." +#endif + +#include <asm/arch/hardware.h> +#include <asm/arch/rda_iomap.h> + + +// ============================================================================= +// MACROS +// ============================================================================= + +// ============================================================================= +// TYPES +// ============================================================================= + +// ============================================================================ +// XCPU_T +// ----------------------------------------------------------------------------- +/// +// ============================================================================= +typedef volatile struct +{ + REG32 Reserved_00000000; //0x00000000 + REG32 rf0_addr; //0x00000004 + REG32 Reserved_00000008[97]; //0x00000008 + REG32 cp0_adr_BadVAddr; //0x0000018C + REG32 cp0_Cause; //0x00000190 + REG32 cp0_Status; //0x00000194 + REG32 cp0_EPC; //0x00000198 + REG32 Reserved_0000019C[5]; //0x0000019C + REG32 cp0_BadVAddr; //0x000001B0 + REG32 Reserved_000001B4[19]; //0x000001B4 + REG32 rf0_data; //0x00000200 + REG32 Reserved_00000204[5]; //0x00000204 + REG32 dc0_result; //0x00000218 + REG32 Reserved_0000021C[89]; //0x0000021C + REG32 Reserved_00000380; //0x00000380 + REG32 Regfile_AT; //0x00000384 + REG32 Regfile_V0; //0x00000388 + REG32 Regfile_V1; //0x0000038C + REG32 Regfile_A0; //0x00000390 + REG32 Regfile_A1; //0x00000394 + REG32 Regfile_A2; //0x00000398 + REG32 Regfile_A3; //0x0000039C + REG32 Regfile_T0; //0x000003A0 + REG32 Regfile_T1; //0x000003A4 + REG32 Regfile_T2; //0x000003A8 + REG32 Regfile_T3; //0x000003AC + REG32 Regfile_T4; //0x000003B0 + REG32 Regfile_T5; //0x000003B4 + REG32 Regfile_T6; //0x000003B8 + REG32 Regfile_T7; //0x000003BC + REG32 Regfile_S0; //0x000003C0 + REG32 Regfile_S1; //0x000003C4 + REG32 Regfile_S2; //0x000003C8 + REG32 Regfile_S3; //0x000003CC + REG32 Regfile_S4; //0x000003D0 + REG32 Regfile_S5; //0x000003D4 + REG32 Regfile_S6; //0x000003D8 + REG32 Regfile_S7; //0x000003DC + REG32 Regfile_T8; //0x000003E0 + REG32 Regfile_T9; //0x000003E4 + REG32 Regfile_K0; //0x000003E8 + REG32 Regfile_K1; //0x000003EC + REG32 Regfile_GP; //0x000003F0 + REG32 Regfile_SP; //0x000003F4 + REG32 Regfile_S8; //0x000003F8 + REG32 Regfile_RA; //0x000003FC + REG32 Reserved_00000400[16]; //0x00000400 + REG32 Debug_Page_Address; //0x00000440 + REG32 Cache_Control; //0x00000444 +} HWP_XCPU_T; + +#define hwp_xcpu ((HWP_XCPU_T*) (RDA_MODEM_XCPU_BASE)) +#define hwp_bcpu ((HWP_XCPU_T*) (RDA_MODEM_BCPU_BASE)) + + +//rf0_addr +#define XCPU_RF0_ADDR(n) (((n)&0xFFFFFFFF)<<0) + +//cp0_adr_BadVAddr +#define XCPU_CP0_ADR_BADVADDR(n) (((n)&0xFFFFFFFF)<<0) + +//cp0_Cause +#define XCPU_CP0_CAUSE_EXCCODE(n) (((n)&15)<<2) +#define XCPU_CP0_CAUSE_EXCCODE_MASK (15<<2) +#define XCPU_CP0_CAUSE_EXCCODE_SHIFT (2) +#define XCPU_CP0_CAUSE_EXCCODE_INT (0<<2) +#define XCPU_CP0_CAUSE_EXCCODE_MOD (1<<2) +#define XCPU_CP0_CAUSE_EXCCODE_TLBL (2<<2) +#define XCPU_CP0_CAUSE_EXCCODE_TLBS (3<<2) +#define XCPU_CP0_CAUSE_EXCCODE_ADEL (4<<2) +#define XCPU_CP0_CAUSE_EXCCODE_ADES (5<<2) +#define XCPU_CP0_CAUSE_EXCCODE_IBE (6<<2) +#define XCPU_CP0_CAUSE_EXCCODE_DBE (7<<2) +#define XCPU_CP0_CAUSE_EXCCODE_SYS (8<<2) +#define XCPU_CP0_CAUSE_EXCCODE_PB (9<<2) +#define XCPU_CP0_CAUSE_EXCCODE_RI (10<<2) +#define XCPU_CP0_CAUSE_EXCCODE_CPU (11<<2) +#define XCPU_CP0_CAUSE_EXCCODE_OV (12<<2) +#define XCPU_CP0_CAUSE_IP_SOFT(n) (((n)&3)<<8) +#define XCPU_CP0_CAUSE_IP_SOFT_MASK (3<<8) +#define XCPU_CP0_CAUSE_IP_SOFT_SHIFT (8) +#define XCPU_CP0_CAUSE_IP_EXT(n) (((n)&0x3F)<<10) +#define XCPU_CP0_CAUSE_IP_EXT_MASK (0x3F<<10) +#define XCPU_CP0_CAUSE_IP_EXT_SHIFT (10) +#define XCPU_CP0_CAUSE_CE(n) (((n)&3)<<28) +#define XCPU_CP0_CAUSE_CE_MASK (3<<28) +#define XCPU_CP0_CAUSE_CE_SHIFT (28) +#define XCPU_CP0_CAUSE_BD_MASK (1<<31) +#define XCPU_CP0_CAUSE_BD_SHIFT (31) +#define XCPU_CP0_CAUSE_BD_NORMAL (0<<31) +#define XCPU_CP0_CAUSE_BD_DELAY_SLOT (1<<31) +#define XCPU_CP0_CAUSE_IP(n) (((n)&0xFF)<<8) +#define XCPU_CP0_CAUSE_IP_MASK (0xFF<<8) +#define XCPU_CP0_CAUSE_IP_SHIFT (8) + +//cp0_Status +#define XCPU_CP0_STATUS_IEC_MASK (1<<0) +#define XCPU_CP0_STATUS_IEC_SHIFT (0) +#define XCPU_CP0_STATUS_IEC_DISABLE (0<<0) +#define XCPU_CP0_STATUS_IEC_ENABLE (1<<0) +#define XCPU_CP0_STATUS_KUC_MASK (1<<1) +#define XCPU_CP0_STATUS_KUC_SHIFT (1) +#define XCPU_CP0_STATUS_KUC_KERNEL (0<<1) +#define XCPU_CP0_STATUS_KUC_USER (1<<1) +#define XCPU_CP0_STATUS_IEP_MASK (1<<2) +#define XCPU_CP0_STATUS_IEP_SHIFT (2) +#define XCPU_CP0_STATUS_IEP_DISABLE (0<<2) +#define XCPU_CP0_STATUS_IEP_ENABLE (1<<2) +#define XCPU_CP0_STATUS_KUP_MASK (1<<3) +#define XCPU_CP0_STATUS_KUP_SHIFT (3) +#define XCPU_CP0_STATUS_KUP_KERNEL (0<<3) +#define XCPU_CP0_STATUS_KUP_USER (1<<3) +#define XCPU_CP0_STATUS_IEO_MASK (1<<4) +#define XCPU_CP0_STATUS_IEO_SHIFT (4) +#define XCPU_CP0_STATUS_IEO_DISABLE (0<<4) +#define XCPU_CP0_STATUS_IEO_ENABLE (1<<4) +#define XCPU_CP0_STATUS_KUO_MASK (1<<5) +#define XCPU_CP0_STATUS_KUO_SHIFT (5) +#define XCPU_CP0_STATUS_KUO_KERNEL (0<<5) +#define XCPU_CP0_STATUS_KUO_USER (1<<5) +#define XCPU_CP0_STATUS_KUI (1<<6) +#define XCPU_CP0_STATUS_INTMASK(n) (((n)&0xFF)<<8) +#define XCPU_CP0_STREAMING_DISABLE (1<<16) +#define XCPU_CP0_STATUS_CM (1<<19) +#define XCPU_CP0_STATUS_TS (1<<21) +#define XCPU_CP0_STATUS_BEV (1<<22) +#define XCPU_CP0_STATUS_RE (1<<25) +#define XCPU_CP0_STATUS_CU_0 (1<<28) +#define XCPU_CP0_STATUS_CU_1 (1<<29) +#define XCPU_CP0_STATUS_CU_2 (1<<30) +#define XCPU_CP0_STATUS_CU_3 (1<<31) +#define XCPU_CP0_STATUS_CU_123(n) (((n)&7)<<29) +#define XCPU_CP0_STATUS_CU_123_MASK (7<<29) +#define XCPU_CP0_STATUS_CU_123_SHIFT (29) +#define XCPU_CP0_STATUS_CU(n) (((n)&15)<<28) +#define XCPU_CP0_STATUS_CU_MASK (15<<28) +#define XCPU_CP0_STATUS_CU_SHIFT (28) + +//cp0_EPC +#define XCPU_CP0_EPC(n) (((n)&0xFFFFFFFF)<<0) + +//cp0_BadVAddr +#define XCPU_CP0_BADVADDR(n) (((n)&0xFFFFFFFF)<<0) + +//rf0_data +#define XCPU_RF0_DATA(n) (((n)&0xFFFFFFFF)<<0) + +//dc0_result +#define XCPU_DC0_RESULT(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_AT +#define XCPU_AT(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_V0 +#define XCPU_V0(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_V1 +#define XCPU_V1(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_A0 +#define XCPU_A0(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_A1 +#define XCPU_A1(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_A2 +#define XCPU_A2(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_A3 +#define XCPU_A3(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_T0 +#define XCPU_T0(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_T1 +#define XCPU_T1(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_T2 +#define XCPU_T2(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_T3 +#define XCPU_T3(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_T4 +#define XCPU_T4(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_T5 +#define XCPU_T5(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_T6 +#define XCPU_T6(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_T7 +#define XCPU_T7(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_S0 +#define XCPU_S0(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_S1 +#define XCPU_S1(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_S2 +#define XCPU_S2(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_S3 +#define XCPU_S3(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_S4 +#define XCPU_S4(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_S5 +#define XCPU_S5(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_S6 +#define XCPU_S6(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_S7 +#define XCPU_S7(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_T8 +#define XCPU_T8(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_T9 +#define XCPU_T9(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_K0 +#define XCPU_K0(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_K1 +#define XCPU_K1(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_GP +#define XCPU_GP(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_SP +#define XCPU_SP(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_S8 +#define XCPU_S8(n) (((n)&0xFFFFFFFF)<<0) + +//Regfile_RA +#define XCPU_RA(n) (((n)&0xFFFFFFFF)<<0) + +//Debug_Page_Address +#define XCPU_DEBUG_PAGE_ADDRESS(n) (((n)&15)<<0) +#define XCPU_DEBUG_PAGE_ADDRESS_MASK (15<<0) +#define XCPU_DEBUG_PAGE_ADDRESS_SHIFT (0) +#define XCPU_DEBUG_PAGE_ADDRESS_ITAG (0<<0) +#define XCPU_DEBUG_PAGE_ADDRESS_DTAG (8<<0) + +//Cache_Control +#define XCPU_DCACHE_INHIBIT (1<<0) +#define XCPU_ICACHE_INHIBIT (1<<1) +#define XCPU_CACHE_HIT_DISABLE (1<<2) + + + + + +#endif + diff --git a/arch/arm/include/asm/arch-rda/rom_api_trampolin.h b/arch/arm/include/asm/arch-rda/rom_api_trampolin.h new file mode 100644 index 0000000000..2104ed8559 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/rom_api_trampolin.h @@ -0,0 +1,180 @@ + +#ifndef __RDA_ROM_API_H__ +#define __RDA_ROM_API_H__ + +struct chip_id { + // ASIC information + uint32_t chip; // CHIP(31:15) NA(15:15) BOND(14:12) METAL(11:0) + uint32_t res1; + // Production information + uint16_t date; // YYYY:MMMM:DDDDD + uint16_t wafer; + uint16_t xy; + uint16_t res2; +}; + +struct chip_security_context { + // Security context + uint8_t rda_key_index; // 0-5 : 0 default key + uint8_t vendor_id; // 0-50 + uint16_t flags; +#define RDA_SE_CFG_UNLOCK_ALLOWED (1<<0) +#define RDA_SE_CFG_SECURITY_ENABLE_BIT (1<<4) +#define RDA_SE_CFG_INDIRECT_SIGN_BIT (1<<5) +#define RDA_SE_CFG_HOST_DISABLE_BIT (1<<6) +#define RDA_SE_CFG_TRACE_DISABLE_BIT (1<<7) +}; + +struct chip_unique_id { + uint8_t id[32]; +}; + +/* security */ +#define RDASIGN "RDAS" +#define PKALG "Ed" +#define KDFALG "BK" + +#define SIGBYTES 64 +#define PUBLICBYTES 32 +#define SECRETBYTES 64 +#define FPLEN 8 + +struct pubkey { + uint8_t rdasign[4];//RDAS + uint8_t pkalg[2]; //Ed + uint8_t dummy[2]; + uint8_t name[16]; + uint8_t fingerprint[FPLEN]; + uint8_t pubkey[PUBLICBYTES]; +}; + +// RDASEdPo +struct sig { + uint8_t rdasign[4];//RDAS + uint8_t pkalg[2]; //Ed + uint8_t hashalg[2];//Po/B2/SH + uint8_t name[16]; + uint8_t fingerprint[FPLEN]; + uint8_t sig[SIGBYTES]; +}; + + +/* ROM Cryto API */ + +struct ROM_crypto_api { + char magic[8]; // "RDA API" + unsigned version; // 100 + + // signature + int (*signature_open) ( + const uint8_t *message, unsigned length, + const struct sig *sig, + const struct pubkey *pubkey); +/* Return values */ +#define ROM_API_SIGNATURE_OK 0 +#define ROM_API_SIGNATURE_FAIL -1 +// positive values is for invalid arguments + + // hash + unsigned sz_hash_context; + int (*hash_init) ( unsigned *S, uint8_t outlen ); + int (*hash_update) ( unsigned *S, const uint8_t *in, unsigned inlen ); + int (*hash_final) ( unsigned *S, uint8_t *out, uint8_t outlen ); + + // info API + void (*get_chip_id) (struct chip_id *id); + void (*get_chip_unique) (struct chip_unique_id *out); + int (*get_chip_security_context) (struct chip_security_context *context, + struct pubkey *pubkey); +/* Return values */ +#define ROM_API_SECURITY_ENABLED 0 +#define ROM_API_SECURITY_DISABLED 1 +#define ROM_API_INVALID_KEYINDEX 2 +#define ROM_API_INVALID_VENDOR_ID 3 +#define ROM_API_SECURITY_UNAVAILABLE 4 + + // RND + void (*get_chip_true_random) (uint8_t *out, uint8_t outlen); + + // NEW in v101: + int (*signature_open_w_hash)(uint8_t message_hash[64], + const struct sig *signature, + const struct pubkey *pubkey); +/* Return values */ +// same as signature_open() plus ROM_API_UNAVAILABLE if method is unavailable. +#define ROM_API_UNAVAILABLE 100 + + // Future extension + unsigned dummy[19]; +}; + +#ifndef BOOTROM + +// The ROMAPI is allocated either at 0x3f00 or 0xff00. +// 8810 - 0xff00 +// 8810H - 0x3f00 +#ifndef ROMAPI_BASE +# define ROMAPI_BASE 0xff00 +#endif + +static const struct ROM_crypto_api *romapi = (void*)ROMAPI_BASE; + + +// info API + +static void inline get_chip_id(struct chip_id *id) +{ + romapi->get_chip_id(id); +} + + +static inline void get_chip_unique(struct chip_unique_id *id ) +{ + romapi->get_chip_unique(id); +} + +/* Replaced with a enhanced version in arch/arm/rda/rda_romapi.c */ +int get_chip_security_context(struct chip_security_context *context, struct pubkey *pubkey); +/* +static inline int get_chip_security_context(struct chip_security_context *context, struct pubkey *pubkey) +{ + return romapi->get_chip_security_context(context, pubkey); +}*/ + + +// +// RND +// +static inline void get_chip_true_random(uint8_t *out, uint8_t outlen) +{ + romapi->get_chip_true_random(out, outlen); +} + +// +// SIGNATURE CHECK +// +static inline int signature_check( + const uint8_t *message, unsigned length, + const struct sig *sig, + const struct pubkey *pubkey) +{ + return romapi->signature_open(message, length, sig, pubkey); +} + +// NEW in v101: +// +// SIGNATURE CHECK variant that can be used to check larger than RAM messages +// +static inline int signature_check_w_hash( + uint8_t message_hash[64], + const struct sig *sig, + const struct pubkey *pubkey) +{ + if (romapi->signature_open_w_hash) + return romapi->signature_open_w_hash(message_hash, sig, pubkey); + else + return ROM_API_UNAVAILABLE; +} + +#endif +#endif diff --git a/arch/arm/include/asm/arch-rda/spl_board_info.h b/arch/arm/include/asm/arch-rda/spl_board_info.h new file mode 100644 index 0000000000..f931d1bb06 --- /dev/null +++ b/arch/arm/include/asm/arch-rda/spl_board_info.h @@ -0,0 +1,43 @@ +#ifndef _SPL_BOARD_INFO_H_ +#define _SPL_BOARD_INFO_H_ + +#include <asm/arch/rom_api_trampolin.h> + +/*!!! + *struct size must < CONFIG_SPL_BOARD_INFO_SIZE (512 bytes) + */ +typedef struct spl_bd_info { + struct { + unsigned long ddr_auto_cal_offs; + u16 ddr_auto_cal_flag; + u16 ddr_auto_cal_val[10]; + } spl_ddr_cal_info; + + struct spl_security_info { + u32 version; + int secure_mode; + struct chip_id chip_id; + struct chip_security_context chip_security_context; + struct chip_unique_id chip_unique_id; + struct pubkey pubkey; + u8 random[32]; + } spl_security_info; + + struct spl_emmc_info{ + u8 manufacturer_id; + u8 reserved[3]; + } spl_emmc_info; +} spl_bd_t; + +static inline spl_bd_t *get_spl_bd_info(void) +{ + spl_bd_t *p = (spl_bd_t *)CONFIG_SPL_BOARD_INFO_ADDR; + + return p; +} + +#define get_bd_spl_security_info() &get_spl_bd_info()->spl_security_info +#define get_bd_spl_ddr_cal_info() &get_spl_bd_info()->spl_ddr_cal_info +#define get_bd_spl_emmc_info() &get_spl_bd_info()->spl_emmc_info +#endif /* _SPL_BOARD_INFO_H_ */ + diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h index adef4ee21d..0f701c9012 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h @@ -21,53 +21,54 @@ #ifndef __ASM_ARCH_MMC_H_ #define __ASM_ARCH_MMC_H_ -#ifndef __ASSEMBLY__ -struct s5p_mmc { - unsigned int sysad; - unsigned short blksize; - unsigned short blkcnt; - unsigned int argument; - unsigned short trnmod; - unsigned short cmdreg; - unsigned int rspreg0; - unsigned int rspreg1; - unsigned int rspreg2; - unsigned int rspreg3; - unsigned int bdata; - unsigned int prnsts; - unsigned char hostctl; - unsigned char pwrcon; - unsigned char blkgap; - unsigned char wakcon; - unsigned short clkcon; - unsigned char timeoutcon; - unsigned char swrst; - unsigned int norintsts; /* errintsts */ - unsigned int norintstsen; /* errintstsen */ - unsigned int norintsigen; /* errintsigen */ - unsigned short acmd12errsts; - unsigned char res1[2]; - unsigned int capareg; - unsigned char res2[4]; - unsigned int maxcurr; - unsigned char res3[0x34]; - unsigned int control2; - unsigned int control3; - unsigned char res4[4]; - unsigned int control4; - unsigned char res5[0x6e]; - unsigned short hcver; - unsigned char res6[0xFFF00]; -}; +#define SDHCI_CONTROL2 0x80 +#define SDHCI_CONTROL3 0x84 +#define SDHCI_CONTROL4 0x8C -struct mmc_host { - struct s5p_mmc *reg; - unsigned int version; /* SDHCI spec. version */ - unsigned int clock; /* Current clock (MHz) */ - int dev_index; -}; +#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) +#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) +#define SDHCI_CTRL2_CDINVRXD3 (1 << 29) +#define SDHCI_CTRL2_SLCARDOUT (1 << 28) -int s5p_mmc_init(int dev_index, int bus_width); +#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) +#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) +#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) -#endif /* __ASSEMBLY__ */ +#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) +#define SDHCI_CTRL2_LVLDAT_SHIFT (16) +#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) + +#define SDHCI_CTRL2_ENFBCLKTX (1 << 15) +#define SDHCI_CTRL2_ENFBCLKRX (1 << 14) +#define SDHCI_CTRL2_SDCDSEL (1 << 13) +#define SDHCI_CTRL2_SDSIGPC (1 << 12) +#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) + +#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9) +#define SDHCI_CTRL2_DFCNT_SHIFT (9) + +#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) +#define SDHCI_CTRL2_RWAITMODE (1 << 7) +#define SDHCI_CTRL2_DISBUFRD (1 << 6) +#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4) +#define SDHCI_CTRL2_SELBASECLK_SHIFT (4) +#define SDHCI_CTRL2_PWRSYNC (1 << 3) +#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) +#define SDHCI_CTRL2_HWINITFIN (1 << 0) + +#define SDHCI_CTRL3_FCSEL3 (1 << 31) +#define SDHCI_CTRL3_FCSEL2 (1 << 23) +#define SDHCI_CTRL3_FCSEL1 (1 << 15) +#define SDHCI_CTRL3_FCSEL0 (1 << 7) + +#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) +#define SDHCI_CTRL4_DRIVE_SHIFT (16) + +int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); + +static inline unsigned int s5p_mmc_init(int index, int bus_width) +{ + unsigned int base = samsung_get_base_mmc() + (0x10000 * index); + return s5p_sdhci_init(base, 52000000, 400000, index); +} #endif diff --git a/arch/arm/include/asm/arch-spear/spr_i2c.h b/arch/arm/include/asm/arch-spear/spr_i2c.h deleted file mode 100644 index 7521ebc6cf..0000000000 --- a/arch/arm/include/asm/arch-spear/spr_i2c.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SPR_I2C_H_ -#define __SPR_I2C_H_ - -struct i2c_regs { - u32 ic_con; - u32 ic_tar; - u32 ic_sar; - u32 ic_hs_maddr; - u32 ic_cmd_data; - u32 ic_ss_scl_hcnt; - u32 ic_ss_scl_lcnt; - u32 ic_fs_scl_hcnt; - u32 ic_fs_scl_lcnt; - u32 ic_hs_scl_hcnt; - u32 ic_hs_scl_lcnt; - u32 ic_intr_stat; - u32 ic_intr_mask; - u32 ic_raw_intr_stat; - u32 ic_rx_tl; - u32 ic_tx_tl; - u32 ic_clr_intr; - u32 ic_clr_rx_under; - u32 ic_clr_rx_over; - u32 ic_clr_tx_over; - u32 ic_clr_rd_req; - u32 ic_clr_tx_abrt; - u32 ic_clr_rx_done; - u32 ic_clr_activity; - u32 ic_clr_stop_det; - u32 ic_clr_start_det; - u32 ic_clr_gen_call; - u32 ic_enable; - u32 ic_status; - u32 ic_txflr; - u32 ix_rxflr; - u32 reserved_1; - u32 ic_tx_abrt_source; -}; - -#define IC_CLK 166 -#define NANO_TO_MICRO 1000 - -/* High and low times in different speed modes (in ns) */ -#define MIN_SS_SCL_HIGHTIME 4000 -#define MIN_SS_SCL_LOWTIME 5000 -#define MIN_FS_SCL_HIGHTIME 800 -#define MIN_FS_SCL_LOWTIME 1700 -#define MIN_HS_SCL_HIGHTIME 60 -#define MIN_HS_SCL_LOWTIME 160 - -/* Worst case timeout for 1 byte is kept as 2ms */ -#define I2C_BYTE_TO (CONFIG_SYS_HZ/500) -#define I2C_STOPDET_TO (CONFIG_SYS_HZ/500) -#define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16) - -/* i2c control register definitions */ -#define IC_CON_SD 0x0040 -#define IC_CON_RE 0x0020 -#define IC_CON_10BITADDRMASTER 0x0010 -#define IC_CON_10BITADDR_SLAVE 0x0008 -#define IC_CON_SPD_MSK 0x0006 -#define IC_CON_SPD_SS 0x0002 -#define IC_CON_SPD_FS 0x0004 -#define IC_CON_SPD_HS 0x0006 -#define IC_CON_MM 0x0001 - -/* i2c target address register definitions */ -#define TAR_ADDR 0x0050 - -/* i2c slave address register definitions */ -#define IC_SLAVE_ADDR 0x0002 - -/* i2c data buffer and command register definitions */ -#define IC_CMD 0x0100 - -/* i2c interrupt status register definitions */ -#define IC_GEN_CALL 0x0800 -#define IC_START_DET 0x0400 -#define IC_STOP_DET 0x0200 -#define IC_ACTIVITY 0x0100 -#define IC_RX_DONE 0x0080 -#define IC_TX_ABRT 0x0040 -#define IC_RD_REQ 0x0020 -#define IC_TX_EMPTY 0x0010 -#define IC_TX_OVER 0x0008 -#define IC_RX_FULL 0x0004 -#define IC_RX_OVER 0x0002 -#define IC_RX_UNDER 0x0001 - -/* fifo threshold register definitions */ -#define IC_TL0 0x00 -#define IC_TL1 0x01 -#define IC_TL2 0x02 -#define IC_TL3 0x03 -#define IC_TL4 0x04 -#define IC_TL5 0x05 -#define IC_TL6 0x06 -#define IC_TL7 0x07 -#define IC_RX_TL IC_TL0 -#define IC_TX_TL IC_TL0 - -/* i2c enable register definitions */ -#define IC_ENABLE_0B 0x0001 - -/* i2c status register definitions */ -#define IC_STATUS_SA 0x0040 -#define IC_STATUS_MA 0x0020 -#define IC_STATUS_RFF 0x0010 -#define IC_STATUS_RFNE 0x0008 -#define IC_STATUS_TFE 0x0004 -#define IC_STATUS_TFNF 0x0002 -#define IC_STATUS_ACT 0x0001 - -/* Speed Selection */ -#define IC_SPEED_MODE_STANDARD 1 -#define IC_SPEED_MODE_FAST 2 -#define IC_SPEED_MODE_MAX 3 - -#define I2C_MAX_SPEED 3400000 -#define I2C_FAST_SPEED 400000 -#define I2C_STANDARD_SPEED 100000 - -#endif /* __SPR_I2C_H_ */ diff --git a/arch/arm/cpu/armv7/tegra2/ap20.h b/arch/arm/include/asm/arch-tegra2/ap20.h index a4b4d73a40..d222c44233 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.h +++ b/arch/arm/include/asm/arch-tegra2/ap20.h @@ -100,3 +100,10 @@ void tegra2_start(void); /* This is the main entry into U-Boot, used by the Cortex-A9 */ extern void _start(void); + +/** + * Works out the SOC type used for clocks settings + * + * @return SOC type - see TEGRA_SOC... + */ +int tegra_get_chip_type(void); diff --git a/arch/arm/include/asm/arch-tegra2/apb_misc.h b/arch/arm/include/asm/arch-tegra2/apb_misc.h new file mode 100644 index 0000000000..eb69d18d01 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/apb_misc.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _GP_PADCTRL_H_ +#define _GP_PADCTRL_H_ + +/* APB_MISC_PP registers */ +struct apb_misc_pp_ctlr { + u32 reserved0[2]; + u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ +}; + +/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */ +#define RAM_CODE_SHIFT 4 +#define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT) + +#endif diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h index 415e420012..8c3be91514 100644 --- a/arch/arm/include/asm/arch-tegra2/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h @@ -117,6 +117,7 @@ struct clk_rst_ctlr { #define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT) #define PLL_LFCON_SHIFT 4 +#define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT) #define PLLU_VCO_FREQ_SHIFT 20 #define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT) @@ -124,6 +125,8 @@ struct clk_rst_ctlr { /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ #define OSC_FREQ_SHIFT 30 #define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT) +#define OSC_XOBP_SHIFT 1 +#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) /* * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h index 6b12c76e8d..1d3ae38644 100644 --- a/arch/arm/include/asm/arch-tegra2/clock.h +++ b/arch/arm/include/asm/arch-tegra2/clock.h @@ -210,6 +210,21 @@ enum clock_osc_freq clock_get_osc_freq(void); unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, u32 divp, u32 cpcon, u32 lfcon); +/** + * Read low-level parameters of a PLL. + * + * @param id clock id to read (note: USB is not supported) + * @param divm returns input divider + * @param divn returns feedback divider + * @param divp returns post divider 2^n + * @param cpcon returns charge pump setup control + * @param lfcon returns loop filter setup control + * + * @returns 0 if ok, -1 on error (invalid clock id) + */ +int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, + u32 *divp, u32 *cpcon, u32 *lfcon); + /* * Enable a clock * @@ -368,6 +383,13 @@ void clock_ll_start_uart(enum periph_id periph_id); */ enum periph_id clock_decode_periph_id(const void *blob, int node); +/** + * Checks if the oscillator bypass is enabled (XOBP bit) + * + * @return 1 if bypass is enabled, 0 if not + */ +int clock_get_osc_bypass(void); + /* * Checks that clocks are valid and prints a warning if not * diff --git a/arch/arm/include/asm/arch-tegra2/emc.h b/arch/arm/include/asm/arch-tegra2/emc.h new file mode 100644 index 0000000000..deb3d36ed2 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/emc.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ARCH_EMC_H_ +#define _ARCH_EMC_H_ + +#include <asm/types.h> + +#define TEGRA_EMC_NUM_REGS 46 + +/* EMC Registers */ +struct emc_ctlr { + u32 cfg; /* 0x00: EMC_CFG */ + u32 reserved0[3]; /* 0x04 ~ 0x0C */ + u32 adr_cfg; /* 0x10: EMC_ADR_CFG */ + u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */ + u32 reserved1[2]; /* 0x18 ~ 0x18 */ + u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */ + u32 pin; /* 0x24: EMC_PIN */ + u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */ + u32 rc; /* 0x2C: EMC_RC */ + u32 rfc; /* 0x30: EMC_RFC */ + u32 ras; /* 0x34: EMC_RAS */ + u32 rp; /* 0x38: EMC_RP */ + u32 r2w; /* 0x3C: EMC_R2W */ + u32 w2r; /* 0x40: EMC_W2R */ + u32 r2p; /* 0x44: EMC_R2P */ + u32 w2p; /* 0x48: EMC_W2P */ + u32 rd_rcd; /* 0x4C: EMC_RD_RCD */ + u32 wd_rcd; /* 0x50: EMC_WD_RCD */ + u32 rrd; /* 0x54: EMC_RRD */ + u32 rext; /* 0x58: EMC_REXT */ + u32 wdv; /* 0x5C: EMC_WDV */ + u32 quse; /* 0x60: EMC_QUSE */ + u32 qrst; /* 0x64: EMC_QRST */ + u32 qsafe; /* 0x68: EMC_QSAFE */ + u32 rdv; /* 0x6C: EMC_RDV */ + u32 refresh; /* 0x70: EMC_REFRESH */ + u32 burst_refresh_num; /* 0x74: EMC_BURST_REFRESH_NUM */ + u32 pdex2wr; /* 0x78: EMC_PDEX2WR */ + u32 pdex2rd; /* 0x7c: EMC_PDEX2RD */ + u32 pchg2pden; /* 0x80: EMC_PCHG2PDEN */ + u32 act2pden; /* 0x84: EMC_ACT2PDEN */ + u32 ar2pden; /* 0x88: EMC_AR2PDEN */ + u32 rw2pden; /* 0x8C: EMC_RW2PDEN */ + u32 txsr; /* 0x90: EMC_TXSR */ + u32 tcke; /* 0x94: EMC_TCKE */ + u32 tfaw; /* 0x98: EMC_TFAW */ + u32 trpab; /* 0x9C: EMC_TRPAB */ + u32 tclkstable; /* 0xA0: EMC_TCLKSTABLE */ + u32 tclkstop; /* 0xA4: EMC_TCLKSTOP */ + u32 trefbw; /* 0xA8: EMC_TREFBW */ + u32 quse_extra; /* 0xAC: EMC_QUSE_EXTRA */ + u32 odt_write; /* 0xB0: EMC_ODT_WRITE */ + u32 odt_read; /* 0xB4: EMC_ODT_READ */ + u32 reserved2[5]; /* 0xB8 ~ 0xC8 */ + u32 mrs; /* 0xCC: EMC_MRS */ + u32 emrs; /* 0xD0: EMC_EMRS */ + u32 ref; /* 0xD4: EMC_REF */ + u32 pre; /* 0xD8: EMC_PRE */ + u32 nop; /* 0xDC: EMC_NOP */ + u32 self_ref; /* 0xE0: EMC_SELF_REF */ + u32 dpd; /* 0xE4: EMC_DPD */ + u32 mrw; /* 0xE8: EMC_MRW */ + u32 mrr; /* 0xEC: EMC_MRR */ + u32 reserved3; /* 0xF0: */ + u32 fbio_cfg1; /* 0xF4: EMC_FBIO_CFG1 */ + u32 fbio_dqsib_dly; /* 0xF8: EMC_FBIO_DQSIB_DLY */ + u32 fbio_dqsib_dly_msb; /* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */ + u32 fbio_spare; /* 0x100: SBIO_SPARE */ + /* There are more registers ... */ +}; + +/** + * Set up the EMC for the given rate. The timing parameters are retrieved + * from the device tree "nvidia,tegra20-emc" node and its + * "nvidia,tegra20-emc-table" sub-nodes. + * + * @param blob Device tree blob + * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) + * @return 0 if ok, else -ve error code (look in emc.c to decode it) + */ +int tegra_set_emc(const void *blob, unsigned rate); + +/** + * Get a pointer to the EMC controller from the device tree. + * + * @param blob Device tree blob + * @return pointer to EMC controller + */ +struct emc_ctlr *emc_get_controller(const void *blob); + +#endif diff --git a/arch/arm/include/asm/arch-tegra2/flow.h b/arch/arm/include/asm/arch-tegra2/flow.h new file mode 100644 index 0000000000..cce6cbf7d0 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/flow.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2010, 2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FLOW_H_ +#define _FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; + u32 halt_cop_events; + u32 cpu_csr; + u32 cop_csr; + u32 halt_cpu1_events; + u32 cpu1_csr; +}; + +#endif diff --git a/arch/arm/include/asm/arch-tegra2/fuse.h b/arch/arm/include/asm/arch-tegra2/fuse.h new file mode 100644 index 0000000000..b7e3808a4f --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/fuse.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FUSE_H_ +#define _FUSE_H_ + +/* FUSE registers */ +struct fuse_regs { + u32 reserved0[64]; /* 0x00 - 0xFC: */ + u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */ + u32 reserved1[3]; /* 0x104 - 0x10c: */ + u32 sku_info; /* 0x110 */ + u32 reserved2[13]; /* 0x114 - 0x144: */ + u32 fa; /* 0x148: FUSE_FA */ + u32 reserved3[21]; /* 0x14C - 0x19C: */ + u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */ +}; + +#endif /* ifndef _FUSE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/gp_padctrl.h b/arch/arm/include/asm/arch-tegra2/gp_padctrl.h new file mode 100644 index 0000000000..1755ab2eaa --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/gp_padctrl.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _GP_PADCTRL_H_ +#define _GP_PADCTRL_H_ + +/* APB_MISC_GP and padctrl registers */ +struct apb_misc_gp_ctlr { + u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ + u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ + u32 reserved0[22]; /* 0x08 - 0x5C: */ + u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ + u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ + u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ + u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ + u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ + u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ + u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */ + u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */ + u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */ + u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */ + u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */ + u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */ + u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */ + u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */ + u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */ + u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */ + u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */ + u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */ + u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */ + u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */ + u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */ + u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */ + u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */ + u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */ + u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */ + u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */ + u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */ + u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */ + u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */ + u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */ +}; + +/* bit fields definitions for APB_MISC_GP_HIDREV register */ +#define HIDREV_CHIPID_SHIFT 8 +#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT) +#define HIDREV_MAJORPREV_SHIFT 4 +#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT) + +/* CHIPID field returned from APB_MISC_GP_HIDREV register */ +#define CHIPID_TEGRA2 0x20 + +#endif diff --git a/arch/arm/include/asm/arch-tegra2/pmu.h b/arch/arm/include/asm/arch-tegra2/pmu.h new file mode 100644 index 0000000000..390815fc24 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/pmu.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ARCH_PMU_H_ +#define _ARCH_PMU_H_ + +/* Set core and CPU voltages to nominal levels */ +int pmu_set_nominal(void); + +#endif /* _ARCH_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/sdram_param.h b/arch/arm/include/asm/arch-tegra2/sdram_param.h new file mode 100644 index 0000000000..6c427d0841 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/sdram_param.h @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2010, 2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SDRAM_PARAM_H_ +#define _SDRAM_PARAM_H_ + +/* + * Defines the number of 32-bit words provided in each set of SDRAM parameters + * for arbitration configuration data. + */ +#define BCT_SDRAM_ARB_CONFIG_WORDS 27 + +enum memory_type { + MEMORY_TYPE_NONE = 0, + MEMORY_TYPE_DDR, + MEMORY_TYPE_LPDDR, + MEMORY_TYPE_DDR2, + MEMORY_TYPE_LPDDR2, + MEMORY_TYPE_NUM, + MEMORY_TYPE_FORCE32 = 0x7FFFFFFF +}; + +/* Defines the SDRAM parameter structure */ +struct sdram_params { + enum memory_type memory_type; + u32 pllm_charge_pump_setup_control; + u32 pllm_loop_filter_setup_control; + u32 pllm_input_divider; + u32 pllm_feedback_divider; + u32 pllm_post_divider; + u32 pllm_stable_time; + u32 emc_clock_divider; + u32 emc_auto_cal_interval; + u32 emc_auto_cal_config; + u32 emc_auto_cal_wait; + u32 emc_pin_program_wait; + u32 emc_rc; + u32 emc_rfc; + u32 emc_ras; + u32 emc_rp; + u32 emc_r2w; + u32 emc_w2r; + u32 emc_r2p; + u32 emc_w2p; + u32 emc_rd_rcd; + u32 emc_wr_rcd; + u32 emc_rrd; + u32 emc_rext; + u32 emc_wdv; + u32 emc_quse; + u32 emc_qrst; + u32 emc_qsafe; + u32 emc_rdv; + u32 emc_refresh; + u32 emc_burst_refresh_num; + u32 emc_pdex2wr; + u32 emc_pdex2rd; + u32 emc_pchg2pden; + u32 emc_act2pden; + u32 emc_ar2pden; + u32 emc_rw2pden; + u32 emc_txsr; + u32 emc_tcke; + u32 emc_tfaw; + u32 emc_trpab; + u32 emc_tclkstable; + u32 emc_tclkstop; + u32 emc_trefbw; + u32 emc_quseextra; + u32 emc_fbioc_fg1; + u32 emc_fbio_dqsib_dly; + u32 emc_fbio_dqsib_dly_msb; + u32 emc_fbio_quse_dly; + u32 emc_fbio_quse_dly_msb; + u32 emc_fbio_cfg5; + u32 emc_fbio_cfg6; + u32 emc_fbio_spare; + u32 emc_mrs; + u32 emc_emrs; + u32 emc_mrw1; + u32 emc_mrw2; + u32 emc_mrw3; + u32 emc_mrw_reset_command; + u32 emc_mrw_reset_init_wait; + u32 emc_adr_cfg; + u32 emc_adr_cfg1; + u32 emc_emem_cfg; + u32 emc_low_latency_config; + u32 emc_cfg; + u32 emc_cfg2; + u32 emc_dbg; + u32 ahb_arbitration_xbar_ctrl; + u32 emc_cfg_dig_dll; + u32 emc_dll_xform_dqs; + u32 emc_dll_xform_quse; + u32 warm_boot_wait; + u32 emc_ctt_term_ctrl; + u32 emc_odt_write; + u32 emc_odt_read; + u32 emc_zcal_ref_cnt; + u32 emc_zcal_wait_cnt; + u32 emc_zcal_mrw_cmd; + u32 emc_mrs_reset_dll; + u32 emc_mrw_zq_init_dev0; + u32 emc_mrw_zq_init_dev1; + u32 emc_mrw_zq_init_wait; + u32 emc_mrs_reset_dll_wait; + u32 emc_emrs_emr2; + u32 emc_emrs_emr3; + u32 emc_emrs_ddr2_dll_enable; + u32 emc_mrs_ddr2_dll_reset; + u32 emc_emrs_ddr2_ocd_calib; + u32 emc_edr2_wait; + u32 emc_cfg_clktrim0; + u32 emc_cfg_clktrim1; + u32 emc_cfg_clktrim2; + u32 pmc_ddr_pwr; + u32 apb_misc_gp_xm2cfga_padctrl; + u32 apb_misc_gp_xm2cfgc_padctrl; + u32 apb_misc_gp_xm2cfgc_padctrl2; + u32 apb_misc_gp_xm2cfgd_padctrl; + u32 apb_misc_gp_xm2cfgd_padctrl2; + u32 apb_misc_gp_xm2clkcfg_padctrl; + u32 apb_misc_gp_xm2comp_padctrl; + u32 apb_misc_gp_xm2vttgen_padctrl; + u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS]; +}; +#endif diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h index ca1881e3a2..d4ada10ea8 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2.h +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h @@ -33,6 +33,7 @@ #define NV_PA_GPIO_BASE 0x6000D000 #define NV_PA_EVP_BASE 0x6000F000 #define NV_PA_APB_MISC_BASE 0x70000000 +#define TEGRA2_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800) #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) #define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) #define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) @@ -40,6 +41,7 @@ #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) #define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) #define TEGRA2_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) +#define TEGRA2_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) #define NV_PA_CSITE_BASE 0x70040000 #define TEGRA_USB1_BASE 0xC5000000 #define TEGRA_USB3_BASE 0xC5008000 @@ -54,6 +56,29 @@ struct timerus { unsigned int cntr_1us; }; + +/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ +#define AP20_WB_RUN_ADDRESS 0x40020000 + +/* These are the available SKUs (product types) for Tegra */ +enum { + SKU_ID_T20 = 0x8, + SKU_ID_T25SE = 0x14, + SKU_ID_AP25 = 0x17, + SKU_ID_T25 = 0x18, + SKU_ID_AP25E = 0x1b, + SKU_ID_T25E = 0x1c, +}; + +/* These are the SOC categories that affect clocking */ +enum { + TEGRA_SOC_T20, + TEGRA_SOC_T25, + + TEGRA_SOC_COUNT, + TEGRA_SOC_UNKNOWN = -1, +}; + #else /* __ASSEMBLY__ */ #define PRM_RSTCTRL TEGRA2_PMC_BASE #endif diff --git a/arch/arm/include/asm/arch-tegra2/tegra_i2c.h b/arch/arm/include/asm/arch-tegra2/tegra_i2c.h index 0a7d99c585..cfb136c466 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra2/tegra_i2c.h @@ -154,4 +154,11 @@ struct i2c_ctlr { #define I2C_INT_ARBITRATION_LOST_SHIFT 2 #define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT) +/** + * Returns the bus number of the DVC controller + * + * @return number of bus, or -1 if there is no DVC active + */ +int tegra_i2c_get_dvc_bus_num(void); + #endif diff --git a/arch/arm/include/asm/arch-tegra2/warmboot.h b/arch/arm/include/asm/arch-tegra2/warmboot.h new file mode 100644 index 0000000000..99ac2e7d23 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/warmboot.h @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2010, 2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _WARM_BOOT_H_ +#define _WARM_BOOT_H_ + +#define STRAP_OPT_A_RAM_CODE_SHIFT 4 +#define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT) + +/* Defines the supported operating modes */ +enum fuse_operating_mode { + MODE_PRODUCTION = 3, + MODE_UNDEFINED, +}; + +/* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */ +enum { + HASH_LENGTH = 4 +}; + +/* Defines the storage for a hash value (128 bits) */ +struct hash { + u32 hash[HASH_LENGTH]; +}; + +/* + * Defines the code header information for the boot rom. + * + * The code immediately follows the code header. + * + * Note that the code header needs to be 16 bytes aligned to preserve + * the alignment of relevant data for hash and decryption computations without + * requiring extra copies to temporary memory areas. + */ +struct wb_header { + u32 length_insecure; /* length of the code header */ + u32 reserved[3]; + struct hash hash; /* hash of header+code, starts next field*/ + struct hash random_aes_block; /* a data block to aid security. */ + u32 length_secure; /* length of the code header */ + u32 destination; /* destination address to put the wb code */ + u32 entry_point; /* execution address of the wb code */ + u32 code_length; /* length of the code */ +}; + +/* + * The warm boot code needs direct access to these registers since it runs in + * SRAM and cannot call other U-Boot code. + */ +union osc_ctrl_reg { + struct { + u32 xoe:1; + u32 xobp:1; + u32 reserved0:2; + u32 xofs:6; + u32 reserved1:2; + u32 xods:5; + u32 reserved2:3; + u32 oscfi_spare:8; + u32 pll_ref_div:2; + u32 osc_freq:2; + }; + u32 word; +}; + +union pllx_base_reg { + struct { + u32 divm:5; + u32 reserved0:3; + u32 divn:10; + u32 reserved1:2; + u32 divp:3; + u32 reserved2:4; + u32 lock:1; + u32 reserved3:1; + u32 ref_dis:1; + u32 enable:1; + u32 bypass:1; + }; + u32 word; +}; + +union pllx_misc_reg { + struct { + u32 vcocon:4; + u32 lfcon:4; + u32 cpcon:4; + u32 lock_sel:6; + u32 reserved0:1; + u32 lock_enable:1; + u32 reserved1:1; + u32 dccon:1; + u32 pts:2; + u32 reserved2:6; + u32 out1_div_byp:1; + u32 out1_inv_clk:1; + }; + u32 word; +}; + +/* + * TODO: This register is not documented in the TRM yet. We could move this + * into the EMC and give it a proper interface, but not while it is + * undocumented. + */ +union scratch3_reg { + struct { + u32 pllx_base_divm:5; + u32 pllx_base_divn:10; + u32 pllx_base_divp:3; + u32 pllx_misc_lfcon:4; + u32 pllx_misc_cpcon:4; + }; + u32 word; +}; + + +/** + * Save warmboot memory settings for a later resume + * + * @return 0 if ok, -1 on error + */ +int warmboot_save_sdram_params(void); + +int warmboot_prepare_code(u32 seg_address, u32 seg_length); +int sign_data_block(u8 *source, u32 length, u8 *signature); +void wb_start(void); /* Start of WB assembly code */ +void wb_end(void); /* End of WB assembly code */ + +#endif diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 5bbb0a0464..fb3a013c20 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -31,6 +31,8 @@ enum dma_data_direction { }; static void *dma_alloc_coherent(size_t len, unsigned long *handle) +__attribute__((unused)); +static void *dma_alloc_coherent(size_t len, unsigned long *handle) { *handle = (unsigned long)malloc(len); return (void *)*handle; diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index e5c7d2cabe..f1e3ad212e 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -226,8 +226,8 @@ #define EMIF_REG_CS_TIM_MASK (0xf << 0) /* PWR_MGMT_CTRL_SHDW */ -#define EMIF_REG_PD_TIM_SHDW_SHIFT 8 -#define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 8) +#define EMIF_REG_PD_TIM_SHDW_SHIFT 12 +#define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 12) #define EMIF_REG_SR_TIM_SHDW_SHIFT 4 #define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4) #define EMIF_REG_CS_TIM_SHDW_SHIFT 0 @@ -530,6 +530,8 @@ (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\ (0xFF << EMIF_SYS_ADDR_SHIFT)) +#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 +#define EMIF_EXT_PHY_CTRL_CONST_REG 0x13 /* Reg mapping structure */ struct emif_reg_struct { @@ -580,10 +582,64 @@ struct emif_reg_struct { u32 emif_zq_config; u32 emif_temp_alert_config; u32 emif_l3_err_log; - u32 padding6[4]; + u32 emif_rd_wr_lvl_rmp_win; + u32 emif_rd_wr_lvl_rmp_ctl; + u32 emif_rd_wr_lvl_ctl; + u32 padding6[1]; u32 emif_ddr_phy_ctrl_1; u32 emif_ddr_phy_ctrl_1_shdw; u32 emif_ddr_phy_ctrl_2; + u32 padding7[12]; + u32 emif_rd_wr_exec_thresh; + u32 padding8[55]; + u32 emif_ddr_ext_phy_ctrl_1; + u32 emif_ddr_ext_phy_ctrl_1_shdw; + u32 emif_ddr_ext_phy_ctrl_2; + u32 emif_ddr_ext_phy_ctrl_2_shdw; + u32 emif_ddr_ext_phy_ctrl_3; + u32 emif_ddr_ext_phy_ctrl_3_shdw; + u32 emif_ddr_ext_phy_ctrl_4; + u32 emif_ddr_ext_phy_ctrl_4_shdw; + u32 emif_ddr_ext_phy_ctrl_5; + u32 emif_ddr_ext_phy_ctrl_5_shdw; + u32 emif_ddr_ext_phy_ctrl_6; + u32 emif_ddr_ext_phy_ctrl_6_shdw; + u32 emif_ddr_ext_phy_ctrl_7; + u32 emif_ddr_ext_phy_ctrl_7_shdw; + u32 emif_ddr_ext_phy_ctrl_8; + u32 emif_ddr_ext_phy_ctrl_8_shdw; + u32 emif_ddr_ext_phy_ctrl_9; + u32 emif_ddr_ext_phy_ctrl_9_shdw; + u32 emif_ddr_ext_phy_ctrl_10; + u32 emif_ddr_ext_phy_ctrl_10_shdw; + u32 emif_ddr_ext_phy_ctrl_11; + u32 emif_ddr_ext_phy_ctrl_11_shdw; + u32 emif_ddr_ext_phy_ctrl_12; + u32 emif_ddr_ext_phy_ctrl_12_shdw; + u32 emif_ddr_ext_phy_ctrl_13; + u32 emif_ddr_ext_phy_ctrl_13_shdw; + u32 emif_ddr_ext_phy_ctrl_14; + u32 emif_ddr_ext_phy_ctrl_14_shdw; + u32 emif_ddr_ext_phy_ctrl_15; + u32 emif_ddr_ext_phy_ctrl_15_shdw; + u32 emif_ddr_ext_phy_ctrl_16; + u32 emif_ddr_ext_phy_ctrl_16_shdw; + u32 emif_ddr_ext_phy_ctrl_17; + u32 emif_ddr_ext_phy_ctrl_17_shdw; + u32 emif_ddr_ext_phy_ctrl_18; + u32 emif_ddr_ext_phy_ctrl_18_shdw; + u32 emif_ddr_ext_phy_ctrl_19; + u32 emif_ddr_ext_phy_ctrl_19_shdw; + u32 emif_ddr_ext_phy_ctrl_20; + u32 emif_ddr_ext_phy_ctrl_20_shdw; + u32 emif_ddr_ext_phy_ctrl_21; + u32 emif_ddr_ext_phy_ctrl_21_shdw; + u32 emif_ddr_ext_phy_ctrl_22; + u32 emif_ddr_ext_phy_ctrl_22_shdw; + u32 emif_ddr_ext_phy_ctrl_23; + u32 emif_ddr_ext_phy_ctrl_23_shdw; + u32 emif_ddr_ext_phy_ctrl_24; + u32 emif_ddr_ext_phy_ctrl_24_shdw; }; struct dmm_lisa_map_regs { @@ -593,6 +649,8 @@ struct dmm_lisa_map_regs { u32 dmm_lisa_map_3; }; +extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; + #define CS0 0 #define CS1 1 /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ @@ -748,7 +806,11 @@ struct dmm_lisa_map_regs { #define DPD_ENABLE 1 /* Maximum delay before Low Power Modes */ +#ifndef CONFIG_OMAP54XX #define REG_CS_TIM 0xF +#else +#define REG_CS_TIM 0x0 +#endif #define REG_SR_TIM 0xF #define REG_PD_TIM 0xF @@ -776,7 +838,7 @@ struct dmm_lisa_map_regs { /* EMIF_L3_CONFIG register value */ #define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF #define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 -#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A300000 +#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A500000 /* * Value of bits 12:31 of DDR_PHY_CTRL_1 register: @@ -798,6 +860,7 @@ struct dmm_lisa_map_regs { * : So nWR is don't care */ #define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23 +#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8 0xc3 /* MR2 */ #define MR2_RL3_WL1 1 @@ -1005,6 +1068,11 @@ struct emif_regs { u32 temp_alert_config; u32 emif_ddr_phy_ctlr_1_init; u32 emif_ddr_phy_ctlr_1; + u32 emif_ddr_ext_phy_ctrl_1; + u32 emif_ddr_ext_phy_ctrl_2; + u32 emif_ddr_ext_phy_ctrl_3; + u32 emif_ddr_ext_phy_ctrl_4; + u32 emif_ddr_ext_phy_ctrl_5; }; /* assert macros */ diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 1fbc531a08..5f5f8d038f 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -75,42 +75,42 @@ static inline phys_addr_t virt_to_phys(void * vaddr) #define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) #define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) -extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen) +static inline void __raw_writesb(unsigned int addr, const void *data, int bytelen) { uint8_t *buf = (uint8_t *)data; while(bytelen--) __arch_putb(*buf++, addr); } -extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen) +static inline void __raw_writesw(unsigned int addr, const void *data, int wordlen) { uint16_t *buf = (uint16_t *)data; while(wordlen--) __arch_putw(*buf++, addr); } -extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen) +static inline void __raw_writesl(unsigned int addr, const void *data, int longlen) { uint32_t *buf = (uint32_t *)data; while(longlen--) __arch_putl(*buf++, addr); } -extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen) +static inline void __raw_readsb(unsigned int addr, void *data, int bytelen) { uint8_t *buf = (uint8_t *)data; while(bytelen--) *buf++ = __arch_getb(addr); } -extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen) +static inline void __raw_readsw(unsigned int addr, void *data, int wordlen) { uint16_t *buf = (uint16_t *)data; while(wordlen--) *buf++ = __arch_getw(addr); } -extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) +static inline void __raw_readsl(unsigned int addr, void *data, int longlen) { uint32_t *buf = (uint32_t *)data; while(longlen--) diff --git a/arch/arm/include/asm/linkage.h b/arch/arm/include/asm/linkage.h new file mode 100644 index 0000000000..dbe4b4e31a --- /dev/null +++ b/arch/arm/include/asm/linkage.h @@ -0,0 +1,7 @@ +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +#define __ALIGN .align 0 +#define __ALIGN_STR ".align 0" + +#endif diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 2d5c3bc376..47ab00aca0 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1105,6 +1105,13 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_UBISYS_P9D_EVP 3493 #define MACH_TYPE_ATDGP318 3494 #define MACH_TYPE_OMAP5_SEVM 3777 +#define MACH_TYPE_RDAARM926EJS 5001 +#define MACH_TYPE_RDA8810 5002 +#define MACH_TYPE_RDA8810E 5003 +#define MACH_TYPE_RDA8820 5004 +#define MACH_TYPE_RDA8850 5005 +#define MACH_TYPE_RDA8850E 5006 +#define MACH_TYPE_RDA8810H 5007 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14222,6 +14229,89 @@ extern unsigned int __machine_arch_type; # define machine_is_omap5_sevm() (0) #endif +#ifdef CONFIG_MACH_RDAARM926EJS +#ifdef machine_arch_type +#undef machine_arch_type +#define machine_arch_type __machine_arch_type +#else +#define machine_arch_type MACH_TYPE_RDAARM926EJS +#endif +#define machine_is_rdaarm926ejs() (machine_arch_type == MACH_TYPE_RDAARM926EJS) +#else +#define machine_is_rdaarm926ejs() (0) +#endif + +#ifdef CONFIG_MACH_RDA8810 +#ifdef machine_arch_type +#undef machine_arch_type +#define machine_arch_type __machine_arch_type +#else +#define machine_arch_type MACH_TYPE_RDA8810 +#endif +#define machine_is_rda8810() (machine_arch_type == MACH_TYPE_RDA8810) +#else +#define machine_is_rda8810() (0) +#endif + +#ifdef CONFIG_MACH_RDA8810E +#ifdef machine_arch_type +#undef machine_arch_type +#define machine_arch_type __machine_arch_type +#else +#define machine_arch_type MACH_TYPE_RDA8810E +#endif +#define machine_is_rda8810e() (machine_arch_type == MACH_TYPE_RDA8810E) +#else +#define machine_is_rda8810e() (0) +#endif + +#ifdef CONFIG_MACH_RDA8820 +#ifdef machine_arch_type +#undef machine_arch_type +#define machine_arch_type __machine_arch_type +#else +#define machine_arch_type MACH_TYPE_RDA8820 +#endif +#define machine_is_rda8820() (machine_arch_type == MACH_TYPE_RDA8820) +#else +#define machine_is_rda8820() (0) +#endif + +#ifdef CONFIG_MACH_RDA8850 +#ifdef machine_arch_type +#undef machine_arch_type +#define machine_arch_type __machine_arch_type +#else +#define machine_arch_type MACH_TYPE_RDA8850 +#endif +#define machine_is_rda8850() (machine_arch_type == MACH_TYPE_RDA8850) +#else +#define machine_is_rda8850() (0) +#endif + +#ifdef CONFIG_MACH_RDA8850E +#ifdef machine_arch_type +#undef machine_arch_type +#define machine_arch_type __machine_arch_type +#else +#define machine_arch_type MACH_TYPE_RDA8850E +#endif +#define machine_is_rda8850E() (machine_arch_type == MACH_TYPE_RDA8850E) +#else +#define machine_is_rda8850E() (0) +#endif + +#ifdef CONFIG_MACH_RDA8810H +#ifdef machine_arch_type +#undef machine_arch_type +#define machine_arch_type __machine_arch_type +#else +#define machine_arch_type MACH_TYPE_RDA8810H +#endif +#define machine_is_rda8810h() (machine_arch_type == MACH_TYPE_RDA8810H) +#else +#define machine_is_rda8810h() (0) +#endif /* * These have not yet been registered */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 6f25948e20..459b6b16e2 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -45,7 +45,7 @@ void preloader_console_init(void); #define BOOT_DEVICE_ONE_NAND 4 #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 -#define BOOT_DEVICE_MMC3 7 +#define BOOT_DEVICE_MMC2_2 7 #elif defined(CONFIG_OMAP44XX) /* OMAP4 */ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 @@ -54,6 +54,7 @@ void preloader_console_init(void); #define BOOT_DEVICE_ONE_NAND 4 #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 +#define BOOT_DEVICE_MMC2_2 0xFF #elif defined(CONFIG_OMAP34XX) /* OMAP3 */ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 @@ -62,11 +63,13 @@ void preloader_console_init(void); #define BOOT_DEVICE_MMC2 5 /*emmc*/ #define BOOT_DEVICE_MMC1 6 #define BOOT_DEVICE_XIPWAIT 7 +#define BOOT_DEVICE_MMC2_2 0xFF #elif defined(CONFIG_AM33XX) /* AM33XX */ #define BOOT_DEVICE_NAND 5 #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 0 #define BOOT_DEVICE_UART 65 +#define BOOT_DEVICE_MMC2_2 0xFF #endif /* Boot type */ @@ -108,6 +111,12 @@ void spl_ymodem_load_image(void); void spl_board_init(void); #endif +static inline u32 omap_revision(void) +{ + extern u32 *const omap_si_rev; + return *omap_si_rev; +} + /* * silicon revisions. * Moving this to common, so that most of code can be moved to common, diff --git a/arch/arm/include/asm/proc b/arch/arm/include/asm/proc new file mode 120000 index 0000000000..c7f3c20248 --- /dev/null +++ b/arch/arm/include/asm/proc @@ -0,0 +1 @@ +proc-armv
\ No newline at end of file diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index 20e1653930..eac3800729 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -38,7 +38,6 @@ typedef struct bd_info { int bi_baudrate; /* serial console baudrate */ - unsigned long bi_ip_addr; /* IP Address */ ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ unsigned long bi_arm_freq; /* arm frequency */ diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 5270c11262..3bb303ec31 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -64,6 +64,9 @@ #include "../drivers/net/lan91c96.h" #endif +/* For test nand easily */ +//#define DO_TEST_NAND_EASILY + DECLARE_GLOBAL_DATA_PTR; ulong monitor_flash_len; @@ -454,7 +457,9 @@ static char *failed = "*** failed ***\n"; * ************************************************************************ */ - +#ifdef TGT_AP_DO_NAND_TEST +extern void test_nand_easily(void); +#endif void board_init_r(gd_t *id, ulong dest_addr) { ulong malloc_start; @@ -532,6 +537,11 @@ void board_init_r(gd_t *id, ulong dest_addr) #if defined(CONFIG_CMD_NAND) puts("NAND: "); nand_init(); /* go init the NAND */ + +#ifdef TGT_AP_DO_NAND_TEST + test_nand_easily(); +#endif + #endif #if defined(CONFIG_CMD_ONENAND) @@ -555,9 +565,6 @@ void board_init_r(gd_t *id, ulong dest_addr) arm_pci_init(); #endif - /* IP Address */ - gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - stdio_init(); /* get the devices list going. */ jumptable_init(); @@ -595,14 +602,6 @@ void board_init_r(gd_t *id, ulong dest_addr) /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); -#if defined(CONFIG_CMD_NET) - { - char *s = getenv("bootfile"); - - if (s != NULL) - copy_filename(BootFile, s, sizeof(BootFile)); - } -#endif #ifdef CONFIG_BOARD_LATE_INIT board_late_init(); @@ -646,7 +645,6 @@ void board_init_r(gd_t *id, ulong dest_addr) setenv("mem", (char *)memsz); } #endif - /* main_loop() can return to retry autoboot, if so just run it again. */ for (;;) { main_loop(); diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h index ff1ed23db9..1d2959a2ad 100644 --- a/arch/avr32/include/asm/u-boot.h +++ b/arch/avr32/include/asm/u-boot.h @@ -24,7 +24,6 @@ typedef struct bd_info { unsigned long bi_baudrate; - unsigned long bi_ip_addr; unsigned char bi_phy_id[4]; unsigned long bi_board_number; void *bi_boot_params; diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index d626c29c00..b390a6c8f8 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -316,8 +316,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) /* initialize environment */ env_relocate(); - bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); - stdio_init(); jumptable_init(); console_init_r(); @@ -329,9 +327,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) bb_miiphy_init(); #endif #if defined(CONFIG_CMD_NET) - s = getenv("bootfile"); - if (s) - copy_filename(BootFile, s, sizeof(BootFile)); puts("Net: "); eth_initialize(gd->bd); #endif diff --git a/arch/blackfin/cpu/.gitignore b/arch/blackfin/cpu/.gitignore deleted file mode 100644 index ba986d8ba8..0000000000 --- a/arch/blackfin/cpu/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -bootrom-asm-offsets.[chs] - -init.lds -init.elf diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.awk b/arch/blackfin/cpu/bootrom-asm-offsets.awk index 1d61824254..1d61824254 100755..100644 --- a/arch/blackfin/cpu/bootrom-asm-offsets.awk +++ b/arch/blackfin/cpu/bootrom-asm-offsets.awk diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h index 1a8de4906d..25cd833865 100644 --- a/arch/blackfin/include/asm/config.h +++ b/arch/blackfin/include/asm/config.h @@ -109,14 +109,8 @@ #ifndef CONFIG_SYS_MALLOC_BASE # define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) #endif -#ifndef CONFIG_SYS_GBL_DATA_ADDR -# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE) -#endif -#ifndef CONFIG_SYS_BD_INFO_ADDR -# define CONFIG_SYS_BD_INFO_ADDR (CONFIG_SYS_GBL_DATA_ADDR - GENERATED_BD_INFO_SIZE) -#endif #ifndef CONFIG_STACKBASE -# define CONFIG_STACKBASE (CONFIG_SYS_BD_INFO_ADDR - 4) +# define CONFIG_STACKBASE (CONFIG_SYS_MALLOC_BASE - 4) #endif #ifndef CONFIG_SYS_MEMTEST_START # define CONFIG_SYS_MEMTEST_START 0 diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h index 67aa30f04c..973ea2929a 100644 --- a/arch/blackfin/include/asm/global_data.h +++ b/arch/blackfin/include/asm/global_data.h @@ -73,6 +73,6 @@ typedef struct global_data { #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ #define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ -#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P3") +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P3") #endif diff --git a/arch/blackfin/include/asm/u-boot.h b/arch/blackfin/include/asm/u-boot.h index 9712fc00ee..df81183e81 100644 --- a/arch/blackfin/include/asm/u-boot.h +++ b/arch/blackfin/include/asm/u-boot.h @@ -30,7 +30,6 @@ typedef struct bd_info { int bi_baudrate; /* serial console baudrate */ - unsigned long bi_ip_addr; /* IP Address */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ phys_size_t bi_memsize; /* size of DRAM memory in bytes */ diff --git a/arch/blackfin/lib/.gitignore b/arch/blackfin/lib/.gitignore deleted file mode 100644 index 09f1be04eb..0000000000 --- a/arch/blackfin/lib/.gitignore +++ /dev/null @@ -1 +0,0 @@ -u-boot.lds diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index e3ee4cd353..c380d271e7 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -86,7 +86,6 @@ static void display_global_data(void) printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt)); printf(" \\-bd: %p\n", gd->bd); printf(" |-bi_baudrate: %x\n", bd->bi_baudrate); - printf(" |-bi_ip_addr: %lx\n", bd->bi_ip_addr); printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params); printf(" |-bi_memstart: %lx\n", bd->bi_memstart); printf(" |-bi_memsize: %lx\n", bd->bi_memsize); @@ -181,6 +180,46 @@ void init_cplbtables(void) } } +static int global_board_data_init(void) +{ +#ifndef CONFIG_SYS_GBL_DATA_ADDR +# define CONFIG_SYS_GBL_DATA_ADDR 0 +#endif +#ifndef CONFIG_SYS_BD_INFO_ADDR +# define CONFIG_SYS_BD_INFO_ADDR 0 +#endif + + bd_t *bd; + + if (CONFIG_SYS_GBL_DATA_ADDR) { + gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR); + memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE); + } else { + static gd_t _bfin_gd; + gd = &_bfin_gd; + } + + if (CONFIG_SYS_BD_INFO_ADDR) { + bd = (bd_t *) (CONFIG_SYS_BD_INFO_ADDR); + memset(bd, 0, GENERATED_BD_INFO_SIZE); + } else { + static bd_t _bfin_bd; + bd = &_bfin_bd; + } + gd->bd = bd; + + bd->bi_r_version = version_string; + bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU); + bd->bi_board_name = BFIN_BOARD_NAME; + bd->bi_vco = get_vco(); + bd->bi_cclk = get_cclk(); + bd->bi_sclk = get_sclk(); + bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + + return 0; +} + /* * All attempts to come up with a "common" initialization sequence * that works for all boards and architectures failed: some of the @@ -201,7 +240,6 @@ extern int timer_init(void); void board_init_f(ulong bootflag) { - bd_t *bd; char buf[32]; #ifdef CONFIG_BOARD_EARLY_INIT_F @@ -234,21 +272,8 @@ void board_init_f(ulong bootflag) hang(); #endif serial_early_puts("Init global data\n"); - gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR); - memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE); - bd = (bd_t *) (CONFIG_SYS_BD_INFO_ADDR); - gd->bd = bd; - memset((void *)bd, 0, GENERATED_BD_INFO_SIZE); - - bd->bi_r_version = version_string; - bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU); - bd->bi_board_name = BFIN_BOARD_NAME; - bd->bi_vco = get_vco(); - bd->bi_cclk = get_cclk(); - bd->bi_sclk = get_sclk(); - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + global_board_data_init(); /* Initialize */ serial_early_puts("IRQ init\n"); @@ -276,7 +301,7 @@ void board_init_f(ulong bootflag) if (CONFIG_MEM_SIZE) { printf("RAM: "); - print_size(bd->bi_memsize, "\n"); + print_size(gd->bd->bi_memsize, "\n"); } #if defined(CONFIG_POST) @@ -294,15 +319,8 @@ static void board_net_init_r(bd_t *bd) bb_miiphy_init(); #endif #ifdef CONFIG_CMD_NET - char *s; - - if ((s = getenv("bootfile")) != NULL) - copy_filename(BootFile, s, sizeof(BootFile)); - - bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - printf("Net: "); - eth_initialize(gd->bd); + eth_initialize(bd); #endif } diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h index 0a48bbdbe6..973c9ee098 100644 --- a/arch/m68k/include/asm/u-boot.h +++ b/arch/m68k/include/asm/u-boot.h @@ -47,7 +47,6 @@ typedef struct bd_info { unsigned long bi_mbar_base; /* base of internal registers */ unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ unsigned long bi_boot_params; /* where this board expects params */ - unsigned long bi_ip_addr; /* IP Address */ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index 1526967fe3..65a8595c2b 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -507,15 +507,6 @@ void board_init_r (gd_t *id, ulong dest_addr) /* relocate environment function pointers etc. */ env_relocate (); - /* - * Fill in missing fields of bd_info. - * We do this here, where we have "normal" access to the - * environment; we used to do this still running from ROM, - * where had to use getenv_f(), which can be pretty slow when - * the environment is in EEPROM. - */ - bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); - WATCHDOG_RESET (); #if defined(CONFIG_PCI) @@ -568,11 +559,6 @@ void board_init_r (gd_t *id, ulong dest_addr) /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); -#if defined(CONFIG_CMD_NET) - if ((s = getenv ("bootfile")) != NULL) { - copy_filename (BootFile, s, sizeof (BootFile)); - } -#endif WATCHDOG_RESET (); diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h index 21c72d5940..a0b1dbf9e6 100644 --- a/arch/microblaze/include/asm/u-boot.h +++ b/arch/microblaze/include/asm/u-boot.h @@ -40,7 +40,6 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_ip_addr; /* IP Address */ unsigned long bi_baudrate; /* Console Baudrate */ } bd_t; diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index 9828b7630f..f3679d536b 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -176,19 +176,12 @@ void board_init (void) load_addr = getenv_ulong("loadaddr", 16, load_addr); #if defined(CONFIG_CMD_NET) - /* IP Address */ - bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - printf("Net: "); eth_initialize(gd->bd); uchar enetaddr[6]; eth_getenv_enetaddr("ethaddr", enetaddr); printf("MAC: %pM\n", enetaddr); - - s = getenv("bootfile"); - if (s != NULL) - copy_filename(BootFile, s, sizeof(BootFile)); #endif /* main_loop */ diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c b/arch/mips/cpu/mips32/au1x00/au1x00_eth.c index c51079961c..ac03a452bc 100644 --- a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c +++ b/arch/mips/cpu/mips32/au1x00/au1x00_eth.c @@ -147,7 +147,8 @@ int au1x00_miiphy_write(const char *devname, unsigned char addr, } #endif -static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){ +static int au1x00_send(struct eth_device *dev, void *packet, int length) +{ volatile mac_fifo_t *fifo_tx = (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS); int i; diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h index edb87bb066..590649aa3e 100644 --- a/arch/mips/include/asm/u-boot.h +++ b/arch/mips/include/asm/u-boot.h @@ -33,7 +33,6 @@ typedef struct bd_info { int bi_baudrate; /* serial console baudrate */ - unsigned long bi_ip_addr; /* IP Address */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index 38e6e77a34..59a80011da 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -320,9 +320,6 @@ void board_init_r(gd_t *id, ulong dest_addr) /* relocate environment function pointers etc. */ env_relocate(); - /* IP Address */ - bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - #if defined(CONFIG_PCI) /* * Do pci configuration @@ -342,14 +339,6 @@ void board_init_r(gd_t *id, ulong dest_addr) /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); -#if defined(CONFIG_CMD_NET) - { - char *s = getenv("bootfile"); - - if (s != NULL) - copy_filename(BootFile, s, sizeof(BootFile)); - } -#endif #ifdef CONFIG_CMD_SPI puts("SPI: "); diff --git a/arch/nds32/cpu/n1213/ag102/Makefile b/arch/nds32/cpu/n1213/ag102/Makefile new file mode 100644 index 0000000000..8716c4e858 --- /dev/null +++ b/arch/nds32/cpu/n1213/ag102/Makefile @@ -0,0 +1,58 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# Copyright (C) 2011 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> +# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS-y := cpu.o timer.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +SOBJS := lowlevel_init.o +endif + +ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG +SOBJS += watchdog.o +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/nds32/cpu/n1213/ag102/asm-offsets.c b/arch/nds32/cpu/n1213/ag102/asm-offsets.c new file mode 100644 index 0000000000..4769a9521d --- /dev/null +++ b/arch/nds32/cpu/n1213/ag102/asm-offsets.c @@ -0,0 +1,54 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * Generate definitions needed by assembly language modules. + * This code generates raw asm output which is post-processed to extract + * and format the required data. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <common.h> + +#include <linux/kbuild.h> + +int main(void) +{ +#ifdef CONFIG_FTSMC020 + OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr); + OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr); +#endif + BLANK(); +#ifdef CONFIG_FTAHBC020S + OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); + OFFSET(FTAHBC020S_CR, ftahbc02s, cr); +#endif + BLANK(); +#ifdef CONFIG_ANDES_PCU + OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */ +#endif + BLANK(); +#ifdef CONFIG_DWCDDR21MCTL + OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */ + OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */ + OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */ + OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */ + OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */ + OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */ + OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */ + OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */ + OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */ + OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */ + OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */ + OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */ + OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */ + OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */ + OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */ + OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */ + OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */ + OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */ + OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */ +#endif + return 0; +} diff --git a/arch/nds32/cpu/n1213/ag102/cpu.c b/arch/nds32/cpu/n1213/ag102/cpu.c new file mode 100644 index 0000000000..ed88b522a4 --- /dev/null +++ b/arch/nds32/cpu/n1213/ag102/cpu.c @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* CPU specific code */ +#include <common.h> +#include <command.h> +#include <watchdog.h> +#include <asm/cache.h> + +#include <faraday/ftwdt010_wdt.h> + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + +#ifdef CONFIG_MMU + /* turn off I/D-cache */ + icache_disable(); + dcache_disable(); + + /* flush I/D-cache */ + invalidate_icac(); + invalidate_dcac(); +#endif + + return 0; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + disable_interrupts(); + + /* + * reset to the base addr of andesboot. + * currently no ROM loader at addr 0. + * do not use reset_cpu(0); + */ +#ifdef CONFIG_FTWDT010_WATCHDOG + /* + * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead + * automatic hardware reset when booting Linux. + * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here. + */ + ftwdt010_wdt_reset(); +#endif /* CONFIG_FTWDT010_WATCHDOG */ + hang(); + + /*NOTREACHED*/ +} + +static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) +{ + if (cache == ICACHE) + return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \ + >> ICM_CFG_OFF_ISZ) - 1); + else + return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \ + >> DCM_CFG_OFF_DSZ) - 1); +} + +void dcache_flush_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(DCACHE); + + while (end > start) { + __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start)); + __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start)); + start += line_size; + } +} + +void icache_inval_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(ICACHE); + while (end > start) { + __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start)); + start += line_size; + } +} + +void flush_cache(unsigned long addr, unsigned long size) +{ + dcache_flush_range(addr, addr + size); + icache_inval_range(addr, addr + size); +} + +void icache_enable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8\n\t" + "ori $p0, $p0, 0x01\n\t" + "mtsr $p0, $mr8\n\t" + "isb\n\t" + ); +} + +void icache_disable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8\n\t" + "li $p1, ~0x01\n\t" + "and $p0, $p0, $p1\n\t" + "mtsr $p0, $mr8\n\t" + "isb\n\t" + ); +} + +int icache_status(void) +{ + int ret; + + __asm__ __volatile__ ( + "mfsr $p0, $mr8\n\t" + "andi %0, $p0, 0x01\n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +} + +void dcache_enable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8\n\t" + "ori $p0, $p0, 0x02\n\t" + "mtsr $p0, $mr8\n\t" + "isb\n\t" + ); +} + +void dcache_disable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8\n\t" + "li $p1, ~0x02\n\t" + "and $p0, $p0, $p1\n\t" + "mtsr $p0, $mr8\n\t" + "isb\n\t" + ); +} + +int dcache_status(void) +{ + int ret; + + __asm__ __volatile__ ( + "mfsr $p0, $mr8\n\t" + "andi %0, $p0, 0x02\n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +} diff --git a/arch/nds32/cpu/n1213/ag102/lowlevel_init.S b/arch/nds32/cpu/n1213/ag102/lowlevel_init.S new file mode 100644 index 0000000000..d842afa4ba --- /dev/null +++ b/arch/nds32/cpu/n1213/ag102/lowlevel_init.S @@ -0,0 +1,297 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.text + +#include <common.h> +#include <config.h> + +#include <asm/macro.h> +#include <generated/asm-offsets.h> + +/* + * parameters for Synopsys DWC DDR2/DDR1 Memory Controller + */ +#define DDR2C_BASE_A (CONFIG_DWCDDR21MCTL_BASE) +#define DDR2C_CCR_A (DDR2C_BASE_A + DWCDDR21MCTL_CCR) +#define DDR2C_DCR_A (DDR2C_BASE_A + DWCDDR21MCTL_DCR) +#define DDR2C_IOCR_A (DDR2C_BASE_A + DWCDDR21MCTL_IOCR) +#define DDR2C_CSR_A (DDR2C_BASE_A + DWCDDR21MCTL_CSR) +#define DDR2C_DRR_A (DDR2C_BASE_A + DWCDDR21MCTL_DRR) +#define DDR2C_DLLCR0_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR0) +#define DDR2C_DLLCR1_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR1) +#define DDR2C_DLLCR2_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR2) +#define DDR2C_DLLCR3_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR3) +#define DDR2C_DLLCR4_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR4) +#define DDR2C_DLLCR5_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR5) +#define DDR2C_DLLCR6_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR6) +#define DDR2C_DLLCR7_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR7) +#define DDR2C_DLLCR8_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR8) +#define DDR2C_DLLCR9_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR9) +#define DDR2C_RSLR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RSLR0) +#define DDR2C_RDGR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RDGR0) +#define DDR2C_DTAR_A (DDR2C_BASE_A + DWCDDR21MCTL_DTAR) +#define DDR2C_MR_A (DDR2C_BASE_A + DWCDDR21MCTL_MR) + +#define DDR2C_CCR_D CONFIG_SYS_DWCDDR21MCTL_CCR +#define DDR2C_CCR_D2 CONFIG_SYS_DWCDDR21MCTL_CCR2 +#define DDR2C_DCR_D CONFIG_SYS_DWCDDR21MCTL_DCR +#define DDR2C_IOCR_D CONFIG_SYS_DWCDDR21MCTL_IOCR +#define DDR2C_CSR_D CONFIG_SYS_DWCDDR21MCTL_CSR +#define DDR2C_DRR_D CONFIG_SYS_DWCDDR21MCTL_DRR +#define DDR2C_RSLR0_D CONFIG_SYS_DWCDDR21MCTL_RSLR0 +#define DDR2C_RDGR0_D CONFIG_SYS_DWCDDR21MCTL_RDGR0 +#define DDR2C_DTAR_D CONFIG_SYS_DWCDDR21MCTL_DTAR +#define DDR2C_MR_D CONFIG_SYS_DWCDDR21MCTL_MR + +#define DDR2C_DLLCR0_D CONFIG_SYS_DWCDDR21MCTL_DLLCR0 /* 0-9 are same */ + +/* + * parameters for the ahbc controller + */ +#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR) +#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6) + +#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 + +/* + * parameters for the ANDES PCU controller + */ +#define PCU_PCS4_A (CONFIG_ANDES_PCU_BASE + ANDES_PCU_PCS4) +#define PCU_PCS4_D CONFIG_SYS_ANDES_CPU_PCS4 + +/* + * numeric 7 segment display + */ +.macro led, num + write32 CONFIG_DEBUG_LED, \num +.endm + +/* + * Waiting for SDRAM to set up + */ +/* +.macro wait_sdram + li $r0, DDR2C_CSR_A +1: + lwi $r1, [$r0+FTSDMC021_CR2] + bnez $r1, 1b +.endm +*/ + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +.globl lowlevel_init +lowlevel_init: + move $r10, $lp + + /* U200 */ +! led 0x00 +! jal scale_to_500mhz + + led 0x10 + jal mem_init + + led 0x20 + jal remap + + led 0x30 + ret $r10 + +scale_to_500mhz: + move $r11, $lp + + /* + * scale to 500Mhz + */ + led 0x01 + write32 PCU_PCS4_A, 0x1102000f ! save data to PCS4 + + move $lp, $r11 + ret + +mem_init: + move $r11, $lp + + /* + * config AHB Controller + */ + led 0x12 + write32 AHBC_BSR6_A, AHBC_BSR6_D + + /* + * config Synopsys DWC DDR2/DDR1 Memory Controller + */ +ddr2c_init: +set_dcr: + led 0x14 + write32 DDR2C_DCR_A, DDR2C_DCR_D ! 0x000020d4 + +auto_sizing: + /* + * ebios: $r10->$r7, $r11->$r8, $r12->$r9, $r13->$r12, $r14->$r13 + */ +set_iocr: + led 0x19 + write32 DDR2C_IOCR_A, DDR2C_IOCR_D +set_drr: + led 0x16 + write32 DDR2C_DRR_A, DDR2C_DRR_D ! 0x00034812 +set_dllcr: + led 0x18 + write32 DDR2C_DLLCR0_A, DDR2C_DLLCR0_D + write32 DDR2C_DLLCR1_A, DDR2C_DLLCR0_D + write32 DDR2C_DLLCR2_A, DDR2C_DLLCR0_D + write32 DDR2C_DLLCR3_A, DDR2C_DLLCR0_D + write32 DDR2C_DLLCR4_A, DDR2C_DLLCR0_D + write32 DDR2C_DLLCR5_A, DDR2C_DLLCR0_D + write32 DDR2C_DLLCR6_A, DDR2C_DLLCR0_D + write32 DDR2C_DLLCR7_A, DDR2C_DLLCR0_D + write32 DDR2C_DLLCR8_A, DDR2C_DLLCR0_D + write32 DDR2C_DLLCR9_A, DDR2C_DLLCR0_D +set_rslr0: + write32 DDR2C_RSLR0_A, DDR2C_RSLR0_D ! 0x00000040 +set_rdgr0: + write32 DDR2C_RDGR0_A, DDR2C_RDGR0_D ! 0x000055cf +set_dtar: + led 0x15 + write32 DDR2C_DTAR_A, DDR2C_DTAR_D ! 0x00100000 +set_mode: + led 0x17 + write32 DDR2C_MR_A, DDR2C_MR_D ! 0x00000852 +set_ccr: + write32 DDR2C_CCR_A, DDR2C_CCR_D + +#ifdef TRIGGER_INIT: +trigger_init: + write32 DDR2C_CCR_A, DDR2C_CCR_D ! 0x80020000 + + /* Wait for ddr init state to be set */ + msync ALL + isb + + /* Wait until the config initialization is finish */ +1: + la $r4, DDR2C_CSR_A + lwi $r5, [$r4] + srli $r5, $r5, 23 + bnez $r5, 1b +#endif + +data_training: +! write32 DDR2C_CCR_A, DDR2C_CCR_D2 ! 0x40020004 + + /* Wait for ddr init state to be set */ + msync ALL + isb + + /* wait until the ddr data trainning is complete */ +1: + la $r4, DDR2C_CSR_A + lwi $r5, [$r4] + srli $r6, $r5, 23 + bnez $r6, 1b + + lwi $r1, [$r4] + srli $r6, $r5, 20 + li $r5, 0x00ffffff + swi $r1, [$r4] + bnez $r6, ddr2c_init + + led 0x1a + move $lp, $r11 + ret + +remap: + move $r11, $lp +#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */ + bal 2f +relo_base: + move $r0, $lp +#else +relo_base: + mfusr $r0, $pc +#endif /* __NDS32_N1213_43U1H__ */ + + /* + * Remapping + */ +#ifdef CONFIG_MEM_REMAP + /* + * Copy ROM code to SDRAM base for memory remap layout. + * This is not the real relocation, the real relocation is the function + * relocate_code() is start.S which supports the systems is memory + * remapped or not. + */ + /* + * Doing memory remap is essential for preparing some non-OS or RTOS + * applications. + * + * This is also a must on ADP-AG101 board. + * The reason is because the ROM/FLASH circuit on PCB board. + * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which + * ROM/FLASH is used to boot. + * + * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0, + * and the FLASH is connected to BANK1. + * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0), + * and the FLASH is connected to BANK0. + * It will occur problem when doing flash probing if the flash is at + * BANK0 (0x00000000) while memory remapping was skipped. + * + * Other board like ADP-AG101P may not enable this since there is only + * a FLASH connected to bank0. + */ + led 0x21 + li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */ + li $r5, 0x0 + la $r1, relo_base /* get $pc or $lp */ + sub $r2, $r0, $r1 + sethi $r6, hi20(_end) + ori $r6, $r6, lo12(_end) + add $r6, $r6, $r2 +1: + lwi.p $r7, [$r5], #4 + swi.p $r7, [$r4], #4 + blt $r5, $r6, 1b + + /* set remap bit */ + /* + * MEM remap bit is operational + * - use it to map writeable memory at 0x00000000, in place of flash + * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff + * - after remap: flash/rom 0x80000000, sdram: 0x00000000 + */ + led 0x2c + setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1 + +#endif /* #ifdef CONFIG_MEM_REMAP */ + move $lp, $r11 +2: + ret + +.globl show_led +show_led: + li $r8, (CONFIG_DEBUG_LED) + swi $r7, [$r8] + ret +#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/arch/nds32/cpu/n1213/ag102/timer.c b/arch/nds32/cpu/n1213/ag102/timer.c new file mode 100644 index 0000000000..caa36b8be8 --- /dev/null +++ b/arch/nds32/cpu/n1213/ag102/timer.c @@ -0,0 +1,205 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert@faraday-tech.com> + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/io.h> +#include <faraday/fttmr010.h> + +static ulong timestamp; +static ulong lastdec; + +int timer_init(void) +{ + struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; + unsigned int cr; + + debug("%s()\n", __func__); + + /* disable timers */ + writel(0, &tmr->cr); + +#ifdef CONFIG_FTTMR010_EXT_CLK + /* use 32768Hz oscillator for RTC, WDT, TIMER */ + ftpmu010_32768osc_enable(); +#endif + + /* setup timer */ + writel(TIMER_LOAD_VAL, &tmr->timer3_load); + writel(TIMER_LOAD_VAL, &tmr->timer3_counter); + writel(0, &tmr->timer3_match1); + writel(0, &tmr->timer3_match2); + + /* we don't want timer to issue interrupts */ + writel(FTTMR010_TM3_MATCH1 | + FTTMR010_TM3_MATCH2 | + FTTMR010_TM3_OVERFLOW, + &tmr->interrupt_mask); + + cr = readl(&tmr->cr); +#ifdef CONFIG_FTTMR010_EXT_CLK + cr |= FTTMR010_TM3_CLOCK; /* use external clock */ +#endif + cr |= FTTMR010_TM3_ENABLE; + writel(cr, &tmr->cr); + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +/* + * reset time + */ +void reset_timer_masked(void) +{ + struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; + + /* capure current decrementer value time */ +#ifdef CONFIG_FTTMR010_EXT_CLK + lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); +#else + lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2); +#endif + timestamp = 0; /* start "advancing" time stamp from 0 */ + + debug("%s(): lastdec = %lx\n", __func__, lastdec); +} + +void reset_timer(void) +{ + debug("%s()\n", __func__); + reset_timer_masked(); +} + +/* + * return timer ticks + */ +ulong get_timer_masked(void) +{ + struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; + + /* current tick value */ +#ifdef CONFIG_FTTMR010_EXT_CLK + ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); +#else + ulong now = readl(&tmr->timer3_counter) / \ + (CONFIG_SYS_CLK_FREQ / 2 / 1024); +#endif + + debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec); + + if (lastdec >= now) { + /* + * normal mode (non roll) + * move stamp fordward with absoulte diff ticks + */ + timestamp += lastdec - now; + } else { + /* + * we have overflow of the count down timer + * + * nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and + * cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + + lastdec = now; + + debug("%s() returns %lx\n", __func__, timestamp); + + return timestamp; +} + +/* + * return difference between timer ticks and base + */ +ulong get_timer(ulong base) +{ + debug("%s(%lx)\n", __func__, base); + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + debug("%s(%lx)\n", __func__, t); + timestamp = t; +} + +/* delay x useconds AND preserve advance timestamp value */ +void __udelay(unsigned long usec) +{ + struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; + +#ifdef CONFIG_FTTMR010_EXT_CLK + long tmo = usec * (TIMER_CLOCK / 1000) / 1000; +#else + long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000; +#endif + unsigned long now, last = readl(&tmr->timer3_counter); + + debug("%s(%lu)\n", __func__, usec); + while (tmo > 0) { + now = readl(&tmr->timer3_counter); + if (now > last) /* count down timer overflow */ + tmo -= TIMER_LOAD_VAL + last - now; + else + tmo -= last - now; + last = now; + } +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + debug("%s()\n", __func__); + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + debug("%s()\n", __func__); +#ifdef CONFIG_FTTMR010_EXT_CLK + return CONFIG_SYS_HZ; +#else + return CONFIG_SYS_CLK_FREQ; +#endif +} diff --git a/arch/nds32/cpu/n1213/ag102/watchdog.S b/arch/nds32/cpu/n1213/ag102/watchdog.S new file mode 100644 index 0000000000..56cecda78f --- /dev/null +++ b/arch/nds32/cpu/n1213/ag102/watchdog.S @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch-ag102/ag102.h> +#include <linux/linkage.h> + +.text + +#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG +ENTRY(turnoff_watchdog) + +#define WD_CR 0xC +#define WD_ENABLE 0x1 + + ! Turn off the watchdog, according to Faraday FTWDT010 spec + li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR + lwi $p1, [$p0] ! Get the config of WD + andi $p1, $p1, 0x1f ! Wipe out useless bits + li $r0, ~WD_ENABLE + and $p1, $p1, $r0 ! Set WD disable + sw $p1, [$p0] ! Write back to WD CR + + ! Disable Interrupts by clear GIE in $PSW reg + setgie.d + + ret + +ENDPROC(turnoff_watchdog) +#endif diff --git a/arch/nds32/include/asm/arch-ag102/ag102.h b/arch/nds32/include/asm/arch-ag102/ag102.h new file mode 100644 index 0000000000..a12a8c52b7 --- /dev/null +++ b/arch/nds32/include/asm/arch-ag102/ag102.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __AG102_H +#define __AG102_H + +/* + * Hardware register bases + */ + +/* PCI Controller */ +#define CONFIG_FTPCI100_BASE 0x90000000 +/* LPC Controller */ +#define CONFIG_LPC_IO_BASE 0x90100000 +/* LPC Controller */ +#define CONFIG_LPC_BASE 0x90200000 + +/* NDS32 Data Local Memory 01 */ +#define CONFIG_NDS_DLM1_BASE 0x90300000 +/* NDS32 Data Local Memory 02 */ +#define CONFIG_NDS_DLM2_BASE 0x90400000 + +/* Synopsys DWC DDR2/1 Controller */ +#define CONFIG_DWCDDR21MCTL_BASE 0x90500000 +/* DMA Controller */ +#define CONFIG_FTDMAC020_BASE 0x90600000 +/* FTIDE020_S IDE (ATA) Controller */ +#define CONFIG_FTIDE020S_BASE 0x90700000 +/* USB OTG Controller */ +#define CONFIG_FZOTG266HD0A_BASE 0x90800000 +/* Andes L2 Cache Controller */ +#define CONFIG_NCEL2C100_BASE 0x90900000 +/* XGI XG22 GPU */ +#define CONFIG_XGI_XG22_BASE 0x90A00000 +/* GMAC Ethernet Controller */ +#define CONFIG_FTGMAC100_BASE 0x90B00000 +/* AHB Controller */ +#define CONFIG_FTAHBC020S_BASE 0x90C00000 +/* AHB-to-APB Bridge Controller */ +#define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000 +/* External AHB2AHB Controller */ +#define CONFIG_EXT_AHB2AHB_BASE 0x90E00000 +/* Andes Multi-core Interrupt Controller */ +#define CONFIG_NCEMIC100_BASE 0x90F00000 + +/* + * APB Device definitions + */ +/* Compat Flash Controller */ +#define CONFIG_FTCFC010_BASE 0x94000000 +/* APB - SSP (SPI) (without AC97) Controller */ +#define CONFIG_FTSSP010_01_BASE 0x94100000 +/* UART1 - APB STUART Controller (UART0 in Linux) */ +#define CONFIG_FTUART010_01_BASE 0x94200000 +/* FTSDC010 SD Controller */ +#define CONFIG_FTSDC010_BASE 0x94400000 +/* APB - SSP with HDA/AC97 Controller */ +#define CONFIG_FTSSP010_02_BASE 0x94500000 +/* UART2 - APB STUART Controller (UART1 in Linux) */ +#define CONFIG_FTUART010_02_BASE 0x94600000 +/* PCU Controller */ +#define CONFIG_ANDES_PCU_BASE 0x94800000 +/* FTTMR010 Timer */ +#define CONFIG_FTTMR010_BASE 0x94900000 +/* Watch Dog Controller */ +#define CONFIG_FTWDT010_BASE 0x94A00000 +/* FTRTC010 Real Time Clock */ +#define CONFIG_FTRTC010_BASE 0x98B00000 +/* GPIO Controller */ +#define CONFIG_FTGPIO010_BASE 0x94C00000 +/* I2C Controller */ +#define CONFIG_FTIIC010_BASE 0x94E00000 +/* PWM - Pulse Width Modulator Controller */ +#define CONFIG_FTPWM010_BASE 0x94F00000 + +/* Debug LED */ +#define CONFIG_DEBUG_LED 0x902FFFFC +/* Power Management Unit */ +#define CONFIG_FTPMU010_BASE 0x98100000 + +#endif /* __AG102_H */ diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h index 7b52b989bc..259e4e7ad9 100644 --- a/arch/nds32/include/asm/mach-types.h +++ b/arch/nds32/include/asm/mach-types.h @@ -40,4 +40,18 @@ extern unsigned int __machine_arch_type; # define machine_is_adpag101p() (1) #endif +#define MACH_TYPE_ADPAG102 2 + +#ifdef CONFIG_ARCH_ADPAG102 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADPAG102 +# endif +# define machine_is_adpag102() (machine_arch_type == MACH_TYPE_ADPAG102) +#else +# define machine_is_adpag102() (2) +#endif + #endif /* __ASM_NDS32_MACH_TYPE_H */ diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h index 9a697501d1..eabbf38fb1 100644 --- a/arch/nds32/include/asm/u-boot.h +++ b/arch/nds32/include/asm/u-boot.h @@ -40,7 +40,6 @@ typedef struct bd_info { int bi_baudrate; /* serial console baudrate */ - unsigned long bi_ip_addr; /* IP Address */ unsigned char bi_enetaddr[6]; /* Ethernet adress */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c index 074aabf1e4..7121313a83 100644 --- a/arch/nds32/lib/board.c +++ b/arch/nds32/lib/board.c @@ -369,9 +369,6 @@ void board_init_r(gd_t *id, ulong dest_addr) nds32_pci_init(); #endif - /* IP Address */ - gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - stdio_init(); /* get the devices list going. */ jumptable_init(); @@ -402,12 +399,6 @@ void board_init_r(gd_t *id, ulong dest_addr) /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); -#if defined(CONFIG_CMD_NET) - s = getenv("bootfile"); - if (s != NULL) - copy_filename(BootFile, s, sizeof(BootFile)); -#endif - #ifdef BOARD_LATE_INIT board_late_init(); #endif diff --git a/arch/nios2/include/asm/u-boot.h b/arch/nios2/include/asm/u-boot.h index f7c70ff0c1..315ef8bedb 100644 --- a/arch/nios2/include/asm/u-boot.h +++ b/arch/nios2/include/asm/u-boot.h @@ -39,7 +39,6 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_ip_addr; /* IP Address */ unsigned long bi_baudrate; /* Console Baudrate */ } bd_t; diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c index 65de26e5c9..ca8a3e5246 100644 --- a/arch/nios2/lib/board.c +++ b/arch/nios2/lib/board.c @@ -143,8 +143,6 @@ void board_init (void) WATCHDOG_RESET (); env_relocate(); - bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); - WATCHDOG_RESET (); stdio_init(); jumptable_init(); diff --git a/arch/openrisc/include/asm/u-boot.h b/arch/openrisc/include/asm/u-boot.h index 2913994932..76b813273f 100644 --- a/arch/openrisc/include/asm/u-boot.h +++ b/arch/openrisc/include/asm/u-boot.h @@ -33,7 +33,6 @@ typedef struct bd_info { unsigned long bi_baudrate; /* serial console baudrate */ - unsigned long bi_ip_addr; /* IP Address */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ diff --git a/arch/powerpc/cpu/mpc8220/fec.c b/arch/powerpc/cpu/mpc8220/fec.c index 2053fea571..aaf9be107a 100644 --- a/arch/powerpc/cpu/mpc8220/fec.c +++ b/arch/powerpc/cpu/mpc8220/fec.c @@ -624,7 +624,7 @@ static void rfifo_print (char *devname, mpc8220_fec_priv * fec) /********************************************************************/ -static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data, +static int mpc8220_fec_send(struct eth_device *dev, void *eth_data, int data_length) { /* @@ -787,8 +787,7 @@ static int mpc8220_fec_recv (struct eth_device *dev) */ /* memcpy(buff, frame->head, 14); memcpy(buff + 14, frame->data, frame_length);*/ - NetReceive ((volatile uchar *) pRbd->dataPointer, - frame_length); + NetReceive((uchar *)pRbd->dataPointer, frame_length); len = frame_length; } /* diff --git a/arch/powerpc/cpu/mpc824x/.gitignore b/arch/powerpc/cpu/mpc824x/.gitignore deleted file mode 100644 index 2d79931e96..0000000000 --- a/arch/powerpc/cpu/mpc824x/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/bedbug_603e.c diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c index 879ec0ea23..18534516a4 100644 --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c +++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c @@ -142,7 +142,7 @@ static RTXBD rtx __attribute__ ((aligned(8))); #error "rtx must be 64-bit aligned" #endif -static int fec_send(struct eth_device* dev, volatile void *packet, int length) +static int fec_send(struct eth_device *dev, void *packet, int length) { int i; int result = 0; @@ -1049,11 +1049,11 @@ eth_loopback_test (void) } else { ushort datlen = bdp->cbd_datlen; - Ethernet_t *ehp; + struct ethernet_hdr *ehp; ushort prot; int ours, tb, n, nbytes; - ehp = (Ethernet_t *) \ + ehp = (struct ethernet_hdr *) \ &ecp->rxbufs[i][0]; ours = memcmp (ehp->et_src, \ @@ -1063,9 +1063,8 @@ eth_loopback_test (void) tb = prot & 0x8000; n = prot & 0x7fff; - nbytes = ELBT_BUFSZ - \ - offsetof (Ethernet_t, \ - et_dsap) - \ + nbytes = ELBT_BUFSZ - + ETHER_HDR_SIZE - ELBT_CRCSZ; /* check the frame is correct */ @@ -1080,10 +1079,10 @@ eth_loopback_test (void) patwords[n]; uint nbb; - nbb = badbits ( \ - &ehp->et_dsap, \ - nbytes, \ - patword); + nbb = badbits( + ((uchar *)&ehp) + + ETHER_HDR_SIZE, + nbytes, patword); ecp->rxeacc.badbit += \ nbb; diff --git a/arch/powerpc/cpu/mpc8260/ether_scc.c b/arch/powerpc/cpu/mpc8260/ether_scc.c index 1c040f0f5b..3c71219575 100644 --- a/arch/powerpc/cpu/mpc8260/ether_scc.c +++ b/arch/powerpc/cpu/mpc8260/ether_scc.c @@ -105,7 +105,7 @@ typedef volatile struct CommonBufferDescriptor { static RTXBD *rtx; -static int sec_send(struct eth_device *dev, volatile void *packet, int length) +static int sec_send(struct eth_device *dev, void *packet, int length) { int i; int result = 0; diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2e4a06c35a..2cd5db7c59 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -37,6 +37,7 @@ #include <asm/mmu.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> +#include <asm/fsl_srio.h> #include <linux/compiler.h> #include "mp.h" #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -48,8 +49,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern void srio_init(void); - #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -443,6 +442,12 @@ skip_l2: #ifdef CONFIG_SYS_SRIO srio_init(); +#ifdef CONFIG_SRIOBOOT_MASTER + srio_boot_master(); +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF + srio_boot_master_release_slave(); +#endif +#endif #endif #if defined(CONFIG_MP) diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c index 41c3c84ae5..7d372aaef6 100644 --- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c +++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c @@ -138,7 +138,7 @@ static RTXBD rtx __attribute__ ((aligned(8))); #undef ET_DEBUG -static int fec_send(struct eth_device* dev, volatile void *packet, int length) +static int fec_send(struct eth_device *dev, void *packet, int length) { int i = 0; int result = 0; diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 4d37d6e863..8e99ef6c68 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -179,41 +179,50 @@ l2_disabled: andi. r1,r3,L1CSR0_DCE@l beq 2b +/* + * Ne need to setup interrupt vector for NAND SPL + * because NAND SPL never compiles it. + */ +#if !defined(CONFIG_NAND_SPL) /* Setup interrupt vectors */ lis r1,CONFIG_SYS_MONITOR_BASE@h mtspr IVPR,r1 - li r1,0x0100 - mtspr IVOR0,r1 /* 0: Critical input */ - li r1,0x0200 - mtspr IVOR1,r1 /* 1: Machine check */ - li r1,0x0300 - mtspr IVOR2,r1 /* 2: Data storage */ - li r1,0x0400 - mtspr IVOR3,r1 /* 3: Instruction storage */ - li r1,0x0500 - mtspr IVOR4,r1 /* 4: External interrupt */ - li r1,0x0600 - mtspr IVOR5,r1 /* 5: Alignment */ - li r1,0x0700 - mtspr IVOR6,r1 /* 6: Program check */ - li r1,0x0800 - mtspr IVOR7,r1 /* 7: floating point unavailable */ - li r1,0x0900 - mtspr IVOR8,r1 /* 8: System call */ + lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h + ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l + + addi r4,r3,CriticalInput - _start + _START_OFFSET + mtspr IVOR0,r4 /* 0: Critical input */ + addi r4,r3,MachineCheck - _start + _START_OFFSET + mtspr IVOR1,r4 /* 1: Machine check */ + addi r4,r3,DataStorage - _start + _START_OFFSET + mtspr IVOR2,r4 /* 2: Data storage */ + addi r4,r3,InstStorage - _start + _START_OFFSET + mtspr IVOR3,r4 /* 3: Instruction storage */ + addi r4,r3,ExtInterrupt - _start + _START_OFFSET + mtspr IVOR4,r4 /* 4: External interrupt */ + addi r4,r3,Alignment - _start + _START_OFFSET + mtspr IVOR5,r4 /* 5: Alignment */ + addi r4,r3,ProgramCheck - _start + _START_OFFSET + mtspr IVOR6,r4 /* 6: Program check */ + addi r4,r3,FPUnavailable - _start + _START_OFFSET + mtspr IVOR7,r4 /* 7: floating point unavailable */ + addi r4,r3,SystemCall - _start + _START_OFFSET + mtspr IVOR8,r4 /* 8: System call */ /* 9: Auxiliary processor unavailable(unsupported) */ - li r1,0x0a00 - mtspr IVOR10,r1 /* 10: Decrementer */ - li r1,0x0b00 - mtspr IVOR11,r1 /* 11: Interval timer */ - li r1,0x0c00 - mtspr IVOR12,r1 /* 12: Watchdog timer */ - li r1,0x0d00 - mtspr IVOR13,r1 /* 13: Data TLB error */ - li r1,0x0e00 - mtspr IVOR14,r1 /* 14: Instruction TLB error */ - li r1,0x0f00 - mtspr IVOR15,r1 /* 15: Debug */ + addi r4,r3,Decrementer - _start + _START_OFFSET + mtspr IVOR10,r4 /* 10: Decrementer */ + addi r4,r3,IntervalTimer - _start + _START_OFFSET + mtspr IVOR11,r4 /* 11: Interval timer */ + addi r4,r3,WatchdogTimer - _start + _START_OFFSET + mtspr IVOR12,r4 /* 12: Watchdog timer */ + addi r4,r3,DataTLBError - _start + _START_OFFSET + mtspr IVOR13,r4 /* 13: Data TLB error */ + addi r4,r3,InstructionTLBError - _start + _START_OFFSET + mtspr IVOR14,r4 /* 14: Instruction TLB error */ + addi r4,r3,DebugBreakpoint - _start + _START_OFFSET + mtspr IVOR15,r4 /* 15: Debug */ +#endif /* Clear and set up some registers. */ li r0,0x0000 @@ -434,13 +443,15 @@ create_ccsr_new_tlb: ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l +#ifdef CONFIG_ENABLE_36BIT_PHYS lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + mtspr MAS7, r7 +#endif mtspr MAS0, r0 mtspr MAS1, r1 mtspr MAS2, r2 mtspr MAS3, r3 - mtspr MAS7, r7 isync msync tlbwe @@ -456,12 +467,14 @@ create_ccsr_old_tlb: ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l +#ifdef CONFIG_ENABLE_36BIT_PHYS li r7, 0 /* The default CCSR address is always a 32-bit number */ + mtspr MAS7, r7 +#endif mtspr MAS0, r0 /* MAS1 is the same as above */ mtspr MAS2, r2 mtspr MAS3, r3 - mtspr MAS7, r7 isync msync tlbwe @@ -1490,6 +1503,39 @@ trap_init: cmplw 0,r7,r8 blt 2b + /* Update IVORs as per relocated vector table address */ + li r7,0x0100 + mtspr IVOR0,r7 /* 0: Critical input */ + li r7,0x0200 + mtspr IVOR1,r7 /* 1: Machine check */ + li r7,0x0300 + mtspr IVOR2,r7 /* 2: Data storage */ + li r7,0x0400 + mtspr IVOR3,r7 /* 3: Instruction storage */ + li r7,0x0500 + mtspr IVOR4,r7 /* 4: External interrupt */ + li r7,0x0600 + mtspr IVOR5,r7 /* 5: Alignment */ + li r7,0x0700 + mtspr IVOR6,r7 /* 6: Program check */ + li r7,0x0800 + mtspr IVOR7,r7 /* 7: floating point unavailable */ + li r7,0x0900 + mtspr IVOR8,r7 /* 8: System call */ + /* 9: Auxiliary processor unavailable(unsupported) */ + li r7,0x0a00 + mtspr IVOR10,r7 /* 10: Decrementer */ + li r7,0x0b00 + mtspr IVOR11,r7 /* 11: Interval timer */ + li r7,0x0c00 + mtspr IVOR12,r7 /* 12: Watchdog timer */ + li r7,0x0d00 + mtspr IVOR13,r7 /* 13: Data TLB error */ + li r7,0x0e00 + mtspr IVOR14,r7 /* 14: Instruction TLB error */ + li r7,0x0f00 + mtspr IVOR15,r7 /* 15: Debug */ + lis r7,0x0 mtspr IVPR,r7 diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index 04bc73170a..8ba9399169 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -51,13 +51,14 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - KEEP(*(.got)) _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : @@ -87,7 +88,7 @@ SECTIONS .bootpg ADDR(.text) - 0x1000 : { - arch/powerpc/cpu/mpc85xx/start.o KEEP(*(.bootpg)) + KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) } :text = 0xffff . = ADDR(.text) + 0x80000; diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds index 852f9aa4a3..668158f702 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -37,10 +37,12 @@ SECTIONS .reloc : { _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; . = ALIGN(8); diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index f2a2c3a736..b348a98c58 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -139,7 +139,7 @@ typedef volatile struct CommonBufferDescriptor { static RTXBD *rtx = NULL; -static int fec_send(struct eth_device* dev, volatile void *packet, int length); +static int fec_send(struct eth_device *dev, void *packet, int length); static int fec_recv(struct eth_device* dev); static int fec_init(struct eth_device* dev, bd_t * bd); static void fec_halt(struct eth_device* dev); @@ -193,7 +193,7 @@ int fec_initialize(bd_t *bis) return 1; } -static int fec_send(struct eth_device* dev, volatile void *packet, int length) +static int fec_send(struct eth_device *dev, void *packet, int length) { int j, rc; struct ether_fcc_info_s *efis = dev->priv; @@ -267,14 +267,14 @@ static int fec_recv (struct eth_device *dev) rtx->rxbd[rxIdx].cbd_sc); #endif } else { - volatile uchar *rx = NetRxPackets[rxIdx]; + uchar *rx = NetRxPackets[rxIdx]; length -= 4; #if defined(CONFIG_CMD_CDP) if ((rx[0] & 1) != 0 && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0 - && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0) + && !is_cdp_packet((uchar *)rx)) rx = NULL; #endif /* diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index e376c64d52..2c93e24f3c 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -65,7 +65,7 @@ typedef volatile struct CommonBufferDescriptor { static RTXBD *rtx; -static int scc_send(struct eth_device* dev, volatile void *packet, int length); +static int scc_send(struct eth_device *dev, void *packet, int length); static int scc_recv(struct eth_device* dev); static int scc_init (struct eth_device* dev, bd_t * bd); static void scc_halt(struct eth_device* dev); @@ -90,7 +90,7 @@ int scc_initialize(bd_t *bis) return 1; } -static int scc_send(struct eth_device* dev, volatile void *packet, int length) +static int scc_send(struct eth_device *dev, void *packet, int length) { int i, j=0; #if 0 diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index e46d328067..c7f394972b 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -21,6 +21,16 @@ #include <config.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> +#include <asm/fsl_srio.h> + +#define SRIO_PORT_ACCEPT_ALL 0x10000001 +#define SRIO_IB_ATMU_AR 0x80f55000 +#define SRIO_OB_ATMU_AR_MAINT 0x80077000 +#define SRIO_OB_ATMU_AR_RW 0x80045000 +#define SRIO_LCSBA1CSR_OFFSET 0x5c +#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */ +#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */ +#define SRIO_LCSBA1CSR 0x60000000 #if defined(CONFIG_FSL_CORENET) #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 @@ -84,3 +94,203 @@ void srio_init(void) setbits_be32(&gur->devdisr, _DEVDISR_RMU); } } + +#ifdef CONFIG_SRIOBOOT_MASTER +void srio_boot_master(void) +{ + struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + + /* set port accept-all */ + out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr, + SRIO_PORT_ACCEPT_ALL); + + debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", + CONFIG_SRIOBOOT_MASTER_PORT); + /* configure inbound window for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window for slave's image; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + + /* configure inbound window for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window for slave's image; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwbar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + + /* configure inbound window for slave's ucode */ + debug("SRIOBOOT - MASTER: Inbound window for slave's ucode; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS, + (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS, + CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar, + CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar, + CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE)); + + /* configure inbound window for slave's ENV */ + debug("SRIOBOOT - MASTER: Inbound window for slave's ENV; " + "Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n", + CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS, + CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS, + CONFIG_SRIOBOOT_SLAVE_ENV_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar, + CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar, + CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE)); +} + +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF +void srio_boot_master_release_slave(void) +{ + struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + u32 escsr; + debug("SRIOBOOT - MASTER: " + "Check the port status and release slave core ...\n"); + + escsr = in_be32((void *)&srio->lp_serial + .port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr); + if (escsr & 0x2) { + if (escsr & 0x10100) { + debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n", + CONFIG_SRIOBOOT_MASTER_PORT); + } else { + debug("SRIOBOOT - MASTER: " + "Port [ %d ] is ready, now release slave's core ...\n", + CONFIG_SRIOBOOT_MASTER_PORT); + /* + * configure outbound window + * with maintenance attribute to set slave's LCSBA1CSR + */ + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowtar, 0); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowtear, 0); + if (CONFIG_SRIOBOOT_MASTER_PORT) + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowbar, + CONFIG_SYS_SRIO2_MEM_PHYS >> 12); + else + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowbar, + CONFIG_SYS_SRIO1_MEM_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowar, + SRIO_OB_ATMU_AR_MAINT + | atmu_size_mask(SRIO_MAINT_WIN_SIZE)); + + /* + * configure outbound window + * with R/W attribute to set slave's BRR + */ + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowtar, + SRIO_LCSBA1CSR >> 9); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowtear, 0); + if (CONFIG_SRIOBOOT_MASTER_PORT) + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowbar, + (CONFIG_SYS_SRIO2_MEM_PHYS + + SRIO_MAINT_WIN_SIZE) >> 12); + else + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowbar, + (CONFIG_SYS_SRIO1_MEM_PHYS + + SRIO_MAINT_WIN_SIZE) >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowar, + SRIO_OB_ATMU_AR_RW + | atmu_size_mask(SRIO_RW_WIN_SIZE)); + + /* + * Set the LCSBA1CSR register in slave + * by the maint-outbound window + */ + if (CONFIG_SRIOBOOT_MASTER_PORT) { + out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET, + SRIO_LCSBA1CSR); + while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET) + != SRIO_LCSBA1CSR) + ; + /* + * And then set the BRR register + * to release slave core + */ + out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + + SRIO_MAINT_WIN_SIZE + + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, + CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + } else { + out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET, + SRIO_LCSBA1CSR); + while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET) + != SRIO_LCSBA1CSR) + ; + /* + * And then set the BRR register + * to release slave core + */ + out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + + SRIO_MAINT_WIN_SIZE + + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, + CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + } + debug("SRIOBOOT - MASTER: " + "Release slave successfully! Now the slave should start up!\n"); + } + } else + debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", + CONFIG_SRIOBOOT_MASTER_PORT); +} +#endif +#endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8654625fac..191629b628 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -65,6 +65,11 @@ #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_RMU +#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1 @@ -85,6 +90,11 @@ #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_RMU +#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_MPC8569) #define CONFIG_MAX_CPUS 1 @@ -94,6 +104,11 @@ #define MAX_QE_RISC 4 #define QE_NUM_OF_SNUM 46 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_RMU +#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_MPC8572) #define CONFIG_MAX_CPUS 2 @@ -298,6 +313,11 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_RMU +#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_PPC_P2040) #define CONFIG_MAX_CPUS 4 @@ -317,6 +337,9 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #elif defined(CONFIG_PPC_P2041) #define CONFIG_MAX_CPUS 4 @@ -338,6 +361,9 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -359,6 +385,9 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #elif defined(CONFIG_PPC_P3060) #define CONFIG_MAX_CPUS 8 @@ -375,6 +404,9 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 @@ -387,6 +419,9 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -417,6 +452,11 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_RMU +#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) @@ -438,6 +478,9 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -458,6 +501,9 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #else #error Processor type not defined for this platform diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h new file mode 100644 index 0000000000..a905a266c4 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_srio.h @@ -0,0 +1,64 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FSL_SRIO_H_ +#define _FSL_SRIO_H_ + +enum atmu_size { + ATMU_SIZE_4K = 0xb, + ATMU_SIZE_8K, + ATMU_SIZE_16K, + ATMU_SIZE_32K, + ATMU_SIZE_64K, + ATMU_SIZE_128K, + ATMU_SIZE_256K, + ATMU_SIZE_512K, + ATMU_SIZE_1M, + ATMU_SIZE_2M, + ATMU_SIZE_4M, + ATMU_SIZE_8M, + ATMU_SIZE_16M, + ATMU_SIZE_32M, + ATMU_SIZE_64M, + ATMU_SIZE_128M, + ATMU_SIZE_256M, + ATMU_SIZE_512M, + ATMU_SIZE_1G, + ATMU_SIZE_2G, + ATMU_SIZE_4G, + ATMU_SIZE_8G, + ATMU_SIZE_16G, + ATMU_SIZE_32G, + ATMU_SIZE_64G, +}; + +#define atmu_size_mask(sz) (__ilog2_u64(sz) - 1) +#define atmu_size_bytes(x) (1ULL << ((x & 0x3f) + 1)) + +extern void srio_init(void); +#ifdef CONFIG_SRIOBOOT_MASTER +extern void srio_boot_master(void); +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF +extern void srio_boot_master_release_slave(void); +#endif +#endif +#endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9b08cb8c1a..632e3c1669 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1353,171 +1353,235 @@ typedef struct ccsr_cpm { } ccsr_cpm_t; #endif -/* RapidIO Registers */ -typedef struct ccsr_rio { - u32 didcar; /* Device Identity Capability */ - u32 dicar; /* Device Information Capability */ - u32 aidcar; /* Assembly Identity Capability */ - u32 aicar; /* Assembly Information Capability */ - u32 pefcar; /* Processing Element Features Capability */ - u32 spicar; /* Switch Port Information Capability */ - u32 socar; /* Source Operations Capability */ - u32 docar; /* Destination Operations Capability */ +#ifdef CONFIG_SYS_SRIO +/* Architectural regsiters */ +struct rio_arch { + u32 didcar; /* Device Identity CAR */ + u32 dicar; /* Device Information CAR */ + u32 aidcar; /* Assembly Identity CAR */ + u32 aicar; /* Assembly Information CAR */ + u32 pefcar; /* Processing Element Features CAR */ + u8 res0[4]; + u32 socar; /* Source Operations CAR */ + u32 docar; /* Destination Operations CAR */ u8 res1[32]; - u32 msr; /* Mailbox Cmd And Status */ - u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */ + u32 mcsr; /* Mailbox CSR */ + u32 pwdcsr; /* Port-Write and Doorbell CSR */ u8 res2[4]; u32 pellccsr; /* Processing Element Logic Layer CCSR */ u8 res3[12]; - u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */ - u32 bdidcsr; /* Base Device ID Cmd & Status */ + u32 lcsbacsr; /* Local Configuration Space BACSR */ + u32 bdidcsr; /* Base Device ID CSR */ u8 res4[4]; - u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */ - u32 ctcsr; /* Component Tag Cmd & Status */ - u8 res5[144]; - u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */ - u8 res6[28]; - u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */ - u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */ - u8 res7[20]; - u32 pgccsr; /* Port General Cmd & Status */ - u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */ - u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */ - u32 plascsr; /* Port Local Ackid Status Cmd & Status */ - u8 res8[12]; - u32 pescsr; /* Port Error & Status Cmd & Status */ - u32 pccsr; /* Port Control Cmd & Status */ - u8 res9[65184]; - u32 cr; /* Port Control Cmd & Status */ - u8 res10[12]; - u32 pcr; /* Port Configuration */ - u32 peir; /* Port Error Injection */ - u8 res11[3048]; - u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */ - u8 res12[12]; - u32 rowar0; /* RIO Outbound Attrs 0 */ - u8 res13[12]; - u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */ - u8 res14[4]; - u32 rowbar1; /* RIO Outbound Window Base Addr 1 */ - u8 res15[4]; - u32 rowar1; /* RIO Outbound Attrs 1 */ - u8 res16[12]; - u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */ - u8 res17[4]; - u32 rowbar2; /* RIO Outbound Window Base Addr 2 */ - u8 res18[4]; - u32 rowar2; /* RIO Outbound Attrs 2 */ - u8 res19[12]; - u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */ - u8 res20[4]; - u32 rowbar3; /* RIO Outbound Window Base Addr 3 */ - u8 res21[4]; - u32 rowar3; /* RIO Outbound Attrs 3 */ - u8 res22[12]; - u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */ - u8 res23[4]; - u32 rowbar4; /* RIO Outbound Window Base Addr 4 */ - u8 res24[4]; - u32 rowar4; /* RIO Outbound Attrs 4 */ - u8 res25[12]; - u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */ - u8 res26[4]; - u32 rowbar5; /* RIO Outbound Window Base Addr 5 */ - u8 res27[4]; - u32 rowar5; /* RIO Outbound Attrs 5 */ - u8 res28[12]; - u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */ - u8 res29[4]; - u32 rowbar6; /* RIO Outbound Window Base Addr 6 */ - u8 res30[4]; - u32 rowar6; /* RIO Outbound Attrs 6 */ - u8 res31[12]; - u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */ - u8 res32[4]; - u32 rowbar7; /* RIO Outbound Window Base Addr 7 */ - u8 res33[4]; - u32 rowar7; /* RIO Outbound Attrs 7 */ - u8 res34[12]; - u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */ - u8 res35[4]; - u32 rowbar8; /* RIO Outbound Window Base Addr 8 */ - u8 res36[4]; - u32 rowar8; /* RIO Outbound Attrs 8 */ - u8 res37[76]; - u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */ - u8 res38[4]; - u32 riwbar4; /* RIO Inbound Window Base Addr 4 */ - u8 res39[4]; - u32 riwar4; /* RIO Inbound Attrs 4 */ - u8 res40[12]; - u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */ - u8 res41[4]; - u32 riwbar3; /* RIO Inbound Window Base Addr 3 */ - u8 res42[4]; - u32 riwar3; /* RIO Inbound Attrs 3 */ - u8 res43[12]; - u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */ - u8 res44[4]; - u32 riwbar2; /* RIO Inbound Window Base Addr 2 */ - u8 res45[4]; - u32 riwar2; /* RIO Inbound Attrs 2 */ - u8 res46[12]; - u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */ - u8 res47[4]; - u32 riwbar1; /* RIO Inbound Window Base Addr 1 */ - u8 res48[4]; - u32 riwar1; /* RIO Inbound Attrs 1 */ - u8 res49[12]; - u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */ - u8 res50[12]; - u32 riwar0; /* RIO Inbound Attrs 0 */ - u8 res51[12]; - u32 pnfedr; /* Port Notification/Fatal Error Detect */ - u32 pnfedir; /* Port Notification/Fatal Error Detect */ - u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */ - u32 pecr; /* Port Error Control */ - u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */ - u32 pepr1; /* Port Error Packet 1 */ - u32 pepr2; /* Port Error Packet 2 */ - u8 res52[4]; - u32 predr; /* Port Recoverable Error Detect */ - u8 res53[4]; - u32 pertr; /* Port Error Recovery Threshold */ - u32 prtr; /* Port Retry Threshold */ - u8 res54[464]; - u32 omr; /* Outbound Mode */ - u32 osr; /* Outbound Status */ - u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */ - u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */ - u32 eosar; /* Extended Outbound Unit Source Addr */ - u32 osar; /* Outbound Unit Source Addr */ - u32 odpr; /* Outbound Destination Port */ - u32 odatr; /* Outbound Destination Attrs */ - u32 odcr; /* Outbound Doubleword Count */ - u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */ - u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */ - u8 res55[52]; - u32 imr; /* Outbound Mode */ - u32 isr; /* Inbound Status */ - u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */ - u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */ - u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */ - u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */ - u8 res56[1000]; - u32 dmr; /* Doorbell Mode */ - u32 dsr; /* Doorbell Status */ - u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */ - u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */ - u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */ - u32 dqhpar; /* Doorbell Queue Head Ptr Addr */ - u8 res57[104]; - u32 pwmr; /* Port-Write Mode */ - u32 pwsr; /* Port-Write Status */ - u32 epwqbar; /* Extended Port-Write Queue Base Addr */ - u32 pwqbar; /* Port-Write Queue Base Addr */ - u8 res58[60176]; -} ccsr_rio_t; + u32 hbdidlcsr; /* Host Base Device ID Lock CSR */ + u32 ctcsr; /* Component Tag CSR */ +}; + +/* Extended Features Space: 1x/4x LP-Serial Port registers */ +struct rio_lp_serial_port { + u32 plmreqcsr; /* Port Link Maintenance Request CSR */ + u32 plmrespcsr; /* Port Link Maintenance Response CS */ + u32 plascsr; /* Port Local Ackid Status CSR */ + u8 res0[12]; + u32 pescsr; /* Port Error and Status CSR */ + u32 pccsr; /* Port Control CSR */ +}; + +/* Extended Features Space: 1x/4x LP-Serial registers */ +struct rio_lp_serial { + u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */ + u8 res0[28]; + u32 pltoccsr; /* Port Link Time-out CCSR */ + u32 prtoccsr; /* Port Response Time-out CCSR */ + u8 res1[20]; + u32 pgccsr; /* Port General CSR */ + struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; +}; + +/* Logical error reporting registers */ +struct rio_logical_err { + u32 erbh; /* Error Reporting Block Header Register */ + u8 res0[4]; + u32 ltledcsr; /* Logical/Transport layer error DCSR */ + u32 ltleecsr; /* Logical/Transport layer error ECSR */ + u8 res1[4]; + u32 ltlaccsr; /* Logical/Transport layer ACCSR */ + u32 ltldidccsr; /* Logical/Transport layer DID CCSR */ + u32 ltlcccsr; /* Logical/Transport layer control CCSR */ +}; + +/* Physical error reporting port registers */ +struct rio_phys_err_port { + u32 edcsr; /* Port error detect CSR */ + u32 erecsr; /* Port error rate enable CSR */ + u32 ecacsr; /* Port error capture attributes CSR */ + u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */ + u32 peccsr[3]; /* Port error capture CSR */ + u8 res0[12]; + u32 ercsr; /* Port error rate CSR */ + u32 ertcsr; /* Port error rate threshold CSR */ + u8 res1[16]; +}; + +/* Physical error reporting registers */ +struct rio_phys_err { + struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; +}; + +/* Implementation Space: General Port-Common */ +struct rio_impl_common { + u8 res0[4]; + u32 llcr; /* Logical Layer Configuration Register */ + u8 res1[8]; + u32 epwisr; /* Error / Port-Write Interrupt SR */ + u8 res2[12]; + u32 lretcr; /* Logical Retry Error Threshold CR */ + u8 res3[92]; + u32 pretcr; /* Physical Retry Erorr Threshold CR */ + u8 res4[124]; +}; + +/* Implementation Space: Port Specific */ +struct rio_impl_port_spec { + u32 adidcsr; /* Port Alt. Device ID CSR */ + u8 res0[28]; + u32 ptaacr; /* Port Pass-Through/Accept-All CR */ + u32 lopttlcr; + u8 res1[8]; + u32 iecsr; /* Port Implementation Error CSR */ + u8 res2[12]; + u32 pcr; /* Port Phsyical Configuration Register */ + u8 res3[20]; + u32 slcsr; /* Port Serial Link CSR */ + u8 res4[4]; + u32 sleicr; /* Port Serial Link Error Injection */ + u32 a0txcr; /* Port Arbitration 0 Tx CR */ + u32 a1txcr; /* Port Arbitration 1 Tx CR */ + u32 a2txcr; /* Port Arbitration 2 Tx CR */ + u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */ + u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */ +}; + +/* Implementation Space: register */ +struct rio_implement { + struct rio_impl_common com; + struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; +}; + +/* Revision Control Register */ +struct rio_rev_ctrl { + u32 ipbrr[2]; /* IP Block Revision Register */ +}; + +struct rio_atmu_row { + u32 rowtar; /* RapidIO Outbound Window TAR */ + u32 rowtear; /* RapidIO Outbound Window TEAR */ + u32 rowbar; + u8 res0[4]; + u32 rowar; /* RapidIO Outbound Attributes Register */ + u32 rowsr[3]; /* Port RapidIO outbound window segment register */ +}; + +struct rio_atmu_riw { + u32 riwtar; /* RapidIO Inbound Window Translation AR */ + u8 res0[4]; + u32 riwbar; /* RapidIO Inbound Window Base AR */ + u8 res1[4]; + u32 riwar; /* RapidIO Inbound Attributes Register */ + u8 res2[12]; +}; + +/* ATMU window registers */ +struct rio_atmu_win { + struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM]; + u8 res0[64]; + struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM]; +}; + +struct rio_atmu { + struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; +}; + +#ifdef CONFIG_SYS_FSL_RMU +struct rio_msg { + u32 omr; /* Outbound Mode Register */ + u32 osr; /* Outbound Status Register */ + u32 eodqdpar; /* Extended Outbound DQ DPAR */ + u32 odqdpar; /* Outbound Descriptor Queue DPAR */ + u32 eosar; /* Extended Outbound Unit Source AR */ + u32 osar; /* Outbound Unit Source AR */ + u32 odpr; /* Outbound Destination Port Register */ + u32 odatr; /* Outbound Destination Attributes Register */ + u32 odcr; /* Outbound Doubleword Count Register */ + u32 eodqepar; /* Extended Outbound DQ EPAR */ + u32 odqepar; /* Outbound Descriptor Queue EPAR */ + u32 oretr; /* Outbound Retry Error Threshold Register */ + u32 omgr; /* Outbound Multicast Group Register */ + u32 omlr; /* Outbound Multicast List Register */ + u8 res0[40]; + u32 imr; /* Outbound Mode Register */ + u32 isr; /* Inbound Status Register */ + u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */ + u32 idqdpar; /* Inbound Descriptor Queue DPAR */ + u32 eifqepar; /* Extended Inbound Frame Queue EPAR */ + u32 ifqepar; /* Inbound Frame Queue EPAR */ + u32 imirir; /* Inbound Maximum Interrutp RIR */ + u8 res1[4]; + u32 eihqepar; /* Extended inbound message header queue EPAR */ + u32 ihqepar; /* Inbound message header queue EPAR */ + u8 res2[120]; +}; + +struct rio_dbell { + u32 odmr; /* Outbound Doorbell Mode Register */ + u32 odsr; /* Outbound Doorbell Status Register */ + u8 res0[16]; + u32 oddpr; /* Outbound Doorbell Destination Port */ + u32 oddatr; /* Outbound Doorbell Destination AR */ + u8 res1[12]; + u32 oddretr; /* Outbound Doorbell Retry Threshold CR */ + u8 res2[48]; + u32 idmr; /* Inbound Doorbell Mode Register */ + u32 idsr; /* Inbound Doorbell Status Register */ + u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */ + u32 iqdpar; /* Inbound Doorbell Queue DPAR */ + u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */ + u32 idqepar; /* Inbound Doorbell Queue EPAR */ + u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */ +}; + +struct rio_pw { + u32 pwmr; /* Port-Write Mode Register */ + u32 pwsr; /* Port-Write Status Register */ + u32 epwqbar; /* Extended Port-Write Queue BAR */ + u32 pwqbar; /* Port-Write Queue Base Address Register */ +}; +#endif + +/* RapidIO Registers */ +struct ccsr_rio { + struct rio_arch arch; + u8 res0[144]; + struct rio_lp_serial lp_serial; + u8 res1[1152]; + struct rio_logical_err logical_err; + u8 res2[32]; + struct rio_phys_err phys_err; + u8 res3[63808]; + struct rio_implement impl; + u8 res4[2552]; + struct rio_rev_ctrl rev; + struct rio_atmu atmu; +#ifdef CONFIG_SYS_FSL_RMU + u8 res5[8192]; + struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM]; + u8 res6[512]; + struct rio_dbell dbell; + u8 res7[100]; + struct rio_pw pw; +#endif +}; +#endif /* Quick Engine Block Pin Muxing Registers */ typedef struct par_io { @@ -2443,6 +2507,7 @@ struct ccsr_rman { #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 +#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) @@ -2516,6 +2581,8 @@ struct ccsr_rman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) #define CONFIG_SYS_FSL_FM2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) +#define CONFIG_SYS_FSL_SRIO_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET) #define CONFIG_SYS_PCI1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index b2fa2b574b..1552054117 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -63,7 +63,6 @@ typedef struct bd_info { unsigned long bi_vcofreq; /* VCO Freq, in MHz */ #endif unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ - unsigned long bi_ip_addr; /* IP Address */ unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index d5b75e5fbd..fea310eedd 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -877,9 +877,6 @@ void board_init_r(gd_t *id, ulong dest_addr) #endif #endif /* CONFIG_CMD_NET */ - /* IP Address */ - bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - WATCHDOG_RESET(); #if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) @@ -935,14 +932,6 @@ void board_init_r(gd_t *id, ulong dest_addr) /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); -#if defined(CONFIG_CMD_NET) - { - char *s = getenv("bootfile"); - - if (s != NULL) - copy_filename(BootFile, s, sizeof(BootFile)); - } -#endif WATCHDOG_RESET(); diff --git a/arch/sandbox/include/asm/u-boot.h b/arch/sandbox/include/asm/u-boot.h index 166ef14341..de8120a723 100644 --- a/arch/sandbox/include/asm/u-boot.h +++ b/arch/sandbox/include/asm/u-boot.h @@ -45,7 +45,6 @@ typedef struct bd_info { unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_ip_addr; /* IP Address */ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ diff --git a/arch/sandbox/lib/board.c b/arch/sandbox/lib/board.c index 306d1ec332..c173bf96f0 100644 --- a/arch/sandbox/lib/board.c +++ b/arch/sandbox/lib/board.c @@ -235,9 +235,6 @@ void board_init_r(gd_t *id, ulong dest_addr) /* initialize environment */ env_relocate(); - /* IP Address */ - gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - stdio_init(); /* get the devices list going. */ jumptable_init(); diff --git a/arch/sh/include/asm/u-boot.h b/arch/sh/include/asm/u-boot.h index 45745129a0..6c04daf3bc 100644 --- a/arch/sh/include/asm/u-boot.h +++ b/arch/sh/include/asm/u-boot.h @@ -33,7 +33,6 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_ip_addr; /* IP Address */ unsigned long bi_baudrate; /* Console Baudrate */ unsigned long bi_boot_params; /* where this board expects params */ } bd_t; diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index eb021e806c..34d7881f44 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -100,14 +100,6 @@ static int sh_mem_env_init(void) return 0; } -#if defined(CONFIG_CMD_NET) -static int sh_net_init(void) -{ - gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - return 0; -} -#endif - #if defined(CONFIG_CMD_MMC) static int sh_mmc_init(void) { @@ -145,9 +137,6 @@ init_fnc_t *init_sequence[] = #ifdef CONFIG_BOARD_LATE_INIT board_late_init, #endif -#if defined(CONFIG_CMD_NET) - sh_net_init, /* SH specific eth init */ -#endif #if defined(CONFIG_CMD_MMC) sh_mmc_init, #endif @@ -201,15 +190,8 @@ void sh_generic_init(void) bb_miiphy_init(); #endif #if defined(CONFIG_CMD_NET) - { - char *s; - puts("Net: "); - eth_initialize(gd->bd); - - s = getenv("bootfile"); - if (s != NULL) - copy_filename(BootFile, s, sizeof(BootFile)); - } + puts("Net: "); + eth_initialize(gd->bd); #endif /* CONFIG_CMD_NET */ while (1) { diff --git a/arch/sparc/include/asm/u-boot.h b/arch/sparc/include/asm/u-boot.h index 1d94087aab..8d011185a0 100644 --- a/arch/sparc/include/asm/u-boot.h +++ b/arch/sparc/include/asm/u-boot.h @@ -51,7 +51,6 @@ typedef struct bd_info { unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_ip_addr; /* IP Address */ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index c0d260840c..7e48775dfe 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -333,8 +333,6 @@ void board_init_f(ulong bootflag) mac_read_from_eeprom(); #endif - /* IP Address */ - bd->bi_ip_addr = getenv_IPaddr("ipaddr"); #if defined(CONFIG_PCI) /* * Do pci configuration @@ -359,11 +357,6 @@ void board_init_f(ulong bootflag) /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); -#if defined(CONFIG_CMD_NET) - if ((s = getenv("bootfile")) != NULL) { - copy_filename(BootFile, s, sizeof(BootFile)); - } -#endif /* CONFIG_CMD_NET */ WATCHDOG_RESET(); diff --git a/arch/x86/include/asm/init_helpers.h b/arch/x86/include/asm/init_helpers.h index 192f18e1d5..8afb443290 100644 --- a/arch/x86/include/asm/init_helpers.h +++ b/arch/x86/include/asm/init_helpers.h @@ -36,9 +36,7 @@ int set_reloc_flag_r(void); int mem_malloc_init_r(void); int init_bd_struct_r(void); int flash_init_r(void); -int init_ip_address_r(void); int status_led_set_r(void); -int set_bootfile_r(void); int set_load_addr_r(void); #endif /* !_INIT_HELPERS_H_ */ diff --git a/arch/x86/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h index 26450ebc44..da667c50a4 100644 --- a/arch/x86/include/asm/u-boot.h +++ b/arch/x86/include/asm/u-boot.h @@ -45,7 +45,6 @@ typedef struct bd_info { unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_ip_addr; /* IP Address */ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index 5f0b62cea6..90cf7fc888 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -157,9 +157,6 @@ init_fnc_t *init_sequence_r[] = { flash_init_r, #endif env_relocate_r, -#ifdef CONFIG_CMD_NET - init_ip_address_r, -#endif #ifdef CONFIG_PCI pci_init_r, #endif @@ -180,9 +177,6 @@ init_fnc_t *init_sequence_r[] = { status_led_set_r, #endif set_load_addr_r, -#if defined(CONFIG_CMD_NET) - set_bootfile_r, -#endif #if defined(CONFIG_CMD_IDE) ide_init_r, #endif diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 9f4dee034f..9ec34ff992 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -179,14 +179,6 @@ int flash_init_r(void) } #endif -int init_ip_address_r(void) -{ - /* IP Address */ - bd_data.bi_ip_addr = getenv_IPaddr("ipaddr"); - - return 0; -} - #ifdef CONFIG_STATUS_LED int status_led_set_r(void) { @@ -196,18 +188,6 @@ int status_led_set_r(void) } #endif -int set_bootfile_r(void) -{ - char *s; - - s = getenv("bootfile"); - - if (s != NULL) - copy_filename(BootFile, s, sizeof(BootFile)); - - return 0; -} - int set_load_addr_r(void) { /* Initialize from environment */ |