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path: root/drivers/gpu/drm/bridge/sil-sii8620.c
AgeCommit message (Expand)Author
2019-01-10drm/edid: Pass connector to AVI infoframe functionsVille Syrjälä
2018-07-04drm/bridge/sii8620: Fix link mode selectionMaciej Purski
2018-07-04drm/bridge/sii8620: Fix display of packed pixel modesMaciej Purski
2018-07-04drm/bridge/sii8620: Send AVI infoframe in all MHL versionsMaciej Purski
2018-06-21drm/bridge/sii8620: fix display of packed pixel modes in MHL2Maciej Purski
2018-06-13drm/bridge/sii8620: fix HDMI cable connection to dongleMaciej Purski
2018-06-13drm/bridge/sii8620: remove HSIC initializationMaciej Purski
2018-06-13drm/bridge/sii8620: start MHL transmission after HDMI signal detectionMaciej Purski
2018-06-13drm/bridge/sii8620: fix potential buffer overflowMaciej Purski
2018-06-13drm/bridge/sii8620: fix display modes validationMaciej Purski
2018-06-13drm/bridge/sii8620: fix loops in EDID fetch logicAndrzej Hajda
2018-06-13drm/bridge/sii8620: simplify hardware reset procedureAndrzej Hajda
2018-03-12drm/bridge/sii8620: use micro-USB cable detection logic to detect MHLMaciej Purski
2017-11-22drm/edid: Allow HDMI infoframe without VIC or S3DVille Syrjälä
2017-11-16drm/bridge/sii8620: add DVI mode supportMaciej Purski
2017-11-16drm/bridge/sii8620: filter unsupported modesMarek Szyprowski
2017-10-11drm/bridge/sii8620: add remote control supportMaciej Purski
2017-08-24drm/bridge/sii8620: Fix memory corruptionMaciej Purski
2017-02-23drm/bridge/sii8620: add missing error handling in probeAndrzej Hajda
2017-02-02drm/bridge/sii8620: enable interlace modesAndrzej Hajda
2017-02-02drm/bridge/sii8620: enable MHL3 mode if possibleAndrzej Hajda
2017-02-02drm/bridge/sii8620: add HSIC initialization codeAndrzej Hajda
2017-02-02drm/bridge/sii8620: improve gen2 write burst IRQ routineAndrzej Hajda
2017-02-02drm/bridge/sii8620: send EMSC features on requestAndrzej Hajda
2017-02-02drm/bridge/sii8620: rewrite hdmi start sequenceAndrzej Hajda
2017-02-02drm/bridge/sii8620: fix disconnect sequenceAndrzej Hajda
2017-02-02drm/bridge/sii8620: split EDID read and write codeAndrzej Hajda
2017-02-02drm/bridge/sii8620: add delay during cbus resetAndrzej Hajda
2017-02-02drm/bridge/sii8620: do not stop MHL output when TMDS input is stoppedAndrzej Hajda
2017-02-02drm/bridge/sii8620: set gen2 write burst before sending MSC commandAndrzej Hajda
2017-02-02drm/bridge/sii8620: abstract out sink detection codeAndrzej Hajda
2017-02-02drm/bridge/sii8620: fix initialization sequence for MHL2 receiversAndrzej Hajda
2017-02-02drm/bridge/sii8620: fix MSC message removalAndrzej Hajda
2017-02-02drm/bridge/sii8620: remove spare CBUS bring-up sequenceAndrzej Hajda
2017-02-02drm/bridge/sii8620: fix peer device capabilities read codeAndrzej Hajda
2017-02-02drm/bridge/sii8620: respond to feature requestsAndrzej Hajda
2017-02-02drm/bridge/sii8620: add support for burst eMSC transmissionsAndrzej Hajda
2017-02-02drm/bridge/sii8620: initial support for eCBUS-S modeAndrzej Hajda
2017-02-02drm/bridge/sii8620: add continuations to messagesAndrzej Hajda
2017-02-02drm/bridge/sii8620: add reading device capability registersAndrzej Hajda
2017-02-02drm/bridge/sii8620: add MHL3 mode check helperAndrzej Hajda
2017-02-02drm/bridge/sii8620: simplify MHL3 mode settingAndrzej Hajda
2016-10-27drm/bridge: fix platform_no_drv_owner.cocci warningskbuild test robot
2016-10-27drm/bridge: fix semicolon.cocci warningskbuild test robot
2016-10-26drm/bridge: add Silicon Image SiI8620 driverAndrzej Hajda
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