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path: root/drivers/clk/tegra/clk-tegra-periph.c
AgeCommit message (Expand)Author
2021-08-11clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clockDmitry Osipenko
2021-05-31clk: tegra: Mark external clocks as not having reset controlDmitry Osipenko
2020-12-10clk: tegra: Fix duplicated SE clock entryDmitry Osipenko
2020-01-08clk: tegra: Mark fuse clock as criticalStephen Warren
2019-11-11clk: tegra: Move SOR0 implementation to Tegra124Thierry Reding
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner
2018-12-14clk: tegra: get rid of duplicate definesMarcel Ziswiler
2018-07-25clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko
2017-11-01clk: tegra: Correct parent of the APBDMA clockDmitry Osipenko
2017-11-01clk: tegra: Add AHB DMA clock entryDmitry Osipenko
2017-10-19clk: tegra: Fix sor1_out clock implementationThierry Reding
2017-10-19clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding
2017-08-23clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2CAlex Frid
2017-04-04clk: tegra: Add missing Tegra210 clocksPeter De Schrijver
2017-03-20clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver
2017-03-20clk: tegra: Correct afi clock parentPeter De Schrijver
2017-03-20clk: tegra: Fix ISP clock modellingPeter De Schrijver
2016-06-22clk: tegra: Mark timer clock as criticalThierry Reding
2016-06-17clk: tegra: Squash sor1 safe/brick/src into a single muxThierry Reding
2016-04-28clk: tegra: dpaux and dpaux1 are fixed factor clocksThierry Reding
2016-04-28clk: tegra: Add dpaux1 clockThierry Reding
2016-04-28clk: tegra: Use correct parent for dpaux clockThierry Reding
2016-04-28clk: tegra: Special-case mipi-cal parent on Tegra114Thierry Reding
2016-04-28clk: tegra: Constify peripheral clock registersThierry Reding
2016-02-02clk: tegra: Add the APB2APE audio clock on Tegra210Jon Hunter
2016-02-02clk: tegra: Fix the misnaming of nvenc from msencRhyland Klein
2016-01-25clk: tegra: Fix divider on VI_I2CRhyland Klein
2015-11-20clk: tegra: periph: Add new periph clks and muxes for Tegra210Rhyland Klein
2015-07-20clk: tegra: Properly include clk.hStephen Boyd
2015-04-10clk: tegra: Fix a bunch of sparse warningsThierry Reding
2015-02-02clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang
2015-02-02clk: tegra: SDMMC controllers are on APBAndrew Bresticker
2014-06-25clk: tegra: fix vi_sensor clocks on Tegra124Peter De Schrijver
2014-05-22clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker
2014-05-22clk: tegra: Fix xusb_fs_src muxJim Lin
2014-02-20clk: tegra: Fix vic03 mux indexPeter De Schrijver
2014-02-17clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker
2014-02-17clk: tegra: Correct clock number for UARTEThierry Reding
2013-11-26clk: tegra124: Add new peripheral clocksPeter De Schrijver
2013-11-26clk: tegra: add TEGRA_PERIPH_NO_GATEPeter De Schrijver
2013-11-26clk: tegra: add locking to periph clksPeter De Schrijver
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver