| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-08-20 | RISC-V: Add mechanism to provide custom IPI operations | Anup Patel |
| 2020-08-04 | RISC-V: Fix build warning for smpboot.c | Atish Patra |
| 2020-06-09 | RISC-V: self-contained IPI handling routine | Anup Patel |
| 2020-03-31 | RISC-V: Support cpu hotplug | Atish Patra |
| 2020-03-31 | RISC-V: Implement new SBI v0.2 extensions | Atish Patra |
| 2019-09-05 | riscv: cleanup riscv_cpuid_to_hartid_mask | Christoph Hellwig |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner |
| 2019-03-04 | RISC-V: Move cpuid to hartid mapping to SMP. | Atish Patra |
| 2018-10-22 | RISC-V: Show IPI stats | Anup Patel |
| 2018-10-22 | RISC-V: Add logical CPU indexing for RISC-V | Atish Patra |
| 2018-10-22 | RISC-V: Provide a cleaner raw_smp_processor_id() | Palmer Dabbelt |
| 2018-08-13 | clocksource: new RISC-V SBI timer driver | Palmer Dabbelt |
| 2018-08-13 | RISC-V: simplify software interrupt / IPI code | Christoph Hellwig |
| 2017-09-26 | RISC-V: Init and Halt Code | Palmer Dabbelt |
 |
index : daniel.thompson/linux.git | |
| Personal repo for development and upstreaming. Contains significant work on NMI/FIQ. |
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