| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-01-14 | riscv: Add uprobes supported | Guo Ren |
| 2020-06-10 | riscv: use vDSO common flow to reduce the latency of the time-related functions | Vincent Chen |
| 2020-06-09 | RISC-V: Rename and move plic_find_hart_id() to arch directory | Anup Patel |
| 2019-11-05 | riscv: abstract out CSR names for supervisor vs machine mode | Christoph Hellwig |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner |
| 2019-01-25 | riscv: Adjust mmap base address at a third of task size | Alexandre Ghiti |
| 2018-10-31 | treewide: remove current_text_addr | Nick Desaulniers |
| 2018-10-22 | RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid | Palmer Dabbelt |
| 2017-09-26 | RISC-V: Task implementation | Palmer Dabbelt |
 |
index : daniel.thompson/linux.git | |
| Personal repo for development and upstreaming. Contains significant work on NMI/FIQ. |
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