diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm')
605 files changed, 14585 insertions, 12370 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/Kbuild index b53de9ba8c73..db3ade125fa9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/Kbuild @@ -1,5 +1,6 @@ # SPDX-License-Identifier: MIT include $(src)/nvkm/core/Kbuild +include $(src)/nvkm/nvfw/Kbuild include $(src)/nvkm/falcon/Kbuild include $(src)/nvkm/subdev/Kbuild include $(src)/nvkm/engine/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/core/client.c b/drivers/gpu/drm/nouveau/nvkm/core/client.c index ac671202919e..0c8c55c73b12 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/client.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/client.c @@ -60,7 +60,7 @@ nvkm_uclient_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, return 0; } -const struct nvkm_sclass +static const struct nvkm_sclass nvkm_uclient_sclass = { .oclass = NVIF_CLASS_CLIENT, .minver = 0, diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engine.c b/drivers/gpu/drm/nouveau/nvkm/core/engine.c index 1a47c40e171b..e41a39ae1597 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/engine.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/engine.c @@ -40,10 +40,11 @@ nvkm_engine_unref(struct nvkm_engine **pengine) { struct nvkm_engine *engine = *pengine; if (engine) { - mutex_lock(&engine->subdev.mutex); - if (--engine->usecount == 0) + if (refcount_dec_and_mutex_lock(&engine->use.refcount, &engine->use.mutex)) { nvkm_subdev_fini(&engine->subdev, false); - mutex_unlock(&engine->subdev.mutex); + engine->use.enabled = false; + mutex_unlock(&engine->use.mutex); + } *pengine = NULL; } } @@ -51,17 +52,21 @@ nvkm_engine_unref(struct nvkm_engine **pengine) struct nvkm_engine * nvkm_engine_ref(struct nvkm_engine *engine) { + int ret; if (engine) { - mutex_lock(&engine->subdev.mutex); - if (++engine->usecount == 1) { - int ret = nvkm_subdev_init(&engine->subdev); - if (ret) { - engine->usecount--; - mutex_unlock(&engine->subdev.mutex); - return ERR_PTR(ret); + if (!refcount_inc_not_zero(&engine->use.refcount)) { + mutex_lock(&engine->use.mutex); + if (!refcount_inc_not_zero(&engine->use.refcount)) { + engine->use.enabled = true; + if ((ret = nvkm_subdev_init(&engine->subdev))) { + engine->use.enabled = false; + mutex_unlock(&engine->use.mutex); + return ERR_PTR(ret); + } + refcount_set(&engine->use.refcount, 1); } + mutex_unlock(&engine->use.mutex); } - mutex_unlock(&engine->subdev.mutex); } return engine; } @@ -114,7 +119,7 @@ nvkm_engine_init(struct nvkm_subdev *subdev) int ret = 0, i; s64 time; - if (!engine->usecount) { + if (!engine->use.enabled) { nvkm_trace(subdev, "init skipped, engine has no users\n"); return ret; } @@ -156,11 +161,12 @@ nvkm_engine_dtor(struct nvkm_subdev *subdev) struct nvkm_engine *engine = nvkm_engine(subdev); if (engine->func->dtor) return engine->func->dtor(engine); + mutex_destroy(&engine->use.mutex); return engine; } -static const struct nvkm_subdev_func -nvkm_engine_func = { +const struct nvkm_subdev_func +nvkm_engine = { .dtor = nvkm_engine_dtor, .preinit = nvkm_engine_preinit, .init = nvkm_engine_init, @@ -170,14 +176,15 @@ nvkm_engine_func = { }; int -nvkm_engine_ctor(const struct nvkm_engine_func *func, - struct nvkm_device *device, int index, bool enable, - struct nvkm_engine *engine) +nvkm_engine_ctor(const struct nvkm_engine_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, bool enable, struct nvkm_engine *engine) { - nvkm_subdev_ctor(&nvkm_engine_func, device, index, &engine->subdev); + nvkm_subdev_ctor(&nvkm_engine, device, type, inst, &engine->subdev); engine->func = func; + refcount_set(&engine->use.refcount, 0); + mutex_init(&engine->use.mutex); - if (!nvkm_boolopt(device->cfgopt, nvkm_subdev_name[index], enable)) { + if (!nvkm_boolopt(device->cfgopt, engine->subdev.name, enable)) { nvkm_debug(&engine->subdev, "disabled\n"); return -ENODEV; } @@ -187,11 +194,11 @@ nvkm_engine_ctor(const struct nvkm_engine_func *func, } int -nvkm_engine_new_(const struct nvkm_engine_func *func, - struct nvkm_device *device, int index, bool enable, +nvkm_engine_new_(const struct nvkm_engine_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, bool enable, struct nvkm_engine **pengine) { if (!(*pengine = kzalloc(sizeof(**pengine), GFP_KERNEL))) return -ENOMEM; - return nvkm_engine_ctor(func, device, index, enable, *pengine); + return nvkm_engine_ctor(func, device, type, inst, enable, *pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/core/firmware.c b/drivers/gpu/drm/nouveau/nvkm/core/firmware.c index 092acdec2c39..ca1f8463cff5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/firmware.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/firmware.c @@ -22,19 +22,53 @@ #include <core/device.h> #include <core/firmware.h> +int +nvkm_firmware_load_name(const struct nvkm_subdev *subdev, const char *base, + const char *name, int ver, const struct firmware **pfw) +{ + char path[64]; + int ret; + + snprintf(path, sizeof(path), "%s%s", base, name); + ret = nvkm_firmware_get(subdev, path, ver, pfw); + if (ret < 0) + return ret; + + return 0; +} + +int +nvkm_firmware_load_blob(const struct nvkm_subdev *subdev, const char *base, + const char *name, int ver, struct nvkm_blob *blob) +{ + const struct firmware *fw; + int ret; + + ret = nvkm_firmware_load_name(subdev, base, name, ver, &fw); + if (ret == 0) { + blob->data = kmemdup(fw->data, fw->size, GFP_KERNEL); + blob->size = fw->size; + nvkm_firmware_put(fw); + if (!blob->data) + return -ENOMEM; + } + + return ret; +} + /** * nvkm_firmware_get - load firmware from the official nvidia/chip/ directory - * @subdev subdevice that will use that firmware - * @fwname name of firmware file to load - * @fw firmware structure to load to + * @subdev: subdevice that will use that firmware + * @fwname: name of firmware file to load + * @ver: firmware version to load + * @fw: firmware structure to load to * * Use this function to load firmware files in the form nvidia/chip/fwname.bin. * Firmware files released by NVIDIA will always follow this format. */ int -nvkm_firmware_get_version(const struct nvkm_subdev *subdev, const char *fwname, - int min_version, int max_version, - const struct firmware **fw) +nvkm_firmware_get(const struct nvkm_subdev *subdev, const char *fwname, int ver, + const struct firmware **fw) { struct nvkm_device *device = subdev->device; char f[64]; @@ -50,32 +84,22 @@ nvkm_firmware_get_version(const struct nvkm_subdev *subdev, const char *fwname, cname[i] = tolower(cname[i]); } - for (i = max_version; i >= min_version; i--) { - if (i != 0) - snprintf(f, sizeof(f), "nvidia/%s/%s-%d.bin", cname, fwname, i); - else - snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); + if (ver != 0) + snprintf(f, sizeof(f), "nvidia/%s/%s-%d.bin", cname, fwname, ver); + else + snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); - if (!firmware_request_nowarn(fw, f, device->dev)) { - nvkm_debug(subdev, "firmware \"%s\" loaded\n", f); - return i; - } - - nvkm_debug(subdev, "firmware \"%s\" unavailable\n", f); + if (!firmware_request_nowarn(fw, f, device->dev)) { + nvkm_debug(subdev, "firmware \"%s\" loaded - %zu byte(s)\n", + f, (*fw)->size); + return 0; } - nvkm_error(subdev, "failed to load firmware \"%s\"", fwname); + nvkm_debug(subdev, "firmware \"%s\" unavailable\n", f); return -ENOENT; } -int -nvkm_firmware_get(const struct nvkm_subdev *subdev, const char *fwname, - const struct firmware **fw) -{ - return nvkm_firmware_get_version(subdev, fwname, 0, 0, fw); -} - -/** +/* * nvkm_firmware_put - release firmware loaded with nvkm_firmware_get */ void diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c index d777df5a64e6..735cb6816f10 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c @@ -426,8 +426,7 @@ nvkm_ioctl_path(struct nvkm_client *client, u64 handle, u32 type, } int -nvkm_ioctl(struct nvkm_client *client, bool supervisor, - void *data, u32 size, void **hack) +nvkm_ioctl(struct nvkm_client *client, void *data, u32 size, void **hack) { struct nvkm_object *object = &client->object; union { @@ -435,7 +434,6 @@ nvkm_ioctl(struct nvkm_client *client, bool supervisor, } *args = data; int ret = -ENOSYS; - client->super = supervisor; nvif_ioctl(object, "size %d\n", size); if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { diff --git a/drivers/gpu/drm/nouveau/nvkm/core/memory.c b/drivers/gpu/drm/nouveau/nvkm/core/memory.c index e85a08ecd9da..c69daac9bac7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/memory.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/memory.c @@ -33,13 +33,13 @@ nvkm_memory_tags_put(struct nvkm_memory *memory, struct nvkm_device *device, struct nvkm_fb *fb = device->fb; struct nvkm_tags *tags = *ptags; if (tags) { - mutex_lock(&fb->subdev.mutex); + mutex_lock(&fb->tags.mutex); if (refcount_dec_and_test(&tags->refcount)) { - nvkm_mm_free(&fb->tags, &tags->mn); + nvkm_mm_free(&fb->tags.mm, &tags->mn); kfree(memory->tags); memory->tags = NULL; } - mutex_unlock(&fb->subdev.mutex); + mutex_unlock(&fb->tags.mutex); *ptags = NULL; } } @@ -52,29 +52,29 @@ nvkm_memory_tags_get(struct nvkm_memory *memory, struct nvkm_device *device, struct nvkm_fb *fb = device->fb; struct nvkm_tags *tags; - mutex_lock(&fb->subdev.mutex); + mutex_lock(&fb->tags.mutex); if ((tags = memory->tags)) { /* If comptags exist for the memory, but a different amount * than requested, the buffer is being mapped with settings * that are incompatible with existing mappings. */ if (tags->mn && tags->mn->length != nr) { - mutex_unlock(&fb->subdev.mutex); + mutex_unlock(&fb->tags.mutex); return -EINVAL; } refcount_inc(&tags->refcount); - mutex_unlock(&fb->subdev.mutex); + mutex_unlock(&fb->tags.mutex); *ptags = tags; return 0; } if (!(tags = kmalloc(sizeof(*tags), GFP_KERNEL))) { - mutex_unlock(&fb->subdev.mutex); + mutex_unlock(&fb->tags.mutex); return -ENOMEM; } - if (!nvkm_mm_head(&fb->tags, 0, 1, nr, nr, 1, &tags->mn)) { + if (!nvkm_mm_head(&fb->tags.mm, 0, 1, nr, nr, 1, &tags->mn)) { if (clr) clr(device, tags->mn->offset, tags->mn->length); } else { @@ -91,8 +91,8 @@ nvkm_memory_tags_get(struct nvkm_memory *memory, struct nvkm_device *device, } refcount_set(&tags->refcount, 1); - mutex_unlock(&fb->subdev.mutex); - *ptags = tags; + *ptags = memory->tags = tags; + mutex_unlock(&fb->tags.mutex); return 0; } @@ -140,7 +140,7 @@ nvkm_memory_new(struct nvkm_device *device, enum nvkm_memory_target target, { struct nvkm_instmem *imem = device->imem; struct nvkm_memory *memory; - int ret = -ENOSYS; + int ret; if (unlikely(target != NVKM_MEM_TARGET_INST || !imem)) return -ENOSYS; diff --git a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c index 245990de1e90..a74b7acb6832 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c @@ -26,69 +26,13 @@ #include <core/option.h> #include <subdev/mc.h> -static struct lock_class_key nvkm_subdev_lock_class[NVKM_SUBDEV_NR]; - const char * -nvkm_subdev_name[NVKM_SUBDEV_NR] = { - [NVKM_SUBDEV_BAR ] = "bar", - [NVKM_SUBDEV_VBIOS ] = "bios", - [NVKM_SUBDEV_BUS ] = "bus", - [NVKM_SUBDEV_CLK ] = "clk", - [NVKM_SUBDEV_DEVINIT ] = "devinit", - [NVKM_SUBDEV_FAULT ] = "fault", - [NVKM_SUBDEV_FB ] = "fb", - [NVKM_SUBDEV_FUSE ] = "fuse", - [NVKM_SUBDEV_GPIO ] = "gpio", - [NVKM_SUBDEV_GSP ] = "gsp", - [NVKM_SUBDEV_I2C ] = "i2c", - [NVKM_SUBDEV_IBUS ] = "priv", - [NVKM_SUBDEV_ICCSENSE] = "iccsense", - [NVKM_SUBDEV_INSTMEM ] = "imem", - [NVKM_SUBDEV_LTC ] = "ltc", - [NVKM_SUBDEV_MC ] = "mc", - [NVKM_SUBDEV_MMU ] = "mmu", - [NVKM_SUBDEV_MXM ] = "mxm", - [NVKM_SUBDEV_PCI ] = "pci", - [NVKM_SUBDEV_PMU ] = "pmu", - [NVKM_SUBDEV_SECBOOT ] = "secboot", - [NVKM_SUBDEV_THERM ] = "therm", - [NVKM_SUBDEV_TIMER ] = "tmr", - [NVKM_SUBDEV_TOP ] = "top", - [NVKM_SUBDEV_VOLT ] = "volt", - [NVKM_ENGINE_BSP ] = "bsp", - [NVKM_ENGINE_CE0 ] = "ce0", - [NVKM_ENGINE_CE1 ] = "ce1", - [NVKM_ENGINE_CE2 ] = "ce2", - [NVKM_ENGINE_CE3 ] = "ce3", - [NVKM_ENGINE_CE4 ] = "ce4", - [NVKM_ENGINE_CE5 ] = "ce5", - [NVKM_ENGINE_CE6 ] = "ce6", - [NVKM_ENGINE_CE7 ] = "ce7", - [NVKM_ENGINE_CE8 ] = "ce8", - [NVKM_ENGINE_CIPHER ] = "cipher", - [NVKM_ENGINE_DISP ] = "disp", - [NVKM_ENGINE_DMAOBJ ] = "dma", - [NVKM_ENGINE_FIFO ] = "fifo", - [NVKM_ENGINE_GR ] = "gr", - [NVKM_ENGINE_IFB ] = "ifb", - [NVKM_ENGINE_ME ] = "me", - [NVKM_ENGINE_MPEG ] = "mpeg", - [NVKM_ENGINE_MSENC ] = "msenc", - [NVKM_ENGINE_MSPDEC ] = "mspdec", - [NVKM_ENGINE_MSPPP ] = "msppp", - [NVKM_ENGINE_MSVLD ] = "msvld", - [NVKM_ENGINE_NVENC0 ] = "nvenc0", - [NVKM_ENGINE_NVENC1 ] = "nvenc1", - [NVKM_ENGINE_NVENC2 ] = "nvenc2", - [NVKM_ENGINE_NVDEC0 ] = "nvdec0", - [NVKM_ENGINE_NVDEC1 ] = "nvdec1", - [NVKM_ENGINE_NVDEC2 ] = "nvdec2", - [NVKM_ENGINE_PM ] = "pm", - [NVKM_ENGINE_SEC ] = "sec", - [NVKM_ENGINE_SEC2 ] = "sec2", - [NVKM_ENGINE_SW ] = "sw", - [NVKM_ENGINE_VIC ] = "vic", - [NVKM_ENGINE_VP ] = "vp", +nvkm_subdev_type[NVKM_SUBDEV_NR] = { +#define NVKM_LAYOUT_ONCE(type,data,ptr,...) [type] = #ptr, +#define NVKM_LAYOUT_INST(A...) NVKM_LAYOUT_ONCE(A) +#include <core/layout.h> +#undef NVKM_LAYOUT_ONCE +#undef NVKM_LAYOUT_INST }; void @@ -125,7 +69,7 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend) } } - nvkm_mc_reset(device, subdev->index); + nvkm_mc_reset(device, subdev->type, subdev->inst); time = ktime_to_us(ktime_get()) - time; nvkm_trace(subdev, "%s completed in %lldus\n", action, time); @@ -199,6 +143,7 @@ nvkm_subdev_del(struct nvkm_subdev **psubdev) if (subdev && !WARN_ON(!subdev->func)) { nvkm_trace(subdev, "destroy running...\n"); time = ktime_to_us(ktime_get()); + list_del(&subdev->head); if (subdev->func->dtor) *psubdev = subdev->func->dtor(subdev); time = ktime_to_us(ktime_get()) - time; @@ -209,15 +154,41 @@ nvkm_subdev_del(struct nvkm_subdev **psubdev) } void -nvkm_subdev_ctor(const struct nvkm_subdev_func *func, - struct nvkm_device *device, int index, - struct nvkm_subdev *subdev) +nvkm_subdev_disable(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) +{ + struct nvkm_subdev *subdev; + list_for_each_entry(subdev, &device->subdev, head) { + if (subdev->type == type && subdev->inst == inst) { + *subdev->pself = NULL; + nvkm_subdev_del(&subdev); + break; + } + } +} + +void +nvkm_subdev_ctor(const struct nvkm_subdev_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_subdev *subdev) { - const char *name = nvkm_subdev_name[index]; subdev->func = func; subdev->device = device; - subdev->index = index; + subdev->type = type; + subdev->inst = inst < 0 ? 0 : inst; + + if (inst >= 0) + snprintf(subdev->name, sizeof(subdev->name), "%s%d", nvkm_subdev_type[type], inst); + else + strscpy(subdev->name, nvkm_subdev_type[type], sizeof(subdev->name)); + subdev->debug = nvkm_dbgopt(device->dbgopt, subdev->name); + list_add_tail(&subdev->head, &device->subdev); +} - __mutex_init(&subdev->mutex, name, &nvkm_subdev_lock_class[index]); - subdev->debug = nvkm_dbgopt(device->dbgopt, name); +int +nvkm_subdev_new_(const struct nvkm_subdev_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_subdev **psubdev) +{ + if (!(*psubdev = kzalloc(sizeof(**psubdev), GFP_KERNEL))) + return -ENOMEM; + nvkm_subdev_ctor(func, device, type, inst, *psubdev); + return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c index 44e116f7880d..39f6db269c7a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c @@ -36,8 +36,9 @@ g84_bsp = { }; int -g84_bsp_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) +g84_bsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_xtensa_new_(&g84_bsp, device, index, + return nvkm_xtensa_new_(&g84_bsp, device, type, inst, device->chipset != 0x92, 0x103000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c index ad9f855c9a40..b9cc39565985 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c @@ -29,9 +29,7 @@ static void gf100_ce_init(struct nvkm_falcon *ce) { - struct nvkm_device *device = ce->engine.subdev.device; - const int index = ce->engine.subdev.index - NVKM_ENGINE_CE0; - nvkm_wr32(device, ce->addr + 0x084, index); + nvkm_wr32(ce->engine.subdev.device, ce->addr + 0x084, ce->engine.subdev.inst); } static const struct nvkm_falcon_func @@ -63,16 +61,9 @@ gf100_ce1 = { }; int -gf100_ce_new(struct nvkm_device *device, int index, +gf100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - if (index == NVKM_ENGINE_CE0) { - return nvkm_falcon_new_(&gf100_ce0, device, index, true, - 0x104000, pengine); - } else - if (index == NVKM_ENGINE_CE1) { - return nvkm_falcon_new_(&gf100_ce1, device, index, true, - 0x105000, pengine); - } - return -ENODEV; + return nvkm_falcon_new_(inst ? &gf100_ce1 : &gf100_ce0, device, type, inst, true, + 0x104000 + (inst * 0x1000), pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c index 9e0b53a10f77..27f29eb0494d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c @@ -58,9 +58,9 @@ gk104_ce_intr_launcherr(struct nvkm_engine *ce, const u32 base) void gk104_ce_intr(struct nvkm_engine *ce) { - const u32 base = (ce->subdev.index - NVKM_ENGINE_CE0) * 0x1000; struct nvkm_subdev *subdev = &ce->subdev; struct nvkm_device *device = subdev->device; + const u32 base = subdev->inst * 0x1000; u32 mask = nvkm_rd32(device, 0x104904 + base); u32 intr = nvkm_rd32(device, 0x104908 + base) & mask; if (intr & 0x00000001) { @@ -94,8 +94,8 @@ gk104_ce = { }; int -gk104_ce_new(struct nvkm_device *device, int index, +gk104_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&gk104_ce, device, index, true, pengine); + return nvkm_engine_new_(&gk104_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c index c0df7daa85e2..c3c476592c43 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c @@ -36,8 +36,8 @@ gm107_ce = { }; int -gm107_ce_new(struct nvkm_device *device, int index, +gm107_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&gm107_ce, device, index, true, pengine); + return nvkm_engine_new_(&gm107_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c index c6fa8b20737e..d2db61865371 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c @@ -35,8 +35,8 @@ gm200_ce = { }; int -gm200_ce_new(struct nvkm_device *device, int index, +gm200_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&gm200_ce, device, index, true, pengine); + return nvkm_engine_new_(&gm200_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c index c7710456bc30..a4f08a4472c9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c @@ -59,9 +59,9 @@ gp100_ce_intr_launcherr(struct nvkm_engine *ce, const u32 base) void gp100_ce_intr(struct nvkm_engine *ce) { - const u32 base = (ce->subdev.index - NVKM_ENGINE_CE0) * 0x80; struct nvkm_subdev *subdev = &ce->subdev; struct nvkm_device *device = subdev->device; + const u32 base = subdev->inst * 0x80; u32 mask = nvkm_rd32(device, 0x10440c + base); u32 intr = nvkm_rd32(device, 0x104410 + base) & mask; if (intr & 0x00000001) { //XXX: guess @@ -95,8 +95,8 @@ gp100_ce = { }; int -gp100_ce_new(struct nvkm_device *device, int index, +gp100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&gp100_ce, device, index, true, pengine); + return nvkm_engine_new_(&gp100_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.c index 985c8f653874..180d497a95eb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.c @@ -37,8 +37,8 @@ gp102_ce = { }; int -gp102_ce_new(struct nvkm_device *device, int index, +gp102_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&gp102_ce, device, index, true, pengine); + return nvkm_engine_new_(&gp102_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c index 63ac51a54fd3..09a112af2f89 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c @@ -44,7 +44,7 @@ gt215_ce_intr(struct nvkm_falcon *ce, struct nvkm_fifo_chan *chan) { struct nvkm_subdev *subdev = &ce->engine.subdev; struct nvkm_device *device = subdev->device; - const u32 base = (subdev->index - NVKM_ENGINE_CE0) * 0x1000; + const u32 base = subdev->inst * 0x1000; u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff; u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16; u32 mthd = (addr & 0x07ff) << 2; @@ -75,9 +75,9 @@ gt215_ce = { }; int -gt215_ce_new(struct nvkm_device *device, int index, +gt215_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_falcon_new_(>215_ce, device, index, + return nvkm_falcon_new_(>215_ce, device, type, -1, (device->chipset != 0xaf), 0x104000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c index fcda3de45857..cd5e9cdca1cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c @@ -33,8 +33,8 @@ gv100_ce = { }; int -gv100_ce_new(struct nvkm_device *device, int index, +gv100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&gv100_ce, device, index, true, pengine); + return nvkm_engine_new_(&gv100_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c index b4308e2d8c75..e5ff92d9364c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c @@ -33,8 +33,8 @@ tu102_ce = { }; int -tu102_ce_new(struct nvkm_device *device, int index, +tu102_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&tu102_ce, device, index, true, pengine); + return nvkm_engine_new_(&tu102_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c index 68ffb520531e..be2a7181dc15 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c @@ -127,8 +127,8 @@ g84_cipher = { }; int -g84_cipher_new(struct nvkm_device *device, int index, +g84_cipher_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&g84_cipher, device, index, true, pengine); + return nvkm_engine_new_(&g84_cipher, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index c3c7159f3411..62efbd0f3846 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -71,2543 +71,2601 @@ nvkm_device_list(u64 *name, int size) static const struct nvkm_device_chip null_chipset = { .name = "NULL", - .bios = nvkm_bios_new, + .bios = { 0x00000001, nvkm_bios_new }, }; static const struct nvkm_device_chip nv4_chipset = { .name = "NV04", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv04_devinit_new, - .fb = nv04_fb_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv04_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv04_fifo_new, - .gr = nv04_gr_new, - .sw = nv04_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv04_devinit_new }, + .fb = { 0x00000001, nv04_fb_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv04_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv04_fifo_new }, + .gr = { 0x00000001, nv04_gr_new }, + .sw = { 0x00000001, nv04_sw_new }, }; static const struct nvkm_device_chip nv5_chipset = { .name = "NV05", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv05_devinit_new, - .fb = nv04_fb_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv04_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv04_fifo_new, - .gr = nv04_gr_new, - .sw = nv04_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv05_devinit_new }, + .fb = { 0x00000001, nv04_fb_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv04_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv04_fifo_new }, + .gr = { 0x00000001, nv04_gr_new }, + .sw = { 0x00000001, nv04_sw_new }, }; static const struct nvkm_device_chip nv10_chipset = { .name = "NV10", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv10_devinit_new, - .fb = nv10_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv04_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .gr = nv10_gr_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv10_devinit_new }, + .fb = { 0x00000001, nv10_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv04_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .gr = { 0x00000001, nv10_gr_new }, }; static const struct nvkm_device_chip nv11_chipset = { .name = "NV11", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv10_devinit_new, - .fb = nv10_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv11_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv10_fifo_new, - .gr = nv15_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv10_devinit_new }, + .fb = { 0x00000001, nv10_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv11_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv10_fifo_new }, + .gr = { 0x00000001, nv15_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv15_chipset = { .name = "NV15", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv10_devinit_new, - .fb = nv10_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv04_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv10_fifo_new, - .gr = nv15_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv10_devinit_new }, + .fb = { 0x00000001, nv10_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv04_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv10_fifo_new }, + .gr = { 0x00000001, nv15_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv17_chipset = { .name = "NV17", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv10_devinit_new, - .fb = nv10_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv17_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv10_devinit_new }, + .fb = { 0x00000001, nv10_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv17_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv18_chipset = { .name = "NV18", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv10_devinit_new, - .fb = nv10_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv17_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv10_devinit_new }, + .fb = { 0x00000001, nv10_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv17_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv1a_chipset = { .name = "nForce", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv1a_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv04_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv10_fifo_new, - .gr = nv15_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv1a_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv04_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv10_fifo_new }, + .gr = { 0x00000001, nv15_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv1f_chipset = { .name = "nForce2", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv1a_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv17_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv1a_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv17_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv20_chipset = { .name = "NV20", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv20_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv20_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv20_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv20_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv25_chipset = { .name = "NV25", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv25_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv25_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv25_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv25_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv28_chipset = { .name = "NV28", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv25_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv25_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv25_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv25_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv2a_chipset = { .name = "NV2A", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv25_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv2a_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv25_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv2a_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv30_chipset = { .name = "NV30", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv30_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv30_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv30_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv30_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv31_chipset = { .name = "NV31", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv30_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv30_gr_new, - .mpeg = nv31_mpeg_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv30_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv30_gr_new }, + .mpeg = { 0x00000001, nv31_mpeg_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv34_chipset = { .name = "NV34", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv04_clk_new, - .devinit = nv10_devinit_new, - .fb = nv10_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv34_gr_new, - .mpeg = nv31_mpeg_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv10_devinit_new }, + .fb = { 0x00000001, nv10_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv34_gr_new }, + .mpeg = { 0x00000001, nv31_mpeg_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv35_chipset = { .name = "NV35", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv35_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv35_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv35_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv35_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv36_chipset = { .name = "NV36", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv36_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv35_gr_new, - .mpeg = nv31_mpeg_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv36_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv35_gr_new }, + .mpeg = { 0x00000001, nv31_mpeg_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv40_chipset = { .name = "NV40", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv40_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv40_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv40_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv40_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv40_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv40_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv41_chipset = { .name = "NV41", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv41_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv41_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv40_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv41_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv41_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv40_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv42_chipset = { .name = "NV42", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv41_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv41_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv40_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv41_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv41_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv40_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv43_chipset = { .name = "NV43", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv41_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv41_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv40_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv41_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv41_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv40_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv44_chipset = { .name = "NV44", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv44_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv44_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv45_chipset = { .name = "NV45", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv40_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv40_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv46_chipset = { .name = "G72", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv46_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv46_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv46_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv46_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv47_chipset = { .name = "G70", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv47_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv41_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv47_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv41_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv49_chipset = { .name = "G71", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv49_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv41_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv49_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv41_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv4a_chipset = { .name = "NV44A", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv44_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv04_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv44_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv4b_chipset = { .name = "G73", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv49_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv41_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv49_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv41_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv4c_chipset = { .name = "C61", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv46_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv4c_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv46_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv4c_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv4e_chipset = { .name = "C51", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv4e_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv4e_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv4c_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv4e_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv4e_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv4c_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv50_chipset = { .name = "G80", - .bar = nv50_bar_new, - .bios = nvkm_bios_new, - .bus = nv50_bus_new, - .clk = nv50_clk_new, - .devinit = nv50_devinit_new, - .fb = nv50_fb_new, - .fuse = nv50_fuse_new, - .gpio = nv50_gpio_new, - .i2c = nv50_i2c_new, - .imem = nv50_instmem_new, - .mc = nv50_mc_new, - .mmu = nv50_mmu_new, - .mxm = nv50_mxm_new, - .pci = nv46_pci_new, - .therm = nv50_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv50_disp_new, - .dma = nv50_dma_new, - .fifo = nv50_fifo_new, - .gr = nv50_gr_new, - .mpeg = nv50_mpeg_new, - .pm = nv50_pm_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, nv50_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv50_bus_new }, + .clk = { 0x00000001, nv50_clk_new }, + .devinit = { 0x00000001, nv50_devinit_new }, + .fb = { 0x00000001, nv50_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, nv50_gpio_new }, + .i2c = { 0x00000001, nv50_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, nv50_mc_new }, + .mmu = { 0x00000001, nv50_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, nv46_pci_new }, + .therm = { 0x00000001, nv50_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv50_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, nv50_fifo_new }, + .gr = { 0x00000001, nv50_gr_new }, + .mpeg = { 0x00000001, nv50_mpeg_new }, + .pm = { 0x00000001, nv50_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nv63_chipset = { .name = "C73", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv46_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv4c_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv46_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv4c_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv67_chipset = { .name = "C67", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv46_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv4c_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv46_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv4c_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv68_chipset = { .name = "C68", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv46_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv4c_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv46_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv4c_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv84_chipset = { .name = "G84", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = nv50_bus_new, - .clk = g84_clk_new, - .devinit = g84_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = nv50_gpio_new, - .i2c = nv50_i2c_new, - .imem = nv50_instmem_new, - .mc = g84_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g84_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .bsp = g84_bsp_new, - .cipher = g84_cipher_new, - .disp = g84_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = g84_gr_new, - .mpeg = g84_mpeg_new, - .pm = g84_pm_new, - .sw = nv50_sw_new, - .vp = g84_vp_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv50_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g84_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, nv50_gpio_new }, + .i2c = { 0x00000001, nv50_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g84_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g84_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .bsp = { 0x00000001, g84_bsp_new }, + .cipher = { 0x00000001, g84_cipher_new }, + .disp = { 0x00000001, g84_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, g84_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .pm = { 0x00000001, g84_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, + .vp = { 0x00000001, g84_vp_new }, }; static const struct nvkm_device_chip nv86_chipset = { .name = "G86", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = nv50_bus_new, - .clk = g84_clk_new, - .devinit = g84_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = nv50_gpio_new, - .i2c = nv50_i2c_new, - .imem = nv50_instmem_new, - .mc = g84_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g84_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .bsp = g84_bsp_new, - .cipher = g84_cipher_new, - .disp = g84_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = g84_gr_new, - .mpeg = g84_mpeg_new, - .pm = g84_pm_new, - .sw = nv50_sw_new, - .vp = g84_vp_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv50_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g84_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, nv50_gpio_new }, + .i2c = { 0x00000001, nv50_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g84_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g84_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .bsp = { 0x00000001, g84_bsp_new }, + .cipher = { 0x00000001, g84_cipher_new }, + .disp = { 0x00000001, g84_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, g84_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .pm = { 0x00000001, g84_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, + .vp = { 0x00000001, g84_vp_new }, }; static const struct nvkm_device_chip nv92_chipset = { .name = "G92", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = nv50_bus_new, - .clk = g84_clk_new, - .devinit = g84_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = nv50_gpio_new, - .i2c = nv50_i2c_new, - .imem = nv50_instmem_new, - .mc = g84_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g92_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .bsp = g84_bsp_new, - .cipher = g84_cipher_new, - .disp = g84_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = g84_gr_new, - .mpeg = g84_mpeg_new, - .pm = g84_pm_new, - .sw = nv50_sw_new, - .vp = g84_vp_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv50_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g84_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, nv50_gpio_new }, + .i2c = { 0x00000001, nv50_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g84_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g92_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .bsp = { 0x00000001, g84_bsp_new }, + .cipher = { 0x00000001, g84_cipher_new }, + .disp = { 0x00000001, g84_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, g84_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .pm = { 0x00000001, g84_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, + .vp = { 0x00000001, g84_vp_new }, }; static const struct nvkm_device_chip nv94_chipset = { .name = "G94", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = g84_clk_new, - .devinit = g84_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = g84_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .bsp = g84_bsp_new, - .cipher = g84_cipher_new, - .disp = g94_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = g84_gr_new, - .mpeg = g84_mpeg_new, - .pm = g84_pm_new, - .sw = nv50_sw_new, - .vp = g84_vp_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g84_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g84_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .bsp = { 0x00000001, g84_bsp_new }, + .cipher = { 0x00000001, g84_cipher_new }, + .disp = { 0x00000001, g94_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, g84_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .pm = { 0x00000001, g84_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, + .vp = { 0x00000001, g84_vp_new }, }; static const struct nvkm_device_chip nv96_chipset = { .name = "G96", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = g84_clk_new, - .devinit = g84_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = g84_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .bsp = g84_bsp_new, - .cipher = g84_cipher_new, - .disp = g94_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = g84_gr_new, - .mpeg = g84_mpeg_new, - .pm = g84_pm_new, - .sw = nv50_sw_new, - .vp = g84_vp_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g84_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g84_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .bsp = { 0x00000001, g84_bsp_new }, + .cipher = { 0x00000001, g84_cipher_new }, + .disp = { 0x00000001, g94_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, g84_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .pm = { 0x00000001, g84_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, + .vp = { 0x00000001, g84_vp_new }, }; static const struct nvkm_device_chip nv98_chipset = { .name = "G98", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = g84_clk_new, - .devinit = g98_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = g98_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = g94_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = g84_gr_new, - .mspdec = g98_mspdec_new, - .msppp = g98_msppp_new, - .msvld = g98_msvld_new, - .pm = g84_pm_new, - .sec = g98_sec_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g98_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g98_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, g94_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, g84_gr_new }, + .mspdec = { 0x00000001, g98_mspdec_new }, + .msppp = { 0x00000001, g98_msppp_new }, + .msvld = { 0x00000001, g98_msvld_new }, + .pm = { 0x00000001, g84_pm_new }, + .sec = { 0x00000001, g98_sec_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nva0_chipset = { .name = "GT200", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = g84_clk_new, - .devinit = g84_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = nv50_i2c_new, - .imem = nv50_instmem_new, - .mc = g84_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .bsp = g84_bsp_new, - .cipher = g84_cipher_new, - .disp = gt200_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = gt200_gr_new, - .mpeg = g84_mpeg_new, - .pm = gt200_pm_new, - .sw = nv50_sw_new, - .vp = g84_vp_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g84_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, nv50_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g84_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .bsp = { 0x00000001, g84_bsp_new }, + .cipher = { 0x00000001, g84_cipher_new }, + .disp = { 0x00000001, gt200_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, gt200_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .pm = { 0x00000001, gt200_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, + .vp = { 0x00000001, g84_vp_new }, }; static const struct nvkm_device_chip nva3_chipset = { .name = "GT215", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = gt215_clk_new, - .devinit = gt215_devinit_new, - .fb = gt215_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = gt215_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .pmu = gt215_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .ce[0] = gt215_ce_new, - .disp = gt215_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = gt215_gr_new, - .mpeg = g84_mpeg_new, - .mspdec = gt215_mspdec_new, - .msppp = gt215_msppp_new, - .msvld = gt215_msvld_new, - .pm = gt215_pm_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, gt215_clk_new }, + .devinit = { 0x00000001, gt215_devinit_new }, + .fb = { 0x00000001, gt215_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, gt215_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .pmu = { 0x00000001, gt215_pmu_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .ce = { 0x00000001, gt215_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, gt215_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .mspdec = { 0x00000001, gt215_mspdec_new }, + .msppp = { 0x00000001, gt215_msppp_new }, + .msvld = { 0x00000001, gt215_msvld_new }, + .pm = { 0x00000001, gt215_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nva5_chipset = { .name = "GT216", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = gt215_clk_new, - .devinit = gt215_devinit_new, - .fb = gt215_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = gt215_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .pmu = gt215_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .ce[0] = gt215_ce_new, - .disp = gt215_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = gt215_gr_new, - .mspdec = gt215_mspdec_new, - .msppp = gt215_msppp_new, - .msvld = gt215_msvld_new, - .pm = gt215_pm_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, gt215_clk_new }, + .devinit = { 0x00000001, gt215_devinit_new }, + .fb = { 0x00000001, gt215_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, gt215_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .pmu = { 0x00000001, gt215_pmu_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .ce = { 0x00000001, gt215_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, gt215_gr_new }, + .mspdec = { 0x00000001, gt215_mspdec_new }, + .msppp = { 0x00000001, gt215_msppp_new }, + .msvld = { 0x00000001, gt215_msvld_new }, + .pm = { 0x00000001, gt215_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nva8_chipset = { .name = "GT218", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = gt215_clk_new, - .devinit = gt215_devinit_new, - .fb = gt215_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = gt215_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .pmu = gt215_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .ce[0] = gt215_ce_new, - .disp = gt215_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = gt215_gr_new, - .mspdec = gt215_mspdec_new, - .msppp = gt215_msppp_new, - .msvld = gt215_msvld_new, - .pm = gt215_pm_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, gt215_clk_new }, + .devinit = { 0x00000001, gt215_devinit_new }, + .fb = { 0x00000001, gt215_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, gt215_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .pmu = { 0x00000001, gt215_pmu_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .ce = { 0x00000001, gt215_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, gt215_gr_new }, + .mspdec = { 0x00000001, gt215_mspdec_new }, + .msppp = { 0x00000001, gt215_msppp_new }, + .msvld = { 0x00000001, gt215_msvld_new }, + .pm = { 0x00000001, gt215_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nvaa_chipset = { .name = "MCP77/MCP78", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = mcp77_clk_new, - .devinit = g98_devinit_new, - .fb = mcp77_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = g98_mc_new, - .mmu = mcp77_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = mcp77_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = gt200_gr_new, - .mspdec = g98_mspdec_new, - .msppp = g98_msppp_new, - .msvld = g98_msvld_new, - .pm = g84_pm_new, - .sec = g98_sec_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, mcp77_clk_new }, + .devinit = { 0x00000001, g98_devinit_new }, + .fb = { 0x00000001, mcp77_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g98_mc_new }, + .mmu = { 0x00000001, mcp77_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, mcp77_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, gt200_gr_new }, + .mspdec = { 0x00000001, g98_mspdec_new }, + .msppp = { 0x00000001, g98_msppp_new }, + .msvld = { 0x00000001, g98_msvld_new }, + .pm = { 0x00000001, g84_pm_new }, + .sec = { 0x00000001, g98_sec_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nvac_chipset = { .name = "MCP79/MCP7A", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = mcp77_clk_new, - .devinit = g98_devinit_new, - .fb = mcp77_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = g98_mc_new, - .mmu = mcp77_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = mcp77_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = mcp79_gr_new, - .mspdec = g98_mspdec_new, - .msppp = g98_msppp_new, - .msvld = g98_msvld_new, - .pm = g84_pm_new, - .sec = g98_sec_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, mcp77_clk_new }, + .devinit = { 0x00000001, g98_devinit_new }, + .fb = { 0x00000001, mcp77_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g98_mc_new }, + .mmu = { 0x00000001, mcp77_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, mcp77_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, mcp79_gr_new }, + .mspdec = { 0x00000001, g98_mspdec_new }, + .msppp = { 0x00000001, g98_msppp_new }, + .msvld = { 0x00000001, g98_msvld_new }, + .pm = { 0x00000001, g84_pm_new }, + .sec = { 0x00000001, g98_sec_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nvaf_chipset = { .name = "MCP89", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = gt215_clk_new, - .devinit = mcp89_devinit_new, - .fb = mcp89_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = gt215_mc_new, - .mmu = mcp77_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .pmu = gt215_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .ce[0] = gt215_ce_new, - .disp = mcp89_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = mcp89_gr_new, - .mspdec = gt215_mspdec_new, - .msppp = gt215_msppp_new, - .msvld = mcp89_msvld_new, - .pm = gt215_pm_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, gt215_clk_new }, + .devinit = { 0x00000001, mcp89_devinit_new }, + .fb = { 0x00000001, mcp89_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, gt215_mc_new }, + .mmu = { 0x00000001, mcp77_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .pmu = { 0x00000001, gt215_pmu_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .ce = { 0x00000001, gt215_ce_new }, + .disp = { 0x00000001, mcp89_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, mcp89_gr_new }, + .mspdec = { 0x00000001, gt215_mspdec_new }, + .msppp = { 0x00000001, gt215_msppp_new }, + .msvld = { 0x00000001, mcp89_msvld_new }, + .pm = { 0x00000001, gt215_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nvc0_chipset = { .name = "GF100", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf100_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .ce[1] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf100_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf100_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf100_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000003, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf100_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf100_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvc1_chipset = { .name = "GF108", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf108_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf106_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf108_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf108_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf108_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf106_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000001, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf108_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf108_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvc3_chipset = { .name = "GF106", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf106_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf104_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf100_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf106_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000001, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf104_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf100_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvc4_chipset = { .name = "GF104", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf100_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .ce[1] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf104_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf100_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf100_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000003, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf104_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf100_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvc8_chipset = { .name = "GF110", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf100_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .ce[1] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf110_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf100_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf100_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000003, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf110_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf100_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvce_chipset = { .name = "GF114", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf100_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .ce[1] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf104_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf100_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf100_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000003, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf104_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf100_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvcf_chipset = { .name = "GF116", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf106_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf104_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf100_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf106_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000001, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf104_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf100_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvd7_chipset = { .name = "GF117", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = gf119_gpio_new, - .i2c = gf117_i2c_new, - .ibus = gf117_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf106_pci_new, - .therm = gf119_therm_new, - .timer = nv41_timer_new, - .volt = gf117_volt_new, - .ce[0] = gf100_ce_new, - .disp = gf119_disp_new, - .dma = gf119_dma_new, - .fifo = gf100_fifo_new, - .gr = gf117_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf117_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gf119_gpio_new }, + .i2c = { 0x00000001, gf117_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf106_pci_new }, + .privring = { 0x00000001, gf117_privring_new }, + .therm = { 0x00000001, gf119_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf117_volt_new }, + .ce = { 0x00000001, gf100_ce_new }, + .disp = { 0x00000001, gf119_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf117_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf117_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvd9_chipset = { .name = "GF119", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = gf119_gpio_new, - .i2c = gf119_i2c_new, - .ibus = gf117_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf106_pci_new, - .pmu = gf119_pmu_new, - .therm = gf119_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .disp = gf119_disp_new, - .dma = gf119_dma_new, - .fifo = gf100_fifo_new, - .gr = gf119_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf117_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gf119_gpio_new }, + .i2c = { 0x00000001, gf119_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf106_pci_new }, + .pmu = { 0x00000001, gf119_pmu_new }, + .privring = { 0x00000001, gf117_privring_new }, + .therm = { 0x00000001, gf119_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000001, gf100_ce_new }, + .disp = { 0x00000001, gf119_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf119_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf117_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nve4_chipset = { .name = "GK104", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk104_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk104_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk104_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk104_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk104_disp_new, - .dma = gf119_dma_new, - .fifo = gk104_fifo_new, - .gr = gk104_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .pm = gk104_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk104_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk104_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk104_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk104_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk104_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk104_fifo_new }, + .gr = { 0x00000001, gk104_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .pm = { 0x00000001, gk104_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nve6_chipset = { .name = "GK106", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk104_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk104_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk104_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk104_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk104_disp_new, - .dma = gf119_dma_new, - .fifo = gk104_fifo_new, - .gr = gk104_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .pm = gk104_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk104_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk104_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk104_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk104_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk104_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk104_fifo_new }, + .gr = { 0x00000001, gk104_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .pm = { 0x00000001, gk104_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nve7_chipset = { .name = "GK107", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk104_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk104_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk104_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk104_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk104_disp_new, - .dma = gf119_dma_new, - .fifo = gk104_fifo_new, - .gr = gk104_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .pm = gk104_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk104_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk104_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk104_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk104_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk104_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk104_fifo_new }, + .gr = { 0x00000001, gk104_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .pm = { 0x00000001, gk104_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvea_chipset = { .name = "GK20A", - .bar = gk20a_bar_new, - .bus = gf100_bus_new, - .clk = gk20a_clk_new, - .fb = gk20a_fb_new, - .fuse = gf100_fuse_new, - .ibus = gk20a_ibus_new, - .imem = gk20a_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk20a_mc_new, - .mmu = gk20a_mmu_new, - .pmu = gk20a_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .volt = gk20a_volt_new, - .ce[2] = gk104_ce_new, - .dma = gf119_dma_new, - .fifo = gk20a_fifo_new, - .gr = gk20a_gr_new, - .pm = gk104_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gk20a_bar_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk20a_clk_new }, + .fb = { 0x00000001, gk20a_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .imem = { 0x00000001, gk20a_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gk20a_mmu_new }, + .pmu = { 0x00000001, gk20a_pmu_new }, + .privring = { 0x00000001, gk20a_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk20a_volt_new }, + .ce = { 0x00000004, gk104_ce_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk20a_fifo_new }, + .gr = { 0x00000001, gk20a_gr_new }, + .pm = { 0x00000001, gk104_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvf0_chipset = { .name = "GK110", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk110_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk104_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk104_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk110_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk110_disp_new, - .dma = gf119_dma_new, - .fifo = gk110_fifo_new, - .gr = gk110_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk110_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk110_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk104_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk110_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk110_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk110_fifo_new }, + .gr = { 0x00000001, gk110_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvf1_chipset = { .name = "GK110B", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk110_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk104_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk104_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk110_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk110_disp_new, - .dma = gf119_dma_new, - .fifo = gk110_fifo_new, - .gr = gk110b_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk110_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk110_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk104_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk110_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk110_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk110_fifo_new }, + .gr = { 0x00000001, gk110b_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv106_chipset = { .name = "GK208B", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk110_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk104_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk20a_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk208_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk110_disp_new, - .dma = gf119_dma_new, - .fifo = gk208_fifo_new, - .gr = gk208_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk110_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk110_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk208_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk110_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk208_fifo_new }, + .gr = { 0x00000001, gk208_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv108_chipset = { .name = "GK208", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk110_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk104_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk20a_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk208_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk110_disp_new, - .dma = gf119_dma_new, - .fifo = gk208_fifo_new, - .gr = gk208_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk110_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk110_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk208_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk110_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk208_fifo_new }, + .gr = { 0x00000001, gk208_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv117_chipset = { .name = "GM107", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gm107_devinit_new, - .fb = gm107_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk104_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gm107_ltc_new, - .mc = gk20a_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gm107_pmu_new, - .therm = gm107_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gm107_ce_new, - .ce[2] = gm107_ce_new, - .disp = gm107_disp_new, - .dma = gf119_dma_new, - .fifo = gm107_fifo_new, - .gr = gm107_gr_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gm107_devinit_new }, + .fb = { 0x00000001, gm107_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk110_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gm107_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gm107_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gm107_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000005, gm107_ce_new }, + .disp = { 0x00000001, gm107_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gm107_fifo_new }, + .gr = { 0x00000001, gm107_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv118_chipset = { .name = "GM108", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gm107_devinit_new, - .fb = gm107_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk104_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gm107_ltc_new, - .mc = gk20a_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gm107_pmu_new, - .therm = gm107_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gm107_ce_new, - .ce[2] = gm107_ce_new, - .disp = gm107_disp_new, - .dma = gf119_dma_new, - .fifo = gm107_fifo_new, - .gr = gm107_gr_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gm107_devinit_new }, + .fb = { 0x00000001, gm107_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk110_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gm107_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gm107_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gm107_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000005, gm107_ce_new }, + .disp = { 0x00000001, gm107_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gm107_fifo_new }, + .gr = { 0x00000001, gm107_gr_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv120_chipset = { .name = "GM200", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fb = gm200_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gm200_ltc_new, - .mc = gk20a_mc_new, - .mmu = gm200_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gm107_pmu_new, - .therm = gm200_therm_new, - .secboot = gm200_secboot_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gm200_ce_new, - .ce[1] = gm200_ce_new, - .ce[2] = gm200_ce_new, - .disp = gm200_disp_new, - .dma = gf119_dma_new, - .fifo = gm200_fifo_new, - .gr = gm200_gr_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gm200_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fb = { 0x00000001, gm200_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gm200_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gm200_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gm200_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gm200_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gm200_ce_new }, + .disp = { 0x00000001, gm200_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gm200_fifo_new }, + .gr = { 0x00000001, gm200_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000003, gm107_nvenc_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv124_chipset = { .name = "GM204", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fb = gm200_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gm200_ltc_new, - .mc = gk20a_mc_new, - .mmu = gm200_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gm107_pmu_new, - .therm = gm200_therm_new, - .secboot = gm200_secboot_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gm200_ce_new, - .ce[1] = gm200_ce_new, - .ce[2] = gm200_ce_new, - .disp = gm200_disp_new, - .dma = gf119_dma_new, - .fifo = gm200_fifo_new, - .gr = gm200_gr_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gm200_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fb = { 0x00000001, gm200_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gm200_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gm200_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gm200_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gm200_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gm200_ce_new }, + .disp = { 0x00000001, gm200_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gm200_fifo_new }, + .gr = { 0x00000001, gm200_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000003, gm107_nvenc_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv126_chipset = { .name = "GM206", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fb = gm200_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gm200_ltc_new, - .mc = gk20a_mc_new, - .mmu = gm200_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gm107_pmu_new, - .therm = gm200_therm_new, - .secboot = gm200_secboot_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gm200_ce_new, - .ce[1] = gm200_ce_new, - .ce[2] = gm200_ce_new, - .disp = gm200_disp_new, - .dma = gf119_dma_new, - .fifo = gm200_fifo_new, - .gr = gm200_gr_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gm200_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fb = { 0x00000001, gm200_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gm200_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gm200_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gm200_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gm200_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gm200_ce_new }, + .disp = { 0x00000001, gm200_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gm200_fifo_new }, + .gr = { 0x00000001, gm200_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv12b_chipset = { .name = "GM20B", - .bar = gm20b_bar_new, - .bus = gf100_bus_new, - .clk = gm20b_clk_new, - .fb = gm20b_fb_new, - .fuse = gm107_fuse_new, - .ibus = gk20a_ibus_new, - .imem = gk20a_instmem_new, - .ltc = gm200_ltc_new, - .mc = gk20a_mc_new, - .mmu = gm20b_mmu_new, - .pmu = gm20b_pmu_new, - .secboot = gm20b_secboot_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[2] = gm200_ce_new, - .volt = gm20b_volt_new, - .dma = gf119_dma_new, - .fifo = gm20b_fifo_new, - .gr = gm20b_gr_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gm20b_acr_new }, + .bar = { 0x00000001, gm20b_bar_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gm20b_clk_new }, + .fb = { 0x00000001, gm20b_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .imem = { 0x00000001, gk20a_instmem_new }, + .ltc = { 0x00000001, gm200_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gm20b_mmu_new }, + .pmu = { 0x00000001, gm20b_pmu_new }, + .privring = { 0x00000001, gk20a_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gm20b_volt_new }, + .ce = { 0x00000004, gm200_ce_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gm20b_fifo_new }, + .gr = { 0x00000001, gm20b_gr_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv130_chipset = { .name = "GP100", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fault = gp100_fault_new, - .fb = gp100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp100_ltc_new, - .mc = gp100_mc_new, - .mmu = gp100_mmu_new, - .therm = gp100_therm_new, - .secboot = gm200_secboot_new, - .pci = gp100_pci_new, - .pmu = gp100_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = gp100_ce_new, - .ce[1] = gp100_ce_new, - .ce[2] = gp100_ce_new, - .ce[3] = gp100_ce_new, - .ce[4] = gp100_ce_new, - .ce[5] = gp100_ce_new, - .dma = gf119_dma_new, - .disp = gp100_disp_new, - .fifo = gp100_fifo_new, - .gr = gp100_gr_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gm200_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fault = { 0x00000001, gp100_fault_new }, + .fb = { 0x00000001, gp100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp100_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gp100_mmu_new }, + .therm = { 0x00000001, gp100_therm_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gm200_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000003f, gp100_ce_new }, + .dma = { 0x00000001, gf119_dma_new }, + .disp = { 0x00000001, gp100_disp_new }, + .fifo = { 0x00000001, gp100_fifo_new }, + .gr = { 0x00000001, gp100_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000007, gm107_nvenc_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv132_chipset = { .name = "GP102", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fault = gp100_fault_new, - .fb = gp102_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = gp100_mc_new, - .mmu = gp100_mmu_new, - .therm = gp100_therm_new, - .secboot = gp102_secboot_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = gp102_ce_new, - .ce[1] = gp102_ce_new, - .ce[2] = gp102_ce_new, - .ce[3] = gp102_ce_new, - .disp = gp102_disp_new, - .dma = gf119_dma_new, - .fifo = gp100_fifo_new, - .gr = gp102_gr_new, - .nvdec[0] = gp102_nvdec_new, - .sec2 = gp102_sec2_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gp102_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fault = { 0x00000001, gp100_fault_new }, + .fb = { 0x00000001, gp102_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gp100_mmu_new }, + .therm = { 0x00000001, gp100_therm_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000000f, gp102_ce_new }, + .disp = { 0x00000001, gp102_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gp100_fifo_new }, + .gr = { 0x00000001, gp102_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000003, gm107_nvenc_new }, + .sec2 = { 0x00000001, gp102_sec2_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv134_chipset = { .name = "GP104", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fault = gp100_fault_new, - .fb = gp102_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = gp100_mc_new, - .mmu = gp100_mmu_new, - .therm = gp100_therm_new, - .secboot = gp102_secboot_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = gp102_ce_new, - .ce[1] = gp102_ce_new, - .ce[2] = gp102_ce_new, - .ce[3] = gp102_ce_new, - .disp = gp102_disp_new, - .dma = gf119_dma_new, - .fifo = gp100_fifo_new, - .gr = gp104_gr_new, - .nvdec[0] = gp102_nvdec_new, - .sec2 = gp102_sec2_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gp102_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fault = { 0x00000001, gp100_fault_new }, + .fb = { 0x00000001, gp102_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gp100_mmu_new }, + .therm = { 0x00000001, gp100_therm_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000000f, gp102_ce_new }, + .disp = { 0x00000001, gp102_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gp100_fifo_new }, + .gr = { 0x00000001, gp104_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000003, gm107_nvenc_new }, + .sec2 = { 0x00000001, gp102_sec2_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv136_chipset = { .name = "GP106", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fault = gp100_fault_new, - .fb = gp102_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = gp100_mc_new, - .mmu = gp100_mmu_new, - .therm = gp100_therm_new, - .secboot = gp102_secboot_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = gp102_ce_new, - .ce[1] = gp102_ce_new, - .ce[2] = gp102_ce_new, - .ce[3] = gp102_ce_new, - .disp = gp102_disp_new, - .dma = gf119_dma_new, - .fifo = gp100_fifo_new, - .gr = gp104_gr_new, - .nvdec[0] = gp102_nvdec_new, - .sec2 = gp102_sec2_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gp102_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fault = { 0x00000001, gp100_fault_new }, + .fb = { 0x00000001, gp102_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gp100_mmu_new }, + .therm = { 0x00000001, gp100_therm_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000000f, gp102_ce_new }, + .disp = { 0x00000001, gp102_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gp100_fifo_new }, + .gr = { 0x00000001, gp104_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sec2 = { 0x00000001, gp102_sec2_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv137_chipset = { .name = "GP107", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fault = gp100_fault_new, - .fb = gp102_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = gp100_mc_new, - .mmu = gp100_mmu_new, - .therm = gp100_therm_new, - .secboot = gp102_secboot_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = gp102_ce_new, - .ce[1] = gp102_ce_new, - .ce[2] = gp102_ce_new, - .ce[3] = gp102_ce_new, - .disp = gp102_disp_new, - .dma = gf119_dma_new, - .fifo = gp100_fifo_new, - .gr = gp107_gr_new, - .nvdec[0] = gp102_nvdec_new, - .sec2 = gp102_sec2_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gp102_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fault = { 0x00000001, gp100_fault_new }, + .fb = { 0x00000001, gp102_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gp100_mmu_new }, + .therm = { 0x00000001, gp100_therm_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000000f, gp102_ce_new }, + .disp = { 0x00000001, gp102_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gp100_fifo_new }, + .gr = { 0x00000001, gp107_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000003, gm107_nvenc_new }, + .sec2 = { 0x00000001, gp102_sec2_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv138_chipset = { .name = "GP108", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fault = gp100_fault_new, - .fb = gp102_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = gp100_mc_new, - .mmu = gp100_mmu_new, - .therm = gp100_therm_new, - .secboot = gp108_secboot_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = gp102_ce_new, - .ce[1] = gp102_ce_new, - .ce[2] = gp102_ce_new, - .ce[3] = gp102_ce_new, - .disp = gp102_disp_new, - .dma = gf119_dma_new, - .fifo = gp100_fifo_new, - .gr = gp107_gr_new, - .nvdec[0] = gp102_nvdec_new, - .sec2 = gp102_sec2_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gp108_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fault = { 0x00000001, gp100_fault_new }, + .fb = { 0x00000001, gp102_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gp100_mmu_new }, + .therm = { 0x00000001, gp100_therm_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000000f, gp102_ce_new }, + .disp = { 0x00000001, gp102_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gp100_fifo_new }, + .gr = { 0x00000001, gp108_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .sec2 = { 0x00000001, gp108_sec2_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv13b_chipset = { .name = "GP10B", - .bar = gm20b_bar_new, - .bus = gf100_bus_new, - .fault = gp100_fault_new, - .fb = gp10b_fb_new, - .fuse = gm107_fuse_new, - .ibus = gp10b_ibus_new, - .imem = gk20a_instmem_new, - .ltc = gp102_ltc_new, - .mc = gp10b_mc_new, - .mmu = gp10b_mmu_new, - .secboot = gp10b_secboot_new, - .pmu = gm20b_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[2] = gp102_ce_new, - .dma = gf119_dma_new, - .fifo = gp10b_fifo_new, - .gr = gp10b_gr_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gp10b_acr_new }, + .bar = { 0x00000001, gm20b_bar_new }, + .bus = { 0x00000001, gf100_bus_new }, + .fault = { 0x00000001, gp10b_fault_new }, + .fb = { 0x00000001, gp10b_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .imem = { 0x00000001, gk20a_instmem_new }, + .ltc = { 0x00000001, gp10b_ltc_new }, + .mc = { 0x00000001, gp10b_mc_new }, + .mmu = { 0x00000001, gp10b_mmu_new }, + .pmu = { 0x00000001, gp10b_pmu_new }, + .privring = { 0x00000001, gp10b_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x00000001, gp100_ce_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gp10b_fifo_new }, + .gr = { 0x00000001, gp10b_gr_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv140_chipset = { .name = "GV100", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gv100_devinit_new, - .fault = gv100_fault_new, - .fb = gv100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .gsp = gv100_gsp_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = gp100_mc_new, - .mmu = gv100_mmu_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .secboot = gp108_secboot_new, - .therm = gp100_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .disp = gv100_disp_new, - .ce[0] = gv100_ce_new, - .ce[1] = gv100_ce_new, - .ce[2] = gv100_ce_new, - .ce[3] = gv100_ce_new, - .ce[4] = gv100_ce_new, - .ce[5] = gv100_ce_new, - .ce[6] = gv100_ce_new, - .ce[7] = gv100_ce_new, - .ce[8] = gv100_ce_new, - .dma = gv100_dma_new, - .fifo = gv100_fifo_new, - .gr = gv100_gr_new, - .nvdec[0] = gp102_nvdec_new, - .sec2 = gp102_sec2_new, + .acr = { 0x00000001, gp108_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gv100_devinit_new }, + .fault = { 0x00000001, gv100_fault_new }, + .fb = { 0x00000001, gv100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .gsp = { 0x00000001, gv100_gsp_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gv100_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gp100_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x000001ff, gv100_ce_new }, + .disp = { 0x00000001, gv100_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, gv100_fifo_new }, + .gr = { 0x00000001, gv100_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000007, gm107_nvenc_new }, + .sec2 = { 0x00000001, gp108_sec2_new }, }; static const struct nvkm_device_chip nv162_chipset = { .name = "TU102", - .bar = tu102_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = tu102_devinit_new, - .fault = tu102_fault_new, - .fb = gv100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .gsp = gv100_gsp_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = tu102_mc_new, - .mmu = tu102_mmu_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .therm = gp100_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = tu102_ce_new, - .ce[1] = tu102_ce_new, - .ce[2] = tu102_ce_new, - .ce[3] = tu102_ce_new, - .ce[4] = tu102_ce_new, - .disp = tu102_disp_new, - .dma = gv100_dma_new, - .fifo = tu102_fifo_new, - .nvdec[0] = gp102_nvdec_new, - .sec2 = tu102_sec2_new, + .acr = { 0x00000001, tu102_acr_new }, + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, tu102_devinit_new }, + .fault = { 0x00000001, tu102_fault_new }, + .fb = { 0x00000001, gv100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .gsp = { 0x00000001, gv100_gsp_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, tu102_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gp100_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000001f, tu102_ce_new }, + .disp = { 0x00000001, tu102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, tu102_fifo_new }, + .gr = { 0x00000001, tu102_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sec2 = { 0x00000001, tu102_sec2_new }, }; static const struct nvkm_device_chip nv164_chipset = { .name = "TU104", - .bar = tu102_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = tu102_devinit_new, - .fault = tu102_fault_new, - .fb = gv100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .gsp = gv100_gsp_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = tu102_mc_new, - .mmu = tu102_mmu_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .therm = gp100_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = tu102_ce_new, - .ce[1] = tu102_ce_new, - .ce[2] = tu102_ce_new, - .ce[3] = tu102_ce_new, - .ce[4] = tu102_ce_new, - .disp = tu102_disp_new, - .dma = gv100_dma_new, - .fifo = tu102_fifo_new, - .nvdec[0] = gp102_nvdec_new, - .sec2 = tu102_sec2_new, + .acr = { 0x00000001, tu102_acr_new }, + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, tu102_devinit_new }, + .fault = { 0x00000001, tu102_fault_new }, + .fb = { 0x00000001, gv100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .gsp = { 0x00000001, gv100_gsp_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, tu102_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gp100_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000001f, tu102_ce_new }, + .disp = { 0x00000001, tu102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, tu102_fifo_new }, + .gr = { 0x00000001, tu102_gr_new }, + .nvdec = { 0x00000003, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sec2 = { 0x00000001, tu102_sec2_new }, }; static const struct nvkm_device_chip nv166_chipset = { .name = "TU106", - .bar = tu102_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = tu102_devinit_new, - .fault = tu102_fault_new, - .fb = gv100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .gsp = gv100_gsp_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = tu102_mc_new, - .mmu = tu102_mmu_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .therm = gp100_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = tu102_ce_new, - .ce[1] = tu102_ce_new, - .ce[2] = tu102_ce_new, - .ce[3] = tu102_ce_new, - .ce[4] = tu102_ce_new, - .disp = tu102_disp_new, - .dma = gv100_dma_new, - .fifo = tu102_fifo_new, - .nvdec[0] = gp102_nvdec_new, - .sec2 = tu102_sec2_new, + .acr = { 0x00000001, tu102_acr_new }, + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, tu102_devinit_new }, + .fault = { 0x00000001, tu102_fault_new }, + .fb = { 0x00000001, gv100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .gsp = { 0x00000001, gv100_gsp_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, tu102_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gp100_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000001f, tu102_ce_new }, + .disp = { 0x00000001, tu102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, tu102_fifo_new }, + .gr = { 0x00000001, tu102_gr_new }, + .nvdec = { 0x00000007, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sec2 = { 0x00000001, tu102_sec2_new }, }; static const struct nvkm_device_chip nv167_chipset = { .name = "TU117", - .bar = tu102_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = tu102_devinit_new, - .fault = tu102_fault_new, - .fb = gv100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .gsp = gv100_gsp_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = tu102_mc_new, - .mmu = tu102_mmu_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .therm = gp100_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = tu102_ce_new, - .ce[1] = tu102_ce_new, - .ce[2] = tu102_ce_new, - .ce[3] = tu102_ce_new, - .ce[4] = tu102_ce_new, - .disp = tu102_disp_new, - .dma = gv100_dma_new, - .fifo = tu102_fifo_new, - .nvdec[0] = gp102_nvdec_new, - .sec2 = tu102_sec2_new, + .acr = { 0x00000001, tu102_acr_new }, + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, tu102_devinit_new }, + .fault = { 0x00000001, tu102_fault_new }, + .fb = { 0x00000001, gv100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .gsp = { 0x00000001, gv100_gsp_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, tu102_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gp100_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000001f, tu102_ce_new }, + .disp = { 0x00000001, tu102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, tu102_fifo_new }, + .gr = { 0x00000001, tu102_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sec2 = { 0x00000001, tu102_sec2_new }, }; static const struct nvkm_device_chip nv168_chipset = { .name = "TU116", - .bar = tu102_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = tu102_devinit_new, - .fault = tu102_fault_new, - .fb = gv100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .gsp = gv100_gsp_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = tu102_mc_new, - .mmu = tu102_mmu_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .therm = gp100_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = tu102_ce_new, - .ce[1] = tu102_ce_new, - .ce[2] = tu102_ce_new, - .ce[3] = tu102_ce_new, - .ce[4] = tu102_ce_new, - .disp = tu102_disp_new, - .dma = gv100_dma_new, - .fifo = tu102_fifo_new, - .nvdec[0] = gp102_nvdec_new, - .sec2 = tu102_sec2_new, + .acr = { 0x00000001, tu102_acr_new }, + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, tu102_devinit_new }, + .fault = { 0x00000001, tu102_fault_new }, + .fb = { 0x00000001, gv100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .gsp = { 0x00000001, gv100_gsp_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, tu102_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gp100_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000001f, tu102_ce_new }, + .disp = { 0x00000001, tu102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, tu102_fifo_new }, + .gr = { 0x00000001, tu102_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sec2 = { 0x00000001, tu102_sec2_new }, +}; + +static const struct nvkm_device_chip +nv170_chipset = { + .name = "GA100", + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .devinit = { 0x00000001, ga100_devinit_new }, + .fb = { 0x00000001, ga100_fb_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, ga100_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, ga100_top_new }, +}; + +static const struct nvkm_device_chip +nv172_chipset = { + .name = "GA102", + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .devinit = { 0x00000001, ga100_devinit_new }, + .fb = { 0x00000001, ga102_fb_new }, + .gpio = { 0x00000001, ga102_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, ga100_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, ga100_top_new }, + .disp = { 0x00000001, ga102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, ga102_fifo_new }, +}; + +static const struct nvkm_device_chip +nv174_chipset = { + .name = "GA104", + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .devinit = { 0x00000001, ga100_devinit_new }, + .fb = { 0x00000001, ga102_fb_new }, + .gpio = { 0x00000001, ga102_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, ga100_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, ga100_top_new }, + .disp = { 0x00000001, ga102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, ga102_fifo_new }, +}; + +static const struct nvkm_device_chip +nv176_chipset = { + .name = "GA106", + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .devinit = { 0x00000001, ga100_devinit_new }, + .fb = { 0x00000001, ga102_fb_new }, + .gpio = { 0x00000001, ga102_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, ga100_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, ga100_top_new }, + .disp = { 0x00000001, ga102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, ga102_fifo_new }, +}; + +static const struct nvkm_device_chip +nv177_chipset = { + .name = "GA107", + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .devinit = { 0x00000001, ga100_devinit_new }, + .fb = { 0x00000001, ga102_fb_new }, + .gpio = { 0x00000001, ga102_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, ga100_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, ga100_top_new }, + .disp = { 0x00000001, ga102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, ga102_fifo_new }, }; static int @@ -2629,97 +2687,24 @@ nvkm_device_event_func = { }; struct nvkm_subdev * -nvkm_device_subdev(struct nvkm_device *device, int index) +nvkm_device_subdev(struct nvkm_device *device, int type, int inst) { - struct nvkm_engine *engine; - - if (device->disable_mask & (1ULL << index)) - return NULL; - - switch (index) { -#define _(n,p,m) case NVKM_SUBDEV_##n: if (p) return (m); break - _(BAR , device->bar , &device->bar->subdev); - _(VBIOS , device->bios , &device->bios->subdev); - _(BUS , device->bus , &device->bus->subdev); - _(CLK , device->clk , &device->clk->subdev); - _(DEVINIT , device->devinit , &device->devinit->subdev); - _(FAULT , device->fault , &device->fault->subdev); - _(FB , device->fb , &device->fb->subdev); - _(FUSE , device->fuse , &device->fuse->subdev); - _(GPIO , device->gpio , &device->gpio->subdev); - _(GSP , device->gsp , &device->gsp->subdev); - _(I2C , device->i2c , &device->i2c->subdev); - _(IBUS , device->ibus , device->ibus); - _(ICCSENSE, device->iccsense, &device->iccsense->subdev); - _(INSTMEM , device->imem , &device->imem->subdev); - _(LTC , device->ltc , &device->ltc->subdev); - _(MC , device->mc , &device->mc->subdev); - _(MMU , device->mmu , &device->mmu->subdev); - _(MXM , device->mxm , device->mxm); - _(PCI , device->pci , &device->pci->subdev); - _(PMU , device->pmu , &device->pmu->subdev); - _(SECBOOT , device->secboot , &device->secboot->subdev); - _(THERM , device->therm , &device->therm->subdev); - _(TIMER , device->timer , &device->timer->subdev); - _(TOP , device->top , &device->top->subdev); - _(VOLT , device->volt , &device->volt->subdev); -#undef _ - default: - engine = nvkm_device_engine(device, index); - if (engine) - return &engine->subdev; - break; + struct nvkm_subdev *subdev; + + list_for_each_entry(subdev, &device->subdev, head) { + if (subdev->type == type && subdev->inst == inst) + return subdev; } + return NULL; } struct nvkm_engine * -nvkm_device_engine(struct nvkm_device *device, int index) +nvkm_device_engine(struct nvkm_device *device, int type, int inst) { - if (device->disable_mask & (1ULL << index)) - return NULL; - - switch (index) { -#define _(n,p,m) case NVKM_ENGINE_##n: if (p) return (m); break - _(BSP , device->bsp , device->bsp); - _(CE0 , device->ce[0] , device->ce[0]); - _(CE1 , device->ce[1] , device->ce[1]); - _(CE2 , device->ce[2] , device->ce[2]); - _(CE3 , device->ce[3] , device->ce[3]); - _(CE4 , device->ce[4] , device->ce[4]); - _(CE5 , device->ce[5] , device->ce[5]); - _(CE6 , device->ce[6] , device->ce[6]); - _(CE7 , device->ce[7] , device->ce[7]); - _(CE8 , device->ce[8] , device->ce[8]); - _(CIPHER , device->cipher , device->cipher); - _(DISP , device->disp , &device->disp->engine); - _(DMAOBJ , device->dma , &device->dma->engine); - _(FIFO , device->fifo , &device->fifo->engine); - _(GR , device->gr , &device->gr->engine); - _(IFB , device->ifb , device->ifb); - _(ME , device->me , device->me); - _(MPEG , device->mpeg , device->mpeg); - _(MSENC , device->msenc , device->msenc); - _(MSPDEC , device->mspdec , device->mspdec); - _(MSPPP , device->msppp , device->msppp); - _(MSVLD , device->msvld , device->msvld); - _(NVENC0 , device->nvenc[0], device->nvenc[0]); - _(NVENC1 , device->nvenc[1], device->nvenc[1]); - _(NVENC2 , device->nvenc[2], device->nvenc[2]); - _(NVDEC0 , device->nvdec[0], &device->nvdec[0]->engine); - _(NVDEC1 , device->nvdec[1], &device->nvdec[1]->engine); - _(NVDEC2 , device->nvdec[2], &device->nvdec[2]->engine); - _(PM , device->pm , &device->pm->engine); - _(SEC , device->sec , device->sec); - _(SEC2 , device->sec2 , &device->sec2->engine); - _(SW , device->sw , &device->sw->engine); - _(VIC , device->vic , device->vic); - _(VP , device->vp , device->vp); -#undef _ - default: - WARN_ON(1); - break; - } + struct nvkm_subdev *subdev = nvkm_device_subdev(device, type, inst); + if (subdev && subdev->func == &nvkm_engine) + return container_of(subdev, struct nvkm_engine, subdev); return NULL; } @@ -2728,7 +2713,7 @@ nvkm_device_fini(struct nvkm_device *device, bool suspend) { const char *action = suspend ? "suspend" : "fini"; struct nvkm_subdev *subdev; - int ret, i; + int ret; s64 time; nvdev_trace(device, "%s running...\n", action); @@ -2736,12 +2721,10 @@ nvkm_device_fini(struct nvkm_device *device, bool suspend) nvkm_acpi_fini(device); - for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { - if ((subdev = nvkm_device_subdev(device, i))) { - ret = nvkm_subdev_fini(subdev, suspend); - if (ret && suspend) - goto fail; - } + list_for_each_entry_reverse(subdev, &device->subdev, head) { + ret = nvkm_subdev_fini(subdev, suspend); + if (ret && suspend) + goto fail; } nvkm_therm_clkgate_fini(device->therm, suspend); @@ -2754,13 +2737,11 @@ nvkm_device_fini(struct nvkm_device *device, bool suspend) return 0; fail: - do { - if ((subdev = nvkm_device_subdev(device, i))) { - int rret = nvkm_subdev_init(subdev); - if (rret) - nvkm_fatal(subdev, "failed restart, %d\n", ret); - } - } while (++i < NVKM_SUBDEV_NR); + list_for_each_entry_from(subdev, &device->subdev, head) { + int rret = nvkm_subdev_init(subdev); + if (rret) + nvkm_fatal(subdev, "failed restart, %d\n", ret); + } nvdev_trace(device, "%s failed with %d\n", action, ret); return ret; @@ -2770,7 +2751,7 @@ static int nvkm_device_preinit(struct nvkm_device *device) { struct nvkm_subdev *subdev; - int ret, i; + int ret; s64 time; nvdev_trace(device, "preinit running...\n"); @@ -2782,15 +2763,13 @@ nvkm_device_preinit(struct nvkm_device *device) goto fail; } - for (i = 0; i < NVKM_SUBDEV_NR; i++) { - if ((subdev = nvkm_device_subdev(device, i))) { - ret = nvkm_subdev_preinit(subdev); - if (ret) - goto fail; - } + list_for_each_entry(subdev, &device->subdev, head) { + ret = nvkm_subdev_preinit(subdev); + if (ret) + goto fail; } - ret = nvkm_devinit_post(device->devinit, &device->disable_mask); + ret = nvkm_devinit_post(device->devinit); if (ret) goto fail; @@ -2807,7 +2786,7 @@ int nvkm_device_init(struct nvkm_device *device) { struct nvkm_subdev *subdev; - int ret, i; + int ret; s64 time; ret = nvkm_device_preinit(device); @@ -2825,12 +2804,10 @@ nvkm_device_init(struct nvkm_device *device) goto fail; } - for (i = 0; i < NVKM_SUBDEV_NR; i++) { - if ((subdev = nvkm_device_subdev(device, i))) { - ret = nvkm_subdev_init(subdev); - if (ret) - goto fail_subdev; - } + list_for_each_entry(subdev, &device->subdev, head) { + ret = nvkm_subdev_init(subdev); + if (ret) + goto fail_subdev; } nvkm_acpi_init(device); @@ -2841,11 +2818,8 @@ nvkm_device_init(struct nvkm_device *device) return 0; fail_subdev: - do { - if ((subdev = nvkm_device_subdev(device, i))) - nvkm_subdev_fini(subdev, false); - } while (--i >= 0); - + list_for_each_entry_from(subdev, &device->subdev, head) + nvkm_subdev_fini(subdev, false); fail: nvkm_device_fini(device, false); @@ -2857,15 +2831,12 @@ void nvkm_device_del(struct nvkm_device **pdevice) { struct nvkm_device *device = *pdevice; - int i; + struct nvkm_subdev *subdev, *subtmp; if (device) { mutex_lock(&nv_devices_mutex); - device->disable_mask = 0; - for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { - struct nvkm_subdev *subdev = - nvkm_device_subdev(device, i); + + list_for_each_entry_safe_reverse(subdev, subtmp, &device->subdev, head) nvkm_subdev_del(&subdev); - } nvkm_event_fini(&device->event); @@ -2882,6 +2853,37 @@ nvkm_device_del(struct nvkm_device **pdevice) } } +/* returns true if the GPU is in the CPU native byte order */ +static inline bool +nvkm_device_endianness(struct nvkm_device *device) +{ +#ifdef __BIG_ENDIAN + const bool big_endian = true; +#else + const bool big_endian = false; +#endif + + /* Read NV_PMC_BOOT_1, and assume non-functional endian switch if it + * doesn't contain the expected values. + */ + u32 pmc_boot_1 = nvkm_rd32(device, 0x000004); + if (pmc_boot_1 && pmc_boot_1 != 0x01000001) + return !big_endian; /* Assume GPU is LE in this case. */ + + /* 0 means LE and 0x01000001 means BE GPU. Condition is true when + * GPU/CPU endianness don't match. + */ + if (big_endian == !pmc_boot_1) { + nvkm_wr32(device, 0x000004, 0x01000001); + nvkm_rd32(device, 0x000000); + if (nvkm_rd32(device, 0x000004) != (big_endian ? 0x01000001 : 0x00000000)) + return !big_endian; /* Assume GPU is LE on any unexpected read-back. */ + } + + /* CPU/GPU endianness should (hopefully) match. */ + return true; +} + int nvkm_device_ctor(const struct nvkm_device_func *func, const struct nvkm_device_quirk *quirk, @@ -2892,9 +2894,8 @@ nvkm_device_ctor(const struct nvkm_device_func *func, { struct nvkm_subdev *subdev; u64 mmio_base, mmio_size; - u32 boot0, strap; - void __iomem *map; - int ret = -EEXIST, i; + u32 boot0, boot1, strap; + int ret = -EEXIST, j; unsigned chipset; mutex_lock(&nv_devices_mutex); @@ -2911,6 +2912,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, device->name = name; list_add_tail(&device->head, &nv_devices); device->debug = nvkm_dbgopt(device->dbgopt, "device"); + INIT_LIST_HEAD(&device->subdev); ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); if (ret) @@ -2919,26 +2921,26 @@ nvkm_device_ctor(const struct nvkm_device_func *func, mmio_base = device->func->resource_addr(device, 0); mmio_size = device->func->resource_size(device, 0); - /* identify the chipset, and determine classes of subdev/engines */ - if (detect) { - map = ioremap(mmio_base, 0x102000); - if (ret = -ENOMEM, map == NULL) + if (detect || mmio) { + device->pri = ioremap(mmio_base, mmio_size); + if (device->pri == NULL) { + nvdev_error(device, "unable to map PRI\n"); + ret = -ENOMEM; goto done; + } + } + /* identify the chipset, and determine classes of subdev/engines */ + if (detect) { /* switch mmio to cpu's native endianness */ -#ifndef __BIG_ENDIAN - if (ioread32_native(map + 0x000004) != 0x00000000) { -#else - if (ioread32_native(map + 0x000004) == 0x00000000) { -#endif - iowrite32_native(0x01000001, map + 0x000004); - ioread32_native(map); + if (!nvkm_device_endianness(device)) { + nvdev_error(device, + "Couldn't switch GPU to CPUs endianness\n"); + ret = -ENOSYS; + goto done; } - /* read boot0 and strapping information */ - boot0 = ioread32_native(map + 0x000000); - strap = ioread32_native(map + 0x101000); - iounmap(map); + boot0 = nvkm_rd32(device, 0x000000); /* chipset can be overridden for devel/testing purposes */ chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0); @@ -2991,6 +2993,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, case 0x130: device->card_type = GP100; break; case 0x140: device->card_type = GV100; break; case 0x160: device->card_type = TU100; break; + case 0x170: device->card_type = GA100; break; default: break; } @@ -3088,14 +3091,41 @@ nvkm_device_ctor(const struct nvkm_device_func *func, case 0x166: device->chip = &nv166_chipset; break; case 0x167: device->chip = &nv167_chipset; break; case 0x168: device->chip = &nv168_chipset; break; + case 0x172: device->chip = &nv172_chipset; break; + case 0x174: device->chip = &nv174_chipset; break; + case 0x176: device->chip = &nv176_chipset; break; + case 0x177: device->chip = &nv177_chipset; break; default: - nvdev_error(device, "unknown chipset (%08x)\n", boot0); - goto done; + if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) { + switch (device->chipset) { + case 0x170: device->chip = &nv170_chipset; break; + default: + break; + } + } + + if (!device->chip) { + nvdev_error(device, "unknown chipset (%08x)\n", boot0); + ret = -ENODEV; + goto done; + } + break; } nvdev_info(device, "NVIDIA %s (%08x)\n", device->chip->name, boot0); + /* vGPU detection */ + boot1 = nvkm_rd32(device, 0x0000004); + if (device->card_type >= TU100 && (boot1 & 0x00030000)) { + nvdev_info(device, "vGPUs are not supported\n"); + ret = -ENODEV; + goto done; + } + + /* read strapping information */ + strap = nvkm_rd32(device, 0x101000); + /* determine frequency of timing crystal */ if ( device->card_type <= NV_10 || device->chipset < 0x17 || (device->chipset >= 0x20 && device->chipset < 0x25)) @@ -3116,102 +3146,54 @@ nvkm_device_ctor(const struct nvkm_device_func *func, if (!device->name) device->name = device->chip->name; - if (mmio) { - device->pri = ioremap(mmio_base, mmio_size); - if (!device->pri) { - nvdev_error(device, "unable to map PRI\n"); - ret = -ENOMEM; - goto done; - } - } - mutex_init(&device->mutex); - for (i = 0; i < NVKM_SUBDEV_NR; i++) { -#define _(s,m) case s: \ - if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \ - ret = device->chip->m(device, (s), &device->m); \ - if (ret) { \ - subdev = nvkm_device_subdev(device, (s)); \ - nvkm_subdev_del(&subdev); \ - device->m = NULL; \ - if (ret != -ENODEV) { \ - nvdev_error(device, "%s ctor failed, %d\n", \ - nvkm_subdev_name[s], ret); \ - goto done; \ - } \ - } \ - } \ - break - switch (i) { - _(NVKM_SUBDEV_BAR , bar); - _(NVKM_SUBDEV_VBIOS , bios); - _(NVKM_SUBDEV_BUS , bus); - _(NVKM_SUBDEV_CLK , clk); - _(NVKM_SUBDEV_DEVINIT , devinit); - _(NVKM_SUBDEV_FAULT , fault); - _(NVKM_SUBDEV_FB , fb); - _(NVKM_SUBDEV_FUSE , fuse); - _(NVKM_SUBDEV_GPIO , gpio); - _(NVKM_SUBDEV_GSP , gsp); - _(NVKM_SUBDEV_I2C , i2c); - _(NVKM_SUBDEV_IBUS , ibus); - _(NVKM_SUBDEV_ICCSENSE, iccsense); - _(NVKM_SUBDEV_INSTMEM , imem); - _(NVKM_SUBDEV_LTC , ltc); - _(NVKM_SUBDEV_MC , mc); - _(NVKM_SUBDEV_MMU , mmu); - _(NVKM_SUBDEV_MXM , mxm); - _(NVKM_SUBDEV_PCI , pci); - _(NVKM_SUBDEV_PMU , pmu); - _(NVKM_SUBDEV_SECBOOT , secboot); - _(NVKM_SUBDEV_THERM , therm); - _(NVKM_SUBDEV_TIMER , timer); - _(NVKM_SUBDEV_TOP , top); - _(NVKM_SUBDEV_VOLT , volt); - _(NVKM_ENGINE_BSP , bsp); - _(NVKM_ENGINE_CE0 , ce[0]); - _(NVKM_ENGINE_CE1 , ce[1]); - _(NVKM_ENGINE_CE2 , ce[2]); - _(NVKM_ENGINE_CE3 , ce[3]); - _(NVKM_ENGINE_CE4 , ce[4]); - _(NVKM_ENGINE_CE5 , ce[5]); - _(NVKM_ENGINE_CE6 , ce[6]); - _(NVKM_ENGINE_CE7 , ce[7]); - _(NVKM_ENGINE_CE8 , ce[8]); - _(NVKM_ENGINE_CIPHER , cipher); - _(NVKM_ENGINE_DISP , disp); - _(NVKM_ENGINE_DMAOBJ , dma); - _(NVKM_ENGINE_FIFO , fifo); - _(NVKM_ENGINE_GR , gr); - _(NVKM_ENGINE_IFB , ifb); - _(NVKM_ENGINE_ME , me); - _(NVKM_ENGINE_MPEG , mpeg); - _(NVKM_ENGINE_MSENC , msenc); - _(NVKM_ENGINE_MSPDEC , mspdec); - _(NVKM_ENGINE_MSPPP , msppp); - _(NVKM_ENGINE_MSVLD , msvld); - _(NVKM_ENGINE_NVENC0 , nvenc[0]); - _(NVKM_ENGINE_NVENC1 , nvenc[1]); - _(NVKM_ENGINE_NVENC2 , nvenc[2]); - _(NVKM_ENGINE_NVDEC0 , nvdec[0]); - _(NVKM_ENGINE_NVDEC1 , nvdec[1]); - _(NVKM_ENGINE_NVDEC2 , nvdec[2]); - _(NVKM_ENGINE_PM , pm); - _(NVKM_ENGINE_SEC , sec); - _(NVKM_ENGINE_SEC2 , sec2); - _(NVKM_ENGINE_SW , sw); - _(NVKM_ENGINE_VIC , vic); - _(NVKM_ENGINE_VP , vp); - default: - WARN_ON(1); - continue; - } -#undef _ +#define NVKM_LAYOUT_ONCE(type,data,ptr) \ + if (device->chip->ptr.inst && (subdev_mask & (BIT_ULL(type)))) { \ + WARN_ON(device->chip->ptr.inst != 0x00000001); \ + ret = device->chip->ptr.ctor(device, (type), -1, &device->ptr); \ + subdev = nvkm_device_subdev(device, (type), 0); \ + if (ret) { \ + nvkm_subdev_del(&subdev); \ + device->ptr = NULL; \ + if (ret != -ENODEV) { \ + nvdev_error(device, "%s ctor failed: %d\n", \ + nvkm_subdev_type[(type)], ret); \ + goto done; \ + } \ + } else { \ + subdev->pself = (void **)&device->ptr; \ + } \ + } +#define NVKM_LAYOUT_INST(type,data,ptr,cnt) \ + WARN_ON(device->chip->ptr.inst & ~((1 << ARRAY_SIZE(device->ptr)) - 1)); \ + for (j = 0; device->chip->ptr.inst && j < ARRAY_SIZE(device->ptr); j++) { \ + if ((device->chip->ptr.inst & BIT(j)) && (subdev_mask & BIT_ULL(type))) { \ + ret = device->chip->ptr.ctor(device, (type), (j), &device->ptr[j]); \ + subdev = nvkm_device_subdev(device, (type), (j)); \ + if (ret) { \ + nvkm_subdev_del(&subdev); \ + device->ptr[j] = NULL; \ + if (ret != -ENODEV) { \ + nvdev_error(device, "%s%d ctor failed: %d\n", \ + nvkm_subdev_type[(type)], (j), ret); \ + goto done; \ + } \ + } else { \ + subdev->pself = (void **)&device->ptr[j]; \ + } \ + } \ } +#include <core/layout.h> +#undef NVKM_LAYOUT_INST +#undef NVKM_LAYOUT_ONCE ret = 0; done: + if (device->pri && (!mmio || ret)) { + iounmap(device->pri); + device->pri = NULL; + } mutex_unlock(&nv_devices_mutex); return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c index b0ece71aefde..ce774579c89d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c @@ -57,7 +57,7 @@ nvkm_control_mthd_pstate_info(struct nvkm_control *ctrl, void *data, u32 size) args->v0.count = 0; args->v0.ustate_ac = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE; args->v0.ustate_dc = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE; - args->v0.pwrsrc = -ENOSYS; + args->v0.pwrsrc = -ENODEV; args->v0.pstate = NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h index d8be2f77ac66..93949b3c7214 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h @@ -3,6 +3,7 @@ #define __NVKM_DEVICE_PRIV_H__ #include <core/device.h> +#include <subdev/acr.h> #include <subdev/bar.h> #include <subdev/bios.h> #include <subdev/bus.h> @@ -14,7 +15,6 @@ #include <subdev/gpio.h> #include <subdev/gsp.h> #include <subdev/i2c.h> -#include <subdev/ibus.h> #include <subdev/iccsense.h> #include <subdev/instmem.h> #include <subdev/ltc.h> @@ -23,11 +23,11 @@ #include <subdev/mxm.h> #include <subdev/pci.h> #include <subdev/pmu.h> +#include <subdev/privring.h> #include <subdev/therm.h> #include <subdev/timer.h> #include <subdev/top.h> #include <subdev/volt.h> -#include <subdev/secboot.h> #include <engine/bsp.h> #include <engine/ce.h> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c index 0e372a190d3f..2ed528c065fa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c @@ -52,18 +52,18 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev) clk_set_rate(tdev->clk_pwr, 204000000); udelay(10); - reset_control_assert(tdev->rst); - udelay(10); - if (!tdev->pdev->dev.pm_domain) { + reset_control_assert(tdev->rst); + udelay(10); + ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D); if (ret) goto err_clamp; udelay(10); - } - reset_control_deassert(tdev->rst); - udelay(10); + reset_control_deassert(tdev->rst); + udelay(10); + } return 0; @@ -123,7 +123,7 @@ nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *tdev) mutex_init(&tdev->iommu.mutex); - if (iommu_present(&platform_bus_type)) { + if (device_iommu_mapped(dev)) { tdev->iommu.domain = iommu_domain_alloc(&platform_bus_type); if (!tdev->iommu.domain) goto error; @@ -133,7 +133,7 @@ nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *tdev) * or equal to the system's PAGE_SIZE, with a preference if * both are equal. */ - pgsize_bitmap = tdev->iommu.domain->ops->pgsize_bitmap; + pgsize_bitmap = tdev->iommu.domain->pgsize_bitmap; if (pgsize_bitmap & PAGE_SIZE) { tdev->iommu.pgshift = PAGE_SHIFT; } else { @@ -279,6 +279,7 @@ nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func, struct nvkm_device **pdevice) { struct nvkm_device_tegra *tdev; + unsigned long rate; int ret; if (!(tdev = kzalloc(sizeof(*tdev), GFP_KERNEL))) @@ -307,6 +308,17 @@ nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func, goto free; } + rate = clk_get_rate(tdev->clk); + if (rate == 0) { + ret = clk_set_rate(tdev->clk, ULONG_MAX); + if (ret < 0) + goto free; + + rate = clk_get_rate(tdev->clk); + + dev_dbg(&pdev->dev, "GPU clock set to %lu\n", rate); + } + if (func->require_ref_clk) tdev->clk_ref = devm_clk_get(&pdev->dev, "ref"); if (IS_ERR(tdev->clk_ref)) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c index 03c6d9aef075..113ddc103ac2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c @@ -43,15 +43,15 @@ static int nvkm_udevice_info_subdev(struct nvkm_device *device, u64 mthd, u64 *data) { struct nvkm_subdev *subdev; - enum nvkm_devidx subidx; + enum nvkm_subdev_type type; switch (mthd & NV_DEVICE_INFO_UNIT) { - case NV_DEVICE_FIFO(0): subidx = NVKM_ENGINE_FIFO; break; + case NV_DEVICE_HOST(0): type = NVKM_ENGINE_FIFO; break; default: return -EINVAL; } - subdev = nvkm_device_subdev(device, subidx); + subdev = nvkm_device_subdev(device, type, 0); if (subdev) return nvkm_subdev_info(subdev, mthd, data); return -ENODEV; @@ -66,37 +66,7 @@ nvkm_udevice_info_v1(struct nvkm_device *device, args->mthd = NV_DEVICE_INFO_INVALID; return; } - - switch (args->mthd) { -#define ENGINE__(A,B,C) NV_DEVICE_INFO_ENGINE_##A: { int _i; \ - for (_i = (B), args->data = 0ULL; _i <= (C); _i++) { \ - if (nvkm_device_engine(device, _i)) \ - args->data |= BIT_ULL(_i); \ - } \ -} -#define ENGINE_A(A) ENGINE__(A, NVKM_ENGINE_##A , NVKM_ENGINE_##A) -#define ENGINE_B(A) ENGINE__(A, NVKM_ENGINE_##A##0, NVKM_ENGINE_##A##_LAST) - case ENGINE_A(SW ); break; - case ENGINE_A(GR ); break; - case ENGINE_A(MPEG ); break; - case ENGINE_A(ME ); break; - case ENGINE_A(CIPHER); break; - case ENGINE_A(BSP ); break; - case ENGINE_A(VP ); break; - case ENGINE_B(CE ); break; - case ENGINE_A(SEC ); break; - case ENGINE_A(MSVLD ); break; - case ENGINE_A(MSPDEC); break; - case ENGINE_A(MSPPP ); break; - case ENGINE_A(MSENC ); break; - case ENGINE_A(VIC ); break; - case ENGINE_A(SEC2 ); break; - case ENGINE_B(NVDEC ); break; - case ENGINE_B(NVENC ); break; - default: - args->mthd = NV_DEVICE_INFO_INVALID; - break; - } + args->mthd = NV_DEVICE_INFO_INVALID; } static int @@ -176,6 +146,7 @@ nvkm_udevice_info(struct nvkm_udevice *udev, void *data, u32 size) case GP100: args->v0.family = NV_DEVICE_INFO_V0_PASCAL; break; case GV100: args->v0.family = NV_DEVICE_INFO_V0_VOLTA; break; case TU100: args->v0.family = NV_DEVICE_INFO_V0_TURING; break; + case GA100: args->v0.family = NV_DEVICE_INFO_V0_AMPERE; break; default: args->v0.family = 0; break; @@ -190,8 +161,8 @@ nvkm_udevice_info(struct nvkm_udevice *udev, void *data, u32 size) if (imem && args->v0.ram_size > 0) args->v0.ram_user = args->v0.ram_user - imem->reserved; - strncpy(args->v0.chip, device->chip->name, sizeof(args->v0.chip)); - strncpy(args->v0.name, device->name, sizeof(args->v0.name)); + snprintf(args->v0.chip, sizeof(args->v0.chip), "%s", device->chip->name); + snprintf(args->v0.name, sizeof(args->v0.name), "%s", device->name); return 0; } @@ -356,7 +327,7 @@ nvkm_udevice_child_get(struct nvkm_object *object, int index, int i; for (; i = __ffs64(mask), mask && !sclass; mask &= ~(1ULL << i)) { - if (!(engine = nvkm_device_engine(device, i)) || + if (!(engine = nvkm_device_engine(device, i, 0)) || !(engine->func->base.sclass)) continue; oclass->engine = engine; @@ -426,7 +397,7 @@ nvkm_udevice_new(const struct nvkm_oclass *oclass, void *data, u32 size, return ret; /* give priviledged clients register access */ - if (client->super) + if (args->v0.priv) func = &nvkm_udevice_super; else func = &nvkm_udevice; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild index 0d584d0da59c..b03f043efe26 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild @@ -17,6 +17,7 @@ nvkm-y += nvkm/engine/disp/gp100.o nvkm-y += nvkm/engine/disp/gp102.o nvkm-y += nvkm/engine/disp/gv100.o nvkm-y += nvkm/engine/disp/tu102.o +nvkm-y += nvkm/engine/disp/ga102.o nvkm-y += nvkm/engine/disp/vga.o nvkm-y += nvkm/engine/disp/head.o @@ -39,14 +40,17 @@ nvkm-y += nvkm/engine/disp/sorgf119.o nvkm-y += nvkm/engine/disp/sorgk104.o nvkm-y += nvkm/engine/disp/sorgm107.o nvkm-y += nvkm/engine/disp/sorgm200.o +nvkm-y += nvkm/engine/disp/sorgp100.o nvkm-y += nvkm/engine/disp/sorgv100.o nvkm-y += nvkm/engine/disp/sortu102.o +nvkm-y += nvkm/engine/disp/sorga102.o nvkm-y += nvkm/engine/disp/outp.o nvkm-y += nvkm/engine/disp/dp.o nvkm-y += nvkm/engine/disp/hdagt215.o nvkm-y += nvkm/engine/disp/hdagf119.o +nvkm-y += nvkm/engine/disp/hdagv100.o nvkm-y += nvkm/engine/disp/hdmi.o nvkm-y += nvkm/engine/disp/hdmig84.o @@ -73,6 +77,9 @@ nvkm-y += nvkm/engine/disp/rootgp100.o nvkm-y += nvkm/engine/disp/rootgp102.o nvkm-y += nvkm/engine/disp/rootgv100.o nvkm-y += nvkm/engine/disp/roottu102.o +nvkm-y += nvkm/engine/disp/rootga102.o + +nvkm-y += nvkm/engine/disp/capsgv100.o nvkm-y += nvkm/engine/disp/channv50.o nvkm-y += nvkm/engine/disp/changf119.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c index cbd33e87b799..5daa77755276 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c @@ -149,10 +149,10 @@ static void nvkm_disp_class_del(struct nvkm_oproxy *oproxy) { struct nvkm_disp *disp = nvkm_disp(oproxy->base.engine); - mutex_lock(&disp->engine.subdev.mutex); - if (disp->client == oproxy) - disp->client = NULL; - mutex_unlock(&disp->engine.subdev.mutex); + spin_lock(&disp->client.lock); + if (disp->client.object == oproxy) + disp->client.object = NULL; + spin_unlock(&disp->client.lock); } static const struct nvkm_oproxy_func @@ -175,13 +175,13 @@ nvkm_disp_class_new(struct nvkm_device *device, return ret; *pobject = &oproxy->base; - mutex_lock(&disp->engine.subdev.mutex); - if (disp->client) { - mutex_unlock(&disp->engine.subdev.mutex); + spin_lock(&disp->client.lock); + if (disp->client.object) { + spin_unlock(&disp->client.lock); return -EBUSY; } - disp->client = oproxy; - mutex_unlock(&disp->engine.subdev.mutex); + disp->client.object = oproxy; + spin_unlock(&disp->client.lock); return sclass->ctor(disp, oclass, data, size, &oproxy->object); } @@ -473,21 +473,22 @@ nvkm_disp = { int nvkm_disp_ctor(const struct nvkm_disp_func *func, struct nvkm_device *device, - int index, struct nvkm_disp *disp) + enum nvkm_subdev_type type, int inst, struct nvkm_disp *disp) { disp->func = func; INIT_LIST_HEAD(&disp->head); INIT_LIST_HEAD(&disp->ior); INIT_LIST_HEAD(&disp->outp); INIT_LIST_HEAD(&disp->conn); - return nvkm_engine_ctor(&nvkm_disp, device, index, true, &disp->engine); + spin_lock_init(&disp->client.lock); + return nvkm_engine_ctor(&nvkm_disp, device, type, inst, true, &disp->engine); } int nvkm_disp_new_(const struct nvkm_disp_func *func, struct nvkm_device *device, - int index, struct nvkm_disp **pdisp) + enum nvkm_subdev_type type, int inst, struct nvkm_disp **pdisp) { if (!(*pdisp = kzalloc(sizeof(**pdisp), GFP_KERNEL))) return -ENOMEM; - return nvkm_disp_ctor(func, device, index, *pdisp); + return nvkm_disp_ctor(func, device, type, inst, *pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/capsgv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/capsgv100.c new file mode 100644 index 000000000000..5026e530f4bb --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/capsgv100.c @@ -0,0 +1,60 @@ +/* + * Copyright 2020 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#define gv100_disp_caps(p) container_of((p), struct gv100_disp_caps, object) +#include "rootnv50.h" + +struct gv100_disp_caps { + struct nvkm_object object; + struct nv50_disp *disp; +}; + +static int +gv100_disp_caps_map(struct nvkm_object *object, void *argv, u32 argc, + enum nvkm_object_map *type, u64 *addr, u64 *size) +{ + struct gv100_disp_caps *caps = gv100_disp_caps(object); + struct nvkm_device *device = caps->disp->base.engine.subdev.device; + *type = NVKM_OBJECT_MAP_IO; + *addr = 0x640000 + device->func->resource_addr(device, 0); + *size = 0x1000; + return 0; +} + +static const struct nvkm_object_func +gv100_disp_caps = { + .map = gv100_disp_caps_map, +}; + +int +gv100_disp_caps_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, + struct nv50_disp *disp, struct nvkm_object **pobject) +{ + struct gv100_disp_caps *caps; + + if (!(caps = kzalloc(sizeof(*caps), GFP_KERNEL))) + return -ENOMEM; + *pobject = &caps->object; + + nvkm_object_ctor(&gv100_disp_caps, oclass, &caps->object); + caps->disp = disp; + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c index bcf32d92ee5a..a7a7eb041515 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c @@ -74,6 +74,8 @@ nv50_disp_chan_mthd(struct nv50_disp_chan *chan, int debug) if (debug > subdev->debug) return; + if (!mthd) + return; for (i = 0; (list = mthd->data[i].mthd) != NULL; i++) { u32 base = chan->head * mthd->addr; @@ -276,7 +278,7 @@ nv50_disp_chan_child_get(struct nvkm_object *object, int index, const struct nvkm_device_oclass *oclass = NULL; if (chan->func->bind) - sclass->engine = nvkm_device_engine(device, NVKM_ENGINE_DMAOBJ); + sclass->engine = nvkm_device_engine(device, NVKM_ENGINE_DMAOBJ, 0); else sclass->engine = NULL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h index e55054b7329f..9cf2cfe2010c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h @@ -21,6 +21,8 @@ struct nv50_disp_chan { struct nvkm_memory *memory; u64 push; + + u32 suspend_put; }; struct nv50_disp_chan_func { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c index d162b9cf4eac..689e3cdd959a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c @@ -182,6 +182,8 @@ gf119_disp_core_fini(struct nv50_disp_chan *chan) nvkm_error(subdev, "core fini: %08x\n", nvkm_rd32(device, 0x610490)); } + + chan->suspend_put = nvkm_rd32(device, 0x640000); } static int @@ -195,7 +197,7 @@ gf119_disp_core_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x610498, 0x00010000); nvkm_wr32(device, 0x61049c, 0x00000001); nvkm_mask(device, 0x610490, 0x00000010, 0x00000010); - nvkm_wr32(device, 0x640000, 0x00000000); + nvkm_wr32(device, 0x640000, chan->suspend_put); nvkm_wr32(device, 0x610490, 0x01000013); /* wait for it to go inactive */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c index 5b7f993c73c7..1b435beef3bf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c @@ -36,7 +36,7 @@ gp102_disp_core_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x611498, 0x00010000); nvkm_wr32(device, 0x61149c, 0x00000001); nvkm_mask(device, 0x610490, 0x00000010, 0x00000010); - nvkm_wr32(device, 0x640000, 0x00000000); + nvkm_wr32(device, 0x640000, chan->suspend_put); nvkm_wr32(device, 0x610490, 0x01000013); /* wait for it to go inactive */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c index 4592d0e69fec..1d333c484a49 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c @@ -23,7 +23,7 @@ #include <subdev/timer.h> -const struct nv50_disp_mthd_list +static const struct nv50_disp_mthd_list gv100_disp_core_mthd_base = { .mthd = 0x0000, .addr = 0x000000, @@ -39,7 +39,7 @@ gv100_disp_core_mthd_base = { } }; -const struct nv50_disp_mthd_list +static const struct nv50_disp_mthd_list gv100_disp_core_mthd_sor = { .mthd = 0x0020, .addr = 0x000020, @@ -106,6 +106,8 @@ gv100_disp_core_mthd_head = { { 0x20a4, 0x6820a4 }, { 0x20a8, 0x6820a8 }, { 0x20ac, 0x6820ac }, + { 0x2180, 0x682180 }, + { 0x2184, 0x682184 }, { 0x218c, 0x68218c }, { 0x2194, 0x682194 }, { 0x2198, 0x682198 }, @@ -167,6 +169,7 @@ gv100_disp_core_fini(struct nv50_disp_chan *chan) nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000000); gv100_disp_core_idle(chan); nvkm_mask(device, 0x6104e0, 0x00000002, 0x00000000); + chan->suspend_put = nvkm_rd32(device, 0x680000); } static int @@ -181,7 +184,7 @@ gv100_disp_core_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x610b2c, 0x00000040); nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000010); - nvkm_wr32(device, 0x680000, 0x00000000); + nvkm_wr32(device, 0x680000, chan->suspend_put); nvkm_wr32(device, 0x6104e0, 0x00000013); return gv100_disp_core_idle(chan); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c index 55db9a22b4be..660310b27f9c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c @@ -179,6 +179,8 @@ nv50_disp_core_fini(struct nv50_disp_chan *chan) nvkm_error(subdev, "core fini: %08x\n", nvkm_rd32(device, 0x610200)); } + + chan->suspend_put = nvkm_rd32(device, 0x640000); } static int @@ -198,7 +200,7 @@ nv50_disp_core_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x610208, 0x00010000); nvkm_wr32(device, 0x61020c, 0x00000000); nvkm_mask(device, 0x610200, 0x00000010, 0x00000010); - nvkm_wr32(device, 0x640000, 0x00000000); + nvkm_wr32(device, 0x640000, chan->suspend_put); nvkm_wr32(device, 0x610200, 0x01000013); /* wait for it to go inactive */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c index edf7dd0d931d..76425e8586da 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c @@ -53,6 +53,8 @@ gf119_disp_dmac_fini(struct nv50_disp_chan *chan) nvkm_error(subdev, "ch %d fini: %08x\n", user, nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); } + + chan->suspend_put = nvkm_rd32(device, 0x640000 + (ctrl * 0x1000)); } static int @@ -68,7 +70,7 @@ gf119_disp_dmac_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x610498 + (ctrl * 0x0010), 0x00010000); nvkm_wr32(device, 0x61049c + (ctrl * 0x0010), 0x00000001); nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000010, 0x00000010); - nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), 0x00000000); + nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), chan->suspend_put); nvkm_wr32(device, 0x610490 + (ctrl * 0x0010), 0x00000013); /* wait for it to go inactive */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c index f21a433199aa..da258df268d7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c @@ -38,7 +38,7 @@ gp102_disp_dmac_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x611498 + (ctrl * 0x0010), 0x00010000); nvkm_wr32(device, 0x61149c + (ctrl * 0x0010), 0x00000001); nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000010, 0x00000010); - nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), 0x00000000); + nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), chan->suspend_put); nvkm_wr32(device, 0x610490 + (ctrl * 0x0010), 0x00000013); /* wait for it to go inactive */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c index eac0e42da354..fdb624ac6b87 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c @@ -50,10 +50,12 @@ void gv100_disp_dmac_fini(struct nv50_disp_chan *chan) { struct nvkm_device *device = chan->disp->base.engine.subdev.device; + const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; const u32 coff = chan->chid.ctrl * 0x04; nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000000); gv100_disp_dmac_idle(chan); nvkm_mask(device, 0x6104e0 + coff, 0x00000002, 0x00000000); + chan->suspend_put = nvkm_rd32(device, 0x690000 + uoff); } int @@ -71,7 +73,7 @@ gv100_disp_dmac_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x610b2c + poff, 0x00000040); nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000010); - nvkm_wr32(device, 0x690000 + uoff, 0x00000000); + nvkm_wr32(device, 0x690000 + uoff, chan->suspend_put); nvkm_wr32(device, 0x6104e0 + coff, 0x00000013); return gv100_disp_dmac_idle(chan); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c index 9e8a9d7a9b68..d0a7da96d62b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c @@ -94,6 +94,8 @@ nv50_disp_dmac_fini(struct nv50_disp_chan *chan) nvkm_error(subdev, "ch %d fini timeout, %08x\n", user, nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); } + + chan->suspend_put = nvkm_rd32(device, 0x640000 + (ctrl * 0x1000)); } static int @@ -109,7 +111,7 @@ nv50_disp_dmac_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x610208 + (ctrl * 0x0010), 0x00010000); nvkm_wr32(device, 0x61020c + (ctrl * 0x0010), ctrl); nvkm_mask(device, 0x610200 + (ctrl * 0x0010), 0x00000010, 0x00000010); - nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), 0x00000000); + nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), chan->suspend_put); nvkm_wr32(device, 0x610200 + (ctrl * 0x0010), 0x00000013); /* wait for it to go inactive */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c index 818d21bd28d3..8e09315b8fb3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c @@ -33,8 +33,18 @@ #include <nvif/event.h> +/* IED scripts are no longer used by UEFI/RM from Ampere, but have been updated for + * the x86 option ROM. However, the relevant VBIOS table versions weren't modified, + * so we're unable to detect this in a nice way. + */ +#define AMPERE_IED_HACK(disp) ((disp)->engine.subdev.device->card_type >= GA100) + struct lt_state { struct nvkm_dp *dp; + + int repeaters; + int repeater; + u8 stat[6]; u8 conf[4]; bool pc2; @@ -46,14 +56,26 @@ static int nvkm_dp_train_sense(struct lt_state *lt, bool pc, u32 delay) { struct nvkm_dp *dp = lt->dp; + u32 addr; int ret; - if (dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL]) - mdelay(dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4); + usleep_range(delay, delay * 2); + + if (lt->repeater) + addr = DPCD_LTTPR_LANE0_1_STATUS(lt->repeater); + else + addr = DPCD_LS02; + + ret = nvkm_rdaux(dp->aux, addr, <->stat[0], 3); + if (ret) + return ret; + + if (lt->repeater) + addr = DPCD_LTTPR_LANE0_1_ADJUST(lt->repeater); else - udelay(delay); + addr = DPCD_LS06; - ret = nvkm_rdaux(dp->aux, DPCD_LS02, lt->stat, 6); + ret = nvkm_rdaux(dp->aux, addr, <->stat[4], 2); if (ret) return ret; @@ -79,6 +101,7 @@ nvkm_dp_train_drive(struct lt_state *lt, bool pc) struct nvbios_dpout info; struct nvbios_dpcfg ocfg; u8 ver, hdr, cnt, len; + u32 addr; u32 data; int ret, i; @@ -107,6 +130,9 @@ nvkm_dp_train_drive(struct lt_state *lt, bool pc) OUTP_TRACE(&dp->outp, "config lane %d %02x %02x", i, lt->conf[i], lpc2); + if (lt->repeater != lt->repeaters) + continue; + data = nvbios_dpout_match(bios, dp->outp.info.hasht, dp->outp.info.hashm, &ver, &hdr, &cnt, &len, &info); @@ -123,7 +149,12 @@ nvkm_dp_train_drive(struct lt_state *lt, bool pc) ocfg.pe, ocfg.tx_pu); } - ret = nvkm_wraux(dp->aux, DPCD_LC03(0), lt->conf, 4); + if (lt->repeater) + addr = DPCD_LTTPR_LANE0_SET(lt->repeater); + else + addr = DPCD_LC03(0); + + ret = nvkm_wraux(dp->aux, addr, lt->conf, 4); if (ret) return ret; @@ -140,32 +171,59 @@ static void nvkm_dp_train_pattern(struct lt_state *lt, u8 pattern) { struct nvkm_dp *dp = lt->dp; + u32 addr; u8 sink_tp; OUTP_TRACE(&dp->outp, "training pattern %d", pattern); dp->outp.ior->func->dp.pattern(dp->outp.ior, pattern); - nvkm_rdaux(dp->aux, DPCD_LC02, &sink_tp, 1); + if (lt->repeater) + addr = DPCD_LTTPR_PATTERN_SET(lt->repeater); + else + addr = DPCD_LC02; + + nvkm_rdaux(dp->aux, addr, &sink_tp, 1); sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET; - sink_tp |= pattern; - nvkm_wraux(dp->aux, DPCD_LC02, &sink_tp, 1); + sink_tp |= (pattern != 4) ? pattern : 7; + + if (pattern != 0) + sink_tp |= DPCD_LC02_SCRAMBLING_DISABLE; + else + sink_tp &= ~DPCD_LC02_SCRAMBLING_DISABLE; + nvkm_wraux(dp->aux, addr, &sink_tp, 1); } static int nvkm_dp_train_eq(struct lt_state *lt) { + struct nvkm_i2c_aux *aux = lt->dp->aux; bool eq_done = false, cr_done = true; - int tries = 0, i; + int tries = 0, usec = 0, i; + u8 data; - if (lt->dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) - nvkm_dp_train_pattern(lt, 3); - else - nvkm_dp_train_pattern(lt, 2); + if (lt->repeater) { + if (!nvkm_rdaux(aux, DPCD_LTTPR_AUX_RD_INTERVAL(lt->repeater), &data, sizeof(data))) + usec = (data & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; + + nvkm_dp_train_pattern(lt, 4); + } else { + if (lt->dp->dpcd[DPCD_RC00_DPCD_REV] >= 0x14 && + lt->dp->dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED) + nvkm_dp_train_pattern(lt, 4); + else + if (lt->dp->dpcd[DPCD_RC00_DPCD_REV] >= 0x12 && + lt->dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) + nvkm_dp_train_pattern(lt, 3); + else + nvkm_dp_train_pattern(lt, 2); + + usec = (lt->dp->dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; + } do { if ((tries && nvkm_dp_train_drive(lt, lt->pc2)) || - nvkm_dp_train_sense(lt, lt->pc2, 400)) + nvkm_dp_train_sense(lt, lt->pc2, usec ? usec : 400)) break; eq_done = !!(lt->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE); @@ -187,13 +245,16 @@ nvkm_dp_train_cr(struct lt_state *lt) { bool cr_done = false, abort = false; int voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; - int tries = 0, i; + int tries = 0, usec = 0, i; nvkm_dp_train_pattern(lt, 1); + if (lt->dp->dpcd[DPCD_RC00_DPCD_REV] < 0x14 && !lt->repeater) + usec = (lt->dp->dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; + do { if (nvkm_dp_train_drive(lt, false) || - nvkm_dp_train_sense(lt, false, 100)) + nvkm_dp_train_sense(lt, false, usec ? usec : 100)) break; cr_done = true; @@ -217,7 +278,7 @@ nvkm_dp_train_cr(struct lt_state *lt) } static int -nvkm_dp_train_links(struct nvkm_dp *dp) +nvkm_dp_train_links(struct nvkm_dp *dp, int rate) { struct nvkm_ior *ior = dp->outp.ior; struct nvkm_disp *disp = dp->outp.disp; @@ -227,17 +288,32 @@ nvkm_dp_train_links(struct nvkm_dp *dp) .dp = dp, }; u32 lnkcmp; - u8 sink[2]; + u8 sink[2], data; int ret; OUTP_DBG(&dp->outp, "training %d x %d MB/s", ior->dp.nr, ior->dp.bw * 27); /* Intersect misc. capabilities of the OR and sink. */ + if (disp->engine.subdev.device->chipset < 0x110) + dp->dpcd[DPCD_RC03] &= ~DPCD_RC03_TPS4_SUPPORTED; if (disp->engine.subdev.device->chipset < 0xd0) dp->dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED; lt.pc2 = dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED; + if (AMPERE_IED_HACK(disp) && (lnkcmp = lt.dp->info.script[0])) { + /* Execute BeforeLinkTraining script from DP Info table. */ + while (ior->dp.bw < nvbios_rd08(bios, lnkcmp)) + lnkcmp += 3; + lnkcmp = nvbios_rd16(bios, lnkcmp + 1); + + nvbios_init(&dp->outp.disp->engine.subdev, lnkcmp, + init.outp = &dp->outp.info; + init.or = ior->id; + init.link = ior->asy.link; + ); + } + /* Set desired link configuration on the source. */ if ((lnkcmp = lt.dp->info.lnkcmp)) { if (dp->version < 0x30) { @@ -268,8 +344,22 @@ nvkm_dp_train_links(struct nvkm_dp *dp) ior->func->dp.power(ior, ior->dp.nr); + /* Select LTTPR non-transparent mode if we have a valid configuration, + * use transparent mode otherwise. + */ + if (dp->lttpr[0] >= 0x14) { + data = DPCD_LTTPR_MODE_TRANSPARENT; + nvkm_wraux(dp->aux, DPCD_LTTPR_MODE, &data, sizeof(data)); + + if (dp->lttprs) { + data = DPCD_LTTPR_MODE_NON_TRANSPARENT; + nvkm_wraux(dp->aux, DPCD_LTTPR_MODE, &data, sizeof(data)); + lt.repeaters = dp->lttprs; + } + } + /* Set desired link configuration on the sink. */ - sink[0] = ior->dp.bw; + sink[0] = (dp->rate[rate].dpcd < 0) ? ior->dp.bw : 0; sink[1] = ior->dp.nr; if (ior->dp.ef) sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN; @@ -278,12 +368,33 @@ nvkm_dp_train_links(struct nvkm_dp *dp) if (ret) return ret; + if (dp->rate[rate].dpcd >= 0) { + ret = nvkm_rdaux(dp->aux, DPCD_LC15_LINK_RATE_SET, &sink[0], sizeof(sink[0])); + if (ret) + return ret; + + sink[0] &= ~DPCD_LC15_LINK_RATE_SET_MASK; + sink[0] |= dp->rate[rate].dpcd; + + ret = nvkm_wraux(dp->aux, DPCD_LC15_LINK_RATE_SET, &sink[0], sizeof(sink[0])); + if (ret) + return ret; + } + /* Attempt to train the link in this configuration. */ - memset(lt.stat, 0x00, sizeof(lt.stat)); - ret = nvkm_dp_train_cr(<); - if (ret == 0) - ret = nvkm_dp_train_eq(<); - nvkm_dp_train_pattern(<, 0); + for (lt.repeater = lt.repeaters; lt.repeater >= 0; lt.repeater--) { + if (lt.repeater) + OUTP_DBG(&dp->outp, "training LTTPR%d", lt.repeater); + else + OUTP_DBG(&dp->outp, "training sink"); + + memset(lt.stat, 0x00, sizeof(lt.stat)); + ret = nvkm_dp_train_cr(<); + if (ret == 0) + ret = nvkm_dp_train_eq(<); + nvkm_dp_train_pattern(<, 0); + } + return ret; } @@ -316,71 +427,23 @@ nvkm_dp_train_init(struct nvkm_dp *dp) ); } - /* Execute BeforeLinkTraining script from DP Info table. */ - nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[0], - init.outp = &dp->outp.info; - init.or = dp->outp.ior->id; - init.link = dp->outp.ior->asy.link; - ); + if (!AMPERE_IED_HACK(dp->outp.disp)) { + /* Execute BeforeLinkTraining script from DP Info table. */ + nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[0], + init.outp = &dp->outp.info; + init.or = dp->outp.ior->id; + init.link = dp->outp.ior->asy.link; + ); + } } -static const struct dp_rates { - u32 rate; - u8 bw; - u8 nr; -} nvkm_dp_rates[] = { - { 2160000, 0x14, 4 }, - { 1080000, 0x0a, 4 }, - { 1080000, 0x14, 2 }, - { 648000, 0x06, 4 }, - { 540000, 0x0a, 2 }, - { 540000, 0x14, 1 }, - { 324000, 0x06, 2 }, - { 270000, 0x0a, 1 }, - { 162000, 0x06, 1 }, - {} -}; - static int nvkm_dp_train(struct nvkm_dp *dp, u32 dataKBps) { struct nvkm_ior *ior = dp->outp.ior; - const u8 sink_nr = dp->dpcd[DPCD_RC02] & DPCD_RC02_MAX_LANE_COUNT; - const u8 sink_bw = dp->dpcd[DPCD_RC01_MAX_LINK_RATE]; - const u8 outp_nr = dp->outp.info.dpconf.link_nr; - const u8 outp_bw = dp->outp.info.dpconf.link_bw; - const struct dp_rates *failsafe = NULL, *cfg; - int ret = -EINVAL; + int ret = -EINVAL, nr, rate; u8 pwr; - /* Find the lowest configuration of the OR that can support - * the required link rate. - * - * We will refuse to program the OR to lower rates, even if - * link training fails at higher rates (or even if the sink - * can't support the rate at all, though the DD is supposed - * to prevent such situations from happening). - * - * Attempting to do so can cause the entire display to hang, - * and it's better to have a failed modeset than that. - */ - for (cfg = nvkm_dp_rates; cfg->rate; cfg++) { - if (cfg->nr <= outp_nr && cfg->nr <= outp_bw) { - /* Try to respect sink limits too when selecting - * lowest link configuration. - */ - if (!failsafe || - (cfg->nr <= sink_nr && cfg->bw <= sink_bw)) - failsafe = cfg; - } - - if (failsafe && cfg[1].rate < dataKBps) - break; - } - - if (WARN_ON(!failsafe)) - return ret; - /* Ensure sink is not in a low-power state. */ if (!nvkm_rdaux(dp->aux, DPCD_SC00, &pwr, 1)) { if ((pwr & DPCD_SC00_SET_POWER) != DPCD_SC00_SET_POWER_D0) { @@ -390,25 +453,22 @@ nvkm_dp_train(struct nvkm_dp *dp, u32 dataKBps) } } + ior->dp.mst = dp->lt.mst; + ior->dp.ef = dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP; + ior->dp.nr = 0; + /* Link training. */ - OUTP_DBG(&dp->outp, "training (min: %d x %d MB/s)", - failsafe->nr, failsafe->bw * 27); + OUTP_DBG(&dp->outp, "training"); nvkm_dp_train_init(dp); - for (cfg = nvkm_dp_rates; ret < 0 && cfg <= failsafe; cfg++) { - /* Skip configurations not supported by both OR and sink. */ - if ((cfg->nr > outp_nr || cfg->bw > outp_bw || - cfg->nr > sink_nr || cfg->bw > sink_bw)) { - if (cfg != failsafe) - continue; - OUTP_ERR(&dp->outp, "link rate unsupported by sink"); + for (nr = dp->links; ret < 0 && nr; nr >>= 1) { + for (rate = 0; ret < 0 && rate < dp->rates; rate++) { + if (dp->rate[rate].rate * nr >= dataKBps || WARN_ON(!ior->dp.nr)) { + /* Program selected link configuration. */ + ior->dp.bw = dp->rate[rate].rate / 27000; + ior->dp.nr = nr; + ret = nvkm_dp_train_links(dp, rate); + } } - ior->dp.mst = dp->lt.mst; - ior->dp.ef = dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP; - ior->dp.bw = cfg->bw; - ior->dp.nr = cfg->nr; - - /* Program selected link configuration. */ - ret = nvkm_dp_train_links(dp); } nvkm_dp_train_fini(dp); if (ret < 0) @@ -419,7 +479,7 @@ nvkm_dp_train(struct nvkm_dp *dp, u32 dataKBps) return ret; } -static void +void nvkm_dp_disable(struct nvkm_outp *outp, struct nvkm_ior *ior) { struct nvkm_dp *dp = nvkm_dp(outp); @@ -506,6 +566,47 @@ done: } static bool +nvkm_dp_enable_supported_link_rates(struct nvkm_dp *dp) +{ + u8 sink_rates[DPCD_RC10_SUPPORTED_LINK_RATES__SIZE]; + int i, j, k; + + if (dp->outp.conn->info.type != DCB_CONNECTOR_eDP || + dp->dpcd[DPCD_RC00_DPCD_REV] < 0x13 || + nvkm_rdaux(dp->aux, DPCD_RC10_SUPPORTED_LINK_RATES(0), sink_rates, sizeof(sink_rates))) + return false; + + for (i = 0; i < ARRAY_SIZE(sink_rates); i += 2) { + const u32 rate = ((sink_rates[i + 1] << 8) | sink_rates[i]) * 200 / 10; + + if (!rate || WARN_ON(dp->rates == ARRAY_SIZE(dp->rate))) + break; + + if (rate > dp->outp.info.dpconf.link_bw * 27000) { + OUTP_DBG(&dp->outp, "rate %d !outp", rate); + continue; + } + + for (j = 0; j < dp->rates; j++) { + if (rate > dp->rate[j].rate) { + for (k = dp->rates; k > j; k--) + dp->rate[k] = dp->rate[k - 1]; + break; + } + } + + dp->rate[j].dpcd = i / 2; + dp->rate[j].rate = rate; + dp->rates++; + } + + for (i = 0; i < dp->rates; i++) + OUTP_DBG(&dp->outp, "link_rate[%d] = %d", dp->rate[i].dpcd, dp->rate[i].rate); + + return dp->rates != 0; +} + +static bool nvkm_dp_enable(struct nvkm_dp *dp, bool enable) { struct nvkm_i2c_aux *aux = dp->aux; @@ -517,9 +618,60 @@ nvkm_dp_enable(struct nvkm_dp *dp, bool enable) dp->present = true; } - if (!nvkm_rdaux(aux, DPCD_RC00_DPCD_REV, dp->dpcd, - sizeof(dp->dpcd))) + /* Detect any LTTPRs before reading DPCD receiver caps. */ + if (!nvkm_rdaux(aux, DPCD_LTTPR_REV, dp->lttpr, sizeof(dp->lttpr)) && + dp->lttpr[0] >= 0x14 && dp->lttpr[2]) { + switch (dp->lttpr[2]) { + case 0x80: dp->lttprs = 1; break; + case 0x40: dp->lttprs = 2; break; + case 0x20: dp->lttprs = 3; break; + case 0x10: dp->lttprs = 4; break; + case 0x08: dp->lttprs = 5; break; + case 0x04: dp->lttprs = 6; break; + case 0x02: dp->lttprs = 7; break; + case 0x01: dp->lttprs = 8; break; + default: + /* Unknown LTTPR count, we'll switch to transparent mode. */ + WARN_ON(1); + dp->lttprs = 0; + break; + } + } else { + /* No LTTPR support, or zero LTTPR count - don't touch it at all. */ + memset(dp->lttpr, 0x00, sizeof(dp->lttpr)); + } + + if (!nvkm_rdaux(aux, DPCD_RC00_DPCD_REV, dp->dpcd, sizeof(dp->dpcd))) { + const u8 rates[] = { 0x1e, 0x14, 0x0a, 0x06, 0 }; + const u8 *rate; + int rate_max; + + dp->rates = 0; + dp->links = dp->dpcd[DPCD_RC02] & DPCD_RC02_MAX_LANE_COUNT; + dp->links = min(dp->links, dp->outp.info.dpconf.link_nr); + if (dp->lttprs && dp->lttpr[4]) + dp->links = min_t(int, dp->links, dp->lttpr[4]); + + rate_max = dp->dpcd[DPCD_RC01_MAX_LINK_RATE]; + rate_max = min(rate_max, dp->outp.info.dpconf.link_bw); + if (dp->lttprs && dp->lttpr[1]) + rate_max = min_t(int, rate_max, dp->lttpr[1]); + + if (!nvkm_dp_enable_supported_link_rates(dp)) { + for (rate = rates; *rate; rate++) { + if (*rate <= rate_max) { + if (WARN_ON(dp->rates == ARRAY_SIZE(dp->rate))) + break; + + dp->rate[dp->rates].dpcd = -1; + dp->rate[dp->rates].rate = *rate * 27000; + dp->rates++; + } + } + } + return true; + } } if (dp->present) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h index 428b3f488f03..8e59dd469da6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h @@ -9,10 +9,7 @@ #include <subdev/bios/dp.h> struct nvkm_dp { - union { - struct nvkm_outp base; - struct nvkm_outp outp; - }; + struct nvkm_outp outp; struct nvbios_dpout info; u8 version; @@ -21,8 +18,17 @@ struct nvkm_dp { struct nvkm_notify hpd; bool present; + u8 lttpr[6]; + u8 lttprs; u8 dpcd[16]; + struct { + int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */ + u32 rate; + } rate[8]; + int rates; + int links; + struct mutex mutex; struct { atomic_t done; @@ -32,6 +38,7 @@ struct nvkm_dp { int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *, struct nvkm_outp **); +void nvkm_dp_disable(struct nvkm_outp *, struct nvkm_ior *); /* DPCD Receiver Capabilities */ #define DPCD_RC00_DPCD_REV 0x00000 @@ -41,8 +48,12 @@ int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *, #define DPCD_RC02_TPS3_SUPPORTED 0x40 #define DPCD_RC02_MAX_LANE_COUNT 0x1f #define DPCD_RC03 0x00003 +#define DPCD_RC03_TPS4_SUPPORTED 0x80 #define DPCD_RC03_MAX_DOWNSPREAD 0x01 -#define DPCD_RC0E_AUX_RD_INTERVAL 0x0000e +#define DPCD_RC0E 0x0000e +#define DPCD_RC0E_AUX_RD_INTERVAL 0x7f +#define DPCD_RC10_SUPPORTED_LINK_RATES(i) 0x00010 +#define DPCD_RC10_SUPPORTED_LINK_RATES__SIZE 16 /* DPCD Link Configuration */ #define DPCD_LC00_LINK_BW_SET 0x00100 @@ -50,7 +61,8 @@ int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *, #define DPCD_LC01_ENHANCED_FRAME_EN 0x80 #define DPCD_LC01_LANE_COUNT_SET 0x1f #define DPCD_LC02 0x00102 -#define DPCD_LC02_TRAINING_PATTERN_SET 0x03 +#define DPCD_LC02_TRAINING_PATTERN_SET 0x0f +#define DPCD_LC02_SCRAMBLING_DISABLE 0x20 #define DPCD_LC03(l) ((l) + 0x00103) #define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED 0x20 #define DPCD_LC03_PRE_EMPHASIS_SET 0x18 @@ -66,6 +78,8 @@ int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *, #define DPCD_LC10_LANE3_POST_CURSOR2_SET 0x30 #define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED 0x04 #define DPCD_LC10_LANE2_POST_CURSOR2_SET 0x03 +#define DPCD_LC15_LINK_RATE_SET 0x00115 +#define DPCD_LC15_LINK_RATE_SET_MASK 0x07 /* DPCD Link/Sink Status */ #define DPCD_LS02 0x00202 @@ -107,4 +121,14 @@ int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *, #define DPCD_SC00_SET_POWER 0x03 #define DPCD_SC00_SET_POWER_D0 0x01 #define DPCD_SC00_SET_POWER_D3 0x03 + +#define DPCD_LTTPR_REV 0xf0000 +#define DPCD_LTTPR_MODE 0xf0003 +#define DPCD_LTTPR_MODE_TRANSPARENT 0x55 +#define DPCD_LTTPR_MODE_NON_TRANSPARENT 0xaa +#define DPCD_LTTPR_PATTERN_SET(i) ((i - 1) * 0x50 + 0xf0010) +#define DPCD_LTTPR_LANE0_SET(i) ((i - 1) * 0x50 + 0xf0011) +#define DPCD_LTTPR_AUX_RD_INTERVAL(i) ((i - 1) * 0x50 + 0xf0020) +#define DPCD_LTTPR_LANE0_1_STATUS(i) ((i - 1) * 0x50 + 0xf0030) +#define DPCD_LTTPR_LANE0_1_ADJUST(i) ((i - 1) * 0x50 + 0xf0033) #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c index 731f188fc1ee..156bbe8b2de3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c @@ -41,7 +41,8 @@ g84_disp = { }; int -g84_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +g84_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&g84_disp, device, index, pdisp); + return nv50_disp_new_(&g84_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c index def54fe1951e..3425b5d3bc72 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c @@ -41,7 +41,8 @@ g94_disp = { }; int -g94_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +g94_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&g94_disp, device, index, pdisp); + return nv50_disp_new_(&g94_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c new file mode 100644 index 000000000000..68aa52588d92 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c @@ -0,0 +1,47 @@ +/* + * Copyright 2021 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "nv50.h" +#include "head.h" +#include "ior.h" +#include "channv50.h" +#include "rootnv50.h" + +static const struct nv50_disp_func +ga102_disp = { + .init = tu102_disp_init, + .fini = gv100_disp_fini, + .intr = gv100_disp_intr, + .uevent = &gv100_disp_chan_uevent, + .super = gv100_disp_super, + .root = &ga102_disp_root_oclass, + .wndw = { .cnt = gv100_disp_wndw_cnt }, + .head = { .cnt = gv100_head_cnt, .new = gv100_head_new }, + .sor = { .cnt = gv100_sor_cnt, .new = ga102_sor_new }, + .ramht_size = 0x2000, +}; + +int +ga102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) +{ + return nv50_disp_new_(&ga102_disp, device, type, inst, pdisp); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c index e675d9b9d5d7..a6bafe7fea1f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c @@ -266,7 +266,8 @@ gf119_disp = { }; int -gf119_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gf119_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gf119_disp, device, index, pdisp); + return nv50_disp_new_(&gf119_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c index 4c3439b1a62d..3b79cf233ac5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c @@ -41,7 +41,8 @@ gk104_disp = { }; int -gk104_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gk104_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gk104_disp, device, index, pdisp); + return nv50_disp_new_(&gk104_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c index bc6f4750c942..988eb12237a6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c @@ -41,7 +41,8 @@ gk110_disp = { }; int -gk110_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gk110_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gk110_disp, device, index, pdisp); + return nv50_disp_new_(&gk110_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c index 031cf6b03a76..5d8108feeacd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c @@ -41,7 +41,8 @@ gm107_disp = { }; int -gm107_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gm107_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gm107_disp, device, index, pdisp); + return nv50_disp_new_(&gm107_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c index ec9c33a5162d..f7bb66087476 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c @@ -41,7 +41,8 @@ gm200_disp = { }; int -gm200_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gm200_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gm200_disp, device, index, pdisp); + return nv50_disp_new_(&gm200_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c index fd6216684f6d..af0ca812a394 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c @@ -36,11 +36,12 @@ gp100_disp = { .super = gf119_disp_super, .root = &gp100_disp_root_oclass, .head = { .cnt = gf119_head_cnt, .new = gf119_head_new }, - .sor = { .cnt = gf119_sor_cnt, .new = gm200_sor_new }, + .sor = { .cnt = gf119_sor_cnt, .new = gp100_sor_new }, }; int -gp100_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gp100_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gp100_disp, device, index, pdisp); + return nv50_disp_new_(&gp100_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c index 3468ddec1270..065fea1bdfd1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c @@ -63,11 +63,12 @@ gp102_disp = { .super = gf119_disp_super, .root = &gp102_disp_root_oclass, .head = { .cnt = gf119_head_cnt, .new = gf119_head_new }, - .sor = { .cnt = gf119_sor_cnt, .new = gm200_sor_new }, + .sor = { .cnt = gf119_sor_cnt, .new = gp100_sor_new }, }; int -gp102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gp102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gp102_disp, device, index, pdisp); + return nv50_disp_new_(&gp102_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c index f80183701f44..22bc269df64a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c @@ -41,7 +41,8 @@ gt200_disp = { }; int -gt200_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gt200_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(>200_disp, device, index, pdisp); + return nv50_disp_new_(>200_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c index 7581efc1357e..63a912b174d7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c @@ -41,7 +41,8 @@ gt215_disp = { }; int -gt215_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gt215_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(>215_disp, device, index, pdisp); + return nv50_disp_new_(>215_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c index 892be6c9b76c..53879d5271cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c @@ -101,15 +101,26 @@ gv100_disp_exception(struct nv50_disp *disp, int chid) u32 stat = nvkm_rd32(device, 0x611020 + (chid * 12)); u32 type = (stat & 0x00007000) >> 12; u32 mthd = (stat & 0x00000fff) << 2; - u32 data = nvkm_rd32(device, 0x611024 + (chid * 12)); - u32 code = nvkm_rd32(device, 0x611028 + (chid * 12)); const struct nvkm_enum *reason = nvkm_enum_find(nv50_disp_intr_error_type, type); - nvkm_error(subdev, "chid %d stat %08x reason %d [%s] mthd %04x " - "data %08x code %08x\n", - chid, stat, type, reason ? reason->name : "", - mthd, data, code); + /*TODO: Suspect 33->41 are for WRBK channel exceptions, but we + * don't support those currently. + * + * CORE+WIN CHIDs map directly to the FE_EXCEPT() slots. + */ + if (chid <= 32) { + u32 data = nvkm_rd32(device, 0x611024 + (chid * 12)); + u32 code = nvkm_rd32(device, 0x611028 + (chid * 12)); + nvkm_error(subdev, "chid %d stat %08x reason %d [%s] " + "mthd %04x data %08x code %08x\n", + chid, stat, type, reason ? reason->name : "", + mthd, data, code); + } else { + nvkm_error(subdev, "chid %d stat %08x reason %d [%s] " + "mthd %04x\n", + chid, stat, type, reason ? reason->name : "", mthd); + } if (chid < ARRAY_SIZE(disp->chan) && disp->chan[chid]) { switch (mthd) { @@ -144,6 +155,12 @@ gv100_disp_intr_ctrl_disp(struct nv50_disp *disp) if (stat & 0x00000008) stat &= ~0x00000008; + if (stat & 0x00000080) { + u32 error = nvkm_mask(device, 0x611848, 0x00000000, 0x00000000); + nvkm_warn(subdev, "error %08x\n", error); + stat &= ~0x00000080; + } + if (stat & 0x00000100) { unsigned long wndws = nvkm_rd32(device, 0x611858); unsigned long other = nvkm_rd32(device, 0x61185c); @@ -424,7 +441,8 @@ gv100_disp = { }; int -gv100_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gv100_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gv100_disp, device, index, pdisp); + return nv50_disp_new_(&gv100_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c index 0fa0ec0a1de0..19d2d58344e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c @@ -24,10 +24,18 @@ #include "ior.h" void -gf119_hda_eld(struct nvkm_ior *ior, u8 *data, u8 size) +gf119_hda_device_entry(struct nvkm_ior *ior, int head) { struct nvkm_device *device = ior->disp->engine.subdev.device; - const u32 soff = 0x030 * ior->id; + const u32 hoff = 0x800 * head; + nvkm_mask(device, 0x616548 + hoff, 0x00000070, head << 4); +} + +void +gf119_hda_eld(struct nvkm_ior *ior, int head, u8 *data, u8 size) +{ + struct nvkm_device *device = ior->disp->engine.subdev.device; + const u32 soff = 0x030 * ior->id + (head * 0x04); int i; for (i = 0; i < size; i++) @@ -41,14 +49,14 @@ void gf119_hda_hpd(struct nvkm_ior *ior, int head, bool present) { struct nvkm_device *device = ior->disp->engine.subdev.device; - const u32 hoff = 0x800 * head; + const u32 soff = 0x030 * ior->id + (head * 0x04); u32 data = 0x80000000; u32 mask = 0x80000001; if (present) { - nvkm_mask(device, 0x616548 + hoff, 0x00000070, 0x00000000); + ior->func->hda.device_entry(ior, head); data |= 0x00000001; } else { mask |= 0x00000002; } - nvkm_mask(device, 0x10ec10 + ior->id * 0x030, mask, data); + nvkm_mask(device, 0x10ec10 + soff, mask, data); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c index 4509d2ba880e..0d1b81fe1093 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c @@ -24,7 +24,7 @@ #include "ior.h" void -gt215_hda_eld(struct nvkm_ior *ior, u8 *data, u8 size) +gt215_hda_eld(struct nvkm_ior *ior, int head, u8 *data, u8 size) { struct nvkm_device *device = ior->disp->engine.subdev.device; const u32 soff = ior->id * 0x800; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagv100.c index e210cd6af816..57d374ecfeef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagv100.c @@ -1,5 +1,5 @@ /* - * Copyright 2016 Red Hat Inc. + * Copyright 2020 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -18,19 +18,13 @@ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs <bskeggs@redhat.com> */ -#include "priv.h" - -static const struct nvkm_pmu_func -gp100_pmu = { - .enabled = gf100_pmu_enabled, - .reset = gf100_pmu_reset, -}; +#include "ior.h" -int -gp100_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +void +gv100_hda_device_entry(struct nvkm_ior *ior, int head) { - return nvkm_pmu_new_(&gp100_pmu, device, index, ppmu); + struct nvkm_device *device = ior->disp->engine.subdev.device; + const u32 hoff = 0x800 * head; + nvkm_mask(device, 0x616528 + hoff, 0x00000070, head << 4); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c index 7147dc6d9018..1ccfc8314812 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c @@ -23,55 +23,55 @@ void pack_hdmi_infoframe(struct packed_hdmi_infoframe *packed_frame, */ case 17: subpack1_high = (raw_frame[16] << 16); - /* fall through */ + fallthrough; case 16: subpack1_high |= (raw_frame[15] << 8); - /* fall through */ + fallthrough; case 15: subpack1_high |= raw_frame[14]; - /* fall through */ + fallthrough; case 14: subpack1_low = (raw_frame[13] << 24); - /* fall through */ + fallthrough; case 13: subpack1_low |= (raw_frame[12] << 16); - /* fall through */ + fallthrough; case 12: subpack1_low |= (raw_frame[11] << 8); - /* fall through */ + fallthrough; case 11: subpack1_low |= raw_frame[10]; - /* fall through */ + fallthrough; case 10: subpack0_high = (raw_frame[9] << 16); - /* fall through */ + fallthrough; case 9: subpack0_high |= (raw_frame[8] << 8); - /* fall through */ + fallthrough; case 8: subpack0_high |= raw_frame[7]; - /* fall through */ + fallthrough; case 7: subpack0_low = (raw_frame[6] << 24); - /* fall through */ + fallthrough; case 6: subpack0_low |= (raw_frame[5] << 16); - /* fall through */ + fallthrough; case 5: subpack0_low |= (raw_frame[4] << 8); - /* fall through */ + fallthrough; case 4: subpack0_low |= raw_frame[3]; - /* fall through */ + fallthrough; case 3: header = (raw_frame[2] << 16); - /* fall through */ + fallthrough; case 2: header |= (raw_frame[1] << 8); - /* fall through */ + fallthrough; case 1: header |= raw_frame[0]; - /* fall through */ + fallthrough; case 0: break; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c index 9b16a08eb4d9..bb32befa6ad4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c @@ -24,13 +24,13 @@ #include "hdmi.h" void -gm200_hdmi_scdc(struct nvkm_ior *ior, int head, u8 scdc) +gm200_hdmi_scdc(struct nvkm_ior *ior, u8 scdc) { struct nvkm_device *device = ior->disp->engine.subdev.device; - const u32 hoff = head * 0x800; + const u32 soff = nv50_ior_base(ior); const u32 ctrl = scdc & 0x3; - nvkm_mask(device, 0x61c5bc + hoff, 0x00000003, ctrl); + nvkm_mask(device, 0x61c5bc + soff, 0x00000003, ctrl); ior->tmds.high_speed = !!(scdc & 0x2); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigv100.c index 6e3c450eaace..3ff49344abc7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigv100.c @@ -62,7 +62,6 @@ gv100_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet, nvkm_wr32(device, 0x6f0108 + hdmi, vendor_infoframe.header); nvkm_wr32(device, 0x6f010c + hdmi, vendor_infoframe.subpack0_low); nvkm_wr32(device, 0x6f0110 + hdmi, vendor_infoframe.subpack0_high); - nvkm_wr32(device, 0x6f0110 + hdmi, 0x00000000); nvkm_wr32(device, 0x6f0114 + hdmi, 0x00000000); nvkm_wr32(device, 0x6f0118 + hdmi, 0x00000000); nvkm_wr32(device, 0x6f011c + hdmi, 0x00000000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h index 009d3a8b7a50..9f0bb7c6b010 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h @@ -66,7 +66,7 @@ struct nvkm_ior_func { void (*ctrl)(struct nvkm_ior *, int head, bool enable, u8 max_ac_packet, u8 rekey, u8 *avi, u8 avi_size, u8 *vendor, u8 vendor_size); - void (*scdc)(struct nvkm_ior *, int head, u8 scdc); + void (*scdc)(struct nvkm_ior *, u8 scdc); } hdmi; struct { @@ -87,7 +87,8 @@ struct nvkm_ior_func { struct { void (*hpd)(struct nvkm_ior *, int head, bool present); - void (*eld)(struct nvkm_ior *, u8 *data, u8 size); + void (*eld)(struct nvkm_ior *, int head, u8 *data, u8 size); + void (*device_entry)(struct nvkm_ior *, int head); } hda; }; @@ -149,19 +150,24 @@ void gv100_sor_dp_audio(struct nvkm_ior *, int, bool); void gv100_sor_dp_audio_sym(struct nvkm_ior *, int, u16, u32); void gv100_sor_dp_watermark(struct nvkm_ior *, int, u8); +void tu102_sor_dp_vcpi(struct nvkm_ior *, int, u8, u8, u16, u16); + void g84_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8); void gt215_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8); void gf119_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8); void gk104_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8); void gv100_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8); -void gm200_hdmi_scdc(struct nvkm_ior *, int, u8); +void gm200_hdmi_scdc(struct nvkm_ior *, u8); void gt215_hda_hpd(struct nvkm_ior *, int, bool); -void gt215_hda_eld(struct nvkm_ior *, u8 *, u8); +void gt215_hda_eld(struct nvkm_ior *, int, u8 *, u8); void gf119_hda_hpd(struct nvkm_ior *, int, bool); -void gf119_hda_eld(struct nvkm_ior *, u8 *, u8); +void gf119_hda_eld(struct nvkm_ior *, int, u8 *, u8); +void gf119_hda_device_entry(struct nvkm_ior *, int); + +void gv100_hda_device_entry(struct nvkm_ior *, int); #define IOR_MSG(i,l,f,a...) do { \ struct nvkm_ior *_ior = (i); \ @@ -197,9 +203,12 @@ int gf119_sor_new(struct nvkm_disp *, int); int gk104_sor_new(struct nvkm_disp *, int); int gm107_sor_new(struct nvkm_disp *, int); int gm200_sor_new(struct nvkm_disp *, int); +int gp100_sor_new(struct nvkm_disp *, int); int gv100_sor_cnt(struct nvkm_disp *, unsigned long *); int gv100_sor_new(struct nvkm_disp *, int); int tu102_sor_new(struct nvkm_disp *, int); + +int ga102_sor_new(struct nvkm_disp *, int); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c index cfdce23ab83a..762a59f24bbb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c @@ -39,7 +39,8 @@ mcp77_disp = { }; int -mcp77_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +mcp77_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&mcp77_disp, device, index, pdisp); + return nv50_disp_new_(&mcp77_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c index 85d9329cfa0e..e5c58aae15de 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c @@ -39,7 +39,8 @@ mcp89_disp = { }; int -mcp89_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +mcp89_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&mcp89_disp, device, index, pdisp); + return nv50_disp_new_(&mcp89_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c index b780ba1a3bc7..a12097db2c2a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c @@ -64,11 +64,12 @@ nv04_disp = { }; int -nv04_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +nv04_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { int ret, i; - ret = nvkm_disp_new_(&nv04_disp, device, index, pdisp); + ret = nvkm_disp_new_(&nv04_disp, device, type, inst, pdisp); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c index e21556bf2cb1..3f20e49070ce 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c @@ -154,7 +154,7 @@ nv50_disp_ = { int nv50_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device, - int index, struct nvkm_disp **pdisp) + enum nvkm_subdev_type type, int inst, struct nvkm_disp **pdisp) { struct nv50_disp *disp; int ret; @@ -164,7 +164,7 @@ nv50_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device, disp->func = func; *pdisp = &disp->base; - ret = nvkm_disp_ctor(&nv50_disp_, device, index, &disp->base); + ret = nvkm_disp_ctor(&nv50_disp_, device, type, inst, &disp->base); if (ret) return ret; @@ -769,7 +769,8 @@ nv50_disp = { }; int -nv50_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +nv50_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&nv50_disp, device, index, pdisp); + return nv50_disp_new_(&nv50_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h index a677161c7f3a..025cacd7c3b0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h @@ -47,8 +47,8 @@ void nv50_disp_super_2_1(struct nv50_disp *, struct nvkm_head *); void nv50_disp_super_2_2(struct nv50_disp *, struct nvkm_head *); void nv50_disp_super_3_0(struct nv50_disp *, struct nvkm_head *); -int nv50_disp_new_(const struct nv50_disp_func *, struct nvkm_device *, - int index, struct nvkm_disp **); +int nv50_disp_new_(const struct nv50_disp_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_disp **); struct nv50_disp_func { int (*init)(struct nv50_disp *); @@ -86,6 +86,8 @@ void gv100_disp_intr(struct nv50_disp *); void gv100_disp_super(struct work_struct *); int gv100_disp_wndw_cnt(struct nvkm_disp *, unsigned long *); +int tu102_disp_init(struct nv50_disp *); + void nv50_disp_dptmds_war_2(struct nv50_disp *, struct dcb_output *); void nv50_disp_dptmds_war_3(struct nv50_disp *, struct dcb_output *); void nv50_disp_update_sppll1(struct nv50_disp *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c index c62030c96fba..129982fef7ef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c @@ -22,6 +22,7 @@ * Authors: Ben Skeggs */ #include "outp.h" +#include "dp.h" #include "ior.h" #include <subdev/bios.h> @@ -111,8 +112,35 @@ nvkm_outp_acquire_ior(struct nvkm_outp *outp, u8 user, struct nvkm_ior *ior) return 0; } +static inline int +nvkm_outp_acquire_hda(struct nvkm_outp *outp, enum nvkm_ior_type type, + u8 user, bool hda) +{ + struct nvkm_ior *ior; + + /* Failing that, a completely unused OR is the next best thing. */ + list_for_each_entry(ior, &outp->disp->ior, head) { + if (!ior->identity && !!ior->func->hda.hpd == hda && + !ior->asy.outp && ior->type == type && !ior->arm.outp && + (ior->func->route.set || ior->id == __ffs(outp->info.or))) + return nvkm_outp_acquire_ior(outp, user, ior); + } + + /* Last resort is to assign an OR that's already active on HW, + * but will be released during the next modeset. + */ + list_for_each_entry(ior, &outp->disp->ior, head) { + if (!ior->identity && !!ior->func->hda.hpd == hda && + !ior->asy.outp && ior->type == type && + (ior->func->route.set || ior->id == __ffs(outp->info.or))) + return nvkm_outp_acquire_ior(outp, user, ior); + } + + return -ENOSPC; +} + int -nvkm_outp_acquire(struct nvkm_outp *outp, u8 user) +nvkm_outp_acquire(struct nvkm_outp *outp, u8 user, bool hda) { struct nvkm_ior *ior = outp->ior; enum nvkm_ior_proto proto; @@ -141,28 +169,42 @@ nvkm_outp_acquire(struct nvkm_outp *outp, u8 user) * on HW, if any, in order to prevent unnecessary switching. */ list_for_each_entry(ior, &outp->disp->ior, head) { - if (!ior->identity && !ior->asy.outp && ior->arm.outp == outp) - return nvkm_outp_acquire_ior(outp, user, ior); - } - - /* Failing that, a completely unused OR is the next best thing. */ - list_for_each_entry(ior, &outp->disp->ior, head) { - if (!ior->identity && - !ior->asy.outp && ior->type == type && !ior->arm.outp && - (ior->func->route.set || ior->id == __ffs(outp->info.or))) + if (!ior->identity && !ior->asy.outp && ior->arm.outp == outp) { + /*XXX: For various complicated reasons, we can't outright switch + * the boot-time OR on the first modeset without some fairly + * invasive changes. + * + * The systems that were fixed by modifying the OR selection + * code to account for HDA support shouldn't regress here as + * the HDA-enabled ORs match the relevant output's pad macro + * index, and the firmware seems to select an OR this way. + * + * This warning is to make it obvious if that proves wrong. + */ + WARN_ON(hda && !ior->func->hda.hpd); return nvkm_outp_acquire_ior(outp, user, ior); + } } - /* Last resort is to assign an OR that's already active on HW, - * but will be released during the next modeset. + /* If we don't need HDA, first try to acquire an OR that doesn't + * support it to leave free the ones that do. */ - list_for_each_entry(ior, &outp->disp->ior, head) { - if (!ior->identity && !ior->asy.outp && ior->type == type && - (ior->func->route.set || ior->id == __ffs(outp->info.or))) - return nvkm_outp_acquire_ior(outp, user, ior); + if (!hda) { + if (!nvkm_outp_acquire_hda(outp, type, user, false)) + return 0; + + /* Use a HDA-supporting SOR anyway. */ + return nvkm_outp_acquire_hda(outp, type, user, true); } - return -ENOSPC; + /* We want HDA, try to acquire an OR that supports it. */ + if (!nvkm_outp_acquire_hda(outp, type, user, true)) + return 0; + + /* There weren't any free ORs that support HDA, grab one that + * doesn't and at least allow display to work still. + */ + return nvkm_outp_acquire_hda(outp, type, user, false); } void @@ -216,6 +258,14 @@ nvkm_outp_init_route(struct nvkm_outp *outp) if (!ior->arm.head || ior->arm.proto != proto) { OUTP_DBG(outp, "no heads (%x %d %d)", ior->arm.head, ior->arm.proto, proto); + + /* The EFI GOP driver on Ampere can leave unused DP links routed, + * which we don't expect. The DisableLT IED script *should* get + * us back to where we need to be. + */ + if (ior->func->route.get && !ior->arm.head && outp->info.type == DCB_OUTPUT_DP) + nvkm_dp_disable(outp, ior); + return; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h index 721b068b87ef..ee028d30cfe7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h @@ -32,7 +32,7 @@ int nvkm_outp_new(struct nvkm_disp *, int index, struct dcb_output *, void nvkm_outp_del(struct nvkm_outp **); void nvkm_outp_init(struct nvkm_outp *); void nvkm_outp_fini(struct nvkm_outp *); -int nvkm_outp_acquire(struct nvkm_outp *, u8 user); +int nvkm_outp_acquire(struct nvkm_outp *, u8 user, bool hda); void nvkm_outp_release(struct nvkm_outp *, u8 user); void nvkm_outp_route(struct nvkm_disp *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h index f815a5342880..ec57d8b6bce9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h @@ -4,10 +4,10 @@ #include <engine/disp.h> #include "outp.h" -int nvkm_disp_ctor(const struct nvkm_disp_func *, struct nvkm_device *, - int index, struct nvkm_disp *); -int nvkm_disp_new_(const struct nvkm_disp_func *, struct nvkm_device *, - int index, struct nvkm_disp **); +int nvkm_disp_ctor(const struct nvkm_disp_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_disp *); +int nvkm_disp_new_(const struct nvkm_disp_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_disp **); void nvkm_disp_vblank(struct nvkm_disp *, int head); struct nvkm_disp_func { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootga102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootga102.c new file mode 100644 index 000000000000..9af07c3cf9fc --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootga102.c @@ -0,0 +1,52 @@ +/* + * Copyright 2021 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "rootnv50.h" +#include "channv50.h" + +#include <nvif/class.h> + +static const struct nv50_disp_root_func +ga102_disp_root = { + .user = { + {{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new }, + {{0,0,GA102_DISP_CURSOR }, gv100_disp_curs_new }, + {{0,0,GA102_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new }, + {{0,0,GA102_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new }, + {{0,0,GA102_DISP_WINDOW_CHANNEL_DMA }, gv100_disp_wndw_new }, + {} + }, +}; + +static int +ga102_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, + void *data, u32 size, struct nvkm_object **pobject) +{ + return nv50_disp_root_new_(&ga102_disp_root, disp, oclass, data, size, pobject); +} + +const struct nvkm_disp_oclass +ga102_disp_root_oclass = { + .base.oclass = GA102_DISP, + .base.minver = -1, + .base.maxver = -1, + .ctor = ga102_disp_root_new, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c index 9c658d632d37..47efb48d769a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c @@ -27,6 +27,7 @@ static const struct nv50_disp_root_func gv100_disp_root = { .user = { + {{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new }, {{0,0,GV100_DISP_CURSOR }, gv100_disp_curs_new }, {{0,0,GV100_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new }, {{0,0,GV100_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c index 5f758948d6e1..ecde98dd2454 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c @@ -99,7 +99,7 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) } *args = data; int ret = -ENOSYS; if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { - ret = nvkm_outp_acquire(outp, NVKM_OUTP_USER); + ret = nvkm_outp_acquire(outp, NVKM_OUTP_USER, args->v0.hda); if (ret == 0) { args->v0.or = outp->ior->id; args->v0.link = outp->ior->asy.link; @@ -119,7 +119,7 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { if (args->v0.data & 0xfff00000) return -EINVAL; - ret = nvkm_outp_acquire(outp, NVKM_OUTP_PRIV); + ret = nvkm_outp_acquire(outp, NVKM_OUTP_PRIV, false); if (ret) return ret; ret = outp->ior->func->sense(outp->ior, args->v0.data); @@ -155,7 +155,7 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) if (outp->info.type == DCB_OUTPUT_DP) ior->func->dp.audio(ior, hidx, true); ior->func->hda.hpd(ior, hidx, true); - ior->func->hda.eld(ior, data, size); + ior->func->hda.eld(ior, hidx, data, size); } else { if (outp->info.type == DCB_OUTPUT_DP) ior->func->dp.audio(ior, hidx, false); @@ -205,8 +205,7 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) vendor, vendor_size); if (outp->ior->func->hdmi.scdc) - outp->ior->func->hdmi.scdc( - outp->ior, hidx, args->v0.scdc); + outp->ior->func->hdmi.scdc(outp->ior, args->v0.scdc); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h index a1f942793f98..27bb170d0293 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h @@ -24,6 +24,9 @@ int nv50_disp_root_new_(const struct nv50_disp_root_func *, struct nvkm_disp *, const struct nvkm_oclass *, void *data, u32 size, struct nvkm_object **); +int gv100_disp_caps_new(const struct nvkm_oclass *, void *, u32, + struct nv50_disp *, struct nvkm_object **); + extern const struct nvkm_disp_oclass nv50_disp_root_oclass; extern const struct nvkm_disp_oclass g84_disp_root_oclass; extern const struct nvkm_disp_oclass g94_disp_root_oclass; @@ -38,4 +41,5 @@ extern const struct nvkm_disp_oclass gp100_disp_root_oclass; extern const struct nvkm_disp_oclass gp102_disp_root_oclass; extern const struct nvkm_disp_oclass gv100_disp_root_oclass; extern const struct nvkm_disp_oclass tu102_disp_root_oclass; +extern const struct nvkm_disp_oclass ga102_disp_root_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c index 579a5d02308a..d8719d38b98a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c @@ -27,6 +27,7 @@ static const struct nv50_disp_root_func tu102_disp_root = { .user = { + {{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new }, {{0,0,TU102_DISP_CURSOR }, gv100_disp_curs_new }, {{0,0,TU102_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new }, {{0,0,TU102_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c index 4d59d02525d9..56b8f4411988 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c @@ -77,7 +77,18 @@ g94_sor_dp_pattern(struct nvkm_ior *sor, int pattern) { struct nvkm_device *device = sor->disp->engine.subdev.device; const u32 loff = nv50_sor_link(sor); - nvkm_mask(device, 0x61c10c + loff, 0x0f000000, pattern << 24); + u32 data; + + switch (pattern) { + case 0: data = 0x00001000; break; + case 1: data = 0x01000000; break; + case 2: data = 0x02000000; break; + default: + WARN_ON(1); + return; + } + + nvkm_mask(device, 0x61c10c + loff, 0x0f001000, data); } void diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorga102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorga102.c new file mode 100644 index 000000000000..d2c05f5c4aa0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorga102.c @@ -0,0 +1,144 @@ +/* + * Copyright 2021 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "ior.h" + +#include <subdev/timer.h> + +static int +ga102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux) +{ + struct nvkm_device *device = sor->disp->engine.subdev.device; + const u32 soff = nv50_ior_base(sor); + const u32 loff = nv50_sor_link(sor); + u32 dpctrl = 0x00000000; + u32 clksor = 0x00000000; + + switch (sor->dp.bw) { + case 0x06: clksor |= 0x00000000; break; + case 0x0a: clksor |= 0x00040000; break; + case 0x14: clksor |= 0x00080000; break; + case 0x1e: clksor |= 0x000c0000; break; + case 0x08: clksor |= 0x00100000; break; + case 0x09: clksor |= 0x00140000; break; + case 0x0c: clksor |= 0x00180000; break; + case 0x10: clksor |= 0x001c0000; break; + default: + WARN_ON(1); + return -EINVAL; + } + + dpctrl |= ((1 << sor->dp.nr) - 1) << 16; + if (sor->dp.mst) + dpctrl |= 0x40000000; + if (sor->dp.ef) + dpctrl |= 0x00004000; + + nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor); + + /*XXX*/ + nvkm_msec(device, 40, NVKM_DELAY); + nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000); + nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001); + + nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl); + return 0; +} + +static void +ga102_sor_clock(struct nvkm_ior *sor) +{ + struct nvkm_device *device = sor->disp->engine.subdev.device; + u32 div2 = 0; + if (sor->asy.proto == TMDS) { + if (sor->tmds.high_speed) + div2 = 1; + } + nvkm_wr32(device, 0x00ec08 + (sor->id * 0x10), 0x00000000); + nvkm_wr32(device, 0x00ec04 + (sor->id * 0x10), div2); +} + +static const struct nvkm_ior_func +ga102_sor_hda = { + .route = { + .get = gm200_sor_route_get, + .set = gm200_sor_route_set, + }, + .state = gv100_sor_state, + .power = nv50_sor_power, + .clock = ga102_sor_clock, + .hdmi = { + .ctrl = gv100_hdmi_ctrl, + .scdc = gm200_hdmi_scdc, + }, + .dp = { + .lanes = { 0, 1, 2, 3 }, + .links = ga102_sor_dp_links, + .power = g94_sor_dp_power, + .pattern = gm107_sor_dp_pattern, + .drive = gm200_sor_dp_drive, + .vcpi = tu102_sor_dp_vcpi, + .audio = gv100_sor_dp_audio, + .audio_sym = gv100_sor_dp_audio_sym, + .watermark = gv100_sor_dp_watermark, + }, + .hda = { + .hpd = gf119_hda_hpd, + .eld = gf119_hda_eld, + .device_entry = gv100_hda_device_entry, + }, +}; + +static const struct nvkm_ior_func +ga102_sor = { + .route = { + .get = gm200_sor_route_get, + .set = gm200_sor_route_set, + }, + .state = gv100_sor_state, + .power = nv50_sor_power, + .clock = ga102_sor_clock, + .hdmi = { + .ctrl = gv100_hdmi_ctrl, + .scdc = gm200_hdmi_scdc, + }, + .dp = { + .lanes = { 0, 1, 2, 3 }, + .links = ga102_sor_dp_links, + .power = g94_sor_dp_power, + .pattern = gm107_sor_dp_pattern, + .drive = gm200_sor_dp_drive, + .vcpi = tu102_sor_dp_vcpi, + .audio = gv100_sor_dp_audio, + .audio_sym = gv100_sor_dp_audio_sym, + .watermark = gv100_sor_dp_watermark, + }, +}; + +int +ga102_sor_new(struct nvkm_disp *disp, int id) +{ + struct nvkm_device *device = disp->engine.subdev.device; + u32 hda = nvkm_rd32(device, 0x08a15c); + if (hda & BIT(id)) + return nvkm_ior_new_(&ga102_sor_hda, disp, SOR, id); + return nvkm_ior_new_(&ga102_sor, disp, SOR, id); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c index 456a5a143522..c431e0b9fc11 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c @@ -92,7 +92,19 @@ gf119_sor_dp_pattern(struct nvkm_ior *sor, int pattern) { struct nvkm_device *device = sor->disp->engine.subdev.device; const u32 soff = nv50_ior_base(sor); - nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, 0x01010101 * pattern); + u32 data; + + switch (pattern) { + case 0: data = 0x10101010; break; + case 1: data = 0x01010101; break; + case 2: data = 0x02020202; break; + case 3: data = 0x03030303; break; + default: + WARN_ON(1); + return; + } + + nvkm_mask(device, 0x61c110 + soff, 0x1f1f1f1f, data); } int @@ -177,6 +189,7 @@ gf119_sor = { .hda = { .hpd = gf119_hda_hpd, .eld = gf119_hda_eld, + .device_entry = gf119_hda_device_entry, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgk104.c index b94090edaebf..0c0925680790 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgk104.c @@ -43,6 +43,7 @@ gk104_sor = { .hda = { .hpd = gf119_hda_hpd, .eld = gf119_hda_eld, + .device_entry = gf119_hda_device_entry, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c index e6965dec09c9..3696bfd3bfd7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c @@ -28,11 +28,23 @@ gm107_sor_dp_pattern(struct nvkm_ior *sor, int pattern) { struct nvkm_device *device = sor->disp->engine.subdev.device; const u32 soff = nv50_ior_base(sor); - const u32 data = 0x01010101 * pattern; + u32 mask = 0x1f1f1f1f, data; + + switch (pattern) { + case 0: data = 0x10101010; break; + case 1: data = 0x01010101; break; + case 2: data = 0x02020202; break; + case 3: data = 0x03030303; break; + case 4: data = 0x1b1b1b1b; break; + default: + WARN_ON(1); + return; + } + if (sor->asy.link & 1) - nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, data); + nvkm_mask(device, 0x61c110 + soff, mask, data); else - nvkm_mask(device, 0x61c12c + soff, 0x0f0f0f0f, data); + nvkm_mask(device, 0x61c12c + soff, mask, data); } static const struct nvkm_ior_func @@ -57,6 +69,7 @@ gm107_sor = { .hda = { .hpd = gf119_hda_hpd, .eld = gf119_hda_eld, + .device_entry = gf119_hda_device_entry, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c index 384f82652bec..4dd7f382968e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c @@ -89,7 +89,7 @@ gm200_sor_route_get(struct nvkm_outp *outp, int *link) } static const struct nvkm_ior_func -gm200_sor = { +gm200_sor_hda = { .route = { .get = gm200_sor_route_get, .set = gm200_sor_route_set, @@ -115,11 +115,46 @@ gm200_sor = { .hda = { .hpd = gf119_hda_hpd, .eld = gf119_hda_eld, + .device_entry = gf119_hda_device_entry, + }, +}; + +static const struct nvkm_ior_func +gm200_sor = { + .route = { + .get = gm200_sor_route_get, + .set = gm200_sor_route_set, + }, + .state = gf119_sor_state, + .power = nv50_sor_power, + .clock = gf119_sor_clock, + .hdmi = { + .ctrl = gk104_hdmi_ctrl, + .scdc = gm200_hdmi_scdc, + }, + .dp = { + .lanes = { 0, 1, 2, 3 }, + .links = gf119_sor_dp_links, + .power = g94_sor_dp_power, + .pattern = gm107_sor_dp_pattern, + .drive = gm200_sor_dp_drive, + .vcpi = gf119_sor_dp_vcpi, + .audio = gf119_sor_dp_audio, + .audio_sym = gf119_sor_dp_audio_sym, + .watermark = gf119_sor_dp_watermark, }, }; int gm200_sor_new(struct nvkm_disp *disp, int id) { + struct nvkm_device *device = disp->engine.subdev.device; + u32 hda; + + if (!((hda = nvkm_rd32(device, 0x08a15c)) & 0x40000000)) + hda = nvkm_rd32(device, 0x101034); + + if (hda & BIT(id)) + return nvkm_ior_new_(&gm200_sor_hda, disp, SOR, id); return nvkm_ior_new_(&gm200_sor, disp, SOR, id); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgp100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgp100.c new file mode 100644 index 000000000000..c54f88317a07 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgp100.c @@ -0,0 +1,93 @@ +/* + * Copyright 2020 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "ior.h" + +static const struct nvkm_ior_func +gp100_sor_hda = { + .route = { + .get = gm200_sor_route_get, + .set = gm200_sor_route_set, + }, + .state = gf119_sor_state, + .power = nv50_sor_power, + .clock = gf119_sor_clock, + .hdmi = { + .ctrl = gk104_hdmi_ctrl, + .scdc = gm200_hdmi_scdc, + }, + .dp = { + .lanes = { 0, 1, 2, 3 }, + .links = gf119_sor_dp_links, + .power = g94_sor_dp_power, + .pattern = gm107_sor_dp_pattern, + .drive = gm200_sor_dp_drive, + .vcpi = gf119_sor_dp_vcpi, + .audio = gf119_sor_dp_audio, + .audio_sym = gf119_sor_dp_audio_sym, + .watermark = gf119_sor_dp_watermark, + }, + .hda = { + .hpd = gf119_hda_hpd, + .eld = gf119_hda_eld, + .device_entry = gf119_hda_device_entry, + }, +}; + +static const struct nvkm_ior_func +gp100_sor = { + .route = { + .get = gm200_sor_route_get, + .set = gm200_sor_route_set, + }, + .state = gf119_sor_state, + .power = nv50_sor_power, + .clock = gf119_sor_clock, + .hdmi = { + .ctrl = gk104_hdmi_ctrl, + .scdc = gm200_hdmi_scdc, + }, + .dp = { + .lanes = { 0, 1, 2, 3 }, + .links = gf119_sor_dp_links, + .power = g94_sor_dp_power, + .pattern = gm107_sor_dp_pattern, + .drive = gm200_sor_dp_drive, + .vcpi = gf119_sor_dp_vcpi, + .audio = gf119_sor_dp_audio, + .audio_sym = gf119_sor_dp_audio_sym, + .watermark = gf119_sor_dp_watermark, + }, +}; + +int +gp100_sor_new(struct nvkm_disp *disp, int id) +{ + struct nvkm_device *device = disp->engine.subdev.device; + u32 hda; + + if (!((hda = nvkm_rd32(device, 0x08a15c)) & 0x40000000)) + hda = nvkm_rd32(device, 0x10ebb0) >> 8; + + if (hda & BIT(id)) + return nvkm_ior_new_(&gp100_sor_hda, disp, SOR, id); + return nvkm_ior_new_(&gp100_sor, disp, SOR, id); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c index b0597ff9a714..4441187e8ec9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c @@ -78,7 +78,7 @@ gv100_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state) } static const struct nvkm_ior_func -gv100_sor = { +gv100_sor_hda = { .route = { .get = gm200_sor_route_get, .set = gm200_sor_route_set, @@ -103,12 +103,46 @@ gv100_sor = { .hda = { .hpd = gf119_hda_hpd, .eld = gf119_hda_eld, + .device_entry = gv100_hda_device_entry, + }, +}; + +static const struct nvkm_ior_func +gv100_sor = { + .route = { + .get = gm200_sor_route_get, + .set = gm200_sor_route_set, + }, + .state = gv100_sor_state, + .power = nv50_sor_power, + .clock = gf119_sor_clock, + .hdmi = { + .ctrl = gv100_hdmi_ctrl, + .scdc = gm200_hdmi_scdc, + }, + .dp = { + .lanes = { 0, 1, 2, 3 }, + .links = gf119_sor_dp_links, + .power = g94_sor_dp_power, + .pattern = gm107_sor_dp_pattern, + .drive = gm200_sor_dp_drive, + .audio = gv100_sor_dp_audio, + .audio_sym = gv100_sor_dp_audio_sym, + .watermark = gv100_sor_dp_watermark, }, }; int gv100_sor_new(struct nvkm_disp *disp, int id) { + struct nvkm_device *device = disp->engine.subdev.device; + u32 hda; + + if (!((hda = nvkm_rd32(device, 0x08a15c)) & 0x40000000)) + hda = nvkm_rd32(device, 0x118fb0) >> 8; + + if (hda & BIT(id)) + return nvkm_ior_new_(&gv100_sor_hda, disp, SOR, id); return nvkm_ior_new_(&gv100_sor, disp, SOR, id); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c index 4d5f3791ea7b..0cf9e8752d25 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c @@ -23,7 +23,7 @@ #include <subdev/timer.h> -static void +void tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head, u8 slot, u8 slot_nr, u16 pbn, u16 aligned) { @@ -62,7 +62,7 @@ tu102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux) } static const struct nvkm_ior_func -tu102_sor = { +tu102_sor_hda = { .route = { .get = gm200_sor_route_get, .set = gm200_sor_route_set, @@ -88,11 +88,42 @@ tu102_sor = { .hda = { .hpd = gf119_hda_hpd, .eld = gf119_hda_eld, + .device_entry = gv100_hda_device_entry, + }, +}; + +static const struct nvkm_ior_func +tu102_sor = { + .route = { + .get = gm200_sor_route_get, + .set = gm200_sor_route_set, + }, + .state = gv100_sor_state, + .power = nv50_sor_power, + .clock = gf119_sor_clock, + .hdmi = { + .ctrl = gv100_hdmi_ctrl, + .scdc = gm200_hdmi_scdc, + }, + .dp = { + .lanes = { 0, 1, 2, 3 }, + .links = tu102_sor_dp_links, + .power = g94_sor_dp_power, + .pattern = gm107_sor_dp_pattern, + .drive = gm200_sor_dp_drive, + .vcpi = tu102_sor_dp_vcpi, + .audio = gv100_sor_dp_audio, + .audio_sym = gv100_sor_dp_audio_sym, + .watermark = gv100_sor_dp_watermark, }, }; int tu102_sor_new(struct nvkm_disp *disp, int id) { + struct nvkm_device *device = disp->engine.subdev.device; + u32 hda = nvkm_rd32(device, 0x08a15c); + if (hda & BIT(id)) + return nvkm_ior_new_(&tu102_sor_hda, disp, SOR, id); return nvkm_ior_new_(&tu102_sor, disp, SOR, id); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c index 883ae4151ff8..f5f8dc8e8f35 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c @@ -28,7 +28,7 @@ #include <core/gpuobj.h> #include <subdev/timer.h> -static int +int tu102_disp_init(struct nv50_disp *disp) { struct nvkm_device *device = disp->base.engine.subdev.device; @@ -146,7 +146,8 @@ tu102_disp = { }; int -tu102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +tu102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&tu102_disp, device, index, pdisp); + return nv50_disp_new_(&tu102_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c index 89d783368b4f..bb4db6351ddf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c @@ -35,7 +35,7 @@ gv100_disp_wimm_intr(struct nv50_disp_chan *chan, bool en) nvkm_mask(device, 0x611da8, mask, data); } -const struct nv50_disp_chan_func +static const struct nv50_disp_chan_func gv100_disp_wimm = { .init = gv100_disp_dmac_init, .fini = gv100_disp_dmac_fini, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c index 5d3b641dbb14..e635247d794f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c @@ -116,7 +116,7 @@ gv100_disp_wndw_mthd_base = { } }; -const struct nv50_disp_chan_mthd +static const struct nv50_disp_chan_mthd gv100_disp_wndw_mthd = { .name = "Window", .addr = 0x001000, @@ -136,7 +136,7 @@ gv100_disp_wndw_intr(struct nv50_disp_chan *chan, bool en) nvkm_mask(device, 0x611da4, mask, data); } -const struct nv50_disp_chan_func +static const struct nv50_disp_chan_func gv100_disp_wndw = { .init = gv100_disp_dmac_init, .fini = gv100_disp_dmac_fini, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c index 11b7b8fd5dda..425cde35f128 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c @@ -104,7 +104,7 @@ nvkm_dma = { int nvkm_dma_new_(const struct nvkm_dma_func *func, struct nvkm_device *device, - int index, struct nvkm_dma **pdma) + enum nvkm_subdev_type type, int inst, struct nvkm_dma **pdma) { struct nvkm_dma *dma; @@ -112,5 +112,5 @@ nvkm_dma_new_(const struct nvkm_dma_func *func, struct nvkm_device *device, return -ENOMEM; dma->func = func; - return nvkm_engine_ctor(&nvkm_dma, device, index, true, &dma->engine); + return nvkm_engine_ctor(&nvkm_dma, device, type, inst, true, &dma->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c index efec5d322179..99a1e07fa204 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c @@ -30,7 +30,8 @@ gf100_dma = { }; int -gf100_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +gf100_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_dma **pdma) { - return nvkm_dma_new_(&gf100_dma, device, index, pdma); + return nvkm_dma_new_(&gf100_dma, device, type, inst, pdma); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c index 34c766039aed..fd1d1fc22dc6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c @@ -30,7 +30,8 @@ gf119_dma = { }; int -gf119_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +gf119_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_dma **pdma) { - return nvkm_dma_new_(&gf119_dma, device, index, pdma); + return nvkm_dma_new_(&gf119_dma, device, type, inst, pdma); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.c index c65a4c2ea93d..a5af0df30663 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.c @@ -28,7 +28,8 @@ gv100_dma = { }; int -gv100_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +gv100_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_dma **pdma) { - return nvkm_dma_new_(&gv100_dma, device, index, pdma); + return nvkm_dma_new_(&gv100_dma, device, type, inst, pdma); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c index 30747a0ce488..ea5a889f60c2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c @@ -30,7 +30,8 @@ nv04_dma = { }; int -nv04_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +nv04_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_dma **pdma) { - return nvkm_dma_new_(&nv04_dma, device, index, pdma); + return nvkm_dma_new_(&nv04_dma, device, type, inst, pdma); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c index 77aca7b71c83..6e8f79660014 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c @@ -30,7 +30,8 @@ nv50_dma = { }; int -nv50_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +nv50_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_dma **pdma) { - return nvkm_dma_new_(&nv50_dma, device, index, pdma); + return nvkm_dma_new_(&nv50_dma, device, type, inst, pdma); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h index 0c9d9640a59d..d403bedb485a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h @@ -9,8 +9,8 @@ struct nvkm_dmaobj_func { struct nvkm_gpuobj **); }; -int nvkm_dma_new_(const struct nvkm_dma_func *, struct nvkm_device *, - int index, struct nvkm_dma **); +int nvkm_dma_new_(const struct nvkm_dma_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_dma **); struct nvkm_dma_func { int (*class_new)(struct nvkm_dma *, const struct nvkm_oclass *, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c index d20cc0681a88..797131ed7d67 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c @@ -26,7 +26,6 @@ #include <core/client.h> #include <core/gpuobj.h> #include <subdev/fb.h> -#include <subdev/instmem.h> #include <nvif/cl0002.h> #include <nvif/unpack.h> @@ -72,11 +71,7 @@ nvkm_dmaobj_ctor(const struct nvkm_dmaobj_func *func, struct nvkm_dma *dma, union { struct nv_dma_v0 v0; } *args = *pdata; - struct nvkm_device *device = dma->engine.subdev.device; - struct nvkm_client *client = oclass->client; struct nvkm_object *parent = oclass->parent; - struct nvkm_instmem *instmem = device->imem; - struct nvkm_fb *fb = device->fb; void *data = *pdata; u32 size = *psize; int ret = -ENOSYS; @@ -109,23 +104,13 @@ nvkm_dmaobj_ctor(const struct nvkm_dmaobj_func *func, struct nvkm_dma *dma, dmaobj->target = NV_MEM_TARGET_VM; break; case NV_DMA_V0_TARGET_VRAM: - if (!client->super) { - if (dmaobj->limit >= fb->ram->size - instmem->reserved) - return -EACCES; - if (device->card_type >= NV_50) - return -EACCES; - } dmaobj->target = NV_MEM_TARGET_VRAM; break; case NV_DMA_V0_TARGET_PCI: - if (!client->super) - return -EACCES; dmaobj->target = NV_MEM_TARGET_PCI; break; case NV_DMA_V0_TARGET_PCI_US: case NV_DMA_V0_TARGET_AGP: - if (!client->super) - return -EACCES; dmaobj->target = NV_MEM_TARGET_PCI_NOSNOOP; break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c index 7f1adab21a5f..5159d5df20a2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c @@ -122,7 +122,7 @@ nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, break; case NV_MEM_ACCESS_WO: dmaobj->flags0 |= 0x00008000; - /* fall through */ + fallthrough; case NV_MEM_ACCESS_RW: dmaobj->flags2 |= 0x00000002; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c index 8675613e142b..43b7dec45179 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c @@ -108,7 +108,7 @@ nvkm_falcon_fini(struct nvkm_engine *engine, bool suspend) } } - if (nvkm_mc_enabled(device, engine->subdev.index)) { + if (nvkm_mc_enabled(device, engine->subdev.type, engine->subdev.inst)) { nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000); nvkm_wr32(device, base + 0x014, 0xffffffff); } @@ -335,9 +335,9 @@ nvkm_falcon = { }; int -nvkm_falcon_new_(const struct nvkm_falcon_func *func, - struct nvkm_device *device, int index, bool enable, - u32 addr, struct nvkm_engine **pengine) +nvkm_falcon_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, bool enable, u32 addr, + struct nvkm_engine **pengine) { struct nvkm_falcon *falcon; @@ -351,6 +351,5 @@ nvkm_falcon_new_(const struct nvkm_falcon_func *func, falcon->data.size = func->data.size; *pengine = &falcon->engine; - return nvkm_engine_ctor(&nvkm_falcon, device, index, - enable, &falcon->engine); + return nvkm_engine_ctor(&nvkm_falcon, device, type, inst, enable, &falcon->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild index 90e9a0972a44..5e831d347a95 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild @@ -18,6 +18,7 @@ nvkm-y += nvkm/engine/fifo/gp100.o nvkm-y += nvkm/engine/fifo/gp10b.o nvkm-y += nvkm/engine/fifo/gv100.o nvkm-y += nvkm/engine/fifo/tu102.o +nvkm-y += nvkm/engine/fifo/ga102.o nvkm-y += nvkm/engine/fifo/chan.o nvkm-y += nvkm/engine/fifo/channv50.o @@ -27,8 +28,6 @@ nvkm-y += nvkm/engine/fifo/dmanv04.o nvkm-y += nvkm/engine/fifo/dmanv10.o nvkm-y += nvkm/engine/fifo/dmanv17.o nvkm-y += nvkm/engine/fifo/dmanv40.o -nvkm-y += nvkm/engine/fifo/dmanv50.o -nvkm-y += nvkm/engine/fifo/dmag84.o nvkm-y += nvkm/engine/fifo/gpfifonv50.o nvkm-y += nvkm/engine/fifo/gpfifog84.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index c773caf21f6b..2ed4ff05d207 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -292,7 +292,7 @@ nvkm_fifo_info(struct nvkm_engine *engine, u64 mthd, u64 *data) { struct nvkm_fifo *fifo = nvkm_fifo(engine); switch (mthd) { - case NV_DEVICE_FIFO_CHANNELS: *data = fifo->nr; return 0; + case NV_DEVICE_HOST_CHANNELS: *data = fifo->nr; return 0; default: if (fifo->func->info) return fifo->func->info(fifo, mthd, data); @@ -313,7 +313,7 @@ nvkm_fifo_oneinit(struct nvkm_engine *engine) static void nvkm_fifo_preinit(struct nvkm_engine *engine) { - nvkm_mc_reset(engine->subdev.device, NVKM_ENGINE_FIFO); + nvkm_mc_reset(engine->subdev.device, NVKM_ENGINE_FIFO, 0); } static int @@ -334,6 +334,7 @@ nvkm_fifo_dtor(struct nvkm_engine *engine) nvkm_event_fini(&fifo->kevent); nvkm_event_fini(&fifo->cevent); nvkm_event_fini(&fifo->uevent); + mutex_destroy(&fifo->mutex); return data; } @@ -351,13 +352,14 @@ nvkm_fifo = { int nvkm_fifo_ctor(const struct nvkm_fifo_func *func, struct nvkm_device *device, - int index, int nr, struct nvkm_fifo *fifo) + enum nvkm_subdev_type type, int inst, int nr, struct nvkm_fifo *fifo) { int ret; fifo->func = func; INIT_LIST_HEAD(&fifo->chan); spin_lock_init(&fifo->lock); + mutex_init(&fifo->mutex); if (WARN_ON(fifo->nr > NVKM_FIFO_CHID_NR)) fifo->nr = NVKM_FIFO_CHID_NR; @@ -365,7 +367,7 @@ nvkm_fifo_ctor(const struct nvkm_fifo_func *func, struct nvkm_device *device, fifo->nr = nr; bitmap_clear(fifo->mask, 0, fifo->nr); - ret = nvkm_engine_ctor(&nvkm_fifo, device, index, true, &fifo->engine); + ret = nvkm_engine_ctor(&nvkm_fifo, device, type, inst, true, &fifo->engine); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c index d83485385934..8d957643940a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c @@ -35,6 +35,15 @@ struct nvkm_fifo_chan_object { int hash; }; +static struct nvkm_fifo_engn * +nvkm_fifo_chan_engn(struct nvkm_fifo_chan *chan, struct nvkm_engine *engine) +{ + int engi = chan->fifo->func->engine_id(chan->fifo, engine); + if (engi >= 0) + return &chan->engn[engi]; + return NULL; +} + static int nvkm_fifo_chan_child_fini(struct nvkm_oproxy *base, bool suspend) { @@ -42,8 +51,8 @@ nvkm_fifo_chan_child_fini(struct nvkm_oproxy *base, bool suspend) container_of(base, typeof(*object), oproxy); struct nvkm_engine *engine = object->oproxy.object->engine; struct nvkm_fifo_chan *chan = object->chan; - struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; - const char *name = nvkm_subdev_name[engine->subdev.index]; + struct nvkm_fifo_engn *engn = nvkm_fifo_chan_engn(chan, engine); + const char *name = engine->subdev.name; int ret = 0; if (--engn->usecount) @@ -75,8 +84,8 @@ nvkm_fifo_chan_child_init(struct nvkm_oproxy *base) container_of(base, typeof(*object), oproxy); struct nvkm_engine *engine = object->oproxy.object->engine; struct nvkm_fifo_chan *chan = object->chan; - struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; - const char *name = nvkm_subdev_name[engine->subdev.index]; + struct nvkm_fifo_engn *engn = nvkm_fifo_chan_engn(chan, engine); + const char *name = engine->subdev.name; int ret; if (engn->usecount++) @@ -108,7 +117,7 @@ nvkm_fifo_chan_child_del(struct nvkm_oproxy *base) container_of(base, typeof(*object), oproxy); struct nvkm_engine *engine = object->oproxy.base.engine; struct nvkm_fifo_chan *chan = object->chan; - struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; + struct nvkm_fifo_engn *engn = nvkm_fifo_chan_engn(chan, engine); if (chan->func->object_dtor) chan->func->object_dtor(chan, object->hash); @@ -118,7 +127,7 @@ nvkm_fifo_chan_child_del(struct nvkm_oproxy *base) chan->func->engine_dtor(chan, engine); nvkm_object_del(&engn->object); if (chan->vmm) - atomic_dec(&chan->vmm->engref[engine->subdev.index]); + atomic_dec(&chan->vmm->engref[engine->subdev.type]); } } @@ -135,7 +144,7 @@ nvkm_fifo_chan_child_new(const struct nvkm_oclass *oclass, void *data, u32 size, { struct nvkm_engine *engine = oclass->engine; struct nvkm_fifo_chan *chan = nvkm_fifo_chan(oclass->parent); - struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; + struct nvkm_fifo_engn *engn = nvkm_fifo_chan_engn(chan, engine); struct nvkm_fifo_chan_object *object; int ret = 0; @@ -152,7 +161,7 @@ nvkm_fifo_chan_child_new(const struct nvkm_oclass *oclass, void *data, u32 size, }; if (chan->vmm) - atomic_inc(&chan->vmm->engref[engine->subdev.index]); + atomic_inc(&chan->vmm->engref[engine->subdev.type]); if (engine->func->fifo.cclass) { ret = engine->func->fifo.cclass(chan, &cclass, @@ -203,13 +212,12 @@ nvkm_fifo_chan_child_get(struct nvkm_object *object, int index, { struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object); struct nvkm_fifo *fifo = chan->fifo; - struct nvkm_device *device = fifo->engine.subdev.device; struct nvkm_engine *engine; - u64 mask = chan->engines; - int ret, i, c; + u32 engm = chan->engm; + int engi, ret, c; - for (; c = 0, i = __ffs64(mask), mask; mask &= ~(1ULL << i)) { - if (!(engine = nvkm_device_engine(device, i))) + for (; c = 0, engi = __ffs(engm), engm; engm &= ~(1ULL << engi)) { + if (!(engine = fifo->func->id_engine(fifo, engi))) continue; oclass->engine = engine; oclass->base.oclass = 0; @@ -352,7 +360,7 @@ nvkm_fifo_chan_func = { int nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, struct nvkm_fifo *fifo, u32 size, u32 align, bool zero, - u64 hvmm, u64 push, u64 engines, int bar, u32 base, + u64 hvmm, u64 push, u32 engm, int bar, u32 base, u32 user, const struct nvkm_oclass *oclass, struct nvkm_fifo_chan *chan) { @@ -365,7 +373,7 @@ nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, nvkm_object_ctor(&nvkm_fifo_chan_func, oclass, &chan->object); chan->func = func; chan->fifo = fifo; - chan->engines = engines; + chan->engm = engm; INIT_LIST_HEAD(&chan->head); /* instance memory */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h index 177e10562600..e53504354841 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h @@ -22,7 +22,7 @@ struct nvkm_fifo_chan_func { int nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *, struct nvkm_fifo *, u32 size, u32 align, bool zero, u64 vm, u64 push, - u64 engines, int bar, u32 base, u32 user, + u32 engm, int bar, u32 base, u32 user, const struct nvkm_oclass *, struct nvkm_fifo_chan *); struct nvkm_fifo_chan_oclass { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c index a5c998fe4485..3492c561f2cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c @@ -45,29 +45,9 @@ g84_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type, } static int -g84_fifo_chan_engine(struct nvkm_engine *engine) -{ - switch (engine->subdev.index) { - case NVKM_ENGINE_GR : return 0; - case NVKM_ENGINE_MPEG : - case NVKM_ENGINE_MSPPP : return 1; - case NVKM_ENGINE_CE0 : return 2; - case NVKM_ENGINE_VP : - case NVKM_ENGINE_MSPDEC: return 3; - case NVKM_ENGINE_CIPHER: - case NVKM_ENGINE_SEC : return 4; - case NVKM_ENGINE_BSP : - case NVKM_ENGINE_MSVLD : return 5; - default: - WARN_ON(1); - return 0; - } -} - -static int g84_fifo_chan_engine_addr(struct nvkm_engine *engine) { - switch (engine->subdev.index) { + switch (engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW : return -1; case NVKM_ENGINE_GR : return 0x0020; @@ -79,7 +59,7 @@ g84_fifo_chan_engine_addr(struct nvkm_engine *engine) case NVKM_ENGINE_MSVLD : return 0x0080; case NVKM_ENGINE_CIPHER: case NVKM_ENGINE_SEC : return 0x00a0; - case NVKM_ENGINE_CE0 : return 0x00c0; + case NVKM_ENGINE_CE : return 0x00c0; default: WARN_ON(1); return -1; @@ -102,7 +82,7 @@ g84_fifo_chan_engine_fini(struct nvkm_fifo_chan *base, if (offset < 0) return 0; - engn = g84_fifo_chan_engine(engine); + engn = fifo->base.func->engine_id(&fifo->base, engine) - 1; save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn); nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12); done = nvkm_msec(device, 2000, @@ -134,7 +114,7 @@ g84_fifo_chan_engine_init(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct nv50_fifo_chan *chan = nv50_fifo_chan(base); - struct nvkm_gpuobj *engn = chan->engn[engine->subdev.index]; + struct nvkm_gpuobj *engn = *nv50_fifo_chan_engine(chan, engine); u64 limit, start; int offset; @@ -162,12 +142,11 @@ g84_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, struct nvkm_object *object) { struct nv50_fifo_chan *chan = nv50_fifo_chan(base); - int engn = engine->subdev.index; if (g84_fifo_chan_engine_addr(engine) < 0) return 0; - return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); + return nvkm_object_bind(object, NULL, 0, nv50_fifo_chan_engine(chan, engine)); } static int @@ -178,14 +157,14 @@ g84_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, u32 handle = object->handle; u32 context; - switch (object->engine->subdev.index) { + switch (object->engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW : context = 0x00000000; break; case NVKM_ENGINE_GR : context = 0x00100000; break; case NVKM_ENGINE_MPEG : case NVKM_ENGINE_MSPPP : context = 0x00200000; break; case NVKM_ENGINE_ME : - case NVKM_ENGINE_CE0 : context = 0x00300000; break; + case NVKM_ENGINE_CE : context = 0x00300000; break; case NVKM_ENGINE_VP : case NVKM_ENGINE_MSPDEC: context = 0x00400000; break; case NVKM_ENGINE_CIPHER: @@ -241,20 +220,20 @@ g84_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vmm, u64 push, ret = nvkm_fifo_chan_ctor(&g84_fifo_chan_func, &fifo->base, 0x10000, 0x1000, false, vmm, push, - (1ULL << NVKM_ENGINE_BSP) | - (1ULL << NVKM_ENGINE_CE0) | - (1ULL << NVKM_ENGINE_CIPHER) | - (1ULL << NVKM_ENGINE_DMAOBJ) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_ME) | - (1ULL << NVKM_ENGINE_MPEG) | - (1ULL << NVKM_ENGINE_MSPDEC) | - (1ULL << NVKM_ENGINE_MSPPP) | - (1ULL << NVKM_ENGINE_MSVLD) | - (1ULL << NVKM_ENGINE_SEC) | - (1ULL << NVKM_ENGINE_SW) | - (1ULL << NVKM_ENGINE_VIC) | - (1ULL << NVKM_ENGINE_VP), + BIT(G84_FIFO_ENGN_SW) | + BIT(G84_FIFO_ENGN_GR) | + BIT(G84_FIFO_ENGN_MPEG) | + BIT(G84_FIFO_ENGN_MSPPP) | + BIT(G84_FIFO_ENGN_ME) | + BIT(G84_FIFO_ENGN_CE0) | + BIT(G84_FIFO_ENGN_VP) | + BIT(G84_FIFO_ENGN_MSPDEC) | + BIT(G84_FIFO_ENGN_CIPHER) | + BIT(G84_FIFO_ENGN_SEC) | + BIT(G84_FIFO_ENGN_VIC) | + BIT(G84_FIFO_ENGN_BSP) | + BIT(G84_FIFO_ENGN_MSVLD) | + BIT(G84_FIFO_ENGN_DMA), 0, 0xc00000, 0x2000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h index 7c125a15f963..f7ac1061fa84 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h @@ -12,10 +12,17 @@ struct gf100_fifo_chan { struct list_head head; bool killed; - struct { +#define GF100_FIFO_ENGN_GR 0 +#define GF100_FIFO_ENGN_MSPDEC 1 +#define GF100_FIFO_ENGN_MSPPP 2 +#define GF100_FIFO_ENGN_MSVLD 3 +#define GF100_FIFO_ENGN_CE0 4 +#define GF100_FIFO_ENGN_CE1 5 +#define GF100_FIFO_ENGN_SW 15 + struct gf100_fifo_engn { struct nvkm_gpuobj *inst; struct nvkm_vma *vma; - } engn[NVKM_SUBDEV_NR]; + } engn[NVKM_FIFO_ENGN_NR]; }; extern const struct nvkm_fifo_chan_oclass gf100_fifo_gpfifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h index 22698661aa85..cfbe096e604f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h @@ -16,10 +16,11 @@ struct gk104_fifo_chan { struct nvkm_memory *mthd; - struct { +#define GK104_FIFO_ENGN_SW 15 + struct gk104_fifo_engn { struct nvkm_gpuobj *inst; struct nvkm_vma *vma; - } engn[NVKM_SUBDEV_NR]; + } engn[NVKM_FIFO_ENGN_NR]; }; extern const struct nvkm_fifo_chan_func gk104_fifo_gpfifo_func; @@ -29,6 +30,7 @@ int gk104_fifo_gpfifo_new(struct gk104_fifo *, const struct nvkm_oclass *, void *gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan *); void gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *); void gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *); +struct gk104_fifo_engn *gk104_fifo_gpfifo_engine(struct gk104_fifo_chan *, struct nvkm_engine *); int gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *, struct nvkm_engine *, struct nvkm_object *); void gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h index 60ca79465aff..727bc8976b40 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h @@ -9,7 +9,11 @@ struct nv04_fifo_chan { struct nvkm_fifo_chan base; struct nv04_fifo *fifo; u32 ramfc; - struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR]; +#define NV04_FIFO_ENGN_SW 0 +#define NV04_FIFO_ENGN_GR 1 +#define NV04_FIFO_ENGN_MPEG 2 +#define NV04_FIFO_ENGN_DMA 3 + struct nvkm_gpuobj *engn[NVKM_FIFO_ENGN_NR]; }; extern const struct nvkm_fifo_chan_func nv04_fifo_dma_func; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c index 85f7dbf53c99..c44d7c81dd52 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c @@ -31,7 +31,7 @@ static int nv50_fifo_chan_engine_addr(struct nvkm_engine *engine) { - switch (engine->subdev.index) { + switch (engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW : return -1; case NVKM_ENGINE_GR : return 0x0000; @@ -42,6 +42,15 @@ nv50_fifo_chan_engine_addr(struct nvkm_engine *engine) } } +struct nvkm_gpuobj ** +nv50_fifo_chan_engine(struct nv50_fifo_chan *chan, struct nvkm_engine *engine) +{ + int engi = chan->base.fifo->func->engine_id(chan->base.fifo, engine); + if (engi >= 0) + return &chan->engn[engi]; + return NULL; +} + static int nv50_fifo_chan_engine_fini(struct nvkm_fifo_chan *base, struct nvkm_engine *engine, bool suspend) @@ -103,7 +112,7 @@ nv50_fifo_chan_engine_init(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct nv50_fifo_chan *chan = nv50_fifo_chan(base); - struct nvkm_gpuobj *engn = chan->engn[engine->subdev.index]; + struct nvkm_gpuobj *engn = *nv50_fifo_chan_engine(chan, engine); u64 limit, start; int offset; @@ -130,7 +139,7 @@ nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct nv50_fifo_chan *chan = nv50_fifo_chan(base); - nvkm_gpuobj_del(&chan->engn[engine->subdev.index]); + nvkm_gpuobj_del(nv50_fifo_chan_engine(chan, engine)); } static int @@ -139,12 +148,11 @@ nv50_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, struct nvkm_object *object) { struct nv50_fifo_chan *chan = nv50_fifo_chan(base); - int engn = engine->subdev.index; if (nv50_fifo_chan_engine_addr(engine) < 0) return 0; - return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); + return nvkm_object_bind(object, NULL, 0, nv50_fifo_chan_engine(chan, engine)); } void @@ -162,7 +170,7 @@ nv50_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, u32 handle = object->handle; u32 context; - switch (object->engine->subdev.index) { + switch (object->engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW : context = 0x00000000; break; case NVKM_ENGINE_GR : context = 0x00100000; break; @@ -240,10 +248,10 @@ nv50_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vmm, u64 push, ret = nvkm_fifo_chan_ctor(&nv50_fifo_chan_func, &fifo->base, 0x10000, 0x1000, false, vmm, push, - (1ULL << NVKM_ENGINE_DMAOBJ) | - (1ULL << NVKM_ENGINE_SW) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_MPEG), + BIT(NV50_FIFO_ENGN_SW) | + BIT(NV50_FIFO_ENGN_GR) | + BIT(NV50_FIFO_ENGN_MPEG) | + BIT(NV50_FIFO_ENGN_DMA), 0, 0xc00000, 0x2000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h index 5735ff72a9d1..3a95730d7ff5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h @@ -15,21 +15,39 @@ struct nv50_fifo_chan { struct nvkm_gpuobj *pgd; struct nvkm_ramht *ramht; - struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR]; +#define NV50_FIFO_ENGN_SW 0 +#define NV50_FIFO_ENGN_GR 1 +#define NV50_FIFO_ENGN_MPEG 2 +#define NV50_FIFO_ENGN_DMA 3 + +#define G84_FIFO_ENGN_SW 0 +#define G84_FIFO_ENGN_GR 1 +#define G84_FIFO_ENGN_MPEG 2 +#define G84_FIFO_ENGN_MSPPP 2 +#define G84_FIFO_ENGN_ME 3 +#define G84_FIFO_ENGN_CE0 3 +#define G84_FIFO_ENGN_VP 4 +#define G84_FIFO_ENGN_MSPDEC 4 +#define G84_FIFO_ENGN_CIPHER 5 +#define G84_FIFO_ENGN_SEC 5 +#define G84_FIFO_ENGN_VIC 5 +#define G84_FIFO_ENGN_BSP 6 +#define G84_FIFO_ENGN_MSVLD 6 +#define G84_FIFO_ENGN_DMA 7 + struct nvkm_gpuobj *engn[NVKM_FIFO_ENGN_NR]; }; int nv50_fifo_chan_ctor(struct nv50_fifo *, u64 vmm, u64 push, const struct nvkm_oclass *, struct nv50_fifo_chan *); void *nv50_fifo_chan_dtor(struct nvkm_fifo_chan *); void nv50_fifo_chan_fini(struct nvkm_fifo_chan *); +struct nvkm_gpuobj **nv50_fifo_chan_engine(struct nv50_fifo_chan *, struct nvkm_engine *); void nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *, struct nvkm_engine *); void nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *, int); int g84_fifo_chan_ctor(struct nv50_fifo *, u64 vmm, u64 push, const struct nvkm_oclass *, struct nv50_fifo_chan *); -extern const struct nvkm_fifo_chan_oclass nv50_fifo_dma_oclass; extern const struct nvkm_fifo_chan_oclass nv50_fifo_gpfifo_oclass; -extern const struct nvkm_fifo_chan_oclass g84_fifo_dma_oclass; extern const struct nvkm_fifo_chan_oclass g84_fifo_gpfifo_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c deleted file mode 100644 index fc34cddcd2f5..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include "channv50.h" - -#include <core/client.h> -#include <core/ramht.h> - -#include <nvif/class.h> -#include <nvif/cl826e.h> -#include <nvif/unpack.h> - -static int -g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, - void *data, u32 size, struct nvkm_object **pobject) -{ - struct nvkm_object *parent = oclass->parent; - union { - struct g82_channel_dma_v0 v0; - } *args = data; - struct nv50_fifo *fifo = nv50_fifo(base); - struct nv50_fifo_chan *chan; - int ret = -ENOSYS; - - nvif_ioctl(parent, "create channel dma size %d\n", size); - if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { - nvif_ioctl(parent, "create channel dma vers %d vmm %llx " - "pushbuf %llx offset %016llx\n", - args->v0.version, args->v0.vmm, args->v0.pushbuf, - args->v0.offset); - if (!args->v0.pushbuf) - return -EINVAL; - } else - return ret; - - if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) - return -ENOMEM; - *pobject = &chan->base.object; - - ret = g84_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf, - oclass, chan); - if (ret) - return ret; - - args->v0.chid = chan->base.chid; - - nvkm_kmap(chan->ramfc); - nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); - nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); - nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); - nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); - nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); - nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); - nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); - nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); - nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); - nvkm_wo32(chan->ramfc, 0x78, 0x00000000); - nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); - nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | - (4 << 24) /* SEARCH_FULL */ | - (chan->ramht->gpuobj->node->offset >> 4)); - nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10); - nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12); - nvkm_done(chan->ramfc); - return 0; -} - -const struct nvkm_fifo_chan_oclass -g84_fifo_dma_oclass = { - .base.oclass = G82_CHANNEL_DMA, - .base.minver = 0, - .base.maxver = 0, - .ctor = g84_fifo_dma_new, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c index c213122cf088..dbcdc5fab990 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c @@ -38,9 +38,9 @@ nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *base, int cookie) struct nv04_fifo_chan *chan = nv04_fifo_chan(base); struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; - mutex_lock(&chan->fifo->base.engine.subdev.mutex); + mutex_lock(&chan->fifo->base.mutex); nvkm_ramht_remove(imem->ramht, cookie); - mutex_unlock(&chan->fifo->base.engine.subdev.mutex); + mutex_unlock(&chan->fifo->base.mutex); } static int @@ -53,7 +53,7 @@ nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, u32 handle = object->handle; int hash; - switch (object->engine->subdev.index) { + switch (object->engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW : context |= 0x00000000; break; case NVKM_ENGINE_GR : context |= 0x00010000; break; @@ -63,10 +63,10 @@ nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, return -EINVAL; } - mutex_lock(&chan->fifo->base.engine.subdev.mutex); + mutex_lock(&chan->fifo->base.mutex); hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, handle, context); - mutex_unlock(&chan->fifo->base.engine.subdev.mutex); + mutex_unlock(&chan->fifo->base.mutex); return hash; } @@ -191,9 +191,9 @@ nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, 0x1000, 0x1000, false, 0, args->v0.pushbuf, - (1ULL << NVKM_ENGINE_DMAOBJ) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_SW), + BIT(NV04_FIFO_ENGN_SW) | + BIT(NV04_FIFO_ENGN_GR) | + BIT(NV04_FIFO_ENGN_DMA), 0, 0x800000, 0x10000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c index f5f355ff005d..07d80d54a07c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c @@ -62,9 +62,9 @@ nv10_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, 0x1000, 0x1000, false, 0, args->v0.pushbuf, - (1ULL << NVKM_ENGINE_DMAOBJ) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_SW), + BIT(NV04_FIFO_ENGN_SW) | + BIT(NV04_FIFO_ENGN_GR) | + BIT(NV04_FIFO_ENGN_DMA), 0, 0x800000, 0x10000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c index 7edc6a564b5d..edd70a114218 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c @@ -62,10 +62,10 @@ nv17_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, 0x1000, 0x1000, false, 0, args->v0.pushbuf, - (1ULL << NVKM_ENGINE_DMAOBJ) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_MPEG) | /* NV31- */ - (1ULL << NVKM_ENGINE_SW), + BIT(NV04_FIFO_ENGN_SW) | + BIT(NV04_FIFO_ENGN_GR) | + BIT(NV04_FIFO_ENGN_MPEG) | /* NV31- */ + BIT(NV04_FIFO_ENGN_DMA), 0, 0x800000, 0x10000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c index 5f722c6e8a2f..0411fb908457 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c @@ -35,7 +35,7 @@ static bool nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx) { - switch (engine->subdev.index) { + switch (engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW: return false; @@ -55,6 +55,15 @@ nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx) } } +static struct nvkm_gpuobj ** +nv40_fifo_dma_engn(struct nv04_fifo_chan *chan, struct nvkm_engine *engine) +{ + int engi = chan->base.fifo->func->engine_id(chan->base.fifo, engine); + if (engi >= 0) + return &chan->engn[engi]; + return NULL; +} + static int nv40_fifo_dma_engine_fini(struct nvkm_fifo_chan *base, struct nvkm_engine *engine, bool suspend) @@ -99,7 +108,7 @@ nv40_fifo_dma_engine_init(struct nvkm_fifo_chan *base, if (!nv40_fifo_dma_engine(engine, ®, &ctx)) return 0; - inst = chan->engn[engine->subdev.index]->addr >> 4; + inst = (*nv40_fifo_dma_engn(chan, engine))->addr >> 4; spin_lock_irqsave(&fifo->base.lock, flags); nvkm_mask(device, 0x002500, 0x00000001, 0x00000000); @@ -121,7 +130,7 @@ nv40_fifo_dma_engine_dtor(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct nv04_fifo_chan *chan = nv04_fifo_chan(base); - nvkm_gpuobj_del(&chan->engn[engine->subdev.index]); + nvkm_gpuobj_del(nv40_fifo_dma_engn(chan, engine)); } static int @@ -130,13 +139,12 @@ nv40_fifo_dma_engine_ctor(struct nvkm_fifo_chan *base, struct nvkm_object *object) { struct nv04_fifo_chan *chan = nv04_fifo_chan(base); - const int engn = engine->subdev.index; u32 reg, ctx; if (!nv40_fifo_dma_engine(engine, ®, &ctx)) return 0; - return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); + return nvkm_object_bind(object, NULL, 0, nv40_fifo_dma_engn(chan, engine)); } static int @@ -149,7 +157,7 @@ nv40_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, u32 handle = object->handle; int hash; - switch (object->engine->subdev.index) { + switch (object->engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW : context |= 0x00000000; break; case NVKM_ENGINE_GR : context |= 0x00100000; break; @@ -159,10 +167,10 @@ nv40_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, return -EINVAL; } - mutex_lock(&chan->fifo->base.engine.subdev.mutex); + mutex_lock(&chan->fifo->base.mutex); hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, handle, context); - mutex_unlock(&chan->fifo->base.engine.subdev.mutex); + mutex_unlock(&chan->fifo->base.mutex); return hash; } @@ -209,10 +217,10 @@ nv40_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&nv40_fifo_dma_func, &fifo->base, 0x1000, 0x1000, false, 0, args->v0.pushbuf, - (1ULL << NVKM_ENGINE_DMAOBJ) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_MPEG) | - (1ULL << NVKM_ENGINE_SW), + BIT(NV04_FIFO_ENGN_SW) | + BIT(NV04_FIFO_ENGN_GR) | + BIT(NV04_FIFO_ENGN_MPEG) | + BIT(NV04_FIFO_ENGN_DMA), 0, 0xc00000, 0x1000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c deleted file mode 100644 index 8043718ad150..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include "channv50.h" - -#include <core/client.h> -#include <core/ramht.h> - -#include <nvif/class.h> -#include <nvif/cl506e.h> -#include <nvif/unpack.h> - -static int -nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, - void *data, u32 size, struct nvkm_object **pobject) -{ - struct nvkm_object *parent = oclass->parent; - union { - struct nv50_channel_dma_v0 v0; - } *args = data; - struct nv50_fifo *fifo = nv50_fifo(base); - struct nv50_fifo_chan *chan; - int ret = -ENOSYS; - - nvif_ioctl(parent, "create channel dma size %d\n", size); - if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { - nvif_ioctl(parent, "create channel dma vers %d vmm %llx " - "pushbuf %llx offset %016llx\n", - args->v0.version, args->v0.vmm, args->v0.pushbuf, - args->v0.offset); - if (!args->v0.pushbuf) - return -EINVAL; - } else - return ret; - - if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) - return -ENOMEM; - *pobject = &chan->base.object; - - ret = nv50_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf, - oclass, chan); - if (ret) - return ret; - - args->v0.chid = chan->base.chid; - - nvkm_kmap(chan->ramfc); - nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); - nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); - nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); - nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); - nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); - nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); - nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); - nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); - nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); - nvkm_wo32(chan->ramfc, 0x78, 0x00000000); - nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); - nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | - (4 << 24) /* SEARCH_FULL */ | - (chan->ramht->gpuobj->node->offset >> 4)); - nvkm_done(chan->ramfc); - return 0; -} - -const struct nvkm_fifo_chan_oclass -nv50_fifo_dma_oclass = { - .base.oclass = NV50_CHANNEL_DMA, - .base.minver = 0, - .base.maxver = 0, - .ctor = nv50_fifo_dma_new, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c index ff7b529764fe..3885c3830b94 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c @@ -38,25 +38,95 @@ g84_fifo_uevent_init(struct nvkm_fifo *fifo) nvkm_mask(device, 0x002140, 0x40000000, 0x40000000); } +static struct nvkm_engine * +g84_fifo_id_engine(struct nvkm_fifo *fifo, int engi) +{ + struct nvkm_device *device = fifo->engine.subdev.device; + struct nvkm_engine *engine; + enum nvkm_subdev_type type; + + switch (engi) { + case G84_FIFO_ENGN_SW : type = NVKM_ENGINE_SW; break; + case G84_FIFO_ENGN_GR : type = NVKM_ENGINE_GR; break; + case G84_FIFO_ENGN_MPEG : + if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSPPP, 0))) + return engine; + type = NVKM_ENGINE_MPEG; + break; + case G84_FIFO_ENGN_ME : + if ((engine = nvkm_device_engine(device, NVKM_ENGINE_CE, 0))) + return engine; + type = NVKM_ENGINE_ME; + break; + case G84_FIFO_ENGN_VP : + if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSPDEC, 0))) + return engine; + type = NVKM_ENGINE_VP; + break; + case G84_FIFO_ENGN_CIPHER: + if ((engine = nvkm_device_engine(device, NVKM_ENGINE_VIC, 0))) + return engine; + if ((engine = nvkm_device_engine(device, NVKM_ENGINE_SEC, 0))) + return engine; + type = NVKM_ENGINE_CIPHER; + break; + case G84_FIFO_ENGN_BSP : + if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSVLD, 0))) + return engine; + type = NVKM_ENGINE_BSP; + break; + case G84_FIFO_ENGN_DMA : type = NVKM_ENGINE_DMAOBJ; break; + default: + WARN_ON(1); + return NULL; + } + + return nvkm_device_engine(fifo->engine.subdev.device, type, 0); +} + +static int +g84_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine) +{ + switch (engine->subdev.type) { + case NVKM_ENGINE_SW : return G84_FIFO_ENGN_SW; + case NVKM_ENGINE_GR : return G84_FIFO_ENGN_GR; + case NVKM_ENGINE_MPEG : + case NVKM_ENGINE_MSPPP : return G84_FIFO_ENGN_MPEG; + case NVKM_ENGINE_CE : return G84_FIFO_ENGN_CE0; + case NVKM_ENGINE_VP : + case NVKM_ENGINE_MSPDEC: return G84_FIFO_ENGN_VP; + case NVKM_ENGINE_CIPHER: + case NVKM_ENGINE_SEC : return G84_FIFO_ENGN_CIPHER; + case NVKM_ENGINE_BSP : + case NVKM_ENGINE_MSVLD : return G84_FIFO_ENGN_BSP; + case NVKM_ENGINE_DMAOBJ: return G84_FIFO_ENGN_DMA; + default: + WARN_ON(1); + return -1; + } +} + static const struct nvkm_fifo_func g84_fifo = { .dtor = nv50_fifo_dtor, .oneinit = nv50_fifo_oneinit, .init = nv50_fifo_init, .intr = nv04_fifo_intr, + .engine_id = g84_fifo_engine_id, + .id_engine = g84_fifo_id_engine, .pause = nv04_fifo_pause, .start = nv04_fifo_start, .uevent_init = g84_fifo_uevent_init, .uevent_fini = g84_fifo_uevent_fini, .chan = { - &g84_fifo_dma_oclass, &g84_fifo_gpfifo_oclass, NULL }, }; int -g84_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +g84_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return nv50_fifo_new_(&g84_fifo, device, index, pfifo); + return nv50_fifo_new_(&g84_fifo, device, type, inst, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c new file mode 100644 index 000000000000..c630dbd2911a --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c @@ -0,0 +1,311 @@ +/* + * Copyright 2021 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#define ga102_fifo(p) container_of((p), struct ga102_fifo, base.engine) +#define ga102_chan(p) container_of((p), struct ga102_chan, object) +#include <engine/fifo.h> +#include "user.h" + +#include <core/memory.h> +#include <subdev/mmu.h> +#include <subdev/timer.h> +#include <subdev/top.h> + +#include <nvif/cl0080.h> +#include <nvif/clc36f.h> +#include <nvif/class.h> + +struct ga102_fifo { + struct nvkm_fifo base; +}; + +struct ga102_chan { + struct nvkm_object object; + + struct { + u32 runl; + u32 chan; + } ctrl; + + struct nvkm_memory *mthd; + struct nvkm_memory *inst; + struct nvkm_memory *user; + struct nvkm_memory *runl; + + struct nvkm_vmm *vmm; +}; + +static int +ga102_chan_sclass(struct nvkm_object *object, int index, struct nvkm_oclass *oclass) +{ + if (index == 0) { + oclass->ctor = nvkm_object_new; + oclass->base = (struct nvkm_sclass) { -1, -1, AMPERE_DMA_COPY_B }; + return 0; + } + + return -EINVAL; +} + +static int +ga102_chan_map(struct nvkm_object *object, void *argv, u32 argc, + enum nvkm_object_map *type, u64 *addr, u64 *size) +{ + struct ga102_chan *chan = ga102_chan(object); + struct nvkm_device *device = chan->object.engine->subdev.device; + u64 bar2 = nvkm_memory_bar2(chan->user); + + if (bar2 == ~0ULL) + return -EFAULT; + + *type = NVKM_OBJECT_MAP_IO; + *addr = device->func->resource_addr(device, 3) + bar2; + *size = 0x1000; + return 0; +} + +static int +ga102_chan_fini(struct nvkm_object *object, bool suspend) +{ + struct ga102_chan *chan = ga102_chan(object); + struct nvkm_device *device = chan->object.engine->subdev.device; + + nvkm_wr32(device, chan->ctrl.chan, 0x00000003); + + nvkm_wr32(device, chan->ctrl.runl + 0x098, 0x01000000); + nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, chan->ctrl.runl + 0x098) & 0x00100000)) + break; + ); + + nvkm_wr32(device, chan->ctrl.runl + 0x088, 0); + + nvkm_wr32(device, chan->ctrl.chan, 0xffffffff); + return 0; +} + +static int +ga102_chan_init(struct nvkm_object *object) +{ + struct ga102_chan *chan = ga102_chan(object); + struct nvkm_device *device = chan->object.engine->subdev.device; + + nvkm_mask(device, chan->ctrl.runl + 0x300, 0x80000000, 0x80000000); + + nvkm_wr32(device, chan->ctrl.runl + 0x080, lower_32_bits(nvkm_memory_addr(chan->runl))); + nvkm_wr32(device, chan->ctrl.runl + 0x084, upper_32_bits(nvkm_memory_addr(chan->runl))); + nvkm_wr32(device, chan->ctrl.runl + 0x088, 2); + + nvkm_wr32(device, chan->ctrl.chan, 0x00000002); + nvkm_wr32(device, chan->ctrl.runl + 0x0090, 0); + return 0; +} + +static void * +ga102_chan_dtor(struct nvkm_object *object) +{ + struct ga102_chan *chan = ga102_chan(object); + + if (chan->vmm) { + nvkm_vmm_part(chan->vmm, chan->inst); + nvkm_vmm_unref(&chan->vmm); + } + + nvkm_memory_unref(&chan->runl); + nvkm_memory_unref(&chan->user); + nvkm_memory_unref(&chan->inst); + nvkm_memory_unref(&chan->mthd); + return chan; +} + +static const struct nvkm_object_func +ga102_chan = { + .dtor = ga102_chan_dtor, + .init = ga102_chan_init, + .fini = ga102_chan_fini, + .map = ga102_chan_map, + .sclass = ga102_chan_sclass, +}; + +static int +ga102_chan_new(struct nvkm_device *device, + const struct nvkm_oclass *oclass, void *argv, u32 argc, struct nvkm_object **pobject) +{ + struct volta_channel_gpfifo_a_v0 *args = argv; + struct nvkm_top_device *tdev; + struct nvkm_vmm *vmm; + struct ga102_chan *chan; + int ret; + + if (argc != sizeof(*args)) + return -ENOSYS; + + vmm = nvkm_uvmm_search(oclass->client, args->vmm); + if (IS_ERR(vmm)) + return PTR_ERR(vmm); + + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + + nvkm_object_ctor(&ga102_chan, oclass, &chan->object); + *pobject = &chan->object; + + list_for_each_entry(tdev, &device->top->device, head) { + if (tdev->type == NVKM_ENGINE_CE) { + chan->ctrl.runl = tdev->runlist; + break; + } + } + + if (!chan->ctrl.runl) + return -ENODEV; + + chan->ctrl.chan = nvkm_rd32(device, chan->ctrl.runl + 0x004) & 0xfffffff0; + + args->chid = 0; + args->inst = 0; + args->token = nvkm_rd32(device, chan->ctrl.runl + 0x008) & 0xffff0000; + + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, true, &chan->mthd); + if (ret) + return ret; + + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, true, &chan->inst); + if (ret) + return ret; + + nvkm_kmap(chan->inst); + nvkm_wo32(chan->inst, 0x010, 0x0000face); + nvkm_wo32(chan->inst, 0x030, 0x7ffff902); + nvkm_wo32(chan->inst, 0x048, lower_32_bits(args->ioffset)); + nvkm_wo32(chan->inst, 0x04c, upper_32_bits(args->ioffset) | + (order_base_2(args->ilength / 8) << 16)); + nvkm_wo32(chan->inst, 0x084, 0x20400000); + nvkm_wo32(chan->inst, 0x094, 0x30000001); + nvkm_wo32(chan->inst, 0x0ac, 0x00020000); + nvkm_wo32(chan->inst, 0x0e4, 0x00000000); + nvkm_wo32(chan->inst, 0x0e8, 0); + nvkm_wo32(chan->inst, 0x0f4, 0x00001000); + nvkm_wo32(chan->inst, 0x0f8, 0x10003080); + nvkm_mo32(chan->inst, 0x218, 0x00000000, 0x00000000); + nvkm_wo32(chan->inst, 0x220, lower_32_bits(nvkm_memory_bar2(chan->mthd))); + nvkm_wo32(chan->inst, 0x224, upper_32_bits(nvkm_memory_bar2(chan->mthd))); + nvkm_done(chan->inst); + + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, true, &chan->user); + if (ret) + return ret; + + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, true, &chan->runl); + if (ret) + return ret; + + nvkm_kmap(chan->runl); + nvkm_wo32(chan->runl, 0x00, 0x80030001); + nvkm_wo32(chan->runl, 0x04, 1); + nvkm_wo32(chan->runl, 0x08, 0); + nvkm_wo32(chan->runl, 0x0c, 0x00000000); + nvkm_wo32(chan->runl, 0x10, lower_32_bits(nvkm_memory_addr(chan->user))); + nvkm_wo32(chan->runl, 0x14, upper_32_bits(nvkm_memory_addr(chan->user))); + nvkm_wo32(chan->runl, 0x18, lower_32_bits(nvkm_memory_addr(chan->inst))); + nvkm_wo32(chan->runl, 0x1c, upper_32_bits(nvkm_memory_addr(chan->inst))); + nvkm_done(chan->runl); + + ret = nvkm_vmm_join(vmm, chan->inst); + if (ret) + return ret; + + chan->vmm = nvkm_vmm_ref(vmm); + return 0; +} + +static const struct nvkm_device_oclass +ga102_chan_oclass = { + .ctor = ga102_chan_new, +}; + +static int +ga102_user_new(struct nvkm_device *device, + const struct nvkm_oclass *oclass, void *argv, u32 argc, struct nvkm_object **pobject) +{ + return tu102_fifo_user_new(oclass, argv, argc, pobject); +} + +static const struct nvkm_device_oclass +ga102_user_oclass = { + .ctor = ga102_user_new, +}; + +static int +ga102_fifo_sclass(struct nvkm_oclass *oclass, int index, const struct nvkm_device_oclass **class) +{ + if (index == 0) { + oclass->base = (struct nvkm_sclass) { -1, -1, VOLTA_USERMODE_A }; + *class = &ga102_user_oclass; + return 0; + } else + if (index == 1) { + oclass->base = (struct nvkm_sclass) { 0, 0, AMPERE_CHANNEL_GPFIFO_B }; + *class = &ga102_chan_oclass; + return 0; + } + + return 2; +} + +static int +ga102_fifo_info(struct nvkm_engine *engine, u64 mthd, u64 *data) +{ + switch (mthd) { + case NV_DEVICE_HOST_CHANNELS: *data = 1; return 0; + default: + break; + } + + return -ENOSYS; +} + +static void * +ga102_fifo_dtor(struct nvkm_engine *engine) +{ + return ga102_fifo(engine); +} + +static const struct nvkm_engine_func +ga102_fifo = { + .dtor = ga102_fifo_dtor, + .info = ga102_fifo_info, + .base.sclass = ga102_fifo_sclass, +}; + +int +ga102_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) +{ + struct ga102_fifo *fifo; + + if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) + return -ENOMEM; + + nvkm_engine_ctor(&ga102_fifo, device, type, inst, true, &fifo->base.engine); + *pfifo = &fifo->base; + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index 10a2e7039a75..8b4f36b3e34b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -28,6 +28,7 @@ #include <core/enum.h> #include <core/gpuobj.h> #include <subdev/bar.h> +#include <subdev/fault.h> #include <engine/sw.h> #include <nvif/class.h> @@ -56,7 +57,7 @@ gf100_fifo_runlist_commit(struct gf100_fifo *fifo) int nr = 0; int target; - mutex_lock(&subdev->mutex); + mutex_lock(&fifo->base.mutex); cur = fifo->runlist.mem[fifo->runlist.active]; fifo->runlist.active = !fifo->runlist.active; @@ -72,7 +73,7 @@ gf100_fifo_runlist_commit(struct gf100_fifo *fifo) case NVKM_MEM_TARGET_VRAM: target = 0; break; case NVKM_MEM_TARGET_NCOH: target = 3; break; default: - mutex_unlock(&subdev->mutex); + mutex_unlock(&fifo->base.mutex); WARN_ON(1); return; } @@ -85,59 +86,61 @@ gf100_fifo_runlist_commit(struct gf100_fifo *fifo) !(nvkm_rd32(device, 0x00227c) & 0x00100000), msecs_to_jiffies(2000)) == 0) nvkm_error(subdev, "runlist update timeout\n"); - mutex_unlock(&subdev->mutex); + mutex_unlock(&fifo->base.mutex); } void gf100_fifo_runlist_remove(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan) { - mutex_lock(&fifo->base.engine.subdev.mutex); + mutex_lock(&fifo->base.mutex); list_del_init(&chan->head); - mutex_unlock(&fifo->base.engine.subdev.mutex); + mutex_unlock(&fifo->base.mutex); } void gf100_fifo_runlist_insert(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan) { - mutex_lock(&fifo->base.engine.subdev.mutex); + mutex_lock(&fifo->base.mutex); list_add_tail(&chan->head, &fifo->chan); - mutex_unlock(&fifo->base.engine.subdev.mutex); + mutex_unlock(&fifo->base.mutex); } -static inline int -gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn) +static struct nvkm_engine * +gf100_fifo_id_engine(struct nvkm_fifo *fifo, int engi) { - switch (engn) { - case NVKM_ENGINE_GR : engn = 0; break; - case NVKM_ENGINE_MSVLD : engn = 1; break; - case NVKM_ENGINE_MSPPP : engn = 2; break; - case NVKM_ENGINE_MSPDEC: engn = 3; break; - case NVKM_ENGINE_CE0 : engn = 4; break; - case NVKM_ENGINE_CE1 : engn = 5; break; + enum nvkm_subdev_type type; + int inst; + + switch (engi) { + case GF100_FIFO_ENGN_GR : type = NVKM_ENGINE_GR ; inst = 0; break; + case GF100_FIFO_ENGN_MSPDEC: type = NVKM_ENGINE_MSPDEC; inst = 0; break; + case GF100_FIFO_ENGN_MSPPP : type = NVKM_ENGINE_MSPPP ; inst = 0; break; + case GF100_FIFO_ENGN_MSVLD : type = NVKM_ENGINE_MSVLD ; inst = 0; break; + case GF100_FIFO_ENGN_CE0 : type = NVKM_ENGINE_CE ; inst = 0; break; + case GF100_FIFO_ENGN_CE1 : type = NVKM_ENGINE_CE ; inst = 1; break; + case GF100_FIFO_ENGN_SW : type = NVKM_ENGINE_SW ; inst = 0; break; default: - return -1; + WARN_ON(1); + return NULL; } - return engn; + return nvkm_device_engine(fifo->engine.subdev.device, type, inst); } -static inline struct nvkm_engine * -gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn) +static int +gf100_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine) { - struct nvkm_device *device = fifo->base.engine.subdev.device; - - switch (engn) { - case 0: engn = NVKM_ENGINE_GR; break; - case 1: engn = NVKM_ENGINE_MSVLD; break; - case 2: engn = NVKM_ENGINE_MSPPP; break; - case 3: engn = NVKM_ENGINE_MSPDEC; break; - case 4: engn = NVKM_ENGINE_CE0; break; - case 5: engn = NVKM_ENGINE_CE1; break; + switch (engine->subdev.type) { + case NVKM_ENGINE_GR : return GF100_FIFO_ENGN_GR; + case NVKM_ENGINE_MSPDEC: return GF100_FIFO_ENGN_MSPDEC; + case NVKM_ENGINE_MSPPP : return GF100_FIFO_ENGN_MSPPP; + case NVKM_ENGINE_MSVLD : return GF100_FIFO_ENGN_MSVLD; + case NVKM_ENGINE_CE : return GF100_FIFO_ENGN_CE0 + engine->subdev.inst; + case NVKM_ENGINE_SW : return GF100_FIFO_ENGN_SW; default: - return NULL; + WARN_ON(1); + return -1; } - - return nvkm_device_engine(device, engn); } static void @@ -147,20 +150,17 @@ gf100_fifo_recover_work(struct work_struct *w) struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_engine *engine; unsigned long flags; - u32 engn, engm = 0; - u64 mask, todo; + u32 engm, engn, todo; spin_lock_irqsave(&fifo->base.lock, flags); - mask = fifo->recover.mask; + engm = fifo->recover.mask; fifo->recover.mask = 0ULL; spin_unlock_irqrestore(&fifo->base.lock, flags); - for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn)) - engm |= 1 << gf100_fifo_engidx(fifo, engn); nvkm_mask(device, 0x002630, engm, engm); - for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn)) { - if ((engine = nvkm_device_engine(device, engn))) { + for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT_ULL(engn)) { + if ((engine = gf100_fifo_id_engine(&fifo->base, engn))) { nvkm_subdev_fini(&engine->subdev, false); WARN_ON(nvkm_subdev_init(&engine->subdev)); } @@ -178,84 +178,23 @@ gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine, struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; u32 chid = chan->base.chid; + int engi = gf100_fifo_engine_id(&fifo->base, engine); nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n", - nvkm_subdev_name[engine->subdev.index], chid); + engine->subdev.name, chid); assert_spin_locked(&fifo->base.lock); nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); list_del_init(&chan->head); chan->killed = true; - if (engine != &fifo->base.engine) - fifo->recover.mask |= 1ULL << engine->subdev.index; + if (engi >= 0 && engi != GF100_FIFO_ENGN_SW) + fifo->recover.mask |= BIT(engi); schedule_work(&fifo->recover.work); nvkm_fifo_kevent(&fifo->base, chid); } static const struct nvkm_enum -gf100_fifo_sched_reason[] = { - { 0x0a, "CTXSW_TIMEOUT" }, - {} -}; - -static void -gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo) -{ - struct nvkm_device *device = fifo->base.engine.subdev.device; - struct nvkm_engine *engine; - struct gf100_fifo_chan *chan; - unsigned long flags; - u32 engn; - - spin_lock_irqsave(&fifo->base.lock, flags); - for (engn = 0; engn < 6; engn++) { - u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); - u32 busy = (stat & 0x80000000); - u32 save = (stat & 0x00100000); /* maybe? */ - u32 unk0 = (stat & 0x00040000); - u32 unk1 = (stat & 0x00001000); - u32 chid = (stat & 0x0000007f); - (void)save; - - if (busy && unk0 && unk1) { - list_for_each_entry(chan, &fifo->chan, head) { - if (chan->base.chid == chid) { - engine = gf100_fifo_engine(fifo, engn); - if (!engine) - break; - gf100_fifo_recover(fifo, engine, chan); - break; - } - } - } - } - spin_unlock_irqrestore(&fifo->base.lock, flags); -} - -static void -gf100_fifo_intr_sched(struct gf100_fifo *fifo) -{ - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; - struct nvkm_device *device = subdev->device; - u32 intr = nvkm_rd32(device, 0x00254c); - u32 code = intr & 0x000000ff; - const struct nvkm_enum *en; - - en = nvkm_enum_find(gf100_fifo_sched_reason, code); - - nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : ""); - - switch (code) { - case 0x0a: - gf100_fifo_intr_sched_ctxsw(fifo); - break; - default: - break; - } -} - -static const struct nvkm_enum gf100_fifo_fault_engine[] = { { 0x00, "PGRAPH", NULL, NVKM_ENGINE_GR }, { 0x03, "PEEPHOLE", NULL, NVKM_ENGINE_IFB }, @@ -266,8 +205,8 @@ gf100_fifo_fault_engine[] = { { 0x11, "PMSPPP", NULL, NVKM_ENGINE_MSPPP }, { 0x13, "PCOUNTER" }, { 0x14, "PMSPDEC", NULL, NVKM_ENGINE_MSPDEC }, - { 0x15, "PCE0", NULL, NVKM_ENGINE_CE0 }, - { 0x16, "PCE1", NULL, NVKM_ENGINE_CE1 }, + { 0x15, "PCE0", NULL, NVKM_ENGINE_CE, 0 }, + { 0x16, "PCE1", NULL, NVKM_ENGINE_CE, 1 }, { 0x17, "PMU" }, {} }; @@ -315,32 +254,24 @@ gf100_fifo_fault_gpcclient[] = { }; static void -gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit) +gf100_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) { + struct gf100_fifo *fifo = gf100_fifo(base); struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; - u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); - u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); - u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); - u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10)); - u32 gpc = (stat & 0x1f000000) >> 24; - u32 client = (stat & 0x00001f00) >> 8; - u32 write = (stat & 0x00000080); - u32 hub = (stat & 0x00000040); - u32 reason = (stat & 0x0000000f); const struct nvkm_enum *er, *eu, *ec; struct nvkm_engine *engine = NULL; struct nvkm_fifo_chan *chan; unsigned long flags; char gpcid[8] = ""; - er = nvkm_enum_find(gf100_fifo_fault_reason, reason); - eu = nvkm_enum_find(gf100_fifo_fault_engine, unit); - if (hub) { - ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client); + er = nvkm_enum_find(gf100_fifo_fault_reason, info->reason); + eu = nvkm_enum_find(gf100_fifo_fault_engine, info->engine); + if (info->hub) { + ec = nvkm_enum_find(gf100_fifo_fault_hubclient, info->client); } else { - ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client); - snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc); + ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, info->client); + snprintf(gpcid, sizeof(gpcid), "GPC%d/", info->gpc); } if (eu && eu->data2) { @@ -355,27 +286,113 @@ gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit) nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); break; default: - engine = nvkm_device_engine(device, eu->data2); + engine = nvkm_device_engine(device, eu->data2, eu->inst); break; } } - chan = nvkm_fifo_chan_inst(&fifo->base, (u64)inst << 12, &flags); + chan = nvkm_fifo_chan_inst(&fifo->base, info->inst, &flags); nvkm_error(subdev, "%s fault at %010llx engine %02x [%s] client %02x [%s%s] " "reason %02x [%s] on channel %d [%010llx %s]\n", - write ? "write" : "read", (u64)vahi << 32 | valo, - unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "", - reason, er ? er->name : "", chan ? chan->chid : -1, - (u64)inst << 12, - chan ? chan->object.client->name : "unknown"); + info->access ? "write" : "read", info->addr, + info->engine, eu ? eu->name : "", + info->client, gpcid, ec ? ec->name : "", + info->reason, er ? er->name : "", chan ? chan->chid : -1, + info->inst, chan ? chan->object.client->name : "unknown"); if (engine && chan) gf100_fifo_recover(fifo, engine, (void *)chan); nvkm_fifo_chan_put(&fifo->base, flags, &chan); } +static const struct nvkm_enum +gf100_fifo_sched_reason[] = { + { 0x0a, "CTXSW_TIMEOUT" }, + {} +}; + +static void +gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo) +{ + struct nvkm_device *device = fifo->base.engine.subdev.device; + struct nvkm_engine *engine; + struct gf100_fifo_chan *chan; + unsigned long flags; + u32 engn; + + spin_lock_irqsave(&fifo->base.lock, flags); + for (engn = 0; engn < 6; engn++) { + u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); + u32 busy = (stat & 0x80000000); + u32 save = (stat & 0x00100000); /* maybe? */ + u32 unk0 = (stat & 0x00040000); + u32 unk1 = (stat & 0x00001000); + u32 chid = (stat & 0x0000007f); + (void)save; + + if (busy && unk0 && unk1) { + list_for_each_entry(chan, &fifo->chan, head) { + if (chan->base.chid == chid) { + engine = gf100_fifo_id_engine(&fifo->base, engn); + if (!engine) + break; + gf100_fifo_recover(fifo, engine, chan); + break; + } + } + } + } + spin_unlock_irqrestore(&fifo->base.lock, flags); +} + +static void +gf100_fifo_intr_sched(struct gf100_fifo *fifo) +{ + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + u32 intr = nvkm_rd32(device, 0x00254c); + u32 code = intr & 0x000000ff; + const struct nvkm_enum *en; + + en = nvkm_enum_find(gf100_fifo_sched_reason, code); + + nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : ""); + + switch (code) { + case 0x0a: + gf100_fifo_intr_sched_ctxsw(fifo); + break; + default: + break; + } +} + +void +gf100_fifo_intr_fault(struct nvkm_fifo *fifo, int unit) +{ + struct nvkm_device *device = fifo->engine.subdev.device; + u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); + u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); + u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); + u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); + struct nvkm_fault_data info; + + info.inst = (u64)inst << 12; + info.addr = ((u64)vahi << 32) | valo; + info.time = 0; + info.engine = unit; + info.valid = 1; + info.gpc = (type & 0x1f000000) >> 24; + info.client = (type & 0x00001f00) >> 8; + info.access = (type & 0x00000080) >> 7; + info.hub = (type & 0x00000040) >> 6; + info.reason = (type & 0x0000000f); + + nvkm_fifo_fault(fifo, &info); +} + static const struct nvkm_bitfield gf100_fifo_pbdma_intr[] = { /* { 0x00008000, "" } seen with null ib push */ @@ -518,7 +535,7 @@ gf100_fifo_intr(struct nvkm_fifo *base) u32 mask = nvkm_rd32(device, 0x00259c); while (mask) { u32 unit = __ffs(mask); - gf100_fifo_intr_fault(fifo, unit); + gf100_fifo_intr_fault(&fifo->base, unit); nvkm_wr32(device, 0x00259c, (1 << unit)); mask &= ~(1 << unit); } @@ -655,6 +672,9 @@ gf100_fifo = { .init = gf100_fifo_init, .fini = gf100_fifo_fini, .intr = gf100_fifo_intr, + .fault = gf100_fifo_fault, + .engine_id = gf100_fifo_engine_id, + .id_engine = gf100_fifo_id_engine, .uevent_init = gf100_fifo_uevent_init, .uevent_fini = gf100_fifo_uevent_fini, .chan = { @@ -664,7 +684,8 @@ gf100_fifo = { }; int -gf100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gf100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { struct gf100_fifo *fifo; @@ -674,5 +695,5 @@ gf100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) INIT_WORK(&fifo->recover.work, gf100_fifo_recover_work); *pfifo = &fifo->base; - return nvkm_fifo_ctor(&gf100_fifo, device, index, 128, &fifo->base); + return nvkm_fifo_ctor(&gf100_fifo, device, type, inst, 128, &fifo->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 1053fe796466..e771bd519ee2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -36,19 +36,7 @@ #include <nvif/class.h> #include <nvif/cl0080.h> -struct gk104_fifo_engine_status { - bool busy; - bool faulted; - bool chsw; - bool save; - bool load; - struct { - bool tsg; - u32 id; - } prev, next, *chan; -}; - -static void +void gk104_fifo_engine_status(struct gk104_fifo *fifo, int engn, struct gk104_fifo_engine_status *status) { @@ -95,7 +83,7 @@ gk104_fifo_engine_status(struct gk104_fifo *fifo, int engn, status->chan == &status->next ? "*" : " "); } -static int +int gk104_fifo_class_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, void *argv, u32 argc, struct nvkm_object **pobject) { @@ -112,7 +100,7 @@ gk104_fifo_class_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, return -EINVAL; } -static int +int gk104_fifo_class_get(struct nvkm_fifo *base, int index, struct nvkm_oclass *oclass) { @@ -134,14 +122,14 @@ gk104_fifo_class_get(struct nvkm_fifo *base, int index, return c; } -static void +void gk104_fifo_uevent_fini(struct nvkm_fifo *fifo) { struct nvkm_device *device = fifo->engine.subdev.device; nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); } -static void +void gk104_fifo_uevent_init(struct nvkm_fifo *fifo) { struct nvkm_device *device = fifo->engine.subdev.device; @@ -180,12 +168,11 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, int runl) { const struct gk104_fifo_runlist_func *func = fifo->func->runlist; struct gk104_fifo_chan *chan; - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_memory *mem; struct nvkm_fifo_cgrp *cgrp; int nr = 0; - mutex_lock(&subdev->mutex); + mutex_lock(&fifo->base.mutex); mem = fifo->runlist[runl].mem[fifo->runlist[runl].next]; fifo->runlist[runl].next = !fifo->runlist[runl].next; @@ -203,27 +190,27 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, int runl) nvkm_done(mem); func->commit(fifo, runl, mem, nr); - mutex_unlock(&subdev->mutex); + mutex_unlock(&fifo->base.mutex); } void gk104_fifo_runlist_remove(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) { struct nvkm_fifo_cgrp *cgrp = chan->cgrp; - mutex_lock(&fifo->base.engine.subdev.mutex); + mutex_lock(&fifo->base.mutex); if (!list_empty(&chan->head)) { list_del_init(&chan->head); if (cgrp && !--cgrp->chan_nr) list_del_init(&cgrp->head); } - mutex_unlock(&fifo->base.engine.subdev.mutex); + mutex_unlock(&fifo->base.mutex); } void gk104_fifo_runlist_insert(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) { struct nvkm_fifo_cgrp *cgrp = chan->cgrp; - mutex_lock(&fifo->base.engine.subdev.mutex); + mutex_lock(&fifo->base.mutex); if (cgrp) { if (!cgrp->chan_nr++) list_add_tail(&cgrp->head, &fifo->runlist[chan->runl].cgrp); @@ -231,7 +218,7 @@ gk104_fifo_runlist_insert(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) } else { list_add_tail(&chan->head, &fifo->runlist[chan->runl].chan); } - mutex_unlock(&fifo->base.engine.subdev.mutex); + mutex_unlock(&fifo->base.mutex); } void @@ -271,6 +258,33 @@ gk104_fifo_pbdma = { .init = gk104_fifo_pbdma_init, }; +struct nvkm_engine * +gk104_fifo_id_engine(struct nvkm_fifo *base, int engi) +{ + if (engi == GK104_FIFO_ENGN_SW) + return nvkm_device_engine(base->engine.subdev.device, NVKM_ENGINE_SW, 0); + + return gk104_fifo(base)->engine[engi].engine; +} + +int +gk104_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine) +{ + struct gk104_fifo *fifo = gk104_fifo(base); + int engn; + + if (engine->subdev.type == NVKM_ENGINE_SW) + return GK104_FIFO_ENGN_SW; + + for (engn = 0; engn < fifo->engine_nr && engine; engn++) { + if (fifo->engine[engn].engine == engine) + return engn; + } + + WARN_ON(1); + return -1; +} + static void gk104_fifo_recover_work(struct work_struct *w) { @@ -422,11 +436,12 @@ gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn) * called from the fault handler already. */ if (!status.faulted && engine) { - mmui = nvkm_top_fault_id(device, engine->subdev.index); + mmui = nvkm_top_fault_id(device, engine->subdev.type, engine->subdev.inst); if (mmui < 0) { const struct nvkm_enum *en = fifo->func->fault.engine; for (; en && en->name; en++) { - if (en->data2 == engine->subdev.index) { + if (en->data2 == engine->subdev.type && + en->inst == engine->subdev.inst) { mmui = en->value; break; } @@ -471,8 +486,8 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) struct nvkm_engine *engine = NULL; struct nvkm_fifo_chan *chan; unsigned long flags; - char ct[8] = "HUB/", en[16] = ""; - int engn; + const char *en = ""; + char ct[8] = "HUB/"; er = nvkm_enum_find(fifo->func->fault.reason, info->reason); ee = nvkm_enum_find(fifo->func->fault.engine, info->engine); @@ -496,23 +511,20 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); break; default: - engine = nvkm_device_engine(device, ee->data2); + engine = nvkm_device_engine(device, ee->data2, 0); break; } } if (ee == NULL) { - enum nvkm_devidx engidx = nvkm_top_fault(device, info->engine); - if (engidx < NVKM_SUBDEV_NR) { - const char *src = nvkm_subdev_name[engidx]; - char *dst = en; - do { - *dst++ = toupper(*src++); - } while(*src); - engine = nvkm_device_engine(device, engidx); + struct nvkm_subdev *subdev = nvkm_top_fault(device, info->engine); + if (subdev) { + if (subdev->func == &nvkm_engine) + engine = container_of(subdev, typeof(*engine), subdev); + en = engine->subdev.name; } } else { - snprintf(en, sizeof(en), "%s", ee->name); + en = ee->name; } spin_lock_irqsave(&fifo->base.lock, flags); @@ -535,11 +547,10 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) * correct engine(s), but just in case we can't find the channel * information... */ - for (engn = 0; engn < fifo->engine_nr && engine; engn++) { - if (fifo->engine[engn].engine == engine) { + if (engine) { + int engn = fifo->base.func->engine_id(&fifo->base, engine); + if (engn >= 0 && engn != GK104_FIFO_ENGN_SW) gk104_fifo_recover_engn(fifo, engn); - break; - } } spin_unlock_irqrestore(&fifo->base.lock, flags); @@ -556,7 +567,7 @@ gk104_fifo_bind_reason[] = { {} }; -static void +void gk104_fifo_intr_bind(struct gk104_fifo *fifo) { struct nvkm_subdev *subdev = &fifo->base.engine.subdev; @@ -627,7 +638,7 @@ gk104_fifo_intr_sched(struct gk104_fifo *fifo) } } -static void +void gk104_fifo_intr_chsw(struct gk104_fifo *fifo) { struct nvkm_subdev *subdev = &fifo->base.engine.subdev; @@ -637,7 +648,7 @@ gk104_fifo_intr_chsw(struct gk104_fifo *fifo) nvkm_wr32(device, 0x00256c, stat); } -static void +void gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo) { struct nvkm_subdev *subdev = &fifo->base.engine.subdev; @@ -646,31 +657,6 @@ gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo) nvkm_error(subdev, "DROPPED_MMU_FAULT %08x\n", stat); } -static void -gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) -{ - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; - struct nvkm_device *device = subdev->device; - u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); - u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); - u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); - u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); - struct nvkm_fault_data info; - - info.inst = (u64)inst << 12; - info.addr = ((u64)vahi << 32) | valo; - info.time = 0; - info.engine = unit; - info.valid = 1; - info.gpc = (type & 0x1f000000) >> 24; - info.client = (type & 0x00001f00) >> 8; - info.access = (type & 0x00000080) >> 7; - info.hub = (type & 0x00000040) >> 6; - info.reason = (type & 0x000000ff); - - nvkm_fifo_fault(&fifo->base, &info); -} - static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = { { 0x00000001, "MEMREQ" }, { 0x00000002, "MEMACK_TIMEOUT" }, @@ -705,7 +691,7 @@ static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = { {} }; -static void +void gk104_fifo_intr_pbdma_0(struct gk104_fifo *fifo, int unit) { struct nvkm_subdev *subdev = &fifo->base.engine.subdev; @@ -754,7 +740,7 @@ static const struct nvkm_bitfield gk104_fifo_pbdma_intr_1[] = { {} }; -static void +void gk104_fifo_intr_pbdma_1(struct gk104_fifo *fifo, int unit) { struct nvkm_subdev *subdev = &fifo->base.engine.subdev; @@ -775,7 +761,7 @@ gk104_fifo_intr_pbdma_1(struct gk104_fifo *fifo, int unit) nvkm_wr32(device, 0x040148 + (unit * 0x2000), stat); } -static void +void gk104_fifo_intr_runlist(struct gk104_fifo *fifo) { struct nvkm_device *device = fifo->base.engine.subdev.device; @@ -788,7 +774,7 @@ gk104_fifo_intr_runlist(struct gk104_fifo *fifo) } } -static void +void gk104_fifo_intr_engine(struct gk104_fifo *fifo) { nvkm_fifo_uevent(&fifo->base); @@ -849,7 +835,7 @@ gk104_fifo_intr(struct nvkm_fifo *base) u32 mask = nvkm_rd32(device, 0x00259c); while (mask) { u32 unit = __ffs(mask); - gk104_fifo_intr_fault(fifo, unit); + fifo->func->intr.fault(&fifo->base, unit); nvkm_wr32(device, 0x00259c, (1 << unit)); mask &= ~(1 << unit); } @@ -886,7 +872,7 @@ gk104_fifo_intr(struct nvkm_fifo *base) } } -static void +void gk104_fifo_fini(struct nvkm_fifo *base) { struct gk104_fifo *fifo = gk104_fifo(base); @@ -896,24 +882,46 @@ gk104_fifo_fini(struct nvkm_fifo *base) nvkm_mask(device, 0x002140, 0x10000000, 0x10000000); } -static int +int gk104_fifo_info(struct nvkm_fifo *base, u64 mthd, u64 *data) { struct gk104_fifo *fifo = gk104_fifo(base); switch (mthd) { - case NV_DEVICE_FIFO_RUNLISTS: + case NV_DEVICE_HOST_RUNLISTS: *data = (1ULL << fifo->runlist_nr) - 1; return 0; - case NV_DEVICE_FIFO_RUNLIST_ENGINES(0)... - NV_DEVICE_FIFO_RUNLIST_ENGINES(63): { - int runl = mthd - NV_DEVICE_FIFO_RUNLIST_ENGINES(0), engn; - if (runl < fifo->runlist_nr) { - unsigned long engm = fifo->runlist[runl].engm; + case NV_DEVICE_HOST_RUNLIST_ENGINES: { + if (*data < fifo->runlist_nr) { + unsigned long engm = fifo->runlist[*data].engm; struct nvkm_engine *engine; + int engn; *data = 0; for_each_set_bit(engn, &engm, fifo->engine_nr) { - if ((engine = fifo->engine[engn].engine)) - *data |= BIT_ULL(engine->subdev.index); + if ((engine = fifo->engine[engn].engine)) { +#define CASE(n) case NVKM_ENGINE_##n: *data |= NV_DEVICE_HOST_RUNLIST_ENGINES_##n; break + switch (engine->subdev.type) { + CASE(SW ); + CASE(GR ); + CASE(MPEG ); + CASE(ME ); + CASE(CIPHER); + CASE(BSP ); + CASE(VP ); + CASE(CE ); + CASE(SEC ); + CASE(MSVLD ); + CASE(MSPDEC); + CASE(MSPPP ); + CASE(MSENC ); + CASE(VIC ); + CASE(SEC2 ); + CASE(NVDEC ); + CASE(NVENC ); + default: + WARN_ON(1); + break; + } + } } return 0; } @@ -924,15 +932,15 @@ gk104_fifo_info(struct nvkm_fifo *base, u64 mthd, u64 *data) } } -static int +int gk104_fifo_oneinit(struct nvkm_fifo *base) { struct gk104_fifo *fifo = gk104_fifo(base); struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; struct nvkm_vmm *bar = nvkm_bar_bar1_vmm(device); - int engn, runl, pbid, ret, i, j; - enum nvkm_devidx engidx; + struct nvkm_top_device *tdev; + int pbid, ret, i, j; u32 *map; fifo->pbdma_nr = fifo->func->pbdma->nr(fifo); @@ -946,25 +954,41 @@ gk104_fifo_oneinit(struct nvkm_fifo *base) map[i] = nvkm_rd32(device, 0x002390 + (i * 0x04)); /* Determine runlist configuration from topology device info. */ - i = 0; - while ((int)(engidx = nvkm_top_engine(device, i++, &runl, &engn)) >= 0) { + list_for_each_entry(tdev, &device->top->device, head) { + const int engn = tdev->engine; + char _en[16], *en; + + if (engn < 0) + continue; + /* Determine which PBDMA handles requests for this engine. */ for (j = 0, pbid = -1; j < fifo->pbdma_nr; j++) { - if (map[j] & (1 << runl)) { + if (map[j] & BIT(tdev->runlist)) { pbid = j; break; } } + fifo->engine[engn].engine = nvkm_device_engine(device, tdev->type, tdev->inst); + if (!fifo->engine[engn].engine) { + snprintf(_en, sizeof(_en), "%s, %d", + nvkm_subdev_type[tdev->type], tdev->inst); + en = _en; + } else { + en = fifo->engine[engn].engine->subdev.name; + } + nvkm_debug(subdev, "engine %2d: runlist %2d pbdma %2d (%s)\n", - engn, runl, pbid, nvkm_subdev_name[engidx]); + tdev->engine, tdev->runlist, pbid, en); - fifo->engine[engn].engine = nvkm_device_engine(device, engidx); - fifo->engine[engn].runl = runl; + fifo->engine[engn].runl = tdev->runlist; fifo->engine[engn].pbid = pbid; fifo->engine_nr = max(fifo->engine_nr, engn + 1); - fifo->runlist[runl].engm |= 1 << engn; - fifo->runlist_nr = max(fifo->runlist_nr, runl + 1); + fifo->runlist[tdev->runlist].engm |= BIT(engn); + fifo->runlist[tdev->runlist].engm_sw |= BIT(engn); + if (tdev->type == NVKM_ENGINE_GR) + fifo->runlist[tdev->runlist].engm_sw |= BIT(GK104_FIFO_ENGN_SW); + fifo->runlist_nr = max(fifo->runlist_nr, tdev->runlist + 1); } kfree(map); @@ -999,7 +1023,7 @@ gk104_fifo_oneinit(struct nvkm_fifo *base) return nvkm_memory_map(fifo->user.mem, 0, bar, fifo->user.bar, NULL, 0); } -static void +void gk104_fifo_init(struct nvkm_fifo *base) { struct gk104_fifo *fifo = gk104_fifo(base); @@ -1031,7 +1055,7 @@ gk104_fifo_init(struct nvkm_fifo *base) nvkm_wr32(device, 0x002140, 0x7fffffff); } -static void * +void * gk104_fifo_dtor(struct nvkm_fifo *base) { struct gk104_fifo *fifo = gk104_fifo(base); @@ -1058,6 +1082,8 @@ gk104_fifo_ = { .fini = gk104_fifo_fini, .intr = gk104_fifo_intr, .fault = gk104_fifo_fault, + .engine_id = gk104_fifo_engine_id, + .id_engine = gk104_fifo_id_engine, .uevent_init = gk104_fifo_uevent_init, .uevent_fini = gk104_fifo_uevent_fini, .recover_chan = gk104_fifo_recover_chan, @@ -1067,7 +1093,7 @@ gk104_fifo_ = { int gk104_fifo_new_(const struct gk104_fifo_func *func, struct nvkm_device *device, - int index, int nr, struct nvkm_fifo **pfifo) + enum nvkm_subdev_type type, int inst, int nr, struct nvkm_fifo **pfifo) { struct gk104_fifo *fifo; @@ -1077,7 +1103,7 @@ gk104_fifo_new_(const struct gk104_fifo_func *func, struct nvkm_device *device, INIT_WORK(&fifo->recover.work, gk104_fifo_recover_work); *pfifo = &fifo->base; - return nvkm_fifo_ctor(&gk104_fifo_, device, index, nr, &fifo->base); + return nvkm_fifo_ctor(&gk104_fifo_, device, type, inst, nr, &fifo->base); } const struct nvkm_enum @@ -1109,12 +1135,12 @@ gk104_fifo_fault_engine[] = { { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP }, { 0x13, "PERF" }, { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC }, - { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 }, - { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 }, + { 0x15, "CE0", NULL, NVKM_ENGINE_CE, 0 }, + { 0x16, "CE1", NULL, NVKM_ENGINE_CE, 1 }, { 0x17, "PMU" }, { 0x18, "PTP" }, { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC }, - { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 }, + { 0x1b, "CE2", NULL, NVKM_ENGINE_CE, 2 }, {} }; @@ -1204,6 +1230,7 @@ gk104_fifo_fault_gpcclient[] = { static const struct gk104_fifo_func gk104_fifo = { + .intr.fault = gf100_fifo_intr_fault, .pbdma = &gk104_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gk104_fifo_fault_engine, @@ -1215,7 +1242,8 @@ gk104_fifo = { }; int -gk104_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gk104_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gk104_fifo, device, index, 4096, pfifo); + return gk104_fifo_new_(&gk104_fifo, device, type, inst, 4096, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h index c33f4593cbc6..f2d12ae73944 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h @@ -35,6 +35,7 @@ struct gk104_fifo { struct list_head cgrp; struct list_head chan; u32 engm; + u32 engm_sw; } runlist[16]; int runlist_nr; @@ -45,6 +46,10 @@ struct gk104_fifo { }; struct gk104_fifo_func { + struct { + void (*fault)(struct nvkm_fifo *, int unit); + } intr; + const struct gk104_fifo_pbdma_func { int (*nr)(struct gk104_fifo *); void (*init)(struct gk104_fifo *); @@ -83,11 +88,43 @@ struct gk104_fifo_func { bool cgrp_force; }; -int gk104_fifo_new_(const struct gk104_fifo_func *, struct nvkm_device *, +struct gk104_fifo_engine_status { + bool busy; + bool faulted; + bool chsw; + bool save; + bool load; + struct { + bool tsg; + u32 id; + } prev, next, *chan; +}; + +int gk104_fifo_new_(const struct gk104_fifo_func *, struct nvkm_device *, enum nvkm_subdev_type, int index, int nr, struct nvkm_fifo **); void gk104_fifo_runlist_insert(struct gk104_fifo *, struct gk104_fifo_chan *); void gk104_fifo_runlist_remove(struct gk104_fifo *, struct gk104_fifo_chan *); void gk104_fifo_runlist_update(struct gk104_fifo *, int runl); +void gk104_fifo_engine_status(struct gk104_fifo *fifo, int engn, + struct gk104_fifo_engine_status *status); +void gk104_fifo_intr_bind(struct gk104_fifo *fifo); +void gk104_fifo_intr_chsw(struct gk104_fifo *fifo); +void gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo); +void gk104_fifo_intr_pbdma_0(struct gk104_fifo *fifo, int unit); +void gk104_fifo_intr_pbdma_1(struct gk104_fifo *fifo, int unit); +void gk104_fifo_intr_runlist(struct gk104_fifo *fifo); +void gk104_fifo_intr_engine(struct gk104_fifo *fifo); +void *gk104_fifo_dtor(struct nvkm_fifo *base); +int gk104_fifo_oneinit(struct nvkm_fifo *base); +int gk104_fifo_info(struct nvkm_fifo *base, u64 mthd, u64 *data); +void gk104_fifo_init(struct nvkm_fifo *base); +void gk104_fifo_fini(struct nvkm_fifo *base); +int gk104_fifo_class_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, + void *argv, u32 argc, struct nvkm_object **pobject); +int gk104_fifo_class_get(struct nvkm_fifo *base, int index, + struct nvkm_oclass *oclass); +void gk104_fifo_uevent_fini(struct nvkm_fifo *fifo); +void gk104_fifo_uevent_init(struct nvkm_fifo *fifo); extern const struct gk104_fifo_pbdma_func gk104_fifo_pbdma; int gk104_fifo_pbdma_nr(struct gk104_fifo *); @@ -110,12 +147,14 @@ void gk110_fifo_runlist_cgrp(struct nvkm_fifo_cgrp *, extern const struct gk104_fifo_pbdma_func gk208_fifo_pbdma; void gk208_fifo_pbdma_init_timeout(struct gk104_fifo *); +void gm107_fifo_intr_fault(struct nvkm_fifo *, int); extern const struct nvkm_enum gm107_fifo_fault_engine[]; extern const struct gk104_fifo_runlist_func gm107_fifo_runlist; extern const struct gk104_fifo_pbdma_func gm200_fifo_pbdma; int gm200_fifo_pbdma_nr(struct gk104_fifo *); +void gp100_fifo_intr_fault(struct nvkm_fifo *, int); extern const struct nvkm_enum gp100_fifo_fault_engine[]; extern const struct nvkm_enum gv100_fifo_fault_access[]; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c index 8adfa6b182cb..915278c7e012 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c @@ -48,6 +48,7 @@ gk110_fifo_runlist = { static const struct gk104_fifo_func gk110_fifo = { + .intr.fault = gf100_fifo_intr_fault, .pbdma = &gk104_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gk104_fifo_fault_engine, @@ -59,7 +60,8 @@ gk110_fifo = { }; int -gk110_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gk110_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gk110_fifo, device, index, 4096, pfifo); + return gk104_fifo_new_(&gk110_fifo, device, type, inst, 4096, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c index 9553fb4af601..cb703693de52 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c @@ -45,6 +45,7 @@ gk208_fifo_pbdma = { static const struct gk104_fifo_func gk208_fifo = { + .intr.fault = gf100_fifo_intr_fault, .pbdma = &gk208_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gk104_fifo_fault_engine, @@ -56,7 +57,8 @@ gk208_fifo = { }; int -gk208_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gk208_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gk208_fifo, device, index, 1024, pfifo); + return gk104_fifo_new_(&gk208_fifo, device, type, inst, 1024, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c index a4c6ac3cd6c7..6e35cf44c640 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c @@ -26,6 +26,7 @@ static const struct gk104_fifo_func gk20a_fifo = { + .intr.fault = gf100_fifo_intr_fault, .pbdma = &gk208_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gk104_fifo_fault_engine, @@ -37,7 +38,8 @@ gk20a_fifo = { }; int -gk20a_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gk20a_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gk20a_fifo, device, index, 128, pfifo); + return gk104_fifo_new_(&gk20a_fifo, device, type, inst, 128, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c index acf230764cb0..7af6e687d474 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c @@ -25,6 +25,7 @@ #include "changk104.h" #include <core/gpuobj.h> +#include <subdev/fault.h> #include <nvif/class.h> @@ -67,8 +68,33 @@ gm107_fifo_fault_engine[] = { {} }; +void +gm107_fifo_intr_fault(struct nvkm_fifo *fifo, int unit) +{ + struct nvkm_device *device = fifo->engine.subdev.device; + u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); + u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); + u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); + u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); + struct nvkm_fault_data info; + + info.inst = (u64)inst << 12; + info.addr = ((u64)vahi << 32) | valo; + info.time = 0; + info.engine = unit; + info.valid = 1; + info.gpc = (type & 0x1f000000) >> 24; + info.client = (type & 0x00003f00) >> 8; + info.access = (type & 0x00000080) >> 7; + info.hub = (type & 0x00000040) >> 6; + info.reason = (type & 0x0000000f); + + nvkm_fifo_fault(fifo, &info); +} + static const struct gk104_fifo_func gm107_fifo = { + .intr.fault = gm107_fifo_intr_fault, .pbdma = &gk208_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gm107_fifo_fault_engine, @@ -80,7 +106,8 @@ gm107_fifo = { }; int -gm107_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gm107_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gm107_fifo, device, index, 2048, pfifo); + return gk104_fifo_new_(&gm107_fifo, device, type, inst, 2048, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c index b96c1c5d6577..573658cb6c73 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c @@ -42,6 +42,7 @@ gm200_fifo_pbdma = { static const struct gk104_fifo_func gm200_fifo = { + .intr.fault = gm107_fifo_intr_fault, .pbdma = &gm200_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gm107_fifo_fault_engine, @@ -53,7 +54,8 @@ gm200_fifo = { }; int -gm200_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gm200_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gm200_fifo, device, index, 4096, pfifo); + return gk104_fifo_new_(&gm200_fifo, device, type, inst, 4096, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c index a49539b9e4ec..556c97e54f14 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c @@ -26,6 +26,7 @@ static const struct gk104_fifo_func gm20b_fifo = { + .intr.fault = gm107_fifo_intr_fault, .pbdma = &gm200_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gm107_fifo_fault_engine, @@ -37,7 +38,8 @@ gm20b_fifo = { }; int -gm20b_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gm20b_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gm20b_fifo, device, index, 512, pfifo); + return gk104_fifo_new_(&gm20b_fifo, device, type, inst, 512, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c index 54377e0f6a88..6b46b6b65b87 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c @@ -24,6 +24,8 @@ #include "gk104.h" #include "changk104.h" +#include <subdev/fault.h> + #include <nvif/class.h> const struct nvkm_enum @@ -50,8 +52,33 @@ gp100_fifo_fault_engine[] = { {} }; +void +gp100_fifo_intr_fault(struct nvkm_fifo *fifo, int unit) +{ + struct nvkm_device *device = fifo->engine.subdev.device; + u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); + u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); + u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); + u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); + struct nvkm_fault_data info; + + info.inst = (u64)inst << 12; + info.addr = ((u64)vahi << 32) | valo; + info.time = 0; + info.engine = unit; + info.valid = 1; + info.gpc = (type & 0x1f000000) >> 24; + info.hub = (type & 0x00100000) >> 20; + info.access = (type & 0x00070000) >> 16; + info.client = (type & 0x00007f00) >> 8; + info.reason = (type & 0x0000001f); + + nvkm_fifo_fault(fifo, &info); +} + static const struct gk104_fifo_func gp100_fifo = { + .intr.fault = gp100_fifo_intr_fault, .pbdma = &gm200_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gp100_fifo_fault_engine, @@ -64,7 +91,8 @@ gp100_fifo = { }; int -gp100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gp100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gp100_fifo, device, index, 4096, pfifo); + return gk104_fifo_new_(&gp100_fifo, device, type, inst, 4096, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c index 778ba7e46fb3..7a5929cb4d29 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c @@ -26,6 +26,7 @@ static const struct gk104_fifo_func gp10b_fifo = { + .intr.fault = gp100_fifo_intr_fault, .pbdma = &gm200_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gp100_fifo_fault_engine, @@ -38,7 +39,8 @@ gp10b_fifo = { }; int -gp10b_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gp10b_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gp10b_fifo, device, index, 512, pfifo); + return gk104_fifo_new_(&gp10b_fifo, device, type, inst, 512, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c index 75f9632789b3..4e78bbe3b94b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c @@ -52,11 +52,10 @@ gf100_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type, static u32 gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) { - switch (engine->subdev.index) { + switch (engine->subdev.type) { case NVKM_ENGINE_SW : return 0; case NVKM_ENGINE_GR : return 0x0210; - case NVKM_ENGINE_CE0 : return 0x0230; - case NVKM_ENGINE_CE1 : return 0x0240; + case NVKM_ENGINE_CE : return 0x0230 + (engine->subdev.inst * 0x10); case NVKM_ENGINE_MSPDEC: return 0x0250; case NVKM_ENGINE_MSPPP : return 0x0260; case NVKM_ENGINE_MSVLD : return 0x0270; @@ -66,6 +65,15 @@ gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) } } +static struct gf100_fifo_engn * +gf100_fifo_gpfifo_engine(struct gf100_fifo_chan *chan, struct nvkm_engine *engine) +{ + int engi = chan->base.fifo->func->engine_id(chan->base.fifo, engine); + if (engi >= 0) + return &chan->engn[engi]; + return NULL; +} + static int gf100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, struct nvkm_engine *engine, bool suspend) @@ -77,7 +85,7 @@ gf100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, struct nvkm_gpuobj *inst = chan->base.inst; int ret = 0; - mutex_lock(&subdev->mutex); + mutex_lock(&chan->fifo->base.mutex); nvkm_wr32(device, 0x002634, chan->base.chid); if (nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x002634) == chan->base.chid) @@ -87,7 +95,7 @@ gf100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, chan->base.chid, chan->base.object.client->name); ret = -ETIMEDOUT; } - mutex_unlock(&subdev->mutex); + mutex_unlock(&chan->fifo->base.mutex); if (ret && suspend) return ret; @@ -108,13 +116,13 @@ gf100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base, { const u32 offset = gf100_fifo_gpfifo_engine_addr(engine); struct gf100_fifo_chan *chan = gf100_fifo_chan(base); + struct gf100_fifo_engn *engn = gf100_fifo_gpfifo_engine(chan, engine); struct nvkm_gpuobj *inst = chan->base.inst; if (offset) { - u64 addr = chan->engn[engine->subdev.index].vma->addr; nvkm_kmap(inst); - nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4); - nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr)); + nvkm_wo32(inst, offset + 0x00, lower_32_bits(engn->vma->addr) | 4); + nvkm_wo32(inst, offset + 0x04, upper_32_bits(engn->vma->addr)); nvkm_done(inst); } @@ -126,8 +134,9 @@ gf100_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct gf100_fifo_chan *chan = gf100_fifo_chan(base); - nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma); - nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst); + struct gf100_fifo_engn *engn = gf100_fifo_gpfifo_engine(chan, engine); + nvkm_vmm_put(chan->base.vmm, &engn->vma); + nvkm_gpuobj_del(&engn->inst); } static int @@ -136,23 +145,21 @@ gf100_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base, struct nvkm_object *object) { struct gf100_fifo_chan *chan = gf100_fifo_chan(base); - int engn = engine->subdev.index; + struct gf100_fifo_engn *engn = gf100_fifo_gpfifo_engine(chan, engine); int ret; if (!gf100_fifo_gpfifo_engine_addr(engine)) return 0; - ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst); + ret = nvkm_object_bind(object, NULL, 0, &engn->inst); if (ret) return ret; - ret = nvkm_vmm_get(chan->base.vmm, 12, chan->engn[engn].inst->size, - &chan->engn[engn].vma); + ret = nvkm_vmm_get(chan->base.vmm, 12, engn->inst->size, &engn->vma); if (ret) return ret; - return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm, - chan->engn[engn].vma, NULL, 0); + return nvkm_memory_map(engn->inst, 0, chan->base.vmm, engn->vma, NULL, 0); } static void @@ -243,13 +250,13 @@ gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&gf100_fifo_gpfifo_func, &fifo->base, 0x1000, 0x1000, true, args->v0.vmm, 0, - (1ULL << NVKM_ENGINE_CE0) | - (1ULL << NVKM_ENGINE_CE1) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_MSPDEC) | - (1ULL << NVKM_ENGINE_MSPPP) | - (1ULL << NVKM_ENGINE_MSVLD) | - (1ULL << NVKM_ENGINE_SW), + BIT(GF100_FIFO_ENGN_GR) | + BIT(GF100_FIFO_ENGN_MSPDEC) | + BIT(GF100_FIFO_ENGN_MSPPP) | + BIT(GF100_FIFO_ENGN_MSVLD) | + BIT(GF100_FIFO_ENGN_CE0) | + BIT(GF100_FIFO_ENGN_CE1) | + BIT(GF100_FIFO_ENGN_SW), 1, fifo->user.bar->addr, 0x1000, oclass, &chan->base); if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c index 728a1edbf98c..ae6c4d846eb5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c @@ -65,19 +65,18 @@ int gk104_fifo_gpfifo_kick(struct gk104_fifo_chan *chan) { int ret; - mutex_lock(&chan->base.fifo->engine.subdev.mutex); + mutex_lock(&chan->base.fifo->mutex); ret = gk104_fifo_gpfifo_kick_locked(chan); - mutex_unlock(&chan->base.fifo->engine.subdev.mutex); + mutex_unlock(&chan->base.fifo->mutex); return ret; } static u32 gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) { - switch (engine->subdev.index) { + switch (engine->subdev.type) { case NVKM_ENGINE_SW : - case NVKM_ENGINE_CE0...NVKM_ENGINE_CE_LAST: - return 0; + case NVKM_ENGINE_CE : return 0; case NVKM_ENGINE_GR : return 0x0210; case NVKM_ENGINE_SEC : return 0x0220; case NVKM_ENGINE_MSPDEC: return 0x0250; @@ -85,15 +84,26 @@ gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) case NVKM_ENGINE_MSVLD : return 0x0270; case NVKM_ENGINE_VIC : return 0x0280; case NVKM_ENGINE_MSENC : return 0x0290; - case NVKM_ENGINE_NVDEC0: return 0x02100270; - case NVKM_ENGINE_NVENC0: return 0x02100290; - case NVKM_ENGINE_NVENC1: return 0x0210; + case NVKM_ENGINE_NVDEC : return 0x02100270; + case NVKM_ENGINE_NVENC : + if (engine->subdev.inst) + return 0x0210; + return 0x02100290; default: WARN_ON(1); return 0; } } +struct gk104_fifo_engn * +gk104_fifo_gpfifo_engine(struct gk104_fifo_chan *chan, struct nvkm_engine *engine) +{ + int engi = chan->base.fifo->func->engine_id(chan->base.fifo, engine); + if (engi >= 0) + return &chan->engn[engi]; + return NULL; +} + static int gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, struct nvkm_engine *engine, bool suspend) @@ -126,13 +136,13 @@ gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct gk104_fifo_chan *chan = gk104_fifo_chan(base); + struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine); struct nvkm_gpuobj *inst = chan->base.inst; u32 offset = gk104_fifo_gpfifo_engine_addr(engine); if (offset) { - u64 addr = chan->engn[engine->subdev.index].vma->addr; - u32 datalo = lower_32_bits(addr) | 0x00000004; - u32 datahi = upper_32_bits(addr); + u32 datalo = lower_32_bits(engn->vma->addr) | 0x00000004; + u32 datahi = upper_32_bits(engn->vma->addr); nvkm_kmap(inst); nvkm_wo32(inst, (offset & 0xffff) + 0x00, datalo); nvkm_wo32(inst, (offset & 0xffff) + 0x04, datahi); @@ -151,8 +161,9 @@ gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct gk104_fifo_chan *chan = gk104_fifo_chan(base); - nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma); - nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst); + struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine); + nvkm_vmm_put(chan->base.vmm, &engn->vma); + nvkm_gpuobj_del(&engn->inst); } int @@ -161,23 +172,21 @@ gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base, struct nvkm_object *object) { struct gk104_fifo_chan *chan = gk104_fifo_chan(base); - int engn = engine->subdev.index; + struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine); int ret; if (!gk104_fifo_gpfifo_engine_addr(engine)) return 0; - ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst); + ret = nvkm_object_bind(object, NULL, 0, &engn->inst); if (ret) return ret; - ret = nvkm_vmm_get(chan->base.vmm, 12, chan->engn[engn].inst->size, - &chan->engn[engn].vma); + ret = nvkm_vmm_get(chan->base.vmm, 12, engn->inst->size, &engn->vma); if (ret) return ret; - return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm, - chan->engn[engn].vma, NULL, 0); + return nvkm_memory_map(engn->inst, 0, chan->base.vmm, engn->vma, NULL, 0); } void @@ -247,23 +256,12 @@ gk104_fifo_gpfifo_new_(struct gk104_fifo *fifo, u64 *runlists, u16 *chid, { struct gk104_fifo_chan *chan; int runlist = ffs(*runlists) -1, ret, i; - unsigned long engm; - u64 subdevs = 0; u64 usermem; if (!vmm || runlist < 0 || runlist >= fifo->runlist_nr) return -EINVAL; *runlists = BIT_ULL(runlist); - engm = fifo->runlist[runlist].engm; - for_each_set_bit(i, &engm, fifo->engine_nr) { - if (fifo->engine[i].engine) - subdevs |= BIT_ULL(fifo->engine[i].engine->subdev.index); - } - - if (subdevs & BIT_ULL(NVKM_ENGINE_GR)) - subdevs |= BIT_ULL(NVKM_ENGINE_SW); - /* Allocate the channel. */ if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) return -ENOMEM; @@ -273,7 +271,7 @@ gk104_fifo_gpfifo_new_(struct gk104_fifo *fifo, u64 *runlists, u16 *chid, INIT_LIST_HEAD(&chan->head); ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base, - 0x1000, 0x1000, true, vmm, 0, subdevs, + 0x1000, 0x1000, true, vmm, 0, fifo->runlist[runlist].engm_sw, 1, fifo->user.bar->addr, 0x200, oclass, &chan->base); if (ret) @@ -343,8 +341,6 @@ gk104_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass, "runlist %016llx priv %d\n", args->v0.version, args->v0.vmm, args->v0.ioffset, args->v0.ilength, args->v0.runlist, args->v0.priv); - if (args->v0.priv && !oclass->client->super) - return -EINVAL; return gk104_fifo_gpfifo_new_(fifo, &args->v0.runlist, &args->v0.chid, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c index a7462cf59d65..743791c514fe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c @@ -44,7 +44,7 @@ gv100_fifo_gpfifo_engine_valid(struct gk104_fifo_chan *chan, bool ce, bool valid int ret; /* Block runlist to prevent the channel from being rescheduled. */ - mutex_lock(&subdev->mutex); + mutex_lock(&chan->fifo->base.mutex); nvkm_mask(device, 0x002630, BIT(chan->runl), BIT(chan->runl)); /* Preempt the channel. */ @@ -58,7 +58,7 @@ gv100_fifo_gpfifo_engine_valid(struct gk104_fifo_chan *chan, bool ce, bool valid /* Resume runlist. */ nvkm_mask(device, 0x002630, BIT(chan->runl), 0); - mutex_unlock(&subdev->mutex); + mutex_unlock(&chan->fifo->base.mutex); return ret; } @@ -70,8 +70,7 @@ gv100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, struct nvkm_gpuobj *inst = chan->base.inst; int ret; - if (engine->subdev.index >= NVKM_ENGINE_CE0 && - engine->subdev.index <= NVKM_ENGINE_CE_LAST) + if (engine->subdev.type == NVKM_ENGINE_CE) return gk104_fifo_gpfifo_kick(chan); ret = gv100_fifo_gpfifo_engine_valid(chan, false, false); @@ -90,17 +89,15 @@ gv100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct gk104_fifo_chan *chan = gk104_fifo_chan(base); + struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine); struct nvkm_gpuobj *inst = chan->base.inst; - u64 addr; - if (engine->subdev.index >= NVKM_ENGINE_CE0 && - engine->subdev.index <= NVKM_ENGINE_CE_LAST) + if (engine->subdev.type == NVKM_ENGINE_CE) return 0; - addr = chan->engn[engine->subdev.index].vma->addr; nvkm_kmap(inst); - nvkm_wo32(inst, 0x210, lower_32_bits(addr) | 0x00000004); - nvkm_wo32(inst, 0x214, upper_32_bits(addr)); + nvkm_wo32(inst, 0x210, lower_32_bits(engn->vma->addr) | 0x00000004); + nvkm_wo32(inst, 0x214, upper_32_bits(engn->vma->addr)); nvkm_done(inst); return gv100_fifo_gpfifo_engine_valid(chan, false, true); @@ -129,8 +126,6 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func, struct nvkm_device *device = fifo->base.engine.subdev.device; struct gk104_fifo_chan *chan; int runlist = ffs(*runlists) -1, ret, i; - unsigned long engm; - u64 subdevs = 0; u64 usermem, mthd; u32 size; @@ -138,12 +133,6 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func, return -EINVAL; *runlists = BIT_ULL(runlist); - engm = fifo->runlist[runlist].engm; - for_each_set_bit(i, &engm, fifo->engine_nr) { - if (fifo->engine[i].engine) - subdevs |= BIT_ULL(fifo->engine[i].engine->subdev.index); - } - /* Allocate the channel. */ if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) return -ENOMEM; @@ -153,7 +142,7 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func, INIT_LIST_HEAD(&chan->head); ret = nvkm_fifo_chan_ctor(func, &fifo->base, 0x1000, 0x1000, true, vmm, - 0, subdevs, 1, fifo->user.bar->addr, 0x200, + 0, fifo->runlist[runlist].engm, 1, fifo->user.bar->addr, 0x200, oclass, &chan->base); if (ret) return ret; @@ -237,8 +226,6 @@ gv100_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass, "runlist %016llx priv %d\n", args->v0.version, args->v0.vmm, args->v0.ioffset, args->v0.ilength, args->v0.runlist, args->v0.priv); - if (args->v0.priv && !oclass->client->super) - return -EINVAL; return gv100_fifo_gpfifo_new_(&gv100_fifo_gpfifo, fifo, &args->v0.runlist, &args->v0.chid, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c index abef7fb6e2d3..99aafa103a31 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c @@ -65,8 +65,6 @@ tu102_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass, "runlist %016llx priv %d\n", args->v0.version, args->v0.vmm, args->v0.ioffset, args->v0.ilength, args->v0.runlist, args->v0.priv); - if (args->v0.priv && !oclass->client->super) - return -EINVAL; return gv100_fifo_gpfifo_new_(&tu102_fifo_gpfifo, fifo, &args->v0.runlist, &args->v0.chid, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c index 6ee1bb32a071..70e16a91ac12 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c @@ -301,7 +301,8 @@ gv100_fifo = { }; int -gv100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gv100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gv100_fifo, device, index, 4096, pfifo); + return gk104_fifo_new_(&gv100_fifo, device, type, inst, 4096, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index 93493b335d76..c6730c124769 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@ -94,6 +94,38 @@ __releases(fifo->base.lock) spin_unlock_irqrestore(&fifo->base.lock, flags); } +struct nvkm_engine * +nv04_fifo_id_engine(struct nvkm_fifo *fifo, int engi) +{ + enum nvkm_subdev_type type; + + switch (engi) { + case NV04_FIFO_ENGN_SW : type = NVKM_ENGINE_SW; break; + case NV04_FIFO_ENGN_GR : type = NVKM_ENGINE_GR; break; + case NV04_FIFO_ENGN_MPEG: type = NVKM_ENGINE_MPEG; break; + case NV04_FIFO_ENGN_DMA : type = NVKM_ENGINE_DMAOBJ; break; + default: + WARN_ON(1); + return NULL; + } + + return nvkm_device_engine(fifo->engine.subdev.device, type, 0); +} + +int +nv04_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine) +{ + switch (engine->subdev.type) { + case NVKM_ENGINE_SW : return NV04_FIFO_ENGN_SW; + case NVKM_ENGINE_GR : return NV04_FIFO_ENGN_GR; + case NVKM_ENGINE_MPEG : return NV04_FIFO_ENGN_MPEG; + case NVKM_ENGINE_DMAOBJ: return NV04_FIFO_ENGN_DMA; + default: + WARN_ON(1); + return 0; + } +} + static const char * nv_dma_state_err(u32 state) { @@ -117,10 +149,10 @@ nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data) switch (mthd) { case 0x0000 ... 0x0000: /* subchannel's engine -> software */ nvkm_wr32(device, 0x003280, (engine &= ~mask)); - /* fall through */ + fallthrough; case 0x0180 ... 0x01fc: /* handle -> instance */ data = nvkm_rd32(device, 0x003258) & 0x0000ffff; - /* fall through */ + fallthrough; case 0x0100 ... 0x017c: case 0x0200 ... 0x1ffc: /* pass method down to sw */ if (!(engine & mask) && sw) @@ -326,7 +358,7 @@ nv04_fifo_init(struct nvkm_fifo *base) int nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, - int index, int nr, const struct nv04_fifo_ramfc *ramfc, + enum nvkm_subdev_type type, int inst, int nr, const struct nv04_fifo_ramfc *ramfc, struct nvkm_fifo **pfifo) { struct nv04_fifo *fifo; @@ -337,7 +369,7 @@ nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, fifo->ramfc = ramfc; *pfifo = &fifo->base; - ret = nvkm_fifo_ctor(func, device, index, nr, &fifo->base); + ret = nvkm_fifo_ctor(func, device, type, inst, nr, &fifo->base); if (ret) return ret; @@ -349,6 +381,8 @@ static const struct nvkm_fifo_func nv04_fifo = { .init = nv04_fifo_init, .intr = nv04_fifo_intr, + .engine_id = nv04_fifo_engine_id, + .id_engine = nv04_fifo_id_engine, .pause = nv04_fifo_pause, .start = nv04_fifo_start, .chan = { @@ -358,8 +392,8 @@ nv04_fifo = { }; int -nv04_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +nv04_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return nv04_fifo_new_(&nv04_fifo, device, index, 16, - nv04_fifo_ramfc, pfifo); + return nv04_fifo_new_(&nv04_fifo, device, type, inst, 16, nv04_fifo_ramfc, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h index e5ecceee77ae..3f23bcde4a54 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h @@ -17,8 +17,7 @@ struct nv04_fifo { const struct nv04_fifo_ramfc *ramfc; }; -int nv04_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *, - int index, int nr, const struct nv04_fifo_ramfc *, - struct nvkm_fifo **); +int nv04_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + int nr, const struct nv04_fifo_ramfc *, struct nvkm_fifo **); void nv04_fifo_init(struct nvkm_fifo *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c index f9a87deb2b3d..f8887f0f2f82 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c @@ -43,6 +43,8 @@ static const struct nvkm_fifo_func nv10_fifo = { .init = nv04_fifo_init, .intr = nv04_fifo_intr, + .engine_id = nv04_fifo_engine_id, + .id_engine = nv04_fifo_id_engine, .pause = nv04_fifo_pause, .start = nv04_fifo_start, .chan = { @@ -52,8 +54,8 @@ nv10_fifo = { }; int -nv10_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +nv10_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return nv04_fifo_new_(&nv10_fifo, device, index, 32, - nv10_fifo_ramfc, pfifo); + return nv04_fifo_new_(&nv10_fifo, device, type, inst, 32, nv10_fifo_ramfc, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c index f6d383a21222..3f94c7b5b054 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c @@ -81,6 +81,8 @@ static const struct nvkm_fifo_func nv17_fifo = { .init = nv17_fifo_init, .intr = nv04_fifo_intr, + .engine_id = nv04_fifo_engine_id, + .id_engine = nv04_fifo_id_engine, .pause = nv04_fifo_pause, .start = nv04_fifo_start, .chan = { @@ -90,8 +92,8 @@ nv17_fifo = { }; int -nv17_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +nv17_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return nv04_fifo_new_(&nv17_fifo, device, index, 32, - nv17_fifo_ramfc, pfifo); + return nv04_fifo_new_(&nv17_fifo, device, type, inst, 32, nv17_fifo_ramfc, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index 47c16821c37f..f9ea46809bc0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -81,7 +81,7 @@ nv40_fifo_init(struct nvkm_fifo *base) case 0x49: case 0x4b: nvkm_wr32(device, 0x002230, 0x00000001); - /* fall through */ + fallthrough; case 0x40: case 0x41: case 0x42: @@ -112,6 +112,8 @@ static const struct nvkm_fifo_func nv40_fifo = { .init = nv40_fifo_init, .intr = nv04_fifo_intr, + .engine_id = nv04_fifo_engine_id, + .id_engine = nv04_fifo_id_engine, .pause = nv04_fifo_pause, .start = nv04_fifo_start, .chan = { @@ -121,8 +123,8 @@ nv40_fifo = { }; int -nv40_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +nv40_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return nv04_fifo_new_(&nv40_fifo, device, index, 32, - nv40_fifo_ramfc, pfifo); + return nv04_fifo_new_(&nv40_fifo, device, type, inst, 32, nv40_fifo_ramfc, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c index fa6e094d8068..a08742cf425a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c @@ -51,9 +51,9 @@ nv50_fifo_runlist_update_locked(struct nv50_fifo *fifo) void nv50_fifo_runlist_update(struct nv50_fifo *fifo) { - mutex_lock(&fifo->base.engine.subdev.mutex); + mutex_lock(&fifo->base.mutex); nv50_fifo_runlist_update_locked(fifo); - mutex_unlock(&fifo->base.engine.subdev.mutex); + mutex_unlock(&fifo->base.mutex); } int @@ -107,7 +107,7 @@ nv50_fifo_dtor(struct nvkm_fifo *base) int nv50_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, - int index, struct nvkm_fifo **pfifo) + enum nvkm_subdev_type type, int inst, struct nvkm_fifo **pfifo) { struct nv50_fifo *fifo; int ret; @@ -116,7 +116,7 @@ nv50_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, return -ENOMEM; *pfifo = &fifo->base; - ret = nvkm_fifo_ctor(func, device, index, 128, &fifo->base); + ret = nvkm_fifo_ctor(func, device, type, inst, 128, &fifo->base); if (ret) return ret; @@ -131,17 +131,19 @@ nv50_fifo = { .oneinit = nv50_fifo_oneinit, .init = nv50_fifo_init, .intr = nv04_fifo_intr, + .engine_id = nv04_fifo_engine_id, + .id_engine = nv04_fifo_id_engine, .pause = nv04_fifo_pause, .start = nv04_fifo_start, .chan = { - &nv50_fifo_dma_oclass, &nv50_fifo_gpfifo_oclass, NULL }, }; int -nv50_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +nv50_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return nv50_fifo_new_(&nv50_fifo, device, index, pfifo); + return nv50_fifo_new_(&nv50_fifo, device, type, inst, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h index 87d30b6bd2ea..0111e7e5a4e3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h @@ -10,8 +10,8 @@ struct nv50_fifo { int cur_runlist; }; -int nv50_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *, - int index, struct nvkm_fifo **); +int nv50_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_fifo **); void *nv50_fifo_dtor(struct nvkm_fifo *); int nv50_fifo_oneinit(struct nvkm_fifo *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h index c66f5370b21f..899272801a8b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h @@ -4,8 +4,8 @@ #define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine) #include <engine/fifo.h> -int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *, - int index, int nr, struct nvkm_fifo *); +int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + int nr, struct nvkm_fifo *); void nvkm_fifo_uevent(struct nvkm_fifo *); void nvkm_fifo_cevent(struct nvkm_fifo *); void nvkm_fifo_kevent(struct nvkm_fifo *, int chid); @@ -23,6 +23,8 @@ struct nvkm_fifo_func { void (*fini)(struct nvkm_fifo *); void (*intr)(struct nvkm_fifo *); void (*fault)(struct nvkm_fifo *, struct nvkm_fault_data *); + int (*engine_id)(struct nvkm_fifo *, struct nvkm_engine *); + struct nvkm_engine *(*id_engine)(struct nvkm_fifo *, int engi); void (*pause)(struct nvkm_fifo *, unsigned long *); void (*start)(struct nvkm_fifo *, unsigned long *); void (*uevent_init)(struct nvkm_fifo *); @@ -35,6 +37,13 @@ struct nvkm_fifo_func { }; void nv04_fifo_intr(struct nvkm_fifo *); +int nv04_fifo_engine_id(struct nvkm_fifo *, struct nvkm_engine *); +struct nvkm_engine *nv04_fifo_id_engine(struct nvkm_fifo *, int); void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *); void nv04_fifo_start(struct nvkm_fifo *, unsigned long *); + +void gf100_fifo_intr_fault(struct nvkm_fifo *, int); + +int gk104_fifo_engine_id(struct nvkm_fifo *, struct nvkm_engine *); +struct nvkm_engine *gk104_fifo_id_engine(struct nvkm_fifo *, int); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c index 005f3e1729b9..260b197f81bc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c @@ -24,7 +24,13 @@ #include "changk104.h" #include "user.h" +#include <core/client.h> #include <core/gpuobj.h> +#include <subdev/bar.h> +#include <subdev/fault.h> +#include <subdev/top.h> +#include <subdev/timer.h> +#include <engine/sw.h> #include <nvif/class.h> @@ -43,7 +49,7 @@ tu102_fifo_runlist_commit(struct gk104_fifo *fifo, int runl, /*XXX: how to wait? can you even wait? */ } -const struct gk104_fifo_runlist_func +static const struct gk104_fifo_runlist_func tu102_fifo_runlist = { .size = 16, .cgrp = gv100_fifo_runlist_cgrp, @@ -109,8 +115,363 @@ tu102_fifo = { .cgrp_force = true, }; +static void +tu102_fifo_recover_work(struct work_struct *w) +{ + struct gk104_fifo *fifo = container_of(w, typeof(*fifo), recover.work); + struct nvkm_device *device = fifo->base.engine.subdev.device; + struct nvkm_engine *engine; + unsigned long flags; + u32 engm, runm, todo; + int engn, runl; + + spin_lock_irqsave(&fifo->base.lock, flags); + runm = fifo->recover.runm; + engm = fifo->recover.engm; + fifo->recover.engm = 0; + fifo->recover.runm = 0; + spin_unlock_irqrestore(&fifo->base.lock, flags); + + nvkm_mask(device, 0x002630, runm, runm); + + for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT(engn)) { + if ((engine = fifo->engine[engn].engine)) { + nvkm_subdev_fini(&engine->subdev, false); + WARN_ON(nvkm_subdev_init(&engine->subdev)); + } + } + + for (todo = runm; runl = __ffs(todo), todo; todo &= ~BIT(runl)) + gk104_fifo_runlist_update(fifo, runl); + + nvkm_mask(device, 0x002630, runm, 0x00000000); +} + +static void tu102_fifo_recover_engn(struct gk104_fifo *fifo, int engn); + +static void +tu102_fifo_recover_runl(struct gk104_fifo *fifo, int runl) +{ + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + const u32 runm = BIT(runl); + + assert_spin_locked(&fifo->base.lock); + if (fifo->recover.runm & runm) + return; + fifo->recover.runm |= runm; + + /* Block runlist to prevent channel assignment(s) from changing. */ + nvkm_mask(device, 0x002630, runm, runm); + + /* Schedule recovery. */ + nvkm_warn(subdev, "runlist %d: scheduled for recovery\n", runl); + schedule_work(&fifo->recover.work); +} + +static struct gk104_fifo_chan * +tu102_fifo_recover_chid(struct gk104_fifo *fifo, int runl, int chid) +{ + struct gk104_fifo_chan *chan; + struct nvkm_fifo_cgrp *cgrp; + + list_for_each_entry(chan, &fifo->runlist[runl].chan, head) { + if (chan->base.chid == chid) { + list_del_init(&chan->head); + return chan; + } + } + + list_for_each_entry(cgrp, &fifo->runlist[runl].cgrp, head) { + if (cgrp->id == chid) { + chan = list_first_entry(&cgrp->chan, typeof(*chan), head); + list_del_init(&chan->head); + if (!--cgrp->chan_nr) + list_del_init(&cgrp->head); + return chan; + } + } + + return NULL; +} + +static void +tu102_fifo_recover_chan(struct nvkm_fifo *base, int chid) +{ + struct gk104_fifo *fifo = gk104_fifo(base); + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + const u32 stat = nvkm_rd32(device, 0x800004 + (chid * 0x08)); + const u32 runl = (stat & 0x000f0000) >> 16; + const bool used = (stat & 0x00000001); + unsigned long engn, engm = fifo->runlist[runl].engm; + struct gk104_fifo_chan *chan; + + assert_spin_locked(&fifo->base.lock); + if (!used) + return; + + /* Lookup SW state for channel, and mark it as dead. */ + chan = tu102_fifo_recover_chid(fifo, runl, chid); + if (chan) { + chan->killed = true; + nvkm_fifo_kevent(&fifo->base, chid); + } + + /* Disable channel. */ + nvkm_wr32(device, 0x800004 + (chid * 0x08), stat | 0x00000800); + nvkm_warn(subdev, "channel %d: killed\n", chid); + + /* Block channel assignments from changing during recovery. */ + tu102_fifo_recover_runl(fifo, runl); + + /* Schedule recovery for any engines the channel is on. */ + for_each_set_bit(engn, &engm, fifo->engine_nr) { + struct gk104_fifo_engine_status status; + + gk104_fifo_engine_status(fifo, engn, &status); + if (!status.chan || status.chan->id != chid) + continue; + tu102_fifo_recover_engn(fifo, engn); + } +} + +static void +tu102_fifo_recover_engn(struct gk104_fifo *fifo, int engn) +{ + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + const u32 runl = fifo->engine[engn].runl; + const u32 engm = BIT(engn); + struct gk104_fifo_engine_status status; + + assert_spin_locked(&fifo->base.lock); + if (fifo->recover.engm & engm) + return; + fifo->recover.engm |= engm; + + /* Block channel assignments from changing during recovery. */ + tu102_fifo_recover_runl(fifo, runl); + + /* Determine which channel (if any) is currently on the engine. */ + gk104_fifo_engine_status(fifo, engn, &status); + if (status.chan) { + /* The channel is not longer viable, kill it. */ + tu102_fifo_recover_chan(&fifo->base, status.chan->id); + } + + /* Preempt the runlist */ + nvkm_wr32(device, 0x2638, BIT(runl)); + + /* Schedule recovery. */ + nvkm_warn(subdev, "engine %d: scheduled for recovery\n", engn); + schedule_work(&fifo->recover.work); +} + +static void +tu102_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) +{ + struct gk104_fifo *fifo = gk104_fifo(base); + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + const struct nvkm_enum *er, *ee, *ec, *ea; + struct nvkm_engine *engine = NULL; + struct nvkm_fifo_chan *chan; + unsigned long flags; + const char *en = ""; + char ct[8] = "HUB/"; + int engn; + + er = nvkm_enum_find(fifo->func->fault.reason, info->reason); + ee = nvkm_enum_find(fifo->func->fault.engine, info->engine); + if (info->hub) { + ec = nvkm_enum_find(fifo->func->fault.hubclient, info->client); + } else { + ec = nvkm_enum_find(fifo->func->fault.gpcclient, info->client); + snprintf(ct, sizeof(ct), "GPC%d/", info->gpc); + } + ea = nvkm_enum_find(fifo->func->fault.access, info->access); + + if (ee && ee->data2) { + switch (ee->data2) { + case NVKM_SUBDEV_BAR: + nvkm_bar_bar1_reset(device); + break; + case NVKM_SUBDEV_INSTMEM: + nvkm_bar_bar2_reset(device); + break; + case NVKM_ENGINE_IFB: + nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); + break; + default: + engine = nvkm_device_engine(device, ee->data2, 0); + break; + } + } + + if (ee == NULL) { + struct nvkm_subdev *subdev = nvkm_top_fault(device, info->engine); + if (subdev) { + if (subdev->func == &nvkm_engine) + engine = container_of(subdev, typeof(*engine), subdev); + en = engine->subdev.name; + } + } else { + en = ee->name; + } + + spin_lock_irqsave(&fifo->base.lock, flags); + chan = nvkm_fifo_chan_inst_locked(&fifo->base, info->inst); + + nvkm_error(subdev, + "fault %02x [%s] at %016llx engine %02x [%s] client %02x " + "[%s%s] reason %02x [%s] on channel %d [%010llx %s]\n", + info->access, ea ? ea->name : "", info->addr, + info->engine, ee ? ee->name : en, + info->client, ct, ec ? ec->name : "", + info->reason, er ? er->name : "", chan ? chan->chid : -1, + info->inst, chan ? chan->object.client->name : "unknown"); + + /* Kill the channel that caused the fault. */ + if (chan) + tu102_fifo_recover_chan(&fifo->base, chan->chid); + + /* Channel recovery will probably have already done this for the + * correct engine(s), but just in case we can't find the channel + * information... + */ + for (engn = 0; engn < fifo->engine_nr && engine; engn++) { + if (fifo->engine[engn].engine == engine) { + tu102_fifo_recover_engn(fifo, engn); + break; + } + } + + spin_unlock_irqrestore(&fifo->base.lock, flags); +} + +static void +tu102_fifo_intr_ctxsw_timeout(struct gk104_fifo *fifo) +{ + struct nvkm_device *device = fifo->base.engine.subdev.device; + unsigned long flags, engm; + u32 engn; + + spin_lock_irqsave(&fifo->base.lock, flags); + + engm = nvkm_rd32(device, 0x2a30); + nvkm_wr32(device, 0x2a30, engm); + + for_each_set_bit(engn, &engm, 32) + tu102_fifo_recover_engn(fifo, engn); + + spin_unlock_irqrestore(&fifo->base.lock, flags); +} + +static void +tu102_fifo_intr_sched(struct gk104_fifo *fifo) +{ + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + u32 intr = nvkm_rd32(device, 0x00254c); + u32 code = intr & 0x000000ff; + + nvkm_error(subdev, "SCHED_ERROR %02x\n", code); +} + +static void +tu102_fifo_intr(struct nvkm_fifo *base) +{ + struct gk104_fifo *fifo = gk104_fifo(base); + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + u32 mask = nvkm_rd32(device, 0x002140); + u32 stat = nvkm_rd32(device, 0x002100) & mask; + + if (stat & 0x00000001) { + gk104_fifo_intr_bind(fifo); + nvkm_wr32(device, 0x002100, 0x00000001); + stat &= ~0x00000001; + } + + if (stat & 0x00000002) { + tu102_fifo_intr_ctxsw_timeout(fifo); + stat &= ~0x00000002; + } + + if (stat & 0x00000100) { + tu102_fifo_intr_sched(fifo); + nvkm_wr32(device, 0x002100, 0x00000100); + stat &= ~0x00000100; + } + + if (stat & 0x00010000) { + gk104_fifo_intr_chsw(fifo); + nvkm_wr32(device, 0x002100, 0x00010000); + stat &= ~0x00010000; + } + + if (stat & 0x20000000) { + u32 mask = nvkm_rd32(device, 0x0025a0); + + while (mask) { + u32 unit = __ffs(mask); + + gk104_fifo_intr_pbdma_0(fifo, unit); + gk104_fifo_intr_pbdma_1(fifo, unit); + nvkm_wr32(device, 0x0025a0, (1 << unit)); + mask &= ~(1 << unit); + } + stat &= ~0x20000000; + } + + if (stat & 0x40000000) { + gk104_fifo_intr_runlist(fifo); + stat &= ~0x40000000; + } + + if (stat & 0x80000000) { + nvkm_wr32(device, 0x002100, 0x80000000); + gk104_fifo_intr_engine(fifo); + stat &= ~0x80000000; + } + + if (stat) { + nvkm_error(subdev, "INTR %08x\n", stat); + nvkm_mask(device, 0x002140, stat, 0x00000000); + nvkm_wr32(device, 0x002100, stat); + } +} + +static const struct nvkm_fifo_func +tu102_fifo_ = { + .dtor = gk104_fifo_dtor, + .oneinit = gk104_fifo_oneinit, + .info = gk104_fifo_info, + .init = gk104_fifo_init, + .fini = gk104_fifo_fini, + .intr = tu102_fifo_intr, + .fault = tu102_fifo_fault, + .engine_id = gk104_fifo_engine_id, + .id_engine = gk104_fifo_id_engine, + .uevent_init = gk104_fifo_uevent_init, + .uevent_fini = gk104_fifo_uevent_fini, + .recover_chan = tu102_fifo_recover_chan, + .class_get = gk104_fifo_class_get, + .class_new = gk104_fifo_class_new, +}; + int -tu102_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +tu102_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&tu102_fifo, device, index, 4096, pfifo); + struct gk104_fifo *fifo; + + if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) + return -ENOMEM; + fifo->func = &tu102_fifo; + INIT_WORK(&fifo->recover.work, tu102_fifo_recover_work); + *pfifo = &fifo->base; + + return nvkm_fifo_ctor(&tu102_fifo_, device, type, inst, 4096, &fifo->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild index 73724a8cb861..558c86fd8e82 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild @@ -36,8 +36,10 @@ nvkm-y += nvkm/engine/gr/gp100.o nvkm-y += nvkm/engine/gr/gp102.o nvkm-y += nvkm/engine/gr/gp104.o nvkm-y += nvkm/engine/gr/gp107.o +nvkm-y += nvkm/engine/gr/gp108.o nvkm-y += nvkm/engine/gr/gp10b.o nvkm-y += nvkm/engine/gr/gv100.o +nvkm-y += nvkm/engine/gr/tu102.o nvkm-y += nvkm/engine/gr/ctxnv40.o nvkm-y += nvkm/engine/gr/ctxnv50.o @@ -60,3 +62,4 @@ nvkm-y += nvkm/engine/gr/ctxgp102.o nvkm-y += nvkm/engine/gr/ctxgp104.o nvkm-y += nvkm/engine/gr/ctxgp107.o nvkm-y += nvkm/engine/gr/ctxgv100.o +nvkm-y += nvkm/engine/gr/ctxtu102.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c index d41fb94524e9..61759f54406e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c @@ -175,8 +175,8 @@ nvkm_gr = { int nvkm_gr_ctor(const struct nvkm_gr_func *func, struct nvkm_device *device, - int index, bool enable, struct nvkm_gr *gr) + enum nvkm_subdev_type type, int inst, bool enable, struct nvkm_gr *gr) { gr->func = func; - return nvkm_engine_ctor(&nvkm_gr, device, index, enable, &gr->engine); + return nvkm_engine_ctor(&nvkm_gr, device, type, inst, enable, &gr->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c index 85f2d1e950e8..297915719bf2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c @@ -1324,10 +1324,8 @@ gf100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) void gf100_grctx_generate_floorsweep(struct gf100_gr *gr) { - struct nvkm_device *device = gr->base.engine.subdev.device; const struct gf100_grctx_func *func = gr->func->grctx; - int gpc, sm, i, j; - u32 data; + int sm; for (sm = 0; sm < gr->sm_nr; sm++) { func->sm_id(gr, gr->sm[sm].gpc, gr->sm[sm].tpc, sm); @@ -1335,12 +1333,9 @@ gf100_grctx_generate_floorsweep(struct gf100_gr *gr) func->tpc_nr(gr, gr->sm[sm].gpc); } - for (gpc = 0, i = 0; i < 4; i++) { - for (data = 0, j = 0; j < 8 && gpc < gr->gpc_nr; j++, gpc++) - data |= gr->tpc_nr[gpc] << (j * 4); - nvkm_wr32(device, 0x406028 + (i * 4), data); - nvkm_wr32(device, 0x405870 + (i * 4), data); - } + gf100_gr_init_num_tpc_per_gpc(gr, false, true); + if (!func->skip_pd_num_tpc_per_gpc) + gf100_gr_init_num_tpc_per_gpc(gr, true, false); if (func->r4060a8) func->r4060a8(gr); @@ -1374,7 +1369,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) nvkm_mc_unk260(device, 0); - if (!gr->fuc_sw_ctx) { + if (!gr->sw_ctx) { gf100_gr_mmio(gr, grctx->hub); gf100_gr_mmio(gr, grctx->gpc_0); gf100_gr_mmio(gr, grctx->zcull); @@ -1382,7 +1377,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_mmio(gr, grctx->tpc); gf100_gr_mmio(gr, grctx->ppc); } else { - gf100_gr_mmio(gr, gr->fuc_sw_ctx); + gf100_gr_mmio(gr, gr->sw_ctx); } gf100_gr_wait_idle(gr); @@ -1401,8 +1396,8 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_wait_idle(gr); if (grctx->r400088) grctx->r400088(gr, false); - if (gr->fuc_bundle) - gf100_gr_icmd(gr, gr->fuc_bundle); + if (gr->bundle) + gf100_gr_icmd(gr, gr->bundle); else gf100_gr_icmd(gr, grctx->icmd); if (grctx->sw_veid_bundle_init) @@ -1411,8 +1406,8 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) nvkm_wr32(device, 0x404154, idle_timeout); - if (gr->fuc_method) - gf100_gr_mthd(gr, gr->fuc_method); + if (gr->method) + gf100_gr_mthd(gr, gr->method); else gf100_gr_mthd(gr, grctx->mthd); nvkm_mc_unk260(device, 1); @@ -1431,6 +1426,8 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) grctx->r419a3c(gr); if (grctx->r408840) grctx->r408840(gr); + if (grctx->r419c0c) + grctx->r419c0c(gr); } #define CB_RESERVED 0x80000 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h index 478b4723d0f9..32bbddc0993e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h @@ -57,6 +57,7 @@ struct gf100_grctx_func { /* floorsweeping */ void (*sm_id)(struct gf100_gr *, int gpc, int tpc, int sm); void (*tpc_nr)(struct gf100_gr *, int gpc); + bool skip_pd_num_tpc_per_gpc; void (*r4060a8)(struct gf100_gr *); void (*rop_mapping)(struct gf100_gr *); void (*alpha_beta_tables)(struct gf100_gr *); @@ -76,6 +77,7 @@ struct gf100_grctx_func { void (*r418e94)(struct gf100_gr *); void (*r419a3c)(struct gf100_gr *); void (*r408840)(struct gf100_gr *); + void (*r419c0c)(struct gf100_gr *); }; extern const struct gf100_grctx_func gf100_grctx; @@ -153,6 +155,14 @@ extern const struct gf100_grctx_func gp107_grctx; extern const struct gf100_grctx_func gv100_grctx; +extern const struct gf100_grctx_func tu102_grctx; +void gv100_grctx_unkn88c(struct gf100_gr *, bool); +void gv100_grctx_generate_unkn(struct gf100_gr *); +extern const struct gf100_gr_init gv100_grctx_init_sw_veid_bundle_init_0[]; +void gv100_grctx_generate_attrib(struct gf100_grctx *); +void gv100_grctx_generate_rop_mapping(struct gf100_gr *); +void gv100_grctx_generate_r400088(struct gf100_gr *, bool); + /* context init value lists */ extern const struct gf100_gr_pack gf100_grctx_pack_icmd[]; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c index 896d473dcc0f..c0d36bc601f9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c @@ -32,7 +32,7 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) u32 idle_timeout; int i; - gf100_gr_mmio(gr, gr->fuc_sw_ctx); + gf100_gr_mmio(gr, gr->sw_ctx); gf100_gr_wait_idle(gr); @@ -56,10 +56,10 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) nvkm_wr32(device, 0x404154, idle_timeout); gf100_gr_wait_idle(gr); - gf100_gr_mthd(gr, gr->fuc_method); + gf100_gr_mthd(gr, gr->method); gf100_gr_wait_idle(gr); - gf100_gr_icmd(gr, gr->fuc_bundle); + gf100_gr_icmd(gr, gr->bundle); grctx->pagepool(info); grctx->bundle(info); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c index a1d9e114ebeb..6b92f8aa18a3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c @@ -29,7 +29,7 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) u32 idle_timeout; int i, tmp; - gf100_gr_mmio(gr, gr->fuc_sw_ctx); + gf100_gr_mmio(gr, gr->sw_ctx); gf100_gr_wait_idle(gr); @@ -59,10 +59,10 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) nvkm_wr32(device, 0x404154, idle_timeout); gf100_gr_wait_idle(gr); - gf100_gr_mthd(gr, gr->fuc_method); + gf100_gr_mthd(gr, gr->method); gf100_gr_wait_idle(gr); - gf100_gr_icmd(gr, gr->fuc_bundle); + gf100_gr_icmd(gr, gr->bundle); grctx->pagepool(info); grctx->bundle(info); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c index 0990765ef191..39553d55d3f3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c @@ -25,7 +25,7 @@ * PGRAPH context implementation ******************************************************************************/ -static const struct gf100_gr_init +const struct gf100_gr_init gv100_grctx_init_sw_veid_bundle_init_0[] = { { 0x00001000, 64, 0x00100000, 0x00000008 }, { 0x00000941, 64, 0x00100000, 0x00000000 }, @@ -58,7 +58,7 @@ gv100_grctx_pack_sw_veid_bundle_init[] = { {} }; -static void +void gv100_grctx_generate_attrib(struct gf100_grctx *info) { struct gf100_gr *gr = info->gr; @@ -67,14 +67,14 @@ gv100_grctx_generate_attrib(struct gf100_grctx *info) const u32 attrib = grctx->attrib_nr; const u32 gfxp = grctx->gfxp_nr; const int s = 12; - const int max_batches = 0xffff; u32 size = grctx->alpha_nr_max * gr->tpc_total; u32 ao = 0; u32 bo = ao + size; int gpc, ppc, b, n = 0; - size += grctx->gfxp_nr * gr->tpc_total; - size = ((size * 0x20) + 128) & ~127; + for (gpc = 0; gpc < gr->gpc_nr; gpc++) + size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max; + size = ((size * 0x20) + 127) & ~127; b = mmio_vram(info, size, (1 << s), false); mmio_refn(info, 0x418810, 0x80000000, s, b); @@ -84,13 +84,12 @@ gv100_grctx_generate_attrib(struct gf100_grctx *info) mmio_wr32(info, 0x419e04, 0x80000000 | size >> 7); mmio_wr32(info, 0x405830, attrib); mmio_wr32(info, 0x40585c, alpha); - mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; - const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; - const u32 gs = gfxp * gr->ppc_tpc_nr[gpc][ppc]; + const u32 bs = attrib * gr->ppc_tpc_max; + const u32 gs = gfxp * gr->ppc_tpc_max; const u32 u = 0x418ea0 + (n * 0x04); const u32 o = PPC_UNIT(gpc, ppc, 0); if (!(gr->ppc_mask[gpc] & (1 << ppc))) @@ -110,7 +109,7 @@ gv100_grctx_generate_attrib(struct gf100_grctx *info) mmio_wr32(info, 0x41befc, 0x00000100); } -static void +void gv100_grctx_generate_rop_mapping(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; @@ -147,7 +146,7 @@ gv100_grctx_generate_rop_mapping(struct gf100_gr *gr) gr->screen_tile_row_offset); } -static void +void gv100_grctx_generate_r400088(struct gf100_gr *gr, bool on) { struct nvkm_device *device = gr->base.engine.subdev.device; @@ -163,7 +162,7 @@ gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm); } -static void +void gv100_grctx_generate_unkn(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; @@ -174,7 +173,7 @@ gv100_grctx_generate_unkn(struct gf100_gr *gr) nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008); } -static void +void gv100_grctx_unkn88c(struct gf100_gr *gr, bool on) { struct nvkm_device *device = gr->base.engine.subdev.device; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxtu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxtu102.c new file mode 100644 index 000000000000..2299ca07d04a --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxtu102.c @@ -0,0 +1,95 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "ctxgf100.h" + +static void +tu102_grctx_generate_r419c0c(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + nvkm_mask(device, 0x419c0c, 0x80000000, 0x80000000); + nvkm_mask(device, 0x40584c, 0x00000008, 0x00000000); + nvkm_mask(device, 0x400080, 0x00000000, 0x00000000); +} + +static void +tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm); +} + +static const struct gf100_gr_init +tu102_grctx_init_unknown_bundle_init_0[] = { + { 0x00001000, 1, 0x00000001, 0x00000004 }, + { 0x00002020, 64, 0x00000001, 0x00000000 }, + { 0x0001e100, 1, 0x00000001, 0x00000001 }, + {} +}; + +static const struct gf100_gr_pack +tu102_grctx_pack_sw_veid_bundle_init[] = { + { gv100_grctx_init_sw_veid_bundle_init_0 }, + { tu102_grctx_init_unknown_bundle_init_0 }, + {} +}; + +static void +tu102_grctx_generate_attrib(struct gf100_grctx *info) +{ + const u64 size = 0x80000; /*XXX: educated guess */ + const int s = 8; + const int b = mmio_vram(info, size, (1 << s), true); + + gv100_grctx_generate_attrib(info); + + mmio_refn(info, 0x408070, 0x00000000, s, b); + mmio_wr32(info, 0x408074, size >> s); /*XXX: guess */ + mmio_refn(info, 0x419034, 0x00000000, s, b); + mmio_wr32(info, 0x408078, 0x00000000); +} + +const struct gf100_grctx_func +tu102_grctx = { + .unkn88c = gv100_grctx_unkn88c, + .main = gf100_grctx_generate_main, + .unkn = gv100_grctx_generate_unkn, + .sw_veid_bundle_init = tu102_grctx_pack_sw_veid_bundle_init, + .bundle = gm107_grctx_generate_bundle, + .bundle_size = 0x3000, + .bundle_min_gpm_fifo_depth = 0x180, + .bundle_token_limit = 0xa80, + .pagepool = gp100_grctx_generate_pagepool, + .pagepool_size = 0x20000, + .attrib = tu102_grctx_generate_attrib, + .attrib_nr_max = 0x800, + .attrib_nr = 0x700, + .alpha_nr_max = 0xc00, + .alpha_nr = 0x800, + .gfxp_nr = 0xfa8, + .sm_id = tu102_grctx_generate_sm_id, + .skip_pd_num_tpc_per_gpc = true, + .rop_mapping = gv100_grctx_generate_rop_mapping, + .r406500 = gm200_grctx_generate_r406500, + .r400088 = gv100_grctx_generate_r400088, + .r419c0c = tu102_grctx_generate_r419c0c, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h index c24f35ad56a6..ae2d5b6891cb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h @@ -441,7 +441,7 @@ static uint32_t gk208_grhub_code[] = { 0x020014fe, 0x12004002, 0xbd0002f6, - 0x05c94104, + 0x05ca4104, 0xbd0010fe, 0x07004024, 0xbd0002f6, @@ -460,423 +460,423 @@ static uint32_t gk208_grhub_code[] = { 0x01039204, 0x03090080, 0xbd0003f6, - 0x87044204, - 0xf6040040, - 0x04bd0002, - 0x00400402, - 0x0002f603, - 0x31f404bd, - 0x96048e10, - 0x00657e40, - 0xc7feb200, - 0x01b590f1, - 0x1ff4f003, - 0x01020fb5, - 0x041fbb01, - 0x800112b6, - 0xf6010300, - 0x04bd0001, - 0x01040080, + 0x87048204, + 0x04004000, + 0xbd0002f6, + 0x40040204, + 0x02f60300, + 0xf404bd00, + 0x048e1031, + 0x657e4096, + 0xfeb20000, + 0xb590f1c7, + 0xf4f00301, + 0x020fb51f, + 0x1fbb0101, + 0x0112b604, + 0x01030080, 0xbd0001f6, - 0x01004104, - 0xac7e020f, - 0xbb7e0006, - 0x100f0006, - 0x0006fd7e, - 0x98000e98, - 0x207e010f, - 0x14950001, - 0xc0008008, - 0x0004f601, - 0x008004bd, - 0x04f601c1, - 0xb704bd00, - 0xbb130030, - 0xf5b6001f, - 0xd3008002, - 0x000ff601, - 0x15b604bd, - 0x0110b608, - 0xb20814b6, - 0x02687e1f, - 0x001fbb00, - 0x84020398, -/* 0x041f: init_gpc */ - 0xb8502000, - 0x0008044e, - 0x8f7e1fb2, + 0x04008004, + 0x0001f601, + 0x004104bd, + 0x7e020f01, + 0x7e0006ad, + 0x0f0006bc, + 0x06fe7e10, + 0x000e9800, + 0x7e010f98, + 0x95000120, + 0x00800814, + 0x04f601c0, + 0x8004bd00, + 0xf601c100, + 0x04bd0004, + 0x130030b7, + 0xb6001fbb, + 0x008002f5, + 0x0ff601d3, + 0xb604bd00, + 0x10b60815, + 0x0814b601, + 0x687e1fb2, + 0x1fbb0002, + 0x02039800, + 0x50200084, +/* 0x0420: init_gpc */ + 0x08044eb8, + 0x7e1fb200, + 0xb800008f, + 0x00010c4e, + 0x8f7ef4bd, 0x4eb80000, - 0xbd00010c, - 0x008f7ef4, - 0x044eb800, - 0x8f7e0001, + 0x7e000104, + 0xb800008f, + 0x0001004e, + 0x8f7e020f, 0x4eb80000, - 0x0f000100, - 0x008f7e02, - 0x004eb800, -/* 0x044e: init_gpc_wait */ +/* 0x044f: init_gpc_wait */ + 0x7e000800, + 0xc8000065, + 0x0bf41fff, + 0x044eb8f9, 0x657e0008, - 0xffc80000, - 0xf90bf41f, - 0x08044eb8, - 0x00657e00, - 0x001fbb00, - 0x800040b7, - 0xf40132b6, - 0x000fb41b, - 0x0006fd7e, - 0xac7e000f, - 0x00800006, - 0x01f60201, - 0xbd04bd00, - 0x1f19f014, - 0x02300080, - 0xbd0001f6, -/* 0x0491: wait */ - 0x0028f404, -/* 0x0497: main */ - 0x0d0031f4, - 0x00377e10, - 0xf401f400, - 0x4001e4b1, - 0x00c71bf5, - 0x99f094bd, - 0x37008004, - 0x0009f602, - 0x008104bd, - 0x11cf02c0, - 0xc1008200, - 0x0022cf02, - 0xf41f13c8, - 0x23c8770b, - 0x550bf41f, - 0x12b220f9, - 0x99f094bd, - 0x37008007, - 0x0009f602, - 0x32f404bd, - 0x0231f401, - 0x0008807e, - 0x99f094bd, - 0x17008007, - 0x0009f602, - 0x20fc04bd, - 0x99f094bd, - 0x37008006, - 0x0009f602, - 0x31f404bd, - 0x08807e01, + 0x1fbb0000, + 0x0040b700, + 0x0132b680, + 0x0fb41bf4, + 0x06fe7e00, + 0x7e000f00, + 0x800006ad, + 0xf6020100, + 0x04bd0001, + 0x19f014bd, + 0x3000801f, + 0x0001f602, +/* 0x0492: wait */ + 0x28f404bd, + 0x0031f400, +/* 0x0498: main */ + 0x377e100d, + 0x01f40000, + 0x01e4b1f4, + 0xc71bf540, 0xf094bd00, - 0x00800699, + 0x00800499, + 0x09f60237, + 0x8104bd00, + 0xcf02c000, + 0x00820011, + 0x22cf02c1, + 0x1f13c800, + 0xc8770bf4, + 0x0bf41f23, + 0xb220f955, + 0xf094bd12, + 0x00800799, + 0x09f60237, + 0xf404bd00, + 0x31f40132, + 0x08817e02, + 0xf094bd00, + 0x00800799, 0x09f60217, + 0xfc04bd00, + 0xf094bd20, + 0x00800699, + 0x09f60237, 0xf404bd00, -/* 0x0522: chsw_prev_no_next */ - 0x20f92f0e, - 0x32f412b2, - 0x0232f401, - 0x0008807e, - 0x008020fc, - 0x02f602c0, + 0x817e0131, + 0x94bd0008, + 0x800699f0, + 0xf6021700, + 0x04bd0009, +/* 0x0523: chsw_prev_no_next */ + 0xf92f0ef4, + 0xf412b220, + 0x32f40132, + 0x08817e02, + 0x8020fc00, + 0xf602c000, + 0x04bd0002, +/* 0x053f: chsw_no_prev */ + 0xc8130ef4, + 0x0bf41f23, + 0x0131f40d, + 0x7e0232f4, +/* 0x054f: chsw_done */ + 0x02000881, + 0xc3008001, + 0x0002f602, + 0x94bd04bd, + 0x800499f0, + 0xf6021700, + 0x04bd0009, + 0xff300ef5, +/* 0x056c: main_not_ctx_switch */ + 0xf401e4b0, + 0xf2b20c1b, + 0x0008217e, +/* 0x057b: main_not_ctx_chan */ + 0xb0400ef4, + 0x1bf402e4, + 0xf094bd2c, + 0x00800799, + 0x09f60237, 0xf404bd00, -/* 0x053e: chsw_no_prev */ - 0x23c8130e, - 0x0d0bf41f, - 0xf40131f4, - 0x807e0232, -/* 0x054e: chsw_done */ - 0x01020008, - 0x02c30080, - 0xbd0002f6, - 0xf094bd04, - 0x00800499, + 0x32f40132, + 0x08817e02, + 0xf094bd00, + 0x00800799, 0x09f60217, - 0xf504bd00, -/* 0x056b: main_not_ctx_switch */ - 0xb0ff300e, - 0x1bf401e4, - 0x7ef2b20c, - 0xf4000820, -/* 0x057a: main_not_ctx_chan */ - 0xe4b0400e, - 0x2c1bf402, - 0x99f094bd, - 0x37008007, - 0x0009f602, - 0x32f404bd, - 0x0232f401, - 0x0008807e, - 0x99f094bd, - 0x17008007, - 0x0009f602, - 0x0ef404bd, -/* 0x05a9: main_not_ctx_save */ - 0x10ef9411, - 0x7e01f5f0, - 0xf50002f8, -/* 0x05b7: main_done */ - 0xbdfee40e, - 0x1f29f024, - 0x02300080, - 0xbd0002f6, - 0xd20ef504, -/* 0x05c9: ih */ - 0xf900f9fe, - 0x0188fe80, - 0x90f980f9, - 0xb0f9a0f9, - 0xe0f9d0f9, - 0x04bdf0f9, - 0xcf02004a, - 0xabc400aa, - 0x230bf404, - 0x004e100d, - 0x00eecf1a, - 0xcf19004f, - 0x047e00ff, - 0xb0b70000, - 0x010e0400, - 0xf61d0040, - 0x04bd000e, -/* 0x060c: ih_no_fifo */ - 0x0100abe4, - 0x0d0c0bf4, - 0x40014e10, - 0x0000047e, -/* 0x061c: ih_no_ctxsw */ - 0x0400abe4, - 0x8e560bf4, - 0x7e400708, + 0xf404bd00, +/* 0x05aa: main_not_ctx_save */ + 0xef94110e, + 0x01f5f010, + 0x0002f87e, + 0xfee40ef5, +/* 0x05b8: main_done */ + 0x29f024bd, + 0x3000801f, + 0x0002f602, + 0x0ef504bd, +/* 0x05ca: ih */ + 0x00f9fed2, + 0x88fe80f9, + 0xf980f901, + 0xf9a0f990, + 0xf9d0f9b0, + 0xbdf0f9e0, + 0x02004a04, + 0xc400aacf, + 0x0bf404ab, + 0x4e100d23, + 0xeecf1a00, + 0x19004f00, + 0x7e00ffcf, + 0xb7000004, + 0x0e0400b0, + 0x1d004001, + 0xbd000ef6, +/* 0x060d: ih_no_fifo */ + 0x00abe404, + 0x0c0bf401, + 0x014e100d, + 0x00047e40, +/* 0x061d: ih_no_ctxsw */ + 0x00abe400, + 0x560bf404, + 0x4007088e, + 0x0000657e, + 0x0080ffb2, + 0x0ff60204, + 0x8e04bd00, + 0x7e400704, 0xb2000065, - 0x040080ff, + 0x030080ff, 0x000ff602, - 0x048e04bd, - 0x657e4007, - 0xffb20000, - 0x02030080, - 0xbd000ff6, - 0x50fec704, - 0x8f02ee94, - 0xbb400700, - 0x657e00ef, - 0x00800000, - 0x0ff60202, + 0xfec704bd, + 0x02ee9450, + 0x4007008f, + 0x7e00efbb, + 0x80000065, + 0xf6020200, + 0x04bd000f, + 0xf87e030f, + 0x004b0002, + 0x8ebfb201, + 0x7e400144, +/* 0x0677: ih_no_fwmthd */ + 0x4b00008f, + 0xb0bd0504, + 0xf4b4abff, + 0x00800c0b, + 0x0bf60307, +/* 0x068b: ih_no_other */ + 0x4004bd00, + 0x0af60100, + 0xfc04bd00, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x00fc80fc, + 0xf80032f4, +/* 0x06ad: ctx_4170s */ + 0x10f5f001, + 0x708effb2, + 0x8f7e4041, + 0x00f80000, +/* 0x06bc: ctx_4170w */ + 0x4041708e, + 0x0000657e, + 0xf4f0ffb2, + 0xf31bf410, +/* 0x06ce: ctx_redswitch */ + 0x004e00f8, + 0x40e5f002, + 0xf020e5f0, + 0x008010e5, + 0x0ef60185, 0x0f04bd00, - 0x02f87e03, - 0x01004b00, - 0x448ebfb2, - 0x8f7e4001, -/* 0x0676: ih_no_fwmthd */ - 0x044b0000, - 0xffb0bd05, - 0x0bf4b4ab, - 0x0700800c, - 0x000bf603, -/* 0x068a: ih_no_other */ - 0x004004bd, - 0x000af601, - 0xf0fc04bd, - 0xd0fce0fc, - 0xa0fcb0fc, - 0x80fc90fc, - 0xfc0088fe, - 0xf400fc80, - 0x01f80032, -/* 0x06ac: ctx_4170s */ - 0xb210f5f0, - 0x41708eff, +/* 0x06e5: ctx_redswitch_delay */ + 0x01f2b608, + 0xf1fd1bf4, + 0xf10400e5, + 0x800100e5, + 0xf6018500, + 0x04bd000e, +/* 0x06fe: ctx_86c */ + 0x008000f8, + 0x0ff60223, + 0xb204bd00, + 0x8a148eff, 0x008f7e40, -/* 0x06bb: ctx_4170w */ - 0x8e00f800, - 0x7e404170, - 0xb2000065, - 0x10f4f0ff, - 0xf8f31bf4, -/* 0x06cd: ctx_redswitch */ - 0x02004e00, - 0xf040e5f0, - 0xe5f020e5, - 0x85008010, - 0x000ef601, - 0x080f04bd, -/* 0x06e4: ctx_redswitch_delay */ - 0xf401f2b6, - 0xe5f1fd1b, - 0xe5f10400, - 0x00800100, - 0x0ef60185, - 0xf804bd00, -/* 0x06fd: ctx_86c */ - 0x23008000, + 0x8effb200, + 0x7e41a88c, + 0xf800008f, +/* 0x071d: ctx_mem */ + 0x84008000, 0x000ff602, - 0xffb204bd, - 0x408a148e, - 0x00008f7e, - 0x8c8effb2, - 0x8f7e41a8, - 0x00f80000, -/* 0x071c: ctx_mem */ - 0x02840080, - 0xbd000ff6, -/* 0x0725: ctx_mem_wait */ - 0x84008f04, - 0x00ffcf02, - 0xf405fffd, - 0x00f8f61b, -/* 0x0734: ctx_load */ - 0x99f094bd, - 0x37008005, - 0x0009f602, - 0x0c0a04bd, - 0x0000b87e, - 0x0080f4bd, - 0x0ff60289, - 0x8004bd00, - 0xf602c100, - 0x04bd0002, - 0x02830080, +/* 0x0726: ctx_mem_wait */ + 0x008f04bd, + 0xffcf0284, + 0x05fffd00, + 0xf8f61bf4, +/* 0x0735: ctx_load */ + 0xf094bd00, + 0x00800599, + 0x09f60237, + 0x0a04bd00, + 0x00b87e0c, + 0x80f4bd00, + 0xf6028900, + 0x04bd000f, + 0x02c10080, 0xbd0002f6, - 0x7e070f04, - 0x8000071c, - 0xf602c000, - 0x04bd0002, - 0xf0000bfe, - 0x24b61f2a, - 0x0220b604, - 0x99f094bd, - 0x37008008, - 0x0009f602, - 0x008004bd, - 0x02f60281, - 0xd204bd00, - 0x80000000, - 0x800225f0, - 0xf6028800, - 0x04bd0002, - 0x00421001, - 0x0223f002, - 0xf80512fa, - 0xf094bd03, + 0x83008004, + 0x0002f602, + 0x070f04bd, + 0x00071d7e, + 0x02c00080, + 0xbd0002f6, + 0x000bfe04, + 0xb61f2af0, + 0x20b60424, + 0xf094bd02, 0x00800899, - 0x09f60217, - 0x9804bd00, - 0x14b68101, - 0x80029818, - 0xfd0825b6, - 0x01b50512, - 0xf094bd16, - 0x00800999, 0x09f60237, 0x8004bd00, 0xf6028100, - 0x04bd0001, - 0x00800102, - 0x02f60288, - 0x4104bd00, - 0x13f00100, - 0x0501fa06, + 0x04bd0002, + 0x000000d2, + 0x0225f080, + 0x02880080, + 0xbd0002f6, + 0x42100104, + 0x23f00200, + 0x0512fa02, 0x94bd03f8, - 0x800999f0, + 0x800899f0, 0xf6021700, 0x04bd0009, - 0x99f094bd, - 0x17008005, - 0x0009f602, - 0x00f804bd, -/* 0x0820: ctx_chan */ - 0x0007347e, - 0xb87e0c0a, - 0x050f0000, - 0x00071c7e, -/* 0x0832: ctx_mmio_exec */ - 0x039800f8, - 0x81008041, - 0x0003f602, - 0x34bd04bd, -/* 0x0840: ctx_mmio_loop */ - 0xf4ff34c4, - 0x00450e1b, - 0x0653f002, - 0xf80535fa, -/* 0x0851: ctx_mmio_pull */ - 0x804e9803, - 0x7e814f98, - 0xb600008f, - 0x12b60830, - 0xdf1bf401, -/* 0x0864: ctx_mmio_done */ - 0x80160398, - 0xf6028100, - 0x04bd0003, - 0x414000b5, - 0x13f00100, - 0x0601fa06, - 0x00f803f8, -/* 0x0880: ctx_xfer */ - 0x0080040e, - 0x0ef60302, -/* 0x088b: ctx_xfer_idle */ - 0x8e04bd00, - 0xcf030000, - 0xe4f100ee, - 0x1bf42000, - 0x0611f4f5, -/* 0x089f: ctx_xfer_pre */ - 0x0f0c02f4, - 0x06fd7e10, - 0x1b11f400, -/* 0x08a8: ctx_xfer_pre_load */ - 0xac7e020f, - 0xbb7e0006, - 0xcd7e0006, - 0xf4bd0006, - 0x0006ac7e, - 0x0007347e, -/* 0x08c0: ctx_xfer_exec */ - 0xbd160198, - 0x05008024, - 0x0002f601, - 0x1fb204bd, - 0x41a5008e, - 0x00008f7e, - 0xf001fcf0, - 0x24b6022c, - 0x05f2fd01, - 0x048effb2, - 0x8f7e41a5, - 0x167e0000, - 0x24bd0002, - 0x0247fc80, - 0xbd0002f6, - 0x012cf004, - 0x800320b6, - 0xf6024afc, + 0xb6810198, + 0x02981814, + 0x0825b680, + 0xb50512fd, + 0x94bd1601, + 0x800999f0, + 0xf6023700, + 0x04bd0009, + 0x02810080, + 0xbd0001f6, + 0x80010204, + 0xf6028800, 0x04bd0002, - 0xf001acf0, - 0x000b06a5, - 0x98000c98, - 0x000e010d, - 0x00013d7e, - 0xec7e080a, - 0x0a7e0000, - 0x01f40002, - 0x7e0c0a12, + 0xf0010041, + 0x01fa0613, + 0xbd03f805, + 0x0999f094, + 0x02170080, + 0xbd0009f6, + 0xf094bd04, + 0x00800599, + 0x09f60217, + 0xf804bd00, +/* 0x0821: ctx_chan */ + 0x07357e00, + 0x7e0c0a00, 0x0f0000b8, - 0x071c7e05, - 0x2d02f400, -/* 0x093c: ctx_xfer_post */ - 0xac7e020f, - 0xf4bd0006, - 0x0006fd7e, - 0x0002277e, - 0x0006bb7e, - 0xac7ef4bd, + 0x071d7e05, +/* 0x0833: ctx_mmio_exec */ + 0x9800f800, + 0x00804103, + 0x03f60281, + 0xbd04bd00, +/* 0x0841: ctx_mmio_loop */ + 0xff34c434, + 0x450e1bf4, + 0x53f00200, + 0x0535fa06, +/* 0x0852: ctx_mmio_pull */ + 0x4e9803f8, + 0x814f9880, + 0x00008f7e, + 0xb60830b6, + 0x1bf40112, +/* 0x0865: ctx_mmio_done */ + 0x160398df, + 0x02810080, + 0xbd0003f6, + 0x4000b504, + 0xf0010041, + 0x01fa0613, + 0xf803f806, +/* 0x0881: ctx_xfer */ + 0x80040e00, + 0xf6030200, + 0x04bd000e, +/* 0x088c: ctx_xfer_idle */ + 0x0300008e, + 0xf100eecf, + 0xf42000e4, + 0x11f4f51b, + 0x0c02f406, +/* 0x08a0: ctx_xfer_pre */ + 0xfe7e100f, 0x11f40006, - 0x40019810, - 0xf40511fd, - 0x327e070b, -/* 0x0966: ctx_xfer_no_post_mmio */ -/* 0x0966: ctx_xfer_done */ - 0x00f80008, +/* 0x08a9: ctx_xfer_pre_load */ + 0x7e020f1b, + 0x7e0006ad, + 0x7e0006bc, + 0xbd0006ce, + 0x06ad7ef4, + 0x07357e00, +/* 0x08c1: ctx_xfer_exec */ + 0x16019800, + 0x008024bd, + 0x02f60105, + 0xb204bd00, + 0xa5008e1f, + 0x008f7e41, + 0x01fcf000, + 0xb6022cf0, + 0xf2fd0124, + 0x8effb205, + 0x7e41a504, + 0x7e00008f, + 0xbd000216, + 0x47fc8024, + 0x0002f602, + 0x2cf004bd, + 0x0320b601, + 0x024afc80, + 0xbd0002f6, + 0x01acf004, + 0x0b06a5f0, + 0x000c9800, + 0x0e010d98, + 0x013d7e00, + 0x7e080a00, + 0x7e0000ec, + 0xf400020a, + 0x0c0a1201, + 0x0000b87e, + 0x1d7e050f, + 0x02f40007, +/* 0x093d: ctx_xfer_post */ + 0x7e020f2d, + 0xbd0006ad, + 0x06fe7ef4, + 0x02277e00, + 0x06bc7e00, + 0x7ef4bd00, + 0xf40006ad, + 0x01981011, + 0x0511fd40, + 0x7e070bf4, +/* 0x0967: ctx_xfer_no_post_mmio */ +/* 0x0967: ctx_xfer_done */ + 0xf8000833, 0x00000000, 0x00000000, 0x00000000, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h index 649a442b4390..449dae753203 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h @@ -441,7 +441,7 @@ static uint32_t gm107_grhub_code[] = { 0x020014fe, 0x12004002, 0xbd0002f6, - 0x05c94104, + 0x05ca4104, 0xbd0010fe, 0x07004024, 0xbd0002f6, @@ -460,423 +460,423 @@ static uint32_t gm107_grhub_code[] = { 0x01039204, 0x03090080, 0xbd0003f6, - 0x87044204, - 0xf6040040, - 0x04bd0002, - 0x00400402, - 0x0002f603, - 0x31f404bd, - 0x96048e10, - 0x00657e40, - 0xc7feb200, - 0x01b590f1, - 0x1ff4f003, - 0x01020fb5, - 0x041fbb01, - 0x800112b6, - 0xf6010300, - 0x04bd0001, - 0x01040080, + 0x87048204, + 0x04004000, + 0xbd0002f6, + 0x40040204, + 0x02f60300, + 0xf404bd00, + 0x048e1031, + 0x657e4096, + 0xfeb20000, + 0xb590f1c7, + 0xf4f00301, + 0x020fb51f, + 0x1fbb0101, + 0x0112b604, + 0x01030080, 0xbd0001f6, - 0x01004104, - 0xac7e020f, - 0xbb7e0006, - 0x100f0006, - 0x0006fd7e, - 0x98000e98, - 0x207e010f, - 0x14950001, - 0xc0008008, - 0x0004f601, - 0x008004bd, - 0x04f601c1, - 0xb704bd00, - 0xbb130030, - 0xf5b6001f, - 0xd3008002, - 0x000ff601, - 0x15b604bd, - 0x0110b608, - 0xb20814b6, - 0x02687e1f, - 0x001fbb00, - 0x84020398, -/* 0x041f: init_gpc */ - 0xb8502000, - 0x0008044e, - 0x8f7e1fb2, + 0x04008004, + 0x0001f601, + 0x004104bd, + 0x7e020f01, + 0x7e0006ad, + 0x0f0006bc, + 0x06fe7e10, + 0x000e9800, + 0x7e010f98, + 0x95000120, + 0x00800814, + 0x04f601c0, + 0x8004bd00, + 0xf601c100, + 0x04bd0004, + 0x130030b7, + 0xb6001fbb, + 0x008002f5, + 0x0ff601d3, + 0xb604bd00, + 0x10b60815, + 0x0814b601, + 0x687e1fb2, + 0x1fbb0002, + 0x02039800, + 0x50200084, +/* 0x0420: init_gpc */ + 0x08044eb8, + 0x7e1fb200, + 0xb800008f, + 0x00010c4e, + 0x8f7ef4bd, 0x4eb80000, - 0xbd00010c, - 0x008f7ef4, - 0x044eb800, - 0x8f7e0001, + 0x7e000104, + 0xb800008f, + 0x0001004e, + 0x8f7e020f, 0x4eb80000, - 0x0f000100, - 0x008f7e02, - 0x004eb800, -/* 0x044e: init_gpc_wait */ +/* 0x044f: init_gpc_wait */ + 0x7e000800, + 0xc8000065, + 0x0bf41fff, + 0x044eb8f9, 0x657e0008, - 0xffc80000, - 0xf90bf41f, - 0x08044eb8, - 0x00657e00, - 0x001fbb00, - 0x800040b7, - 0xf40132b6, - 0x000fb41b, - 0x0006fd7e, - 0xac7e000f, - 0x00800006, - 0x01f60201, - 0xbd04bd00, - 0x1f19f014, - 0x02300080, - 0xbd0001f6, -/* 0x0491: wait */ - 0x0028f404, -/* 0x0497: main */ - 0x0d0031f4, - 0x00377e10, - 0xf401f400, - 0x4001e4b1, - 0x00c71bf5, - 0x99f094bd, - 0x37008004, - 0x0009f602, - 0x008104bd, - 0x11cf02c0, - 0xc1008200, - 0x0022cf02, - 0xf41f13c8, - 0x23c8770b, - 0x550bf41f, - 0x12b220f9, - 0x99f094bd, - 0x37008007, - 0x0009f602, - 0x32f404bd, - 0x0231f401, - 0x0008807e, - 0x99f094bd, - 0x17008007, - 0x0009f602, - 0x20fc04bd, - 0x99f094bd, - 0x37008006, - 0x0009f602, - 0x31f404bd, - 0x08807e01, + 0x1fbb0000, + 0x0040b700, + 0x0132b680, + 0x0fb41bf4, + 0x06fe7e00, + 0x7e000f00, + 0x800006ad, + 0xf6020100, + 0x04bd0001, + 0x19f014bd, + 0x3000801f, + 0x0001f602, +/* 0x0492: wait */ + 0x28f404bd, + 0x0031f400, +/* 0x0498: main */ + 0x377e100d, + 0x01f40000, + 0x01e4b1f4, + 0xc71bf540, 0xf094bd00, - 0x00800699, + 0x00800499, + 0x09f60237, + 0x8104bd00, + 0xcf02c000, + 0x00820011, + 0x22cf02c1, + 0x1f13c800, + 0xc8770bf4, + 0x0bf41f23, + 0xb220f955, + 0xf094bd12, + 0x00800799, + 0x09f60237, + 0xf404bd00, + 0x31f40132, + 0x08817e02, + 0xf094bd00, + 0x00800799, 0x09f60217, + 0xfc04bd00, + 0xf094bd20, + 0x00800699, + 0x09f60237, 0xf404bd00, -/* 0x0522: chsw_prev_no_next */ - 0x20f92f0e, - 0x32f412b2, - 0x0232f401, - 0x0008807e, - 0x008020fc, - 0x02f602c0, + 0x817e0131, + 0x94bd0008, + 0x800699f0, + 0xf6021700, + 0x04bd0009, +/* 0x0523: chsw_prev_no_next */ + 0xf92f0ef4, + 0xf412b220, + 0x32f40132, + 0x08817e02, + 0x8020fc00, + 0xf602c000, + 0x04bd0002, +/* 0x053f: chsw_no_prev */ + 0xc8130ef4, + 0x0bf41f23, + 0x0131f40d, + 0x7e0232f4, +/* 0x054f: chsw_done */ + 0x02000881, + 0xc3008001, + 0x0002f602, + 0x94bd04bd, + 0x800499f0, + 0xf6021700, + 0x04bd0009, + 0xff300ef5, +/* 0x056c: main_not_ctx_switch */ + 0xf401e4b0, + 0xf2b20c1b, + 0x0008217e, +/* 0x057b: main_not_ctx_chan */ + 0xb0400ef4, + 0x1bf402e4, + 0xf094bd2c, + 0x00800799, + 0x09f60237, 0xf404bd00, -/* 0x053e: chsw_no_prev */ - 0x23c8130e, - 0x0d0bf41f, - 0xf40131f4, - 0x807e0232, -/* 0x054e: chsw_done */ - 0x01020008, - 0x02c30080, - 0xbd0002f6, - 0xf094bd04, - 0x00800499, + 0x32f40132, + 0x08817e02, + 0xf094bd00, + 0x00800799, 0x09f60217, - 0xf504bd00, -/* 0x056b: main_not_ctx_switch */ - 0xb0ff300e, - 0x1bf401e4, - 0x7ef2b20c, - 0xf4000820, -/* 0x057a: main_not_ctx_chan */ - 0xe4b0400e, - 0x2c1bf402, - 0x99f094bd, - 0x37008007, - 0x0009f602, - 0x32f404bd, - 0x0232f401, - 0x0008807e, - 0x99f094bd, - 0x17008007, - 0x0009f602, - 0x0ef404bd, -/* 0x05a9: main_not_ctx_save */ - 0x10ef9411, - 0x7e01f5f0, - 0xf50002f8, -/* 0x05b7: main_done */ - 0xbdfee40e, - 0x1f29f024, - 0x02300080, - 0xbd0002f6, - 0xd20ef504, -/* 0x05c9: ih */ - 0xf900f9fe, - 0x0188fe80, - 0x90f980f9, - 0xb0f9a0f9, - 0xe0f9d0f9, - 0x04bdf0f9, - 0xcf02004a, - 0xabc400aa, - 0x230bf404, - 0x004e100d, - 0x00eecf1a, - 0xcf19004f, - 0x047e00ff, - 0xb0b70000, - 0x010e0400, - 0xf61d0040, - 0x04bd000e, -/* 0x060c: ih_no_fifo */ - 0x0100abe4, - 0x0d0c0bf4, - 0x40014e10, - 0x0000047e, -/* 0x061c: ih_no_ctxsw */ - 0x0400abe4, - 0x8e560bf4, - 0x7e400708, + 0xf404bd00, +/* 0x05aa: main_not_ctx_save */ + 0xef94110e, + 0x01f5f010, + 0x0002f87e, + 0xfee40ef5, +/* 0x05b8: main_done */ + 0x29f024bd, + 0x3000801f, + 0x0002f602, + 0x0ef504bd, +/* 0x05ca: ih */ + 0x00f9fed2, + 0x88fe80f9, + 0xf980f901, + 0xf9a0f990, + 0xf9d0f9b0, + 0xbdf0f9e0, + 0x02004a04, + 0xc400aacf, + 0x0bf404ab, + 0x4e100d23, + 0xeecf1a00, + 0x19004f00, + 0x7e00ffcf, + 0xb7000004, + 0x0e0400b0, + 0x1d004001, + 0xbd000ef6, +/* 0x060d: ih_no_fifo */ + 0x00abe404, + 0x0c0bf401, + 0x014e100d, + 0x00047e40, +/* 0x061d: ih_no_ctxsw */ + 0x00abe400, + 0x560bf404, + 0x4007088e, + 0x0000657e, + 0x0080ffb2, + 0x0ff60204, + 0x8e04bd00, + 0x7e400704, 0xb2000065, - 0x040080ff, + 0x030080ff, 0x000ff602, - 0x048e04bd, - 0x657e4007, - 0xffb20000, - 0x02030080, - 0xbd000ff6, - 0x50fec704, - 0x8f02ee94, - 0xbb400700, - 0x657e00ef, - 0x00800000, - 0x0ff60202, + 0xfec704bd, + 0x02ee9450, + 0x4007008f, + 0x7e00efbb, + 0x80000065, + 0xf6020200, + 0x04bd000f, + 0xf87e030f, + 0x004b0002, + 0x8ebfb201, + 0x7e400144, +/* 0x0677: ih_no_fwmthd */ + 0x4b00008f, + 0xb0bd0504, + 0xf4b4abff, + 0x00800c0b, + 0x0bf60307, +/* 0x068b: ih_no_other */ + 0x4004bd00, + 0x0af60100, + 0xfc04bd00, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x00fc80fc, + 0xf80032f4, +/* 0x06ad: ctx_4170s */ + 0x10f5f001, + 0x708effb2, + 0x8f7e4041, + 0x00f80000, +/* 0x06bc: ctx_4170w */ + 0x4041708e, + 0x0000657e, + 0xf4f0ffb2, + 0xf31bf410, +/* 0x06ce: ctx_redswitch */ + 0x004e00f8, + 0x40e5f002, + 0xf020e5f0, + 0x008010e5, + 0x0ef60185, 0x0f04bd00, - 0x02f87e03, - 0x01004b00, - 0x448ebfb2, - 0x8f7e4001, -/* 0x0676: ih_no_fwmthd */ - 0x044b0000, - 0xffb0bd05, - 0x0bf4b4ab, - 0x0700800c, - 0x000bf603, -/* 0x068a: ih_no_other */ - 0x004004bd, - 0x000af601, - 0xf0fc04bd, - 0xd0fce0fc, - 0xa0fcb0fc, - 0x80fc90fc, - 0xfc0088fe, - 0xf400fc80, - 0x01f80032, -/* 0x06ac: ctx_4170s */ - 0xb210f5f0, - 0x41708eff, +/* 0x06e5: ctx_redswitch_delay */ + 0x01f2b608, + 0xf1fd1bf4, + 0xf10400e5, + 0x800100e5, + 0xf6018500, + 0x04bd000e, +/* 0x06fe: ctx_86c */ + 0x008000f8, + 0x0ff60223, + 0xb204bd00, + 0x8a148eff, 0x008f7e40, -/* 0x06bb: ctx_4170w */ - 0x8e00f800, - 0x7e404170, - 0xb2000065, - 0x10f4f0ff, - 0xf8f31bf4, -/* 0x06cd: ctx_redswitch */ - 0x02004e00, - 0xf040e5f0, - 0xe5f020e5, - 0x85008010, - 0x000ef601, - 0x080f04bd, -/* 0x06e4: ctx_redswitch_delay */ - 0xf401f2b6, - 0xe5f1fd1b, - 0xe5f10400, - 0x00800100, - 0x0ef60185, - 0xf804bd00, -/* 0x06fd: ctx_86c */ - 0x23008000, + 0x8effb200, + 0x7e41a88c, + 0xf800008f, +/* 0x071d: ctx_mem */ + 0x84008000, 0x000ff602, - 0xffb204bd, - 0x408a148e, - 0x00008f7e, - 0x8c8effb2, - 0x8f7e41a8, - 0x00f80000, -/* 0x071c: ctx_mem */ - 0x02840080, - 0xbd000ff6, -/* 0x0725: ctx_mem_wait */ - 0x84008f04, - 0x00ffcf02, - 0xf405fffd, - 0x00f8f61b, -/* 0x0734: ctx_load */ - 0x99f094bd, - 0x37008005, - 0x0009f602, - 0x0c0a04bd, - 0x0000b87e, - 0x0080f4bd, - 0x0ff60289, - 0x8004bd00, - 0xf602c100, - 0x04bd0002, - 0x02830080, +/* 0x0726: ctx_mem_wait */ + 0x008f04bd, + 0xffcf0284, + 0x05fffd00, + 0xf8f61bf4, +/* 0x0735: ctx_load */ + 0xf094bd00, + 0x00800599, + 0x09f60237, + 0x0a04bd00, + 0x00b87e0c, + 0x80f4bd00, + 0xf6028900, + 0x04bd000f, + 0x02c10080, 0xbd0002f6, - 0x7e070f04, - 0x8000071c, - 0xf602c000, - 0x04bd0002, - 0xf0000bfe, - 0x24b61f2a, - 0x0220b604, - 0x99f094bd, - 0x37008008, - 0x0009f602, - 0x008004bd, - 0x02f60281, - 0xd204bd00, - 0x80000000, - 0x800225f0, - 0xf6028800, - 0x04bd0002, - 0x00421001, - 0x0223f002, - 0xf80512fa, - 0xf094bd03, + 0x83008004, + 0x0002f602, + 0x070f04bd, + 0x00071d7e, + 0x02c00080, + 0xbd0002f6, + 0x000bfe04, + 0xb61f2af0, + 0x20b60424, + 0xf094bd02, 0x00800899, - 0x09f60217, - 0x9804bd00, - 0x14b68101, - 0x80029818, - 0xfd0825b6, - 0x01b50512, - 0xf094bd16, - 0x00800999, 0x09f60237, 0x8004bd00, 0xf6028100, - 0x04bd0001, - 0x00800102, - 0x02f60288, - 0x4104bd00, - 0x13f00100, - 0x0501fa06, + 0x04bd0002, + 0x000000d2, + 0x0225f080, + 0x02880080, + 0xbd0002f6, + 0x42100104, + 0x23f00200, + 0x0512fa02, 0x94bd03f8, - 0x800999f0, + 0x800899f0, 0xf6021700, 0x04bd0009, - 0x99f094bd, - 0x17008005, - 0x0009f602, - 0x00f804bd, -/* 0x0820: ctx_chan */ - 0x0007347e, - 0xb87e0c0a, - 0x050f0000, - 0x00071c7e, -/* 0x0832: ctx_mmio_exec */ - 0x039800f8, - 0x81008041, - 0x0003f602, - 0x34bd04bd, -/* 0x0840: ctx_mmio_loop */ - 0xf4ff34c4, - 0x00450e1b, - 0x0653f002, - 0xf80535fa, -/* 0x0851: ctx_mmio_pull */ - 0x804e9803, - 0x7e814f98, - 0xb600008f, - 0x12b60830, - 0xdf1bf401, -/* 0x0864: ctx_mmio_done */ - 0x80160398, - 0xf6028100, - 0x04bd0003, - 0x414000b5, - 0x13f00100, - 0x0601fa06, - 0x00f803f8, -/* 0x0880: ctx_xfer */ - 0x0080040e, - 0x0ef60302, -/* 0x088b: ctx_xfer_idle */ - 0x8e04bd00, - 0xcf030000, - 0xe4f100ee, - 0x1bf42000, - 0x0611f4f5, -/* 0x089f: ctx_xfer_pre */ - 0x0f0c02f4, - 0x06fd7e10, - 0x1b11f400, -/* 0x08a8: ctx_xfer_pre_load */ - 0xac7e020f, - 0xbb7e0006, - 0xcd7e0006, - 0xf4bd0006, - 0x0006ac7e, - 0x0007347e, -/* 0x08c0: ctx_xfer_exec */ - 0xbd160198, - 0x05008024, - 0x0002f601, - 0x1fb204bd, - 0x41a5008e, - 0x00008f7e, - 0xf001fcf0, - 0x24b6022c, - 0x05f2fd01, - 0x048effb2, - 0x8f7e41a5, - 0x167e0000, - 0x24bd0002, - 0x0247fc80, - 0xbd0002f6, - 0x012cf004, - 0x800320b6, - 0xf6024afc, + 0xb6810198, + 0x02981814, + 0x0825b680, + 0xb50512fd, + 0x94bd1601, + 0x800999f0, + 0xf6023700, + 0x04bd0009, + 0x02810080, + 0xbd0001f6, + 0x80010204, + 0xf6028800, 0x04bd0002, - 0xf001acf0, - 0x000b06a5, - 0x98000c98, - 0x000e010d, - 0x00013d7e, - 0xec7e080a, - 0x0a7e0000, - 0x01f40002, - 0x7e0c0a12, + 0xf0010041, + 0x01fa0613, + 0xbd03f805, + 0x0999f094, + 0x02170080, + 0xbd0009f6, + 0xf094bd04, + 0x00800599, + 0x09f60217, + 0xf804bd00, +/* 0x0821: ctx_chan */ + 0x07357e00, + 0x7e0c0a00, 0x0f0000b8, - 0x071c7e05, - 0x2d02f400, -/* 0x093c: ctx_xfer_post */ - 0xac7e020f, - 0xf4bd0006, - 0x0006fd7e, - 0x0002277e, - 0x0006bb7e, - 0xac7ef4bd, + 0x071d7e05, +/* 0x0833: ctx_mmio_exec */ + 0x9800f800, + 0x00804103, + 0x03f60281, + 0xbd04bd00, +/* 0x0841: ctx_mmio_loop */ + 0xff34c434, + 0x450e1bf4, + 0x53f00200, + 0x0535fa06, +/* 0x0852: ctx_mmio_pull */ + 0x4e9803f8, + 0x814f9880, + 0x00008f7e, + 0xb60830b6, + 0x1bf40112, +/* 0x0865: ctx_mmio_done */ + 0x160398df, + 0x02810080, + 0xbd0003f6, + 0x4000b504, + 0xf0010041, + 0x01fa0613, + 0xf803f806, +/* 0x0881: ctx_xfer */ + 0x80040e00, + 0xf6030200, + 0x04bd000e, +/* 0x088c: ctx_xfer_idle */ + 0x0300008e, + 0xf100eecf, + 0xf42000e4, + 0x11f4f51b, + 0x0c02f406, +/* 0x08a0: ctx_xfer_pre */ + 0xfe7e100f, 0x11f40006, - 0x40019810, - 0xf40511fd, - 0x327e070b, -/* 0x0966: ctx_xfer_no_post_mmio */ -/* 0x0966: ctx_xfer_done */ - 0x00f80008, +/* 0x08a9: ctx_xfer_pre_load */ + 0x7e020f1b, + 0x7e0006ad, + 0x7e0006bc, + 0xbd0006ce, + 0x06ad7ef4, + 0x07357e00, +/* 0x08c1: ctx_xfer_exec */ + 0x16019800, + 0x008024bd, + 0x02f60105, + 0xb204bd00, + 0xa5008e1f, + 0x008f7e41, + 0x01fcf000, + 0xb6022cf0, + 0xf2fd0124, + 0x8effb205, + 0x7e41a504, + 0x7e00008f, + 0xbd000216, + 0x47fc8024, + 0x0002f602, + 0x2cf004bd, + 0x0320b601, + 0x024afc80, + 0xbd0002f6, + 0x01acf004, + 0x0b06a5f0, + 0x000c9800, + 0x0e010d98, + 0x013d7e00, + 0x7e080a00, + 0x7e0000ec, + 0xf400020a, + 0x0c0a1201, + 0x0000b87e, + 0x1d7e050f, + 0x02f40007, +/* 0x093d: ctx_xfer_post */ + 0x7e020f2d, + 0xbd0006ad, + 0x06fe7ef4, + 0x02277e00, + 0x06bc7e00, + 0x7ef4bd00, + 0xf40006ad, + 0x01981011, + 0x0511fd40, + 0x7e070bf4, +/* 0x0967: ctx_xfer_no_post_mmio */ +/* 0x0967: ctx_xfer_done */ + 0xf8000833, 0x00000000, 0x00000000, 0x00000000, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c index da1ba74682b4..65c332118fd6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c @@ -192,7 +192,7 @@ g84_gr = { }; int -g84_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +g84_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv50_gr_new_(&g84_gr, device, index, pgr); + return nv50_gr_new_(&g84_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index c578deb5867a..397ff4fe9df8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -26,9 +26,9 @@ #include "fuc/os.h" #include <core/client.h> -#include <core/option.h> #include <core/firmware.h> -#include <subdev/secboot.h> +#include <core/option.h> +#include <subdev/acr.h> #include <subdev/fb.h> #include <subdev/mc.h> #include <subdev/pmu.h> @@ -741,7 +741,7 @@ gf100_gr_fecs_ctrl_ctxsw(struct gf100_gr *gr, u32 mthd) return -ETIMEDOUT; } -int +static int gf100_gr_fecs_start_ctxsw(struct nvkm_gr *base) { struct gf100_gr *gr = gf100_gr(base); @@ -756,7 +756,7 @@ gf100_gr_fecs_start_ctxsw(struct nvkm_gr *base) return ret; } -int +static int gf100_gr_fecs_stop_ctxsw(struct nvkm_gr *base) { struct gf100_gr *gr = gf100_gr(base); @@ -1636,7 +1636,7 @@ gf100_gr_intr(struct nvkm_gr *base) static void gf100_gr_init_fw(struct nvkm_falcon *falcon, - struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) + struct nvkm_blob *code, struct nvkm_blob *data) { nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0); nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false); @@ -1690,26 +1690,30 @@ gf100_gr_init_ctxctl_ext(struct gf100_gr *gr) { struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_device *device = subdev->device; - struct nvkm_secboot *sb = device->secboot; - u32 secboot_mask = 0; + u32 lsf_mask = 0; int ret; /* load fuc microcode */ nvkm_mc_unk260(device, 0); /* securely-managed falcons must be reset using secure boot */ - if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS)) - secboot_mask |= BIT(NVKM_SECBOOT_FALCON_FECS); - else - gf100_gr_init_fw(gr->fecs.falcon, &gr->fuc409c, &gr->fuc409d); - if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS)) - secboot_mask |= BIT(NVKM_SECBOOT_FALCON_GPCCS); - else - gf100_gr_init_fw(gr->gpccs.falcon, &gr->fuc41ac, &gr->fuc41ad); + if (!nvkm_acr_managed_falcon(device, NVKM_ACR_LSF_FECS)) { + gf100_gr_init_fw(&gr->fecs.falcon, &gr->fecs.inst, + &gr->fecs.data); + } else { + lsf_mask |= BIT(NVKM_ACR_LSF_FECS); + } + + if (!nvkm_acr_managed_falcon(device, NVKM_ACR_LSF_GPCCS)) { + gf100_gr_init_fw(&gr->gpccs.falcon, &gr->gpccs.inst, + &gr->gpccs.data); + } else { + lsf_mask |= BIT(NVKM_ACR_LSF_GPCCS); + } - if (secboot_mask != 0) { - int ret = nvkm_secboot_reset(sb, secboot_mask); + if (lsf_mask) { + ret = nvkm_acr_bootstrap_falcons(device, lsf_mask); if (ret) return ret; } @@ -1721,8 +1725,8 @@ gf100_gr_init_ctxctl_ext(struct gf100_gr *gr) nvkm_wr32(device, 0x41a10c, 0x00000000); nvkm_wr32(device, 0x40910c, 0x00000000); - nvkm_falcon_start(gr->gpccs.falcon); - nvkm_falcon_start(gr->fecs.falcon); + nvkm_falcon_start(&gr->gpccs.falcon); + nvkm_falcon_start(&gr->fecs.falcon); if (nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x409800) & 0x00000001) @@ -1784,18 +1788,18 @@ gf100_gr_init_ctxctl_int(struct gf100_gr *gr) /* load HUB microcode */ nvkm_mc_unk260(device, 0); - nvkm_falcon_load_dmem(gr->fecs.falcon, + nvkm_falcon_load_dmem(&gr->fecs.falcon, gr->func->fecs.ucode->data.data, 0x0, gr->func->fecs.ucode->data.size, 0); - nvkm_falcon_load_imem(gr->fecs.falcon, + nvkm_falcon_load_imem(&gr->fecs.falcon, gr->func->fecs.ucode->code.data, 0x0, gr->func->fecs.ucode->code.size, 0, 0, false); /* load GPC microcode */ - nvkm_falcon_load_dmem(gr->gpccs.falcon, + nvkm_falcon_load_dmem(&gr->gpccs.falcon, gr->func->gpccs.ucode->data.data, 0x0, gr->func->gpccs.ucode->data.size, 0); - nvkm_falcon_load_imem(gr->gpccs.falcon, + nvkm_falcon_load_imem(&gr->gpccs.falcon, gr->func->gpccs.ucode->code.data, 0x0, gr->func->gpccs.ucode->code.size, 0, 0, false); nvkm_mc_unk260(device, 1); @@ -1941,17 +1945,6 @@ gf100_gr_oneinit(struct nvkm_gr *base) struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_device *device = subdev->device; int i, j; - int ret; - - ret = nvkm_falcon_v1_new(subdev, "FECS", 0x409000, &gr->fecs.falcon); - if (ret) - return ret; - - mutex_init(&gr->fecs.mutex); - - ret = nvkm_falcon_v1_new(subdev, "GPCCS", 0x41a000, &gr->gpccs.falcon); - if (ret) - return ret; nvkm_pmu_pgob(device->pmu, false); @@ -1988,15 +1981,41 @@ gf100_gr_init_(struct nvkm_gr *base) { struct gf100_gr *gr = gf100_gr(base); struct nvkm_subdev *subdev = &base->engine.subdev; + struct nvkm_device *device = subdev->device; + bool reset = device->chipset == 0x137 || device->chipset == 0x138; u32 ret; + /* On certain GP107/GP108 boards, we trigger a weird issue where + * GR will stop responding to PRI accesses after we've asked the + * SEC2 RTOS to boot the GR falcons. This happens with far more + * frequency when cold-booting a board (ie. returning from D3). + * + * The root cause for this is not known and has proven difficult + * to isolate, with many avenues being dead-ends. + * + * A workaround was discovered by Karol, whereby putting GR into + * reset for an extended period right before initialisation + * prevents the problem from occuring. + * + * XXX: As RM does not require any such workaround, this is more + * of a hack than a true fix. + */ + reset = nvkm_boolopt(device->cfgopt, "NvGrResetWar", reset); + if (reset) { + nvkm_mask(device, 0x000200, 0x00001000, 0x00000000); + nvkm_rd32(device, 0x000200); + msleep(50); + nvkm_mask(device, 0x000200, 0x00001000, 0x00001000); + nvkm_rd32(device, 0x000200); + } + nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); - ret = nvkm_falcon_get(gr->fecs.falcon, subdev); + ret = nvkm_falcon_get(&gr->fecs.falcon, subdev); if (ret) return ret; - ret = nvkm_falcon_get(gr->gpccs.falcon, subdev); + ret = nvkm_falcon_get(&gr->gpccs.falcon, subdev); if (ret) return ret; @@ -2004,49 +2023,34 @@ gf100_gr_init_(struct nvkm_gr *base) } static int -gf100_gr_fini_(struct nvkm_gr *base, bool suspend) +gf100_gr_fini(struct nvkm_gr *base, bool suspend) { struct gf100_gr *gr = gf100_gr(base); struct nvkm_subdev *subdev = &gr->base.engine.subdev; - nvkm_falcon_put(gr->gpccs.falcon, subdev); - nvkm_falcon_put(gr->fecs.falcon, subdev); + nvkm_falcon_put(&gr->gpccs.falcon, subdev); + nvkm_falcon_put(&gr->fecs.falcon, subdev); return 0; } -void -gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) -{ - kfree(fuc->data); - fuc->data = NULL; -} - -static void -gf100_gr_dtor_init(struct gf100_gr_pack *pack) -{ - vfree(pack); -} - -void * +static void * gf100_gr_dtor(struct nvkm_gr *base) { struct gf100_gr *gr = gf100_gr(base); - if (gr->func->dtor) - gr->func->dtor(gr); kfree(gr->data); - nvkm_falcon_del(&gr->gpccs.falcon); - nvkm_falcon_del(&gr->fecs.falcon); + nvkm_falcon_dtor(&gr->gpccs.falcon); + nvkm_falcon_dtor(&gr->fecs.falcon); - gf100_gr_dtor_fw(&gr->fuc409c); - gf100_gr_dtor_fw(&gr->fuc409d); - gf100_gr_dtor_fw(&gr->fuc41ac); - gf100_gr_dtor_fw(&gr->fuc41ad); + nvkm_blob_dtor(&gr->fecs.inst); + nvkm_blob_dtor(&gr->fecs.data); + nvkm_blob_dtor(&gr->gpccs.inst); + nvkm_blob_dtor(&gr->gpccs.data); - gf100_gr_dtor_init(gr->fuc_bundle); - gf100_gr_dtor_init(gr->fuc_method); - gf100_gr_dtor_init(gr->fuc_sw_ctx); - gf100_gr_dtor_init(gr->fuc_sw_nonctx); + vfree(gr->bundle); + vfree(gr->method); + vfree(gr->sw_ctx); + vfree(gr->sw_nonctx); return gr; } @@ -2056,7 +2060,7 @@ gf100_gr_ = { .dtor = gf100_gr_dtor, .oneinit = gf100_gr_oneinit, .init = gf100_gr_init_, - .fini = gf100_gr_fini_, + .fini = gf100_gr_fini, .intr = gf100_gr_intr, .units = gf100_gr_units, .chan_new = gf100_gr_chan_new, @@ -2067,87 +2071,24 @@ gf100_gr_ = { .ctxsw.inst = gf100_gr_ctxsw_inst, }; -int -gf100_gr_ctor_fw_legacy(struct gf100_gr *gr, const char *fwname, - struct gf100_gr_fuc *fuc, int ret) -{ - struct nvkm_subdev *subdev = &gr->base.engine.subdev; - struct nvkm_device *device = subdev->device; - const struct firmware *fw; - char f[32]; - - /* see if this firmware has a legacy path */ - if (!strcmp(fwname, "fecs_inst")) - fwname = "fuc409c"; - else if (!strcmp(fwname, "fecs_data")) - fwname = "fuc409d"; - else if (!strcmp(fwname, "gpccs_inst")) - fwname = "fuc41ac"; - else if (!strcmp(fwname, "gpccs_data")) - fwname = "fuc41ad"; - else { - /* nope, let's just return the error we got */ - nvkm_error(subdev, "failed to load %s\n", fwname); - return ret; - } - - /* yes, try to load from the legacy path */ - nvkm_debug(subdev, "%s: falling back to legacy path\n", fwname); - - snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname); - ret = request_firmware(&fw, f, device->dev); - if (ret) { - snprintf(f, sizeof(f), "nouveau/%s", fwname); - ret = request_firmware(&fw, f, device->dev); - if (ret) { - nvkm_error(subdev, "failed to load %s\n", fwname); - return ret; - } - } - - fuc->size = fw->size; - fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); - release_firmware(fw); - return (fuc->data != NULL) ? 0 : -ENOMEM; -} - -int -gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, - struct gf100_gr_fuc *fuc) -{ - const struct firmware *fw; - int ret; - - ret = nvkm_firmware_get(&gr->base.engine.subdev, fwname, &fw); - if (ret) { - ret = gf100_gr_ctor_fw_legacy(gr, fwname, fuc, ret); - if (ret) - return -ENODEV; - return 0; - } - - fuc->size = fw->size; - fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); - nvkm_firmware_put(fw); - return (fuc->data != NULL) ? 0 : -ENOMEM; -} - -int -gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device, - int index, struct gf100_gr *gr) -{ - gr->func = func; - gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW", - func->fecs.ucode == NULL); - - return nvkm_gr_ctor(&gf100_gr_, device, index, - gr->firmware || func->fecs.ucode != NULL, - &gr->base); -} +static const struct nvkm_falcon_func +gf100_gr_flcn = { + .fbif = 0x600, + .load_imem = nvkm_falcon_v1_load_imem, + .load_dmem = nvkm_falcon_v1_load_dmem, + .read_dmem = nvkm_falcon_v1_read_dmem, + .bind_context = nvkm_falcon_v1_bind_context, + .wait_for_halt = nvkm_falcon_v1_wait_for_halt, + .clear_interrupt = nvkm_falcon_v1_clear_interrupt, + .set_start_addr = nvkm_falcon_v1_set_start_addr, + .start = nvkm_falcon_v1_start, + .enable = nvkm_falcon_v1_enable, + .disable = nvkm_falcon_v1_disable, +}; int -gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device, - int index, struct nvkm_gr **pgr) +gf100_gr_new_(const struct gf100_gr_fwif *fwif, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { struct gf100_gr *gr; int ret; @@ -2156,22 +2097,49 @@ gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device, return -ENOMEM; *pgr = &gr->base; - ret = gf100_gr_ctor(func, device, index, gr); + ret = nvkm_gr_ctor(&gf100_gr_, device, type, inst, true, &gr->base); if (ret) return ret; - if (gr->firmware) { - if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || - gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || - gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || - gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) - return -ENODEV; - } + fwif = nvkm_firmware_load(&gr->base.engine.subdev, fwif, "Gr", gr); + if (IS_ERR(fwif)) + return PTR_ERR(fwif); + + gr->func = fwif->func; + + ret = nvkm_falcon_ctor(&gf100_gr_flcn, &gr->base.engine.subdev, + "fecs", 0x409000, &gr->fecs.falcon); + if (ret) + return ret; + + mutex_init(&gr->fecs.mutex); + + ret = nvkm_falcon_ctor(&gf100_gr_flcn, &gr->base.engine.subdev, + "gpccs", 0x41a000, &gr->gpccs.falcon); + if (ret) + return ret; return 0; } void +gf100_gr_init_num_tpc_per_gpc(struct gf100_gr *gr, bool pd, bool ds) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + int gpc, i, j; + u32 data; + + for (gpc = 0, i = 0; i < 4; i++) { + for (data = 0, j = 0; j < 8 && gpc < gr->gpc_nr; j++, gpc++) + data |= gr->tpc_nr[gpc] << (j * 4); + if (pd) + nvkm_wr32(device, 0x406028 + (i * 4), data); + if (ds) + nvkm_wr32(device, 0x405870 + (i * 4), data); + } +} + +void gf100_gr_init_400054(struct gf100_gr *gr) { nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x34ce3464); @@ -2295,8 +2263,8 @@ gf100_gr_init(struct gf100_gr *gr) gr->func->init_gpc_mmu(gr); - if (gr->fuc_sw_nonctx) - gf100_gr_mmio(gr, gr->fuc_sw_nonctx); + if (gr->sw_nonctx) + gf100_gr_mmio(gr, gr->sw_nonctx); else gf100_gr_mmio(gr, gr->func->mmio); @@ -2320,6 +2288,8 @@ gf100_gr_init(struct gf100_gr *gr) gr->func->init_bios_2(gr); if (gr->func->init_swdx_pes_mask) gr->func->init_swdx_pes_mask(gr); + if (gr->func->init_fs) + gr->func->init_fs(gr); nvkm_wr32(device, 0x400500, 0x00010001); @@ -2338,8 +2308,8 @@ gf100_gr_init(struct gf100_gr *gr) if (gr->func->init_40601c) gr->func->init_40601c(gr); - nvkm_wr32(device, 0x404490, 0xc0000000); nvkm_wr32(device, 0x406018, 0xc0000000); + nvkm_wr32(device, 0x404490, 0xc0000000); if (gr->func->init_sked_hww_esr) gr->func->init_sked_hww_esr(gr); @@ -2454,7 +2424,66 @@ gf100_gr = { }; int -gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gf100_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) +{ + gr->firmware = false; + return 0; +} + +static int +gf100_gr_load_fw(struct gf100_gr *gr, const char *name, + struct nvkm_blob *blob) +{ + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; + const struct firmware *fw; + char f[32]; + int ret; + + snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, name); + ret = request_firmware(&fw, f, device->dev); + if (ret) { + snprintf(f, sizeof(f), "nouveau/%s", name); + ret = request_firmware(&fw, f, device->dev); + if (ret) { + nvkm_error(subdev, "failed to load %s\n", name); + return ret; + } + } + + blob->size = fw->size; + blob->data = kmemdup(fw->data, blob->size, GFP_KERNEL); + release_firmware(fw); + return (blob->data != NULL) ? 0 : -ENOMEM; +} + +int +gf100_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + + if (!nvkm_boolopt(device->cfgopt, "NvGrUseFW", false)) + return -EINVAL; + + if (gf100_gr_load_fw(gr, "fuc409c", &gr->fecs.inst) || + gf100_gr_load_fw(gr, "fuc409d", &gr->fecs.data) || + gf100_gr_load_fw(gr, "fuc41ac", &gr->gpccs.inst) || + gf100_gr_load_fw(gr, "fuc41ad", &gr->gpccs.data)) + return -ENOENT; + + gr->firmware = true; + return 0; +} + +static const struct gf100_gr_fwif +gf100_gr_fwif[] = { + { -1, gf100_gr_load, &gf100_gr }, + { -1, gf100_gr_nofw, &gf100_gr }, + {} +}; + +int +gf100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(&gf100_gr, device, index, pgr); + return gf100_gr_new_(gf100_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index fafdd0bbea9b..c0038f906135 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -31,6 +31,8 @@ #include <subdev/mmu.h> #include <engine/falcon.h> +struct nvkm_acr_lsfw; + #define GPC_MAX 32 #define TPC_MAX_PER_GPC 8 #define TPC_MAX (GPC_MAX * TPC_MAX_PER_GPC) @@ -55,11 +57,6 @@ struct gf100_gr_mmio { int buffer; }; -struct gf100_gr_fuc { - u32 *data; - u32 size; -}; - struct gf100_gr_zbc_color { u32 format; u32 ds[4]; @@ -83,29 +80,30 @@ struct gf100_gr { struct nvkm_gr base; struct { - struct nvkm_falcon *falcon; + struct nvkm_falcon falcon; + struct nvkm_blob inst; + struct nvkm_blob data; + struct mutex mutex; u32 disable; } fecs; struct { - struct nvkm_falcon *falcon; + struct nvkm_falcon falcon; + struct nvkm_blob inst; + struct nvkm_blob data; } gpccs; - struct gf100_gr_fuc fuc409c; - struct gf100_gr_fuc fuc409d; - struct gf100_gr_fuc fuc41ac; - struct gf100_gr_fuc fuc41ad; bool firmware; /* * Used if the register packs are loaded from NVIDIA fw instead of * using hardcoded arrays. To be allocated with vzalloc(). */ - struct gf100_gr_pack *fuc_sw_nonctx; - struct gf100_gr_pack *fuc_sw_ctx; - struct gf100_gr_pack *fuc_bundle; - struct gf100_gr_pack *fuc_method; + struct gf100_gr_pack *sw_nonctx; + struct gf100_gr_pack *sw_ctx; + struct gf100_gr_pack *bundle; + struct gf100_gr_pack *method; struct gf100_gr_zbc_color zbc_color[NVKM_LTC_MAX_ZBC_CNT]; struct gf100_gr_zbc_depth zbc_depth[NVKM_LTC_MAX_ZBC_CNT]; @@ -140,12 +138,6 @@ struct gf100_gr { u32 size_pm; }; -int gf100_gr_ctor(const struct gf100_gr_func *, struct nvkm_device *, - int, struct gf100_gr *); -int gf100_gr_new_(const struct gf100_gr_func *, struct nvkm_device *, - int, struct nvkm_gr **); -void *gf100_gr_dtor(struct nvkm_gr *); - int gf100_gr_fecs_bind_pointer(struct gf100_gr *, u32 inst); struct gf100_gr_func_zbc { @@ -157,7 +149,6 @@ struct gf100_gr_func_zbc { }; struct gf100_gr_func { - void (*dtor)(struct gf100_gr *); void (*oneinit_tiles)(struct gf100_gr *); void (*oneinit_sm_id)(struct gf100_gr *); int (*init)(struct gf100_gr *); @@ -171,6 +162,7 @@ struct gf100_gr_func { void (*init_rop_active_fbps)(struct gf100_gr *); void (*init_bios_2)(struct gf100_gr *); void (*init_swdx_pes_mask)(struct gf100_gr *); + void (*init_fs)(struct gf100_gr *); void (*init_fecs_exceptions)(struct gf100_gr *); void (*init_ds_hww_esr_2)(struct gf100_gr *); void (*init_40601c)(struct gf100_gr *); @@ -217,6 +209,7 @@ void gf100_gr_init_419eb4(struct gf100_gr *); void gf100_gr_init_tex_hww_esr(struct gf100_gr *, int, int); void gf100_gr_init_shader_exceptions(struct gf100_gr *, int, int); void gf100_gr_init_400054(struct gf100_gr *); +void gf100_gr_init_num_tpc_per_gpc(struct gf100_gr *, bool, bool); extern const struct gf100_gr_func_zbc gf100_gr_zbc; void gf117_gr_init_zcull(struct gf100_gr *); @@ -245,10 +238,18 @@ void gp100_gr_init_fecs_exceptions(struct gf100_gr *); void gp100_gr_init_shader_exceptions(struct gf100_gr *, int, int); void gp100_gr_zbc_clear_color(struct gf100_gr *, int); void gp100_gr_zbc_clear_depth(struct gf100_gr *, int); +extern const struct gf100_gr_func_zbc gp100_gr_zbc; void gp102_gr_init_swdx_pes_mask(struct gf100_gr *); extern const struct gf100_gr_func_zbc gp102_gr_zbc; +extern const struct gf100_gr_func gp107_gr; + +void gv100_gr_init_419bd8(struct gf100_gr *); +void gv100_gr_init_504430(struct gf100_gr *, int, int); +void gv100_gr_init_shader_exceptions(struct gf100_gr *, int, int); +void gv100_gr_trap_mp(struct gf100_gr *, int, int); + #define gf100_gr_chan(p) container_of((p), struct gf100_gr_chan, object) #include <core/object.h> @@ -269,9 +270,6 @@ struct gf100_gr_chan { void gf100_gr_ctxctl_debug(struct gf100_gr *); -void gf100_gr_dtor_fw(struct gf100_gr_fuc *); -int gf100_gr_ctor_fw(struct gf100_gr *, const char *, - struct gf100_gr_fuc *); u64 gf100_gr_units(struct nvkm_gr *); void gf100_gr_zbc_init(struct gf100_gr *); @@ -294,8 +292,8 @@ struct gf100_gr_pack { for (init = pack->init; init && init->count; init++) struct gf100_gr_ucode { - struct gf100_gr_fuc code; - struct gf100_gr_fuc data; + struct nvkm_blob code; + struct nvkm_blob data; }; extern struct gf100_gr_ucode gf100_gr_fecs_ucode; @@ -310,17 +308,6 @@ void gf100_gr_icmd(struct gf100_gr *, const struct gf100_gr_pack *); void gf100_gr_mthd(struct gf100_gr *, const struct gf100_gr_pack *); int gf100_gr_init_ctxctl(struct gf100_gr *); -/* external bundles loading functions */ -int gk20a_gr_av_to_init(struct gf100_gr *, const char *, - struct gf100_gr_pack **); -int gk20a_gr_aiv_to_init(struct gf100_gr *, const char *, - struct gf100_gr_pack **); -int gk20a_gr_av_to_method(struct gf100_gr *, const char *, - struct gf100_gr_pack **); - -int gm200_gr_new_(const struct gf100_gr_func *, struct nvkm_device *, int, - struct nvkm_gr **); - /* register init value lists */ extern const struct gf100_gr_init gf100_gr_init_main_0[]; @@ -403,4 +390,32 @@ extern const struct gf100_gr_init gm107_gr_init_cbm_0[]; void gm107_gr_init_bios(struct gf100_gr *); void gm200_gr_init_gpc_mmu(struct gf100_gr *); + +struct gf100_gr_fwif { + int version; + int (*load)(struct gf100_gr *, int ver, const struct gf100_gr_fwif *); + const struct gf100_gr_func *func; + const struct nvkm_acr_lsf_func *fecs; + const struct nvkm_acr_lsf_func *gpccs; +}; + +int gf100_gr_load(struct gf100_gr *, int, const struct gf100_gr_fwif *); +int gf100_gr_nofw(struct gf100_gr *, int, const struct gf100_gr_fwif *); + +int gk20a_gr_load_sw(struct gf100_gr *, const char *path, int ver); + +int gm200_gr_nofw(struct gf100_gr *, int, const struct gf100_gr_fwif *); +int gm200_gr_load(struct gf100_gr *, int, const struct gf100_gr_fwif *); +extern const struct nvkm_acr_lsf_func gm200_gr_gpccs_acr; +extern const struct nvkm_acr_lsf_func gm200_gr_fecs_acr; + +extern const struct nvkm_acr_lsf_func gm20b_gr_fecs_acr; +void gm20b_gr_acr_bld_write(struct nvkm_acr *, u32, struct nvkm_acr_lsfw *); +void gm20b_gr_acr_bld_patch(struct nvkm_acr *, u32, s64); + +extern const struct nvkm_acr_lsf_func gp108_gr_gpccs_acr; +extern const struct nvkm_acr_lsf_func gp108_gr_fecs_acr; + +int gf100_gr_new_(const struct gf100_gr_fwif *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_gr **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c index 42c2fd9fc04e..3acd99c306f2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c @@ -144,8 +144,15 @@ gf104_gr = { } }; +static const struct gf100_gr_fwif +gf104_gr_fwif[] = { + { -1, gf100_gr_load, &gf104_gr }, + { -1, gf100_gr_nofw, &gf104_gr }, + {} +}; + int -gf104_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gf104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(&gf104_gr, device, index, pgr); + return gf100_gr_new_(gf104_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c index 4731a460adc7..ab3760e804b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c @@ -143,8 +143,15 @@ gf108_gr = { } }; +static const struct gf100_gr_fwif +gf108_gr_fwif[] = { + { -1, gf100_gr_load, &gf108_gr }, + { -1, gf100_gr_nofw, &gf108_gr }, + {} +}; + int -gf108_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gf108_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(&gf108_gr, device, index, pgr); + return gf100_gr_new_(gf108_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c index cdf759c8cd7f..616e2def1865 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c @@ -119,8 +119,15 @@ gf110_gr = { } }; +static const struct gf100_gr_fwif +gf110_gr_fwif[] = { + { -1, gf100_gr_load, &gf110_gr }, + { -1, gf100_gr_nofw, &gf110_gr }, + {} +}; + int -gf110_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gf110_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(&gf110_gr, device, index, pgr); + return gf100_gr_new_(gf110_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c index a4158f84c649..669e7536970e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c @@ -184,8 +184,15 @@ gf117_gr = { } }; +static const struct gf100_gr_fwif +gf117_gr_fwif[] = { + { -1, gf100_gr_load, &gf117_gr }, + { -1, gf100_gr_nofw, &gf117_gr }, + {} +}; + int -gf117_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gf117_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(&gf117_gr, device, index, pgr); + return gf100_gr_new_(gf117_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c index 4197844870b3..5b09bda8110c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c @@ -210,8 +210,15 @@ gf119_gr = { } }; +static const struct gf100_gr_fwif +gf119_gr_fwif[] = { + { -1, gf100_gr_load, &gf119_gr }, + { -1, gf100_gr_nofw, &gf119_gr }, + {} +}; + int -gf119_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gf119_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(&gf119_gr, device, index, pgr); + return gf100_gr_new_(gf119_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c index 477fee3e3715..b680eaa0f350 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c @@ -489,8 +489,15 @@ gk104_gr = { } }; +static const struct gf100_gr_fwif +gk104_gr_fwif[] = { + { -1, gf100_gr_load, &gk104_gr }, + { -1, gf100_gr_nofw, &gk104_gr }, + {} +}; + int -gk104_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gk104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(&gk104_gr, device, index, pgr); + return gf100_gr_new_(gk104_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c index 7cd628c84e07..103e06a77e65 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c @@ -385,8 +385,15 @@ gk110_gr = { } }; +static const struct gf100_gr_fwif +gk110_gr_fwif[] = { + { -1, gf100_gr_load, &gk110_gr }, + { -1, gf100_gr_nofw, &gk110_gr }, + {} +}; + int -gk110_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gk110_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(&gk110_gr, device, index, pgr); + return gf100_gr_new_(gk110_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c index a38faa215635..034d0b11a17d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c @@ -136,8 +136,16 @@ gk110b_gr = { } }; +static const struct gf100_gr_fwif +gk110b_gr_fwif[] = { + { -1, gf100_gr_load, &gk110b_gr }, + { -1, gf100_gr_nofw, &gk110b_gr }, + {} +}; + int -gk110b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gk110b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gr **pgr) { - return gf100_gr_new_(&gk110b_gr, device, index, pgr); + return gf100_gr_new_(gk110b_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c index 58456660e603..116d682f9f96 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c @@ -194,8 +194,15 @@ gk208_gr = { } }; +static const struct gf100_gr_fwif +gk208_gr_fwif[] = { + { -1, gf100_gr_load, &gk208_gr }, + { -1, gf100_gr_nofw, &gk208_gr }, + {} +}; + int -gk208_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gk208_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(&gk208_gr, device, index, pgr); + return gf100_gr_new_(gk208_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index 500cb08dd608..be0b2cefd8e8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -22,6 +22,7 @@ #include "gf100.h" #include "ctxgf100.h" +#include <core/firmware.h> #include <subdev/timer.h> #include <nvif/class.h> @@ -32,22 +33,23 @@ struct gk20a_fw_av u32 data; }; -int -gk20a_gr_av_to_init(struct gf100_gr *gr, const char *fw_name, - struct gf100_gr_pack **ppack) +static int +gk20a_gr_av_to_init(struct gf100_gr *gr, const char *path, const char *name, + int ver, struct gf100_gr_pack **ppack) { - struct gf100_gr_fuc fuc; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_blob blob; struct gf100_gr_init *init; struct gf100_gr_pack *pack; int nent; int ret; int i; - ret = gf100_gr_ctor_fw(gr, fw_name, &fuc); + ret = nvkm_firmware_load_blob(subdev, path, name, ver, &blob); if (ret) return ret; - nent = (fuc.size / sizeof(struct gk20a_fw_av)); + nent = (blob.size / sizeof(struct gk20a_fw_av)); pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1))); if (!pack) { ret = -ENOMEM; @@ -59,7 +61,7 @@ gk20a_gr_av_to_init(struct gf100_gr *gr, const char *fw_name, for (i = 0; i < nent; i++) { struct gf100_gr_init *ent = &init[i]; - struct gk20a_fw_av *av = &((struct gk20a_fw_av *)fuc.data)[i]; + struct gk20a_fw_av *av = &((struct gk20a_fw_av *)blob.data)[i]; ent->addr = av->addr; ent->data = av->data; @@ -70,7 +72,7 @@ gk20a_gr_av_to_init(struct gf100_gr *gr, const char *fw_name, *ppack = pack; end: - gf100_gr_dtor_fw(&fuc); + nvkm_blob_dtor(&blob); return ret; } @@ -81,22 +83,23 @@ struct gk20a_fw_aiv u32 data; }; -int -gk20a_gr_aiv_to_init(struct gf100_gr *gr, const char *fw_name, - struct gf100_gr_pack **ppack) +static int +gk20a_gr_aiv_to_init(struct gf100_gr *gr, const char *path, const char *name, + int ver, struct gf100_gr_pack **ppack) { - struct gf100_gr_fuc fuc; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_blob blob; struct gf100_gr_init *init; struct gf100_gr_pack *pack; int nent; int ret; int i; - ret = gf100_gr_ctor_fw(gr, fw_name, &fuc); + ret = nvkm_firmware_load_blob(subdev, path, name, ver, &blob); if (ret) return ret; - nent = (fuc.size / sizeof(struct gk20a_fw_aiv)); + nent = (blob.size / sizeof(struct gk20a_fw_aiv)); pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1))); if (!pack) { ret = -ENOMEM; @@ -108,7 +111,7 @@ gk20a_gr_aiv_to_init(struct gf100_gr *gr, const char *fw_name, for (i = 0; i < nent; i++) { struct gf100_gr_init *ent = &init[i]; - struct gk20a_fw_aiv *av = &((struct gk20a_fw_aiv *)fuc.data)[i]; + struct gk20a_fw_aiv *av = &((struct gk20a_fw_aiv *)blob.data)[i]; ent->addr = av->addr; ent->data = av->data; @@ -119,15 +122,16 @@ gk20a_gr_aiv_to_init(struct gf100_gr *gr, const char *fw_name, *ppack = pack; end: - gf100_gr_dtor_fw(&fuc); + nvkm_blob_dtor(&blob); return ret; } -int -gk20a_gr_av_to_method(struct gf100_gr *gr, const char *fw_name, - struct gf100_gr_pack **ppack) +static int +gk20a_gr_av_to_method(struct gf100_gr *gr, const char *path, const char *name, + int ver, struct gf100_gr_pack **ppack) { - struct gf100_gr_fuc fuc; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_blob blob; struct gf100_gr_init *init; struct gf100_gr_pack *pack; /* We don't suppose we will initialize more than 16 classes here... */ @@ -137,29 +141,30 @@ gk20a_gr_av_to_method(struct gf100_gr *gr, const char *fw_name, int ret; int i; - ret = gf100_gr_ctor_fw(gr, fw_name, &fuc); + ret = nvkm_firmware_load_blob(subdev, path, name, ver, &blob); if (ret) return ret; - nent = (fuc.size / sizeof(struct gk20a_fw_av)); + nent = (blob.size / sizeof(struct gk20a_fw_av)); - pack = vzalloc((sizeof(*pack) * max_classes) + - (sizeof(*init) * (nent + 1))); + pack = vzalloc((sizeof(*pack) * (max_classes + 1)) + + (sizeof(*init) * (nent + max_classes + 1))); if (!pack) { ret = -ENOMEM; goto end; } - init = (void *)(pack + max_classes); + init = (void *)(pack + max_classes + 1); - for (i = 0; i < nent; i++) { - struct gf100_gr_init *ent = &init[i]; - struct gk20a_fw_av *av = &((struct gk20a_fw_av *)fuc.data)[i]; + for (i = 0; i < nent; i++, init++) { + struct gk20a_fw_av *av = &((struct gk20a_fw_av *)blob.data)[i]; u32 class = av->addr & 0xffff; u32 addr = (av->addr & 0xffff0000) >> 14; if (prevclass != class) { - pack[classidx].init = ent; + if (prevclass) /* Add terminator to the method list. */ + init++; + pack[classidx].init = init; pack[classidx].type = class; prevclass = class; if (++classidx >= max_classes) { @@ -169,16 +174,16 @@ gk20a_gr_av_to_method(struct gf100_gr *gr, const char *fw_name, } } - ent->addr = addr; - ent->data = av->data; - ent->count = 1; - ent->pitch = 1; + init->addr = addr; + init->data = av->data; + init->count = 1; + init->pitch = 1; } *ppack = pack; end: - gf100_gr_dtor_fw(&fuc); + nvkm_blob_dtor(&blob); return ret; } @@ -224,7 +229,7 @@ gk20a_gr_init(struct gf100_gr *gr) /* Clear SCC RAM */ nvkm_wr32(device, 0x40802c, 0x1); - gf100_gr_mmio(gr, gr->fuc_sw_nonctx); + gf100_gr_mmio(gr, gr->sw_nonctx); ret = gk20a_gr_wait_mem_scrubbing(gr); if (ret) @@ -303,40 +308,56 @@ gk20a_gr = { }; int -gk20a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gk20a_gr_load_sw(struct gf100_gr *gr, const char *path, int ver) { - struct gf100_gr *gr; - int ret; + if (gk20a_gr_av_to_init(gr, path, "sw_nonctx", ver, &gr->sw_nonctx) || + gk20a_gr_aiv_to_init(gr, path, "sw_ctx", ver, &gr->sw_ctx) || + gk20a_gr_av_to_init(gr, path, "sw_bundle_init", ver, &gr->bundle) || + gk20a_gr_av_to_method(gr, path, "sw_method_init", ver, &gr->method)) + return -ENOENT; - if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) - return -ENOMEM; - *pgr = &gr->base; + return 0; +} - ret = gf100_gr_ctor(&gk20a_gr, device, index, gr); - if (ret) - return ret; +#if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) || IS_ENABLED(CONFIG_ARCH_TEGRA_132_SOC) +MODULE_FIRMWARE("nvidia/gk20a/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gk20a/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gk20a/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gk20a/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gk20a/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gk20a/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gk20a/sw_method_init.bin"); +MODULE_FIRMWARE("nvidia/gk20a/sw_nonctx.bin"); +#endif - if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || - gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || - gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || - gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) - return -ENODEV; +static int +gk20a_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) +{ + struct nvkm_subdev *subdev = &gr->base.engine.subdev; - ret = gk20a_gr_av_to_init(gr, "sw_nonctx", &gr->fuc_sw_nonctx); - if (ret) - return ret; + if (nvkm_firmware_load_blob(subdev, "", "fecs_inst", ver, + &gr->fecs.inst) || + nvkm_firmware_load_blob(subdev, "", "fecs_data", ver, + &gr->fecs.data) || + nvkm_firmware_load_blob(subdev, "", "gpccs_inst", ver, + &gr->gpccs.inst) || + nvkm_firmware_load_blob(subdev, "", "gpccs_data", ver, + &gr->gpccs.data)) + return -ENOENT; - ret = gk20a_gr_aiv_to_init(gr, "sw_ctx", &gr->fuc_sw_ctx); - if (ret) - return ret; + gr->firmware = true; - ret = gk20a_gr_av_to_init(gr, "sw_bundle_init", &gr->fuc_bundle); - if (ret) - return ret; + return gk20a_gr_load_sw(gr, "", ver); +} - ret = gk20a_gr_av_to_method(gr, "sw_method_init", &gr->fuc_method); - if (ret) - return ret; +static const struct gf100_gr_fwif +gk20a_gr_fwif[] = { + { 0, gk20a_gr_load, &gk20a_gr }, + {} +}; - return 0; +int +gk20a_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(gk20a_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c index 92e31d397207..310987174cb5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c @@ -429,8 +429,15 @@ gm107_gr = { } }; +static const struct gf100_gr_fwif +gm107_gr_fwif[] = { + { -1, gf100_gr_load, &gm107_gr }, + { -1, gf100_gr_nofw, &gm107_gr }, + {} +}; + int -gm107_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gm107_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(&gm107_gr, device, index, pgr); + return gf100_gr_new_(gm107_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c index eff30662b984..5c38ff0fe7f9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c @@ -24,14 +24,71 @@ #include "gf100.h" #include "ctxgf100.h" +#include <core/firmware.h> +#include <subdev/acr.h> #include <subdev/secboot.h> +#include <nvfw/flcn.h> + #include <nvif/class.h> +int +gm200_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) +{ + nvkm_warn(&gr->base.engine.subdev, "firmware unavailable\n"); + return -ENODEV; +} + /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ +static void +gm200_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) +{ + struct flcn_bl_dmem_desc_v1 hdr; + nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); + hdr.code_dma_base = hdr.code_dma_base + adjust; + hdr.data_dma_base = hdr.data_dma_base + adjust; + nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); + flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hdr); +} + +static void +gm200_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, + struct nvkm_acr_lsfw *lsfw) +{ + const u64 base = lsfw->offset.img + lsfw->app_start_offset; + const u64 code = base + lsfw->app_resident_code_offset; + const u64 data = base + lsfw->app_resident_data_offset; + const struct flcn_bl_dmem_desc_v1 hdr = { + .ctx_dma = FALCON_DMAIDX_UCODE, + .code_dma_base = code, + .non_sec_code_off = lsfw->app_resident_code_offset, + .non_sec_code_size = lsfw->app_resident_code_size, + .code_entry_point = lsfw->app_imem_entry, + .data_dma_base = data, + .data_size = lsfw->app_resident_data_size, + }; + + nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); +} + +const struct nvkm_acr_lsf_func +gm200_gr_gpccs_acr = { + .flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD, + .bld_size = sizeof(struct flcn_bl_dmem_desc_v1), + .bld_write = gm200_gr_acr_bld_write, + .bld_patch = gm200_gr_acr_bld_patch, +}; + +const struct nvkm_acr_lsf_func +gm200_gr_fecs_acr = { + .bld_size = sizeof(struct flcn_bl_dmem_desc_v1), + .bld_write = gm200_gr_acr_bld_write, + .bld_patch = gm200_gr_acr_bld_patch, +}; + int gm200_gr_rops(struct gf100_gr *gr) { @@ -124,44 +181,6 @@ gm200_gr_oneinit_tiles(struct gf100_gr *gr) } } -int -gm200_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device, - int index, struct nvkm_gr **pgr) -{ - struct gf100_gr *gr; - int ret; - - if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) - return -ENOMEM; - *pgr = &gr->base; - - ret = gf100_gr_ctor(func, device, index, gr); - if (ret) - return ret; - - /* Load firmwares for non-secure falcons */ - if (!nvkm_secboot_is_managed(device->secboot, - NVKM_SECBOOT_FALCON_FECS)) { - if ((ret = gf100_gr_ctor_fw(gr, "gr/fecs_inst", &gr->fuc409c)) || - (ret = gf100_gr_ctor_fw(gr, "gr/fecs_data", &gr->fuc409d))) - return ret; - } - if (!nvkm_secboot_is_managed(device->secboot, - NVKM_SECBOOT_FALCON_GPCCS)) { - if ((ret = gf100_gr_ctor_fw(gr, "gr/gpccs_inst", &gr->fuc41ac)) || - (ret = gf100_gr_ctor_fw(gr, "gr/gpccs_data", &gr->fuc41ad))) - return ret; - } - - if ((ret = gk20a_gr_av_to_init(gr, "gr/sw_nonctx", &gr->fuc_sw_nonctx)) || - (ret = gk20a_gr_aiv_to_init(gr, "gr/sw_ctx", &gr->fuc_sw_ctx)) || - (ret = gk20a_gr_av_to_init(gr, "gr/sw_bundle_init", &gr->fuc_bundle)) || - (ret = gk20a_gr_av_to_method(gr, "gr/sw_method_init", &gr->fuc_method))) - return ret; - - return 0; -} - static const struct gf100_gr_func gm200_gr = { .oneinit_tiles = gm200_gr_oneinit_tiles, @@ -198,7 +217,78 @@ gm200_gr = { }; int -gm200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gm200_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) +{ + int ret; + + ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev, + &gr->fecs.falcon, + NVKM_ACR_LSF_FECS, + "gr/fecs_", ver, fwif->fecs); + if (ret) + return ret; + + ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev, + &gr->gpccs.falcon, + NVKM_ACR_LSF_GPCCS, + "gr/gpccs_", ver, + fwif->gpccs); + if (ret) + return ret; + + gr->firmware = true; + + return gk20a_gr_load_sw(gr, "gr/", ver); +} + +MODULE_FIRMWARE("nvidia/gm200/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/gm200/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gm200/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gm200/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/gm200/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gm200/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/gm200/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gm200/gr/sw_method_init.bin"); + +MODULE_FIRMWARE("nvidia/gm204/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/gm204/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gm204/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gm204/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/gm204/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gm204/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/gm204/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gm204/gr/sw_method_init.bin"); + +MODULE_FIRMWARE("nvidia/gm206/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/gm206/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gm206/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gm206/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/gm206/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gm206/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/gm206/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gm206/gr/sw_method_init.bin"); + +static const struct gf100_gr_fwif +gm200_gr_fwif[] = { + { 0, gm200_gr_load, &gm200_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, + {} +}; + +int +gm200_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gm200_gr_new_(&gm200_gr, device, index, pgr); + return gf100_gr_new_(gm200_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c index a667770ce3cb..ec1c46e47e00 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c @@ -22,10 +22,61 @@ #include "gf100.h" #include "ctxgf100.h" +#include <core/firmware.h> +#include <subdev/acr.h> #include <subdev/timer.h> +#include <nvfw/flcn.h> + #include <nvif/class.h> +void +gm20b_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) +{ + struct flcn_bl_dmem_desc hdr; + u64 addr; + + nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); + addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8); + hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); + hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); + addr = ((u64)hdr.data_dma_base1 << 40 | hdr.data_dma_base << 8); + hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); + hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); + nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); + + flcn_bl_dmem_desc_dump(&acr->subdev, &hdr); +} + +void +gm20b_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, + struct nvkm_acr_lsfw *lsfw) +{ + const u64 base = lsfw->offset.img + lsfw->app_start_offset; + const u64 code = (base + lsfw->app_resident_code_offset) >> 8; + const u64 data = (base + lsfw->app_resident_data_offset) >> 8; + const struct flcn_bl_dmem_desc hdr = { + .ctx_dma = FALCON_DMAIDX_UCODE, + .code_dma_base = lower_32_bits(code), + .non_sec_code_off = lsfw->app_resident_code_offset, + .non_sec_code_size = lsfw->app_resident_code_size, + .code_entry_point = lsfw->app_imem_entry, + .data_dma_base = lower_32_bits(data), + .data_size = lsfw->app_resident_data_size, + .code_dma_base1 = upper_32_bits(code), + .data_dma_base1 = upper_32_bits(data), + }; + + nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); +} + +const struct nvkm_acr_lsf_func +gm20b_gr_fecs_acr = { + .bld_size = sizeof(struct flcn_bl_dmem_desc), + .bld_write = gm20b_gr_acr_bld_write, + .bld_patch = gm20b_gr_acr_bld_patch, +}; + static void gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) { @@ -33,7 +84,7 @@ gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) u32 val; /* Bypass MMU check for non-secure boot */ - if (!device->secboot) { + if (!device->acr) { nvkm_wr32(device, 0x100ce4, 0xffffffff); if (nvkm_rd32(device, 0x100ce4) != 0xffffffff) @@ -85,8 +136,52 @@ gm20b_gr = { } }; +static int +gm20b_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) +{ + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + int ret; + + ret = nvkm_acr_lsfw_load_bl_inst_data_sig(subdev, &gr->fecs.falcon, + NVKM_ACR_LSF_FECS, + "gr/fecs_", ver, fwif->fecs); + if (ret) + return ret; + + + if (nvkm_firmware_load_blob(subdev, "gr/", "gpccs_inst", ver, + &gr->gpccs.inst) || + nvkm_firmware_load_blob(subdev, "gr/", "gpccs_data", ver, + &gr->gpccs.data)) + return -ENOENT; + + gr->firmware = true; + + return gk20a_gr_load_sw(gr, "gr/", ver); +} + +#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) +MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gm20b/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gm20b/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/gm20b/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gm20b/gr/sw_method_init.bin"); +#endif + +static const struct gf100_gr_fwif +gm20b_gr_fwif[] = { + { 0, gm20b_gr_load, &gm20b_gr, &gm20b_gr_fecs_acr }, + { -1, gm200_gr_nofw }, + {} +}; + int -gm20b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gm20b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gm200_gr_new_(&gm20b_gr, device, index, pgr); + return gf100_gr_new_(gm20b_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c index 9d0521ce309a..0550dd6f46f1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c @@ -62,7 +62,7 @@ gp100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) gr->zbc_depth[zbc].format << ((znum % 4) * 7)); } -static const struct gf100_gr_func_zbc +const struct gf100_gr_func_zbc gp100_gr_zbc = { .clear_color = gp100_gr_zbc_clear_color, .clear_depth = gp100_gr_zbc_clear_depth, @@ -135,8 +135,28 @@ gp100_gr = { } }; +MODULE_FIRMWARE("nvidia/gp100/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp100/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp100/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gp100/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp100/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gp100/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/gp100/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gp100/gr/sw_method_init.bin"); + +static const struct gf100_gr_fwif +gp100_gr_fwif[] = { + { 0, gm200_gr_load, &gp100_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, + {} +}; + int -gp100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gp100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gm200_gr_new_(&gp100_gr, device, index, pgr); + return gf100_gr_new_(gp100_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c index 37f7d739bf80..5b001f374be0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c @@ -131,8 +131,28 @@ gp102_gr = { } }; +MODULE_FIRMWARE("nvidia/gp102/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp102/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp102/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gp102/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp102/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gp102/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/gp102/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gp102/gr/sw_method_init.bin"); + +static const struct gf100_gr_fwif +gp102_gr_fwif[] = { + { 0, gm200_gr_load, &gp102_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, + {} +}; + int -gp102_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gp102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gm200_gr_new_(&gp102_gr, device, index, pgr); + return gf100_gr_new_(gp102_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c index 4573c914c021..2655574ec63b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c @@ -59,8 +59,41 @@ gp104_gr = { } }; +MODULE_FIRMWARE("nvidia/gp104/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp104/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp104/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gp104/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp104/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gp104/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/gp104/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gp104/gr/sw_method_init.bin"); + +MODULE_FIRMWARE("nvidia/gp106/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp106/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp106/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gp106/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp106/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gp106/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/gp106/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gp106/gr/sw_method_init.bin"); + +static const struct gf100_gr_fwif +gp104_gr_fwif[] = { + { 0, gm200_gr_load, &gp104_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, + {} +}; + int -gp104_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gp104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gm200_gr_new_(&gp104_gr, device, index, pgr); + return gf100_gr_new_(gp104_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c index 812aba91653f..adabc04d4f3a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c @@ -26,7 +26,7 @@ #include <nvif/class.h> -static const struct gf100_gr_func +const struct gf100_gr_func gp107_gr = { .oneinit_tiles = gm200_gr_oneinit_tiles, .oneinit_sm_id = gm200_gr_oneinit_sm_id, @@ -61,8 +61,28 @@ gp107_gr = { } }; +MODULE_FIRMWARE("nvidia/gp107/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp107/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp107/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gp107/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp107/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gp107/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/gp107/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gp107/gr/sw_method_init.bin"); + +static const struct gf100_gr_fwif +gp107_gr_fwif[] = { + { 0, gm200_gr_load, &gp107_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, + {} +}; + int -gp107_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gp107_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gm200_gr_new_(&gp107_gr, device, index, pgr); + return gf100_gr_new_(gp107_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c new file mode 100644 index 000000000000..7310f0466bb7 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c @@ -0,0 +1,98 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "gf100.h" + +#include <subdev/acr.h> + +#include <nvfw/flcn.h> + +static void +gp108_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) +{ + struct flcn_bl_dmem_desc_v2 hdr; + nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); + hdr.code_dma_base = hdr.code_dma_base + adjust; + hdr.data_dma_base = hdr.data_dma_base + adjust; + nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); + flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr); +} + +static void +gp108_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, + struct nvkm_acr_lsfw *lsfw) +{ + const u64 base = lsfw->offset.img + lsfw->app_start_offset; + const u64 code = base + lsfw->app_resident_code_offset; + const u64 data = base + lsfw->app_resident_data_offset; + const struct flcn_bl_dmem_desc_v2 hdr = { + .ctx_dma = FALCON_DMAIDX_UCODE, + .code_dma_base = code, + .non_sec_code_off = lsfw->app_resident_code_offset, + .non_sec_code_size = lsfw->app_resident_code_size, + .code_entry_point = lsfw->app_imem_entry, + .data_dma_base = data, + .data_size = lsfw->app_resident_data_size, + }; + + nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); +} + +const struct nvkm_acr_lsf_func +gp108_gr_gpccs_acr = { + .flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD, + .bld_size = sizeof(struct flcn_bl_dmem_desc_v2), + .bld_write = gp108_gr_acr_bld_write, + .bld_patch = gp108_gr_acr_bld_patch, +}; + +const struct nvkm_acr_lsf_func +gp108_gr_fecs_acr = { + .bld_size = sizeof(struct flcn_bl_dmem_desc_v2), + .bld_write = gp108_gr_acr_bld_write, + .bld_patch = gp108_gr_acr_bld_patch, +}; + +MODULE_FIRMWARE("nvidia/gp108/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp108/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp108/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gp108/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp108/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gp108/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/gp108/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gp108/gr/sw_method_init.bin"); + +static const struct gf100_gr_fwif +gp108_gr_fwif[] = { + { 0, gm200_gr_load, &gp107_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, + {} +}; + +int +gp108_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(gp108_gr_fwif, device, type, inst, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c index 303dceddd4a8..e13683b6e7b1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c @@ -23,8 +23,20 @@ #include "gf100.h" #include "ctxgf100.h" +#include <subdev/acr.h> + #include <nvif/class.h> +#include <nvfw/flcn.h> + +static const struct nvkm_acr_lsf_func +gp10b_gr_gpccs_acr = { + .flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD, + .bld_size = sizeof(struct flcn_bl_dmem_desc), + .bld_write = gm20b_gr_acr_bld_write, + .bld_patch = gm20b_gr_acr_bld_patch, +}; + static const struct gf100_gr_func gp10b_gr = { .oneinit_tiles = gm200_gr_oneinit_tiles, @@ -48,8 +60,8 @@ gp10b_gr = { .gpc_nr = 1, .tpc_nr = 2, .ppc_nr = 1, - .grctx = &gp102_grctx, - .zbc = &gp102_gr_zbc, + .grctx = &gp100_grctx, + .zbc = &gp100_gr_zbc, .sclass = { { -1, -1, FERMI_TWOD_A }, { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, @@ -59,8 +71,30 @@ gp10b_gr = { } }; +#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) +MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/gp10b/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gp10b/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/gp10b/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gp10b/gr/sw_method_init.bin"); +#endif + +static const struct gf100_gr_fwif +gp10b_gr_fwif[] = { + { 0, gm200_gr_load, &gp10b_gr, &gm20b_gr_fecs_acr, &gp10b_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, + {} +}; + int -gp10b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gp10b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gm200_gr_new_(&gp10b_gr, device, index, pgr); + return gf100_gr_new_(gp10b_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c index c711a55ce392..1dfc65d45b52 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c @@ -43,7 +43,7 @@ gt200_gr = { }; int -gt200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gt200_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv50_gr_new_(>200_gr, device, index, pgr); + return nv50_gr_new_(>200_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c index fa103df32ec7..fcb5ead345a3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c @@ -44,7 +44,7 @@ gt215_gr = { }; int -gt215_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gt215_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv50_gr_new_(>215_gr, device, index, pgr); + return nv50_gr_new_(>215_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c index 3b3327789ae7..4d043c1173ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c @@ -45,7 +45,7 @@ gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm) nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr); } -static void +void gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) { gv100_gr_trap_sm(gr, gpc, tpc, 0); @@ -59,7 +59,7 @@ gv100_gr_init_4188a4(struct gf100_gr *gr) nvkm_mask(device, 0x4188a4, 0x03000000, 0x03000000); } -static void +void gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) { struct nvkm_device *device = gr->base.engine.subdev.device; @@ -71,14 +71,14 @@ gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) } } -static void +void gv100_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) { struct nvkm_device *device = gr->base.engine.subdev.device; nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0x403f0000); } -static void +void gv100_gr_init_419bd8(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; @@ -120,8 +120,28 @@ gv100_gr = { } }; +MODULE_FIRMWARE("nvidia/gv100/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/gv100/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gv100/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gv100/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/gv100/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gv100/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/gv100/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gv100/gr/sw_method_init.bin"); + +static const struct gf100_gr_fwif +gv100_gr_fwif[] = { + { 0, gm200_gr_load, &gv100_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, + {} +}; + int -gv100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gv100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gm200_gr_new_(&gv100_gr, device, index, pgr); + return gf100_gr_new_(gv100_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c index eb1a90644752..cf782b64f62e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c @@ -42,7 +42,7 @@ mcp79_gr = { }; int -mcp79_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +mcp79_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv50_gr_new_(&mcp79_gr, device, index, pgr); + return nv50_gr_new_(&mcp79_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c index c91eb56e9327..6f90a6395453 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c @@ -44,7 +44,7 @@ mcp89_gr = { }; int -mcp89_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +mcp89_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv50_gr_new_(&mcp89_gr, device, index, pgr); + return nv50_gr_new_(&mcp89_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index 9c2e985dc079..0bc1a238de43 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -1413,7 +1413,7 @@ nv04_gr = { }; int -nv04_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv04_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { struct nv04_gr *gr; @@ -1422,5 +1422,5 @@ nv04_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) spin_lock_init(&gr->lock); *pgr = &gr->base; - return nvkm_gr_ctor(&nv04_gr, device, index, true, &gr->base); + return nvkm_gr_ctor(&nv04_gr, device, type, inst, true, &gr->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 4ebbfbdd8240..942450b33bc6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -1173,7 +1173,7 @@ nv10_gr_init(struct nvkm_gr *base) int nv10_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, - int index, struct nvkm_gr **pgr) + enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { struct nv10_gr *gr; @@ -1182,7 +1182,7 @@ nv10_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, spin_lock_init(&gr->lock); *pgr = &gr->base; - return nvkm_gr_ctor(func, device, index, true, &gr->base); + return nvkm_gr_ctor(func, device, type, inst, true, &gr->base); } static const struct nvkm_gr_func @@ -1215,7 +1215,7 @@ nv10_gr = { }; int -nv10_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv10_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv10_gr_new_(&nv10_gr, device, index, pgr); + return nv10_gr_new_(&nv10_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h index 4327baea02af..5cfe927c9123 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h @@ -3,7 +3,7 @@ #define __NV10_GR_H__ #include "priv.h" -int nv10_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index, +int nv10_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gr **); int nv10_gr_init(struct nvkm_gr *); void nv10_gr_intr(struct nvkm_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c index 3e2c6856b4c4..69ece259df86 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c @@ -53,7 +53,7 @@ nv15_gr = { }; int -nv15_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv15_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv10_gr_new_(&nv15_gr, device, index, pgr); + return nv10_gr_new_(&nv15_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c index 12437d085a73..e39dfc7d4077 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c @@ -53,7 +53,7 @@ nv17_gr = { }; int -nv17_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv17_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv10_gr_new_(&nv17_gr, device, index, pgr); + return nv10_gr_new_(&nv17_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index d837630a3625..6bff10cee71b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -330,7 +330,7 @@ nv20_gr_dtor(struct nvkm_gr *base) int nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, - int index, struct nvkm_gr **pgr) + enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { struct nv20_gr *gr; @@ -338,7 +338,7 @@ nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, return -ENOMEM; *pgr = &gr->base; - return nvkm_gr_ctor(func, device, index, true, &gr->base); + return nvkm_gr_ctor(func, device, type, inst, true, &gr->base); } static const struct nvkm_gr_func @@ -370,7 +370,7 @@ nv20_gr = { }; int -nv20_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv20_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv20_gr_new_(&nv20_gr, device, index, pgr); + return nv20_gr_new_(&nv20_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h index e57407a8a7c3..c0d2be53413e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h @@ -9,8 +9,8 @@ struct nv20_gr { struct nvkm_memory *ctxtab; }; -int nv20_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, - int, struct nvkm_gr **); +int nv20_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_gr **); void *nv20_gr_dtor(struct nvkm_gr *); int nv20_gr_oneinit(struct nvkm_gr *); int nv20_gr_init(struct nvkm_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c index 32d29d3faee0..f3a56f17d94a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c @@ -129,7 +129,7 @@ nv25_gr = { }; int -nv25_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv25_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv20_gr_new_(&nv25_gr, device, index, pgr); + return nv20_gr_new_(&nv25_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c index f941062c66f0..f268d2642d29 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c @@ -120,7 +120,7 @@ nv2a_gr = { }; int -nv2a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv2a_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv20_gr_new_(&nv2a_gr, device, index, pgr); + return nv20_gr_new_(&nv2a_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index 785ec956df0f..e5737cdf2fa1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -194,7 +194,7 @@ nv30_gr = { }; int -nv30_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv30_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv20_gr_new_(&nv30_gr, device, index, pgr); + return nv20_gr_new_(&nv30_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c index bd610d75c677..1ab2da8ebf4e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c @@ -131,7 +131,7 @@ nv34_gr = { }; int -nv34_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv34_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv20_gr_new_(&nv34_gr, device, index, pgr); + return nv20_gr_new_(&nv34_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c index 89db7f523037..591260f5676b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c @@ -131,7 +131,7 @@ nv35_gr = { }; int -nv35_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv35_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv20_gr_new_(&nv35_gr, device, index, pgr); + return nv20_gr_new_(&nv35_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 5f1ad8344ea9..67f3535ff97e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -429,7 +429,7 @@ nv40_gr_init(struct nvkm_gr *base) int nv40_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, - int index, struct nvkm_gr **pgr) + enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { struct nv40_gr *gr; @@ -438,7 +438,7 @@ nv40_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, *pgr = &gr->base; INIT_LIST_HEAD(&gr->chan); - return nvkm_gr_ctor(func, device, index, true, &gr->base); + return nvkm_gr_ctor(func, device, type, inst, true, &gr->base); } static const struct nvkm_gr_func @@ -470,7 +470,7 @@ nv40_gr = { }; int -nv40_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv40_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv40_gr_new_(&nv40_gr, device, index, pgr); + return nv40_gr_new_(&nv40_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h index e6128791b2d2..f3d3d3a5ae5b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h @@ -10,7 +10,7 @@ struct nv40_gr { struct list_head chan; }; -int nv40_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index, +int nv40_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gr **); int nv40_gr_init(struct nvkm_gr *); void nv40_gr_intr(struct nvkm_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c index 45ff80254eb4..22b6a38a7031 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c @@ -102,7 +102,7 @@ nv44_gr = { }; int -nv44_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv44_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv40_gr_new_(&nv44_gr, device, index, pgr); + return nv40_gr_new_(&nv44_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index df16ffda1749..563a10097e95 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -761,7 +761,7 @@ nv50_gr_init(struct nvkm_gr *base) int nv50_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, - int index, struct nvkm_gr **pgr) + enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { struct nv50_gr *gr; @@ -770,7 +770,7 @@ nv50_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, spin_lock_init(&gr->lock); *pgr = &gr->base; - return nvkm_gr_ctor(func, device, index, true, &gr->base); + return nvkm_gr_ctor(func, device, type, inst, true, &gr->base); } static const struct nvkm_gr_func @@ -790,7 +790,7 @@ nv50_gr = { }; int -nv50_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv50_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv50_gr_new_(&nv50_gr, device, index, pgr); + return nv50_gr_new_(&nv50_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h index 465f4da0ddfc..84388c42e5c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h @@ -11,7 +11,7 @@ struct nv50_gr { u32 size; }; -int nv50_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index, +int nv50_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gr **); int nv50_gr_init(struct nvkm_gr *); void nv50_gr_intr(struct nvkm_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h index 3b30f24032cc..9b2c66e8be90 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h @@ -7,8 +7,8 @@ struct nvkm_fb_tile; struct nvkm_fifo_chan; -int nvkm_gr_ctor(const struct nvkm_gr_func *, struct nvkm_device *, - int index, bool enable, struct nvkm_gr *); +int nvkm_gr_ctor(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + bool enable, struct nvkm_gr *); bool nv04_gr_idle(struct nvkm_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c new file mode 100644 index 000000000000..1a8a21844e12 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c @@ -0,0 +1,204 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "gf100.h" +#include "ctxgf100.h" + +#include <nvif/class.h> + +static void +tu102_gr_init_fecs_exceptions(struct gf100_gr *gr) +{ + nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006f0002); +} + +static void +tu102_gr_init_fs(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + int sm; + + gp100_grctx_generate_smid_config(gr); + gk104_grctx_generate_gpc_tpc_nr(gr); + + for (sm = 0; sm < gr->sm_nr; sm++) { + nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + + gr->sm[sm].tpc * 4), sm); + } + + gm200_grctx_generate_dist_skip_table(gr); + gf100_gr_init_num_tpc_per_gpc(gr, true, true); +} + +static void +tu102_gr_init_zcull(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); + const u8 tile_nr = ALIGN(gr->tpc_total, 64); + u8 bank[GPC_MAX] = {}, gpc, i, j; + u32 data; + + for (i = 0; i < tile_nr; i += 8) { + for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { + data |= bank[gr->tile[i + j]] << (j * 4); + bank[gr->tile[i + j]]++; + } + nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data); + } + + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), + gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | + gr->tpc_total); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); + } + + nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); +} + +static void +tu102_gr_init_gpc_mmu(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + + nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff); + nvkm_wr32(device, 0x418890, 0x00000000); + nvkm_wr32(device, 0x418894, 0x00000000); + + nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); + nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); + nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); +} + +static const struct gf100_gr_func +tu102_gr = { + .oneinit_tiles = gm200_gr_oneinit_tiles, + .oneinit_sm_id = gm200_gr_oneinit_sm_id, + .init = gf100_gr_init, + .init_419bd8 = gv100_gr_init_419bd8, + .init_gpc_mmu = tu102_gr_init_gpc_mmu, + .init_vsc_stream_master = gk104_gr_init_vsc_stream_master, + .init_zcull = tu102_gr_init_zcull, + .init_num_active_ltcs = gf100_gr_init_num_active_ltcs, + .init_rop_active_fbps = gp100_gr_init_rop_active_fbps, + .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask, + .init_fs = tu102_gr_init_fs, + .init_fecs_exceptions = tu102_gr_init_fecs_exceptions, + .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2, + .init_sked_hww_esr = gk104_gr_init_sked_hww_esr, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, + .init_504430 = gv100_gr_init_504430, + .init_shader_exceptions = gv100_gr_init_shader_exceptions, + .trap_mp = gv100_gr_trap_mp, + .rops = gm200_gr_rops, + .gpc_nr = 6, + .tpc_nr = 5, + .ppc_nr = 3, + .grctx = &tu102_grctx, + .zbc = &gp102_gr_zbc, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, + { -1, -1, TURING_A, &gf100_fermi }, + { -1, -1, TURING_COMPUTE_A }, + {} + } +}; + +MODULE_FIRMWARE("nvidia/tu102/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/tu102/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/tu102/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/tu102/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/tu102/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/tu102/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/tu102/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/tu102/gr/sw_method_init.bin"); + +MODULE_FIRMWARE("nvidia/tu104/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/tu104/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/tu104/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/tu104/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/tu104/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/tu104/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/tu104/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/tu104/gr/sw_method_init.bin"); + +MODULE_FIRMWARE("nvidia/tu106/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/tu106/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/tu106/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/tu106/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/tu106/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/tu106/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/tu106/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/tu106/gr/sw_method_init.bin"); + +MODULE_FIRMWARE("nvidia/tu117/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/tu117/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/tu117/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/tu117/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/tu117/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/tu117/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/tu117/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/tu117/gr/sw_method_init.bin"); + +MODULE_FIRMWARE("nvidia/tu116/gr/fecs_bl.bin"); +MODULE_FIRMWARE("nvidia/tu116/gr/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/tu116/gr/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/tu116/gr/fecs_sig.bin"); +MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_bl.bin"); +MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_sig.bin"); +MODULE_FIRMWARE("nvidia/tu116/gr/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/tu116/gr/sw_nonctx.bin"); +MODULE_FIRMWARE("nvidia/tu116/gr/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/tu116/gr/sw_method_init.bin"); + +static const struct gf100_gr_fwif +tu102_gr_fwif[] = { + { 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, + {} +}; + +int +tu102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(tu102_gr_fwif, device, type, inst, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c index c0e11a071843..0fcc0ffa1e40 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c @@ -37,7 +37,8 @@ g84_mpeg = { }; int -g84_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) +g84_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pmpeg) { - return nvkm_engine_new_(&g84_mpeg, device, index, true, pmpeg); + return nvkm_engine_new_(&g84_mpeg, device, type, inst, true, pmpeg); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c index 7fea7d45202f..b1054db4c1b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c @@ -274,7 +274,7 @@ nv31_mpeg_ = { int nv31_mpeg_new_(const struct nv31_mpeg_func *func, struct nvkm_device *device, - int index, struct nvkm_engine **pmpeg) + enum nvkm_subdev_type type, int inst, struct nvkm_engine **pmpeg) { struct nv31_mpeg *mpeg; @@ -283,8 +283,7 @@ nv31_mpeg_new_(const struct nv31_mpeg_func *func, struct nvkm_device *device, mpeg->func = func; *pmpeg = &mpeg->engine; - return nvkm_engine_ctor(&nv31_mpeg_, device, index, - true, &mpeg->engine); + return nvkm_engine_ctor(&nv31_mpeg_, device, type, inst, true, &mpeg->engine); } static const struct nv31_mpeg_func @@ -293,7 +292,8 @@ nv31_mpeg = { }; int -nv31_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) +nv31_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pmpeg) { - return nv31_mpeg_new_(&nv31_mpeg, device, index, pmpeg); + return nv31_mpeg_new_(&nv31_mpeg, device, type, inst, pmpeg); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h index b3e131538858..9f30aaaf809e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h @@ -11,8 +11,8 @@ struct nv31_mpeg { struct nv31_mpeg_chan *chan; }; -int nv31_mpeg_new_(const struct nv31_mpeg_func *, struct nvkm_device *, - int index, struct nvkm_engine **); +int nv31_mpeg_new_(const struct nv31_mpeg_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_engine **); struct nv31_mpeg_func { bool (*mthd_dma)(struct nvkm_device *, u32 mthd, u32 data); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c index b5ec7c504dc6..179167484ef1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c @@ -76,7 +76,8 @@ nv40_mpeg = { }; int -nv40_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) +nv40_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pmpeg) { - return nv31_mpeg_new_(&nv40_mpeg, device, index, pmpeg); + return nv31_mpeg_new_(&nv40_mpeg, device, type, inst, pmpeg); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c index c3cf02ed468e..521ce43a2871 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c @@ -203,7 +203,8 @@ nv44_mpeg = { }; int -nv44_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) +nv44_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pmpeg) { struct nv44_mpeg *mpeg; @@ -212,5 +213,5 @@ nv44_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) INIT_LIST_HEAD(&mpeg->chan); *pmpeg = &mpeg->engine; - return nvkm_engine_ctor(&nv44_mpeg, device, index, true, &mpeg->engine); + return nvkm_engine_ctor(&nv44_mpeg, device, type, inst, true, &mpeg->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c index 6df880a39019..e6374f36961c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c @@ -129,7 +129,8 @@ nv50_mpeg = { }; int -nv50_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) +nv50_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pmpeg) { - return nvkm_engine_new_(&nv50_mpeg, device, index, true, pmpeg); + return nvkm_engine_new_(&nv50_mpeg, device, type, inst, true, pmpeg); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c index 80211f76093b..842fcfbd28b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c @@ -24,9 +24,8 @@ #include "priv.h" int -nvkm_mspdec_new_(const struct nvkm_falcon_func *func, - struct nvkm_device *device, int index, - struct nvkm_engine **pengine) +nvkm_mspdec_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_falcon_new_(func, device, index, true, 0x085000, pengine); + return nvkm_falcon_new_(func, device, type, inst, true, 0x085000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c index f30cf1dcfb30..ecb06d68f544 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c @@ -43,8 +43,8 @@ g98_mspdec = { }; int -g98_mspdec_new(struct nvkm_device *device, int index, - struct nvkm_engine **pengine) +g98_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_mspdec_new_(&g98_mspdec, device, index, pengine); + return nvkm_mspdec_new_(&g98_mspdec, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c index cfe1aa81bd14..0a69bd767d69 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c @@ -43,8 +43,8 @@ gf100_mspdec = { }; int -gf100_mspdec_new(struct nvkm_device *device, int index, +gf100_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_mspdec_new_(&gf100_mspdec, device, index, pengine); + return nvkm_mspdec_new_(&gf100_mspdec, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c index 24272b4927bc..a08991dca428 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c @@ -35,8 +35,8 @@ gk104_mspdec = { }; int -gk104_mspdec_new(struct nvkm_device *device, int index, +gk104_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_mspdec_new_(&gk104_mspdec, device, index, pengine); + return nvkm_mspdec_new_(&gk104_mspdec, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c index cf6e59ad6ee2..791fb03a32ad 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c @@ -35,8 +35,8 @@ gt215_mspdec = { }; int -gt215_mspdec_new(struct nvkm_device *device, int index, - struct nvkm_engine **pengine) +gt215_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_mspdec_new_(>215_mspdec, device, index, pengine); + return nvkm_mspdec_new_(>215_mspdec, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h index 86445a2600d0..2bc5537d40a3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h @@ -3,8 +3,8 @@ #define __NVKM_MSPDEC_PRIV_H__ #include <engine/mspdec.h> -int nvkm_mspdec_new_(const struct nvkm_falcon_func *, struct nvkm_device *, - int index, struct nvkm_engine **); +int nvkm_mspdec_new_(const struct nvkm_falcon_func *, struct nvkm_device *, enum nvkm_subdev_type, + int, struct nvkm_engine **); void g98_mspdec_init(struct nvkm_falcon *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c index bfae5e60e925..45a9411ab2e2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c @@ -25,7 +25,7 @@ int nvkm_msppp_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device, - int index, struct nvkm_engine **pengine) + enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_falcon_new_(func, device, index, true, 0x086000, pengine); + return nvkm_falcon_new_(func, device, type, inst, true, 0x086000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c index c45dbf79d1f9..160120b9bd64 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c @@ -43,8 +43,8 @@ g98_msppp = { }; int -g98_msppp_new(struct nvkm_device *device, int index, +g98_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_msppp_new_(&g98_msppp, device, index, pengine); + return nvkm_msppp_new_(&g98_msppp, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c index 803c62ab516e..debed9ae8731 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c @@ -43,8 +43,8 @@ gf100_msppp = { }; int -gf100_msppp_new(struct nvkm_device *device, int index, +gf100_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_msppp_new_(&gf100_msppp, device, index, pengine); + return nvkm_msppp_new_(&gf100_msppp, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c index 49cbf72cee4b..a2fd736fef94 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c @@ -35,8 +35,8 @@ gt215_msppp = { }; int -gt215_msppp_new(struct nvkm_device *device, int index, - struct nvkm_engine **pengine) +gt215_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_msppp_new_(>215_msppp, device, index, pengine); + return nvkm_msppp_new_(>215_msppp, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h index f20b10915db2..582ab8ce1425 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h @@ -3,8 +3,8 @@ #define __NVKM_MSPPP_PRIV_H__ #include <engine/msppp.h> -int nvkm_msppp_new_(const struct nvkm_falcon_func *, struct nvkm_device *, - int index, struct nvkm_engine **); +int nvkm_msppp_new_(const struct nvkm_falcon_func *, struct nvkm_device *, enum nvkm_subdev_type, + int, struct nvkm_engine **); void g98_msppp_init(struct nvkm_falcon *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c index 745bbb653dc0..7be42b980e57 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c @@ -25,7 +25,7 @@ int nvkm_msvld_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device, - int index, struct nvkm_engine **pengine) + enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_falcon_new_(func, device, index, true, 0x084000, pengine); + return nvkm_falcon_new_(func, device, type, inst, true, 0x084000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c index 4a2a9f0494af..cfa2065319a6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c @@ -43,8 +43,8 @@ g98_msvld = { }; int -g98_msvld_new(struct nvkm_device *device, int index, +g98_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_msvld_new_(&g98_msvld, device, index, pengine); + return nvkm_msvld_new_(&g98_msvld, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c index 1695e532c081..8d58ad8e04d3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c @@ -43,8 +43,8 @@ gf100_msvld = { }; int -gf100_msvld_new(struct nvkm_device *device, int index, +gf100_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_msvld_new_(&gf100_msvld, device, index, pengine); + return nvkm_msvld_new_(&gf100_msvld, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c index b640cd63ebe8..b28be28046f1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c @@ -35,8 +35,8 @@ gk104_msvld = { }; int -gk104_msvld_new(struct nvkm_device *device, int index, +gk104_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_msvld_new_(&gk104_msvld, device, index, pengine); + return nvkm_msvld_new_(&gk104_msvld, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c index 201e8ef3519e..d7489f972c99 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c @@ -35,8 +35,8 @@ gt215_msvld = { }; int -gt215_msvld_new(struct nvkm_device *device, int index, - struct nvkm_engine **pengine) +gt215_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_msvld_new_(>215_msvld, device, index, pengine); + return nvkm_msvld_new_(>215_msvld, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c index a0f540ef257b..16c30b62ab09 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c @@ -35,8 +35,8 @@ mcp89_msvld = { }; int -mcp89_msvld_new(struct nvkm_device *device, int index, - struct nvkm_engine **pengine) +mcp89_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_msvld_new_(&mcp89_msvld, device, index, pengine); + return nvkm_msvld_new_(&mcp89_msvld, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h index 5cd1e83badbb..f729d919b054 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h @@ -3,8 +3,8 @@ #define __NVKM_MSVLD_PRIV_H__ #include <engine/msvld.h> -int nvkm_msvld_new_(const struct nvkm_falcon_func *, struct nvkm_device *, - int index, struct nvkm_engine **); +int nvkm_msvld_new_(const struct nvkm_falcon_func *, struct nvkm_device *, enum nvkm_subdev_type, + int, struct nvkm_engine **); void g98_msvld_init(struct nvkm_falcon *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/Kbuild index cdf631822282..9a0fd9812750 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/Kbuild @@ -1,3 +1,3 @@ # SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/nvdec/base.o -nvkm-y += nvkm/engine/nvdec/gp102.o +nvkm-y += nvkm/engine/nvdec/gm107.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c index 4a63581bdd5e..b0181cc5953b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c @@ -20,48 +20,42 @@ * DEALINGS IN THE SOFTWARE. */ #include "priv.h" - -#include <subdev/top.h> -#include <engine/falcon.h> - -static int -nvkm_nvdec_oneinit(struct nvkm_engine *engine) -{ - struct nvkm_nvdec *nvdec = nvkm_nvdec(engine); - struct nvkm_subdev *subdev = &nvdec->engine.subdev; - - nvdec->addr = nvkm_top_addr(subdev->device, subdev->index); - if (!nvdec->addr) - return -EINVAL; - - /*XXX: fix naming of this when adding support for multiple-NVDEC */ - return nvkm_falcon_v1_new(subdev, "NVDEC", nvdec->addr, - &nvdec->falcon); -} +#include <core/firmware.h> static void * nvkm_nvdec_dtor(struct nvkm_engine *engine) { struct nvkm_nvdec *nvdec = nvkm_nvdec(engine); - nvkm_falcon_del(&nvdec->falcon); + nvkm_falcon_dtor(&nvdec->falcon); return nvdec; } static const struct nvkm_engine_func nvkm_nvdec = { .dtor = nvkm_nvdec_dtor, - .oneinit = nvkm_nvdec_oneinit, }; int -nvkm_nvdec_new_(struct nvkm_device *device, int index, - struct nvkm_nvdec **pnvdec) +nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_nvdec **pnvdec) { struct nvkm_nvdec *nvdec; + int ret; if (!(nvdec = *pnvdec = kzalloc(sizeof(*nvdec), GFP_KERNEL))) return -ENOMEM; - return nvkm_engine_ctor(&nvkm_nvdec, device, index, true, - &nvdec->engine); + ret = nvkm_engine_ctor(&nvkm_nvdec, device, type, inst, true, + &nvdec->engine); + if (ret) + return ret; + + fwif = nvkm_firmware_load(&nvdec->engine.subdev, fwif, "Nvdec", nvdec); + if (IS_ERR(fwif)) + return -ENODEV; + + nvdec->func = fwif->func; + + return nvkm_falcon_ctor(nvdec->func->flcn, &nvdec->engine.subdev, + nvdec->engine.subdev.name, 0, &nvdec->falcon); }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.c index fde6328c6d71..8c44ce44a6d7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.c @@ -19,12 +19,45 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - #include "priv.h" +static const struct nvkm_falcon_func +gm107_nvdec_flcn = { + .debug = 0xd00, + .fbif = 0x600, + .load_imem = nvkm_falcon_v1_load_imem, + .load_dmem = nvkm_falcon_v1_load_dmem, + .read_dmem = nvkm_falcon_v1_read_dmem, + .bind_context = nvkm_falcon_v1_bind_context, + .wait_for_halt = nvkm_falcon_v1_wait_for_halt, + .clear_interrupt = nvkm_falcon_v1_clear_interrupt, + .set_start_addr = nvkm_falcon_v1_set_start_addr, + .start = nvkm_falcon_v1_start, + .enable = nvkm_falcon_v1_enable, + .disable = nvkm_falcon_v1_disable, +}; + +static const struct nvkm_nvdec_func +gm107_nvdec = { + .flcn = &gm107_nvdec_flcn, +}; + +static int +gm107_nvdec_nofw(struct nvkm_nvdec *nvdec, int ver, + const struct nvkm_nvdec_fwif *fwif) +{ + return 0; +} + +static const struct nvkm_nvdec_fwif +gm107_nvdec_fwif[] = { + { -1, gm107_nvdec_nofw, &gm107_nvdec }, + {} +}; + int -gp102_nvdec_new(struct nvkm_device *device, int index, +gm107_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_nvdec **pnvdec) { - return nvkm_nvdec_new_(device, index, pnvdec); + return nvkm_nvdec_new_(gm107_nvdec_fwif, device, type, inst, pnvdec); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h index 57bfa3aa1835..0920f6a887e2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h @@ -3,5 +3,17 @@ #define __NVKM_NVDEC_PRIV_H__ #include <engine/nvdec.h> -int nvkm_nvdec_new_(struct nvkm_device *, int, struct nvkm_nvdec **); +struct nvkm_nvdec_func { + const struct nvkm_falcon_func *flcn; +}; + +struct nvkm_nvdec_fwif { + int version; + int (*load)(struct nvkm_nvdec *, int ver, + const struct nvkm_nvdec_fwif *); + const struct nvkm_nvdec_func *func; +}; + +int nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif, struct nvkm_device *, + enum nvkm_subdev_type, int, struct nvkm_nvdec **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild index f316de8d45a8..75bf4436bf3f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild @@ -1,2 +1,3 @@ # SPDX-License-Identifier: MIT -#nvkm-y += nvkm/engine/nvenc/base.o +nvkm-y += nvkm/engine/nvenc/base.o +nvkm-y += nvkm/engine/nvenc/gm107.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c new file mode 100644 index 000000000000..cf5dcfda7b25 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c @@ -0,0 +1,62 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +#include <core/firmware.h> + +static void * +nvkm_nvenc_dtor(struct nvkm_engine *engine) +{ + struct nvkm_nvenc *nvenc = nvkm_nvenc(engine); + nvkm_falcon_dtor(&nvenc->falcon); + return nvenc; +} + +static const struct nvkm_engine_func +nvkm_nvenc = { + .dtor = nvkm_nvenc_dtor, +}; + +int +nvkm_nvenc_new_(const struct nvkm_nvenc_fwif *fwif, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_nvenc **pnvenc) +{ + struct nvkm_nvenc *nvenc; + int ret; + + if (!(nvenc = *pnvenc = kzalloc(sizeof(*nvenc), GFP_KERNEL))) + return -ENOMEM; + + ret = nvkm_engine_ctor(&nvkm_nvenc, device, type, inst, true, + &nvenc->engine); + if (ret) + return ret; + + fwif = nvkm_firmware_load(&nvenc->engine.subdev, fwif, "Nvenc", nvenc); + if (IS_ERR(fwif)) + return -ENODEV; + + nvenc->func = fwif->func; + + return nvkm_falcon_ctor(nvenc->func->flcn, &nvenc->engine.subdev, + nvenc->engine.subdev.name, 0, &nvenc->falcon); +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/gm107.c new file mode 100644 index 000000000000..f44d41bf2034 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/gm107.c @@ -0,0 +1,63 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "priv.h" + +static const struct nvkm_falcon_func +gm107_nvenc_flcn = { + .fbif = 0x800, + .load_imem = nvkm_falcon_v1_load_imem, + .load_dmem = nvkm_falcon_v1_load_dmem, + .read_dmem = nvkm_falcon_v1_read_dmem, + .bind_context = nvkm_falcon_v1_bind_context, + .wait_for_halt = nvkm_falcon_v1_wait_for_halt, + .clear_interrupt = nvkm_falcon_v1_clear_interrupt, + .set_start_addr = nvkm_falcon_v1_set_start_addr, + .start = nvkm_falcon_v1_start, + .enable = nvkm_falcon_v1_enable, + .disable = nvkm_falcon_v1_disable, +}; + +static const struct nvkm_nvenc_func +gm107_nvenc = { + .flcn = &gm107_nvenc_flcn, +}; + +static int +gm107_nvenc_nofw(struct nvkm_nvenc *nvenc, int ver, + const struct nvkm_nvenc_fwif *fwif) +{ + return 0; +} + +static const struct nvkm_nvenc_fwif +gm107_nvenc_fwif[] = { + { -1, gm107_nvenc_nofw, &gm107_nvenc }, + {} +}; + +int +gm107_nvenc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_nvenc **pnvenc) +{ + return nvkm_nvenc_new_(gm107_nvenc_fwif, device, type, inst, pnvenc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/priv.h new file mode 100644 index 000000000000..4130a2bfbb4f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/priv.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVKM_NVENC_PRIV_H__ +#define __NVKM_NVENC_PRIV_H__ +#include <engine/nvenc.h> + +struct nvkm_nvenc_func { + const struct nvkm_falcon_func *flcn; +}; + +struct nvkm_nvenc_fwif { + int version; + int (*load)(struct nvkm_nvenc *, int ver, + const struct nvkm_nvenc_fwif *); + const struct nvkm_nvenc_func *func; +}; + +int nvkm_nvenc_new_(const struct nvkm_nvenc_fwif *, struct nvkm_device *, enum nvkm_subdev_type, + int, struct nvkm_nvenc **pnvenc); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c index b2785bee418e..8fe0444f761e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c @@ -628,10 +628,10 @@ nvkm_perfmon_dtor(struct nvkm_object *object) { struct nvkm_perfmon *perfmon = nvkm_perfmon(object); struct nvkm_pm *pm = perfmon->pm; - mutex_lock(&pm->engine.subdev.mutex); - if (pm->perfmon == &perfmon->object) - pm->perfmon = NULL; - mutex_unlock(&pm->engine.subdev.mutex); + spin_lock(&pm->client.lock); + if (pm->client.object == &perfmon->object) + pm->client.object = NULL; + spin_unlock(&pm->client.lock); return perfmon; } @@ -671,11 +671,11 @@ nvkm_pm_oclass_new(struct nvkm_device *device, const struct nvkm_oclass *oclass, if (ret) return ret; - mutex_lock(&pm->engine.subdev.mutex); - if (pm->perfmon == NULL) - pm->perfmon = *pobject; - ret = (pm->perfmon == *pobject) ? 0 : -EBUSY; - mutex_unlock(&pm->engine.subdev.mutex); + spin_lock(&pm->client.lock); + if (pm->client.object == NULL) + pm->client.object = *pobject; + ret = (pm->client.object == *pobject) ? 0 : -EBUSY; + spin_unlock(&pm->client.lock); return ret; } @@ -858,10 +858,11 @@ nvkm_pm = { int nvkm_pm_ctor(const struct nvkm_pm_func *func, struct nvkm_device *device, - int index, struct nvkm_pm *pm) + enum nvkm_subdev_type type, int inst, struct nvkm_pm *pm) { pm->func = func; INIT_LIST_HEAD(&pm->domains); INIT_LIST_HEAD(&pm->sources); - return nvkm_engine_ctor(&nvkm_pm, device, index, true, &pm->engine); + spin_lock_init(&pm->client.lock); + return nvkm_engine_ctor(&nvkm_pm, device, type, inst, true, &pm->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c index 6e441ddafd86..0086d00eb162 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c @@ -159,7 +159,7 @@ g84_pm[] = { }; int -g84_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +g84_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return nv40_pm_new_(g84_pm, device, index, ppm); + return nv40_pm_new_(g84_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c index fe2532ee4145..8e02701def8e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c @@ -187,7 +187,7 @@ gf100_pm_ = { int gf100_pm_new_(const struct gf100_pm_func *func, struct nvkm_device *device, - int index, struct nvkm_pm **ppm) + enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { struct nvkm_pm *pm; u32 mask; @@ -196,7 +196,7 @@ gf100_pm_new_(const struct gf100_pm_func *func, struct nvkm_device *device, if (!(pm = *ppm = kzalloc(sizeof(*pm), GFP_KERNEL))) return -ENOMEM; - ret = nvkm_pm_ctor(&gf100_pm_, device, index, pm); + ret = nvkm_pm_ctor(&gf100_pm_, device, type, inst, pm); if (ret) return ret; @@ -237,7 +237,7 @@ gf100_pm = { }; int -gf100_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +gf100_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return gf100_pm_new_(&gf100_pm, device, index, ppm); + return gf100_pm_new_(&gf100_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h index 461bb219b1c0..bc4b014c4e8e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h @@ -9,8 +9,8 @@ struct gf100_pm_func { const struct nvkm_specdom *doms_part; }; -int gf100_pm_new_(const struct gf100_pm_func *, struct nvkm_device *, - int index, struct nvkm_pm **); +int gf100_pm_new_(const struct gf100_pm_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_pm **); extern const struct nvkm_funcdom gf100_perfctr_func; extern const struct nvkm_specdom gf100_pm_gpc[]; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c index 49b24c98a7f7..505565866b59 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c @@ -60,7 +60,7 @@ gf108_pm = { }; int -gf108_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +gf108_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return gf100_pm_new_(&gf108_pm, device, index, ppm); + return gf100_pm_new_(&gf108_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c index 9170025fc988..c61e8c010bb3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c @@ -74,7 +74,7 @@ gf117_pm = { }; int -gf117_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +gf117_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return gf100_pm_new_(&gf117_pm, device, index, ppm); + return gf100_pm_new_(&gf117_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c index 07f946d26ac6..75bf3df1cb18 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c @@ -178,7 +178,7 @@ gk104_pm = { }; int -gk104_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +gk104_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return gf100_pm_new_(&gk104_pm, device, index, ppm); + return gf100_pm_new_(&gk104_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c index 5cf5dd536fd0..25874c541486 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c @@ -151,7 +151,7 @@ gt200_pm[] = { }; int -gt200_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +gt200_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return nv40_pm_new_(gt200_pm, device, index, ppm); + return nv40_pm_new_(gt200_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c index c9227ad41b04..54c23e2b6645 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c @@ -132,7 +132,7 @@ gt215_pm[] = { }; int -gt215_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +gt215_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return nv40_pm_new_(gt215_pm, device, index, ppm); + return nv40_pm_new_(gt215_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c index 3fda594700e0..eba5b3b79340 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c @@ -80,7 +80,7 @@ nv40_pm_ = { int nv40_pm_new_(const struct nvkm_specdom *doms, struct nvkm_device *device, - int index, struct nvkm_pm **ppm) + enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { struct nv40_pm *pm; int ret; @@ -89,7 +89,7 @@ nv40_pm_new_(const struct nvkm_specdom *doms, struct nvkm_device *device, return -ENOMEM; *ppm = &pm->base; - ret = nvkm_pm_ctor(&nv40_pm_, device, index, &pm->base); + ret = nvkm_pm_ctor(&nv40_pm_, device, type, inst, &pm->base); if (ret) return ret; @@ -117,7 +117,7 @@ nv40_pm[] = { }; int -nv40_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +nv40_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return nv40_pm_new_(nv40_pm, device, index, ppm); + return nv40_pm_new_(nv40_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h index 8ed19320fda1..afb79843723d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h @@ -9,7 +9,7 @@ struct nv40_pm { u32 sequence; }; -int nv40_pm_new_(const struct nvkm_specdom *, struct nvkm_device *, - int index, struct nvkm_pm **); +int nv40_pm_new_(const struct nvkm_specdom *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_pm **); extern const struct nvkm_funcdom nv40_perfctr_func; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c index cc5a41d4c6f2..bbd3404901f9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c @@ -169,7 +169,7 @@ nv50_pm[] = { }; int -nv50_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +nv50_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return nv40_pm_new_(nv50_pm, device, index, ppm); + return nv40_pm_new_(nv50_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h index cd6f8f79b235..6ae25d3e7f45 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h @@ -4,8 +4,8 @@ #define nvkm_pm(p) container_of((p), struct nvkm_pm, engine) #include <engine/pm.h> -int nvkm_pm_ctor(const struct nvkm_pm_func *, struct nvkm_device *, - int index, struct nvkm_pm *); +int nvkm_pm_ctor(const struct nvkm_pm_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_pm *); struct nvkm_pm_func { void (*fini)(struct nvkm_pm *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c index 6d2a7f0afbb5..1b87df03c823 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c @@ -74,9 +74,8 @@ g98_sec = { }; int -g98_sec_new(struct nvkm_device *device, int index, +g98_sec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_falcon_new_(&g98_sec, device, index, - true, 0x087000, pengine); + return nvkm_falcon_new_(&g98_sec, device, type, inst, true, 0x087000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/Kbuild index 97c4696171f0..63cd2be3de08 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/Kbuild @@ -1,4 +1,5 @@ # SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/sec2/base.o nvkm-y += nvkm/engine/sec2/gp102.o +nvkm-y += nvkm/engine/sec2/gp108.o nvkm-y += nvkm/engine/sec2/tu102.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c index 1b49e5b6717f..092c6d0b8e01 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c @@ -21,97 +21,98 @@ */ #include "priv.h" -#include <core/msgqueue.h> +#include <core/firmware.h> #include <subdev/top.h> -#include <engine/falcon.h> - -static void * -nvkm_sec2_dtor(struct nvkm_engine *engine) -{ - struct nvkm_sec2 *sec2 = nvkm_sec2(engine); - nvkm_msgqueue_del(&sec2->queue); - nvkm_falcon_del(&sec2->falcon); - return sec2; -} static void -nvkm_sec2_intr(struct nvkm_engine *engine) +nvkm_sec2_recv(struct work_struct *work) { - struct nvkm_sec2 *sec2 = nvkm_sec2(engine); - struct nvkm_subdev *subdev = &engine->subdev; - struct nvkm_device *device = subdev->device; - u32 disp = nvkm_rd32(device, sec2->addr + 0x01c); - u32 intr = nvkm_rd32(device, sec2->addr + 0x008) & disp & ~(disp >> 16); - - if (intr & 0x00000040) { - schedule_work(&sec2->work); - nvkm_wr32(device, sec2->addr + 0x004, 0x00000040); - intr &= ~0x00000040; - } + struct nvkm_sec2 *sec2 = container_of(work, typeof(*sec2), work); - if (intr) { - nvkm_error(subdev, "unhandled intr %08x\n", intr); - nvkm_wr32(device, sec2->addr + 0x004, intr); + if (!sec2->initmsg_received) { + int ret = sec2->func->initmsg(sec2); + if (ret) { + nvkm_error(&sec2->engine.subdev, + "error parsing init message: %d\n", ret); + return; + } + sec2->initmsg_received = true; } + + nvkm_falcon_msgq_recv(sec2->msgq); } static void -nvkm_sec2_recv(struct work_struct *work) +nvkm_sec2_intr(struct nvkm_engine *engine) { - struct nvkm_sec2 *sec2 = container_of(work, typeof(*sec2), work); - - if (!sec2->queue) { - nvkm_warn(&sec2->engine.subdev, - "recv function called while no firmware set!\n"); - return; - } - - nvkm_msgqueue_recv(sec2->queue); + struct nvkm_sec2 *sec2 = nvkm_sec2(engine); + sec2->func->intr(sec2); } - static int -nvkm_sec2_oneinit(struct nvkm_engine *engine) +nvkm_sec2_fini(struct nvkm_engine *engine, bool suspend) { struct nvkm_sec2 *sec2 = nvkm_sec2(engine); - struct nvkm_subdev *subdev = &sec2->engine.subdev; - if (!sec2->addr) { - sec2->addr = nvkm_top_addr(subdev->device, subdev->index); - if (WARN_ON(!sec2->addr)) - return -EINVAL; + flush_work(&sec2->work); + + if (suspend) { + nvkm_falcon_cmdq_fini(sec2->cmdq); + sec2->initmsg_received = false; } - return nvkm_falcon_v1_new(subdev, "SEC2", sec2->addr, &sec2->falcon); + return 0; } -static int -nvkm_sec2_fini(struct nvkm_engine *engine, bool suspend) +static void * +nvkm_sec2_dtor(struct nvkm_engine *engine) { struct nvkm_sec2 *sec2 = nvkm_sec2(engine); - flush_work(&sec2->work); - return 0; + nvkm_falcon_msgq_del(&sec2->msgq); + nvkm_falcon_cmdq_del(&sec2->cmdq); + nvkm_falcon_qmgr_del(&sec2->qmgr); + nvkm_falcon_dtor(&sec2->falcon); + return sec2; } static const struct nvkm_engine_func nvkm_sec2 = { .dtor = nvkm_sec2_dtor, - .oneinit = nvkm_sec2_oneinit, .fini = nvkm_sec2_fini, .intr = nvkm_sec2_intr, }; int -nvkm_sec2_new_(struct nvkm_device *device, int index, u32 addr, - struct nvkm_sec2 **psec2) +nvkm_sec2_new_(const struct nvkm_sec2_fwif *fwif, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, u32 addr, struct nvkm_sec2 **psec2) { struct nvkm_sec2 *sec2; + int ret; if (!(sec2 = *psec2 = kzalloc(sizeof(*sec2), GFP_KERNEL))) return -ENOMEM; - sec2->addr = addr; - INIT_WORK(&sec2->work, nvkm_sec2_recv); - return nvkm_engine_ctor(&nvkm_sec2, device, index, true, &sec2->engine); + ret = nvkm_engine_ctor(&nvkm_sec2, device, type, inst, true, &sec2->engine); + if (ret) + return ret; + + fwif = nvkm_firmware_load(&sec2->engine.subdev, fwif, "Sec2", sec2); + if (IS_ERR(fwif)) + return PTR_ERR(fwif); + + sec2->func = fwif->func; + + ret = nvkm_falcon_ctor(sec2->func->flcn, &sec2->engine.subdev, + sec2->engine.subdev.name, addr, &sec2->falcon); + if (ret) + return ret; + + if ((ret = nvkm_falcon_qmgr_new(&sec2->falcon, &sec2->qmgr)) || + (ret = nvkm_falcon_cmdq_new(sec2->qmgr, "cmdq", &sec2->cmdq)) || + (ret = nvkm_falcon_msgq_new(sec2->qmgr, "msgq", &sec2->msgq))) + return ret; + + INIT_WORK(&sec2->work, nvkm_sec2_recv); + return 0; }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c index 858cf27fa010..44e39f5743d5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c @@ -19,12 +19,332 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - #include "priv.h" +#include <core/memory.h> +#include <subdev/acr.h> +#include <subdev/timer.h> + +#include <nvfw/flcn.h> +#include <nvfw/sec2.h> + +int +gp102_sec2_nofw(struct nvkm_sec2 *sec2, int ver, + const struct nvkm_sec2_fwif *fwif) +{ + nvkm_warn(&sec2->engine.subdev, "firmware unavailable\n"); + return 0; +} + +static int +gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr) +{ + struct nv_sec2_acr_bootstrap_falcon_msg *msg = + container_of(hdr, typeof(*msg), msg.hdr); + struct nvkm_subdev *subdev = priv; + const char *name = nvkm_acr_lsf_id(msg->falcon_id); + + if (msg->error_code) { + nvkm_error(subdev, "ACR_BOOTSTRAP_FALCON failed for " + "falcon %d [%s]: %08x\n", + msg->falcon_id, name, msg->error_code); + return -EINVAL; + } + + nvkm_debug(subdev, "%s booted\n", name); + return 0; +} + +static int +gp102_sec2_acr_bootstrap_falcon(struct nvkm_falcon *falcon, + enum nvkm_acr_lsf_id id) +{ + struct nvkm_sec2 *sec2 = container_of(falcon, typeof(*sec2), falcon); + struct nv_sec2_acr_bootstrap_falcon_cmd cmd = { + .cmd.hdr.unit_id = sec2->func->unit_acr, + .cmd.hdr.size = sizeof(cmd), + .cmd.cmd_type = NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON, + .flags = NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES, + .falcon_id = id, + }; + + return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr, + gp102_sec2_acr_bootstrap_falcon_callback, + &sec2->engine.subdev, + msecs_to_jiffies(1000)); +} + +static int +gp102_sec2_acr_boot(struct nvkm_falcon *falcon) +{ + struct nv_sec2_args args = {}; + nvkm_falcon_load_dmem(falcon, &args, + falcon->func->emem_addr, sizeof(args), 0); + nvkm_falcon_start(falcon); + return 0; +} + +static void +gp102_sec2_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) +{ + struct loader_config_v1 hdr; + nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); + hdr.code_dma_base = hdr.code_dma_base + adjust; + hdr.data_dma_base = hdr.data_dma_base + adjust; + hdr.overlay_dma_base = hdr.overlay_dma_base + adjust; + nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); + loader_config_v1_dump(&acr->subdev, &hdr); +} + +static void +gp102_sec2_acr_bld_write(struct nvkm_acr *acr, u32 bld, + struct nvkm_acr_lsfw *lsfw) +{ + const struct loader_config_v1 hdr = { + .dma_idx = FALCON_SEC2_DMAIDX_UCODE, + .code_dma_base = lsfw->offset.img + lsfw->app_start_offset, + .code_size_total = lsfw->app_size, + .code_size_to_load = lsfw->app_resident_code_size, + .code_entry_point = lsfw->app_imem_entry, + .data_dma_base = lsfw->offset.img + lsfw->app_start_offset + + lsfw->app_resident_data_offset, + .data_size = lsfw->app_resident_data_size, + .overlay_dma_base = lsfw->offset.img + lsfw->app_start_offset, + .argc = 1, + .argv = lsfw->falcon->func->emem_addr, + }; + + nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); +} + +static const struct nvkm_acr_lsf_func +gp102_sec2_acr_0 = { + .bld_size = sizeof(struct loader_config_v1), + .bld_write = gp102_sec2_acr_bld_write, + .bld_patch = gp102_sec2_acr_bld_patch, + .boot = gp102_sec2_acr_boot, + .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) | + BIT_ULL(NVKM_ACR_LSF_GPCCS) | + BIT_ULL(NVKM_ACR_LSF_SEC2), + .bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon, +}; + +int +gp102_sec2_initmsg(struct nvkm_sec2 *sec2) +{ + struct nv_sec2_init_msg msg; + int ret, i; + + ret = nvkm_falcon_msgq_recv_initmsg(sec2->msgq, &msg, sizeof(msg)); + if (ret) + return ret; + + if (msg.hdr.unit_id != NV_SEC2_UNIT_INIT || + msg.msg_type != NV_SEC2_INIT_MSG_INIT) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(msg.queue_info); i++) { + if (msg.queue_info[i].id == NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ) { + nvkm_falcon_msgq_init(sec2->msgq, + msg.queue_info[i].index, + msg.queue_info[i].offset, + msg.queue_info[i].size); + } else { + nvkm_falcon_cmdq_init(sec2->cmdq, + msg.queue_info[i].index, + msg.queue_info[i].offset, + msg.queue_info[i].size); + } + } + + return 0; +} + +void +gp102_sec2_intr(struct nvkm_sec2 *sec2) +{ + struct nvkm_subdev *subdev = &sec2->engine.subdev; + struct nvkm_falcon *falcon = &sec2->falcon; + u32 disp = nvkm_falcon_rd32(falcon, 0x01c); + u32 intr = nvkm_falcon_rd32(falcon, 0x008) & disp & ~(disp >> 16); + + if (intr & 0x00000040) { + schedule_work(&sec2->work); + nvkm_falcon_wr32(falcon, 0x004, 0x00000040); + intr &= ~0x00000040; + } + + if (intr) { + nvkm_error(subdev, "unhandled intr %08x\n", intr); + nvkm_falcon_wr32(falcon, 0x004, intr); + } +} + +int +gp102_sec2_flcn_enable(struct nvkm_falcon *falcon) +{ + nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000001); + udelay(10); + nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000000); + return nvkm_falcon_v1_enable(falcon); +} + +void +gp102_sec2_flcn_bind_context(struct nvkm_falcon *falcon, + struct nvkm_memory *ctx) +{ + struct nvkm_device *device = falcon->owner->device; + + nvkm_falcon_v1_bind_context(falcon, ctx); + if (!ctx) + return; + + /* Not sure if this is a WAR for a HW issue, or some additional + * programming sequence that's needed to properly complete the + * context switch we trigger above. + * + * Fixes unreliability of booting the SEC2 RTOS on Quadro P620, + * particularly when resuming from suspend. + * + * Also removes the need for an odd workaround where we needed + * to program SEC2's FALCON_CPUCTL_ALIAS_STARTCPU twice before + * the SEC2 RTOS would begin executing. + */ + nvkm_msec(device, 10, + u32 irqstat = nvkm_falcon_rd32(falcon, 0x008); + u32 flcn0dc = nvkm_falcon_rd32(falcon, 0x0dc); + if ((irqstat & 0x00000008) && + (flcn0dc & 0x00007000) == 0x00005000) + break; + ); + + nvkm_falcon_mask(falcon, 0x004, 0x00000008, 0x00000008); + nvkm_falcon_mask(falcon, 0x058, 0x00000002, 0x00000002); + + nvkm_msec(device, 10, + u32 flcn0dc = nvkm_falcon_rd32(falcon, 0x0dc); + if ((flcn0dc & 0x00007000) == 0x00000000) + break; + ); +} + +static const struct nvkm_falcon_func +gp102_sec2_flcn = { + .debug = 0x408, + .fbif = 0x600, + .load_imem = nvkm_falcon_v1_load_imem, + .load_dmem = nvkm_falcon_v1_load_dmem, + .read_dmem = nvkm_falcon_v1_read_dmem, + .emem_addr = 0x01000000, + .bind_context = gp102_sec2_flcn_bind_context, + .wait_for_halt = nvkm_falcon_v1_wait_for_halt, + .clear_interrupt = nvkm_falcon_v1_clear_interrupt, + .set_start_addr = nvkm_falcon_v1_set_start_addr, + .start = nvkm_falcon_v1_start, + .enable = gp102_sec2_flcn_enable, + .disable = nvkm_falcon_v1_disable, + .cmdq = { 0xa00, 0xa04, 8 }, + .msgq = { 0xa30, 0xa34, 8 }, +}; + +const struct nvkm_sec2_func +gp102_sec2 = { + .flcn = &gp102_sec2_flcn, + .unit_acr = NV_SEC2_UNIT_ACR, + .intr = gp102_sec2_intr, + .initmsg = gp102_sec2_initmsg, +}; + +MODULE_FIRMWARE("nvidia/gp102/sec2/desc.bin"); +MODULE_FIRMWARE("nvidia/gp102/sec2/image.bin"); +MODULE_FIRMWARE("nvidia/gp102/sec2/sig.bin"); +MODULE_FIRMWARE("nvidia/gp104/sec2/desc.bin"); +MODULE_FIRMWARE("nvidia/gp104/sec2/image.bin"); +MODULE_FIRMWARE("nvidia/gp104/sec2/sig.bin"); +MODULE_FIRMWARE("nvidia/gp106/sec2/desc.bin"); +MODULE_FIRMWARE("nvidia/gp106/sec2/image.bin"); +MODULE_FIRMWARE("nvidia/gp106/sec2/sig.bin"); +MODULE_FIRMWARE("nvidia/gp107/sec2/desc.bin"); +MODULE_FIRMWARE("nvidia/gp107/sec2/image.bin"); +MODULE_FIRMWARE("nvidia/gp107/sec2/sig.bin"); + +static void +gp102_sec2_acr_bld_patch_1(struct nvkm_acr *acr, u32 bld, s64 adjust) +{ + struct flcn_bl_dmem_desc_v2 hdr; + nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); + hdr.code_dma_base = hdr.code_dma_base + adjust; + hdr.data_dma_base = hdr.data_dma_base + adjust; + nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); + flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr); +} + +static void +gp102_sec2_acr_bld_write_1(struct nvkm_acr *acr, u32 bld, + struct nvkm_acr_lsfw *lsfw) +{ + const struct flcn_bl_dmem_desc_v2 hdr = { + .ctx_dma = FALCON_SEC2_DMAIDX_UCODE, + .code_dma_base = lsfw->offset.img + lsfw->app_start_offset, + .non_sec_code_off = lsfw->app_resident_code_offset, + .non_sec_code_size = lsfw->app_resident_code_size, + .code_entry_point = lsfw->app_imem_entry, + .data_dma_base = lsfw->offset.img + lsfw->app_start_offset + + lsfw->app_resident_data_offset, + .data_size = lsfw->app_resident_data_size, + .argc = 1, + .argv = lsfw->falcon->func->emem_addr, + }; + + nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); +} + +const struct nvkm_acr_lsf_func +gp102_sec2_acr_1 = { + .bld_size = sizeof(struct flcn_bl_dmem_desc_v2), + .bld_write = gp102_sec2_acr_bld_write_1, + .bld_patch = gp102_sec2_acr_bld_patch_1, + .boot = gp102_sec2_acr_boot, + .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) | + BIT_ULL(NVKM_ACR_LSF_GPCCS) | + BIT_ULL(NVKM_ACR_LSF_SEC2), + .bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon, +}; + +int +gp102_sec2_load(struct nvkm_sec2 *sec2, int ver, + const struct nvkm_sec2_fwif *fwif) +{ + return nvkm_acr_lsfw_load_sig_image_desc_v1(&sec2->engine.subdev, + &sec2->falcon, + NVKM_ACR_LSF_SEC2, "sec2/", + ver, fwif->acr); +} + +MODULE_FIRMWARE("nvidia/gp102/sec2/desc-1.bin"); +MODULE_FIRMWARE("nvidia/gp102/sec2/image-1.bin"); +MODULE_FIRMWARE("nvidia/gp102/sec2/sig-1.bin"); +MODULE_FIRMWARE("nvidia/gp104/sec2/desc-1.bin"); +MODULE_FIRMWARE("nvidia/gp104/sec2/image-1.bin"); +MODULE_FIRMWARE("nvidia/gp104/sec2/sig-1.bin"); +MODULE_FIRMWARE("nvidia/gp106/sec2/desc-1.bin"); +MODULE_FIRMWARE("nvidia/gp106/sec2/image-1.bin"); +MODULE_FIRMWARE("nvidia/gp106/sec2/sig-1.bin"); +MODULE_FIRMWARE("nvidia/gp107/sec2/desc-1.bin"); +MODULE_FIRMWARE("nvidia/gp107/sec2/image-1.bin"); +MODULE_FIRMWARE("nvidia/gp107/sec2/sig-1.bin"); + +static const struct nvkm_sec2_fwif +gp102_sec2_fwif[] = { + { 1, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_1 }, + { 0, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_0 }, + { -1, gp102_sec2_nofw, &gp102_sec2 }, + {} +}; + int -gp102_sec2_new(struct nvkm_device *device, int index, +gp102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sec2 **psec2) { - return nvkm_sec2_new_(device, index, 0, psec2); + return nvkm_sec2_new_(gp102_sec2_fwif, device, type, inst, 0, psec2); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp108.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp108.c new file mode 100644 index 000000000000..3e9f5c842f3c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp108.c @@ -0,0 +1,43 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" +#include <subdev/acr.h> + +MODULE_FIRMWARE("nvidia/gp108/sec2/desc.bin"); +MODULE_FIRMWARE("nvidia/gp108/sec2/image.bin"); +MODULE_FIRMWARE("nvidia/gp108/sec2/sig.bin"); +MODULE_FIRMWARE("nvidia/gv100/sec2/desc.bin"); +MODULE_FIRMWARE("nvidia/gv100/sec2/image.bin"); +MODULE_FIRMWARE("nvidia/gv100/sec2/sig.bin"); + +static const struct nvkm_sec2_fwif +gp108_sec2_fwif[] = { + { 0, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_1 }, + {} +}; + +int +gp108_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_sec2 **psec2) +{ + return nvkm_sec2_new_(gp108_sec2_fwif, device, type, inst, 0, psec2); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h index b331b00517e6..af19229e885d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h @@ -3,7 +3,28 @@ #define __NVKM_SEC2_PRIV_H__ #include <engine/sec2.h> -#define nvkm_sec2(p) container_of((p), struct nvkm_sec2, engine) +struct nvkm_sec2_func { + const struct nvkm_falcon_func *flcn; + u8 unit_acr; + void (*intr)(struct nvkm_sec2 *); + int (*initmsg)(struct nvkm_sec2 *); +}; -int nvkm_sec2_new_(struct nvkm_device *, int, u32 addr, struct nvkm_sec2 **); +void gp102_sec2_intr(struct nvkm_sec2 *); +int gp102_sec2_initmsg(struct nvkm_sec2 *); + +struct nvkm_sec2_fwif { + int version; + int (*load)(struct nvkm_sec2 *, int ver, const struct nvkm_sec2_fwif *); + const struct nvkm_sec2_func *func; + const struct nvkm_acr_lsf_func *acr; +}; + +int gp102_sec2_nofw(struct nvkm_sec2 *, int, const struct nvkm_sec2_fwif *); +int gp102_sec2_load(struct nvkm_sec2 *, int, const struct nvkm_sec2_fwif *); +extern const struct nvkm_sec2_func gp102_sec2; +extern const struct nvkm_acr_lsf_func gp102_sec2_acr_1; + +int nvkm_sec2_new_(const struct nvkm_sec2_fwif *, struct nvkm_device *, enum nvkm_subdev_type, + int, u32 addr, struct nvkm_sec2 **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c index d655576164b1..f3faeb705575 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c @@ -19,15 +19,64 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ - #include "priv.h" +#include <subdev/acr.h> + +static const struct nvkm_falcon_func +tu102_sec2_flcn = { + .debug = 0x408, + .fbif = 0x600, + .load_imem = nvkm_falcon_v1_load_imem, + .load_dmem = nvkm_falcon_v1_load_dmem, + .read_dmem = nvkm_falcon_v1_read_dmem, + .emem_addr = 0x01000000, + .bind_context = gp102_sec2_flcn_bind_context, + .wait_for_halt = nvkm_falcon_v1_wait_for_halt, + .clear_interrupt = nvkm_falcon_v1_clear_interrupt, + .set_start_addr = nvkm_falcon_v1_set_start_addr, + .start = nvkm_falcon_v1_start, + .enable = nvkm_falcon_v1_enable, + .disable = nvkm_falcon_v1_disable, + .cmdq = { 0xc00, 0xc04, 8 }, + .msgq = { 0xc80, 0xc84, 8 }, +}; + +static const struct nvkm_sec2_func +tu102_sec2 = { + .flcn = &tu102_sec2_flcn, + .unit_acr = 0x07, + .intr = gp102_sec2_intr, + .initmsg = gp102_sec2_initmsg, +}; + +MODULE_FIRMWARE("nvidia/tu102/sec2/desc.bin"); +MODULE_FIRMWARE("nvidia/tu102/sec2/image.bin"); +MODULE_FIRMWARE("nvidia/tu102/sec2/sig.bin"); +MODULE_FIRMWARE("nvidia/tu104/sec2/desc.bin"); +MODULE_FIRMWARE("nvidia/tu104/sec2/image.bin"); +MODULE_FIRMWARE("nvidia/tu104/sec2/sig.bin"); +MODULE_FIRMWARE("nvidia/tu106/sec2/desc.bin"); +MODULE_FIRMWARE("nvidia/tu106/sec2/image.bin"); +MODULE_FIRMWARE("nvidia/tu106/sec2/sig.bin"); +MODULE_FIRMWARE("nvidia/tu116/sec2/desc.bin"); +MODULE_FIRMWARE("nvidia/tu116/sec2/image.bin"); +MODULE_FIRMWARE("nvidia/tu116/sec2/sig.bin"); +MODULE_FIRMWARE("nvidia/tu117/sec2/desc.bin"); +MODULE_FIRMWARE("nvidia/tu117/sec2/image.bin"); +MODULE_FIRMWARE("nvidia/tu117/sec2/sig.bin"); + +static const struct nvkm_sec2_fwif +tu102_sec2_fwif[] = { + { 0, gp102_sec2_load, &tu102_sec2, &gp102_sec2_acr_1 }, + { -1, gp102_sec2_nofw, &tu102_sec2 } +}; int -tu102_sec2_new(struct nvkm_device *device, int index, +tu102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sec2 **psec2) { /* TOP info wasn't updated on Turing to reflect the PRI * address change for some reason. We override it here. */ - return nvkm_sec2_new_(device, index, 0x840000, psec2); + return nvkm_sec2_new_(tu102_sec2_fwif, device, type, inst, 0x840000, psec2); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c index 7be3198e11de..14871d0bd746 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c @@ -97,7 +97,7 @@ nvkm_sw = { int nvkm_sw_new_(const struct nvkm_sw_func *func, struct nvkm_device *device, - int index, struct nvkm_sw **psw) + enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw) { struct nvkm_sw *sw; @@ -106,5 +106,5 @@ nvkm_sw_new_(const struct nvkm_sw_func *func, struct nvkm_device *device, INIT_LIST_HEAD(&sw->chan); sw->func = func; - return nvkm_engine_ctor(&nvkm_sw, device, index, true, &sw->engine); + return nvkm_engine_ctor(&nvkm_sw, device, type, inst, true, &sw->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c index ea8f4247b628..55abf839f29d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c @@ -149,7 +149,7 @@ gf100_sw = { }; int -gf100_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw) +gf100_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw) { - return nvkm_sw_new_(&gf100_sw, device, index, psw); + return nvkm_sw_new_(&gf100_sw, device, type, inst, psw); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c index b6675fe1b0ce..4aa57573869c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c @@ -133,7 +133,7 @@ nv04_sw = { }; int -nv04_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw) +nv04_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw) { - return nvkm_sw_new_(&nv04_sw, device, index, psw); + return nvkm_sw_new_(&nv04_sw, device, type, inst, psw); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c index 09d22fcd194c..e79e640ae535 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c @@ -62,7 +62,7 @@ nv10_sw = { }; int -nv10_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw) +nv10_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw) { - return nvkm_sw_new_(&nv10_sw, device, index, psw); + return nvkm_sw_new_(&nv10_sw, device, type, inst, psw); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c index 01573d187f2c..1fdd094c8b7e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c @@ -142,7 +142,7 @@ nv50_sw = { }; int -nv50_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw) +nv50_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw) { - return nvkm_sw_new_(&nv50_sw, device, index, psw); + return nvkm_sw_new_(&nv50_sw, device, type, inst, psw); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h index 6d18fc6180f2..d9d83b1b8849 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h @@ -5,8 +5,8 @@ #include <engine/sw.h> struct nvkm_sw_chan; -int nvkm_sw_new_(const struct nvkm_sw_func *, struct nvkm_device *, - int index, struct nvkm_sw **); +int nvkm_sw_new_(const struct nvkm_sw_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_sw **); struct nvkm_sw_chan_sclass { int (*ctor)(struct nvkm_sw_chan *, const struct nvkm_oclass *, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c index 7a96178786c4..b502266c76fd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c @@ -36,8 +36,8 @@ g84_vp = { }; int -g84_vp_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) +g84_vp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_xtensa_new_(&g84_vp, device, index, - true, 0x00f000, pengine); + return nvkm_xtensa_new_(&g84_vp, device, type, inst, true, 0x00f000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c index 70549381e082..f7d3ba0afb55 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c @@ -175,9 +175,9 @@ nvkm_xtensa = { }; int -nvkm_xtensa_new_(const struct nvkm_xtensa_func *func, - struct nvkm_device *device, int index, bool enable, - u32 addr, struct nvkm_engine **pengine) +nvkm_xtensa_new_(const struct nvkm_xtensa_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, bool enable, u32 addr, + struct nvkm_engine **pengine) { struct nvkm_xtensa *xtensa; @@ -187,6 +187,5 @@ nvkm_xtensa_new_(const struct nvkm_xtensa_func *func, xtensa->addr = addr; *pengine = &xtensa->engine; - return nvkm_engine_ctor(&nvkm_xtensa, device, index, - enable, &xtensa->engine); + return nvkm_engine_ctor(&nvkm_xtensa, device, type, inst, enable, &xtensa->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild b/drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild index b5665ada850a..d79d783904ee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT nvkm-y += nvkm/falcon/base.o +nvkm-y += nvkm/falcon/cmdq.o +nvkm-y += nvkm/falcon/msgq.o +nvkm-y += nvkm/falcon/qmgr.o nvkm-y += nvkm/falcon/v1.o -nvkm-y += nvkm/falcon/msgqueue.o -nvkm-y += nvkm/falcon/msgqueue_0137c63d.o -nvkm-y += nvkm/falcon/msgqueue_0148cdec.o diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/base.c b/drivers/gpu/drm/nouveau/nvkm/falcon/base.c index 366c87de6e72..c91130a6be2a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/base.c @@ -22,6 +22,7 @@ #include "priv.h" #include <subdev/mc.h> +#include <subdev/top.h> void nvkm_falcon_load_imem(struct nvkm_falcon *falcon, void *data, u32 start, @@ -87,13 +88,12 @@ int nvkm_falcon_enable(struct nvkm_falcon *falcon) { struct nvkm_device *device = falcon->owner->device; - enum nvkm_devidx id = falcon->owner->index; int ret; - nvkm_mc_enable(device, id); + nvkm_mc_enable(device, falcon->owner->type, falcon->owner->inst); ret = falcon->func->enable(falcon); if (ret) { - nvkm_mc_disable(device, id); + nvkm_mc_disable(device, falcon->owner->type, falcon->owner->inst); return ret; } @@ -104,22 +104,25 @@ void nvkm_falcon_disable(struct nvkm_falcon *falcon) { struct nvkm_device *device = falcon->owner->device; - enum nvkm_devidx id = falcon->owner->index; /* already disabled, return or wait_idle will timeout */ - if (!nvkm_mc_enabled(device, id)) + if (!nvkm_mc_enabled(device, falcon->owner->type, falcon->owner->inst)) return; falcon->func->disable(falcon); - nvkm_mc_disable(device, id); + nvkm_mc_disable(device, falcon->owner->type, falcon->owner->inst); } int nvkm_falcon_reset(struct nvkm_falcon *falcon) { - nvkm_falcon_disable(falcon); - return nvkm_falcon_enable(falcon); + if (!falcon->func->reset) { + nvkm_falcon_disable(falcon); + return nvkm_falcon_enable(falcon); + } + + return falcon->func->reset(falcon); } int @@ -134,6 +137,37 @@ nvkm_falcon_clear_interrupt(struct nvkm_falcon *falcon, u32 mask) return falcon->func->clear_interrupt(falcon, mask); } +static int +nvkm_falcon_oneinit(struct nvkm_falcon *falcon) +{ + const struct nvkm_falcon_func *func = falcon->func; + const struct nvkm_subdev *subdev = falcon->owner; + u32 reg; + + if (!falcon->addr) { + falcon->addr = nvkm_top_addr(subdev->device, subdev->type, subdev->inst); + if (WARN_ON(!falcon->addr)) + return -ENODEV; + } + + reg = nvkm_falcon_rd32(falcon, 0x12c); + falcon->version = reg & 0xf; + falcon->secret = (reg >> 4) & 0x3; + falcon->code.ports = (reg >> 8) & 0xf; + falcon->data.ports = (reg >> 12) & 0xf; + + reg = nvkm_falcon_rd32(falcon, 0x108); + falcon->code.limit = (reg & 0x1ff) << 8; + falcon->data.limit = (reg & 0x3fe00) >> 1; + + if (func->debug) { + u32 val = nvkm_falcon_rd32(falcon, func->debug); + falcon->debug = (val >> 20) & 0x1; + } + + return 0; +} + void nvkm_falcon_put(struct nvkm_falcon *falcon, const struct nvkm_subdev *user) { @@ -151,79 +185,48 @@ nvkm_falcon_put(struct nvkm_falcon *falcon, const struct nvkm_subdev *user) int nvkm_falcon_get(struct nvkm_falcon *falcon, const struct nvkm_subdev *user) { + int ret = 0; + mutex_lock(&falcon->mutex); if (falcon->user) { nvkm_error(user, "%s falcon already acquired by %s!\n", - falcon->name, nvkm_subdev_name[falcon->user->index]); + falcon->name, falcon->user->name); mutex_unlock(&falcon->mutex); return -EBUSY; } nvkm_debug(user, "acquired %s falcon\n", falcon->name); + if (!falcon->oneinit) + ret = nvkm_falcon_oneinit(falcon); falcon->user = user; mutex_unlock(&falcon->mutex); - return 0; + return ret; } void +nvkm_falcon_dtor(struct nvkm_falcon *falcon) +{ +} + +int nvkm_falcon_ctor(const struct nvkm_falcon_func *func, struct nvkm_subdev *subdev, const char *name, u32 addr, struct nvkm_falcon *falcon) { - u32 debug_reg; - u32 reg; - falcon->func = func; falcon->owner = subdev; falcon->name = name; falcon->addr = addr; mutex_init(&falcon->mutex); mutex_init(&falcon->dmem_mutex); - - reg = nvkm_falcon_rd32(falcon, 0x12c); - falcon->version = reg & 0xf; - falcon->secret = (reg >> 4) & 0x3; - falcon->code.ports = (reg >> 8) & 0xf; - falcon->data.ports = (reg >> 12) & 0xf; - - reg = nvkm_falcon_rd32(falcon, 0x108); - falcon->code.limit = (reg & 0x1ff) << 8; - falcon->data.limit = (reg & 0x3fe00) >> 1; - - switch (subdev->index) { - case NVKM_ENGINE_GR: - debug_reg = 0x0; - break; - case NVKM_SUBDEV_PMU: - debug_reg = 0xc08; - break; - case NVKM_ENGINE_NVDEC0: - debug_reg = 0xd00; - break; - case NVKM_ENGINE_SEC2: - debug_reg = 0x408; - falcon->has_emem = true; - break; - case NVKM_SUBDEV_GSP: - debug_reg = 0x0; /*XXX*/ - break; - default: - nvkm_warn(subdev, "unsupported falcon %s!\n", - nvkm_subdev_name[subdev->index]); - debug_reg = 0; - break; - } - - if (debug_reg) { - u32 val = nvkm_falcon_rd32(falcon, debug_reg); - falcon->debug = (val >> 20) & 0x1; - } + return 0; } void nvkm_falcon_del(struct nvkm_falcon **pfalcon) { if (*pfalcon) { + nvkm_falcon_dtor(*pfalcon); kfree(*pfalcon); *pfalcon = NULL; } diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c b/drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c new file mode 100644 index 000000000000..44cf6a8862e1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "qmgr.h" + +static bool +nvkm_falcon_cmdq_has_room(struct nvkm_falcon_cmdq *cmdq, u32 size, bool *rewind) +{ + u32 head = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->head_reg); + u32 tail = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->tail_reg); + u32 free; + + size = ALIGN(size, QUEUE_ALIGNMENT); + + if (head >= tail) { + free = cmdq->offset + cmdq->size - head; + free -= HDR_SIZE; + + if (size > free) { + *rewind = true; + head = cmdq->offset; + } + } + + if (head < tail) + free = tail - head - 1; + + return size <= free; +} + +static void +nvkm_falcon_cmdq_push(struct nvkm_falcon_cmdq *cmdq, void *data, u32 size) +{ + struct nvkm_falcon *falcon = cmdq->qmgr->falcon; + nvkm_falcon_load_dmem(falcon, data, cmdq->position, size, 0); + cmdq->position += ALIGN(size, QUEUE_ALIGNMENT); +} + +static void +nvkm_falcon_cmdq_rewind(struct nvkm_falcon_cmdq *cmdq) +{ + struct nvfw_falcon_cmd cmd; + + cmd.unit_id = NV_FALCON_CMD_UNIT_ID_REWIND; + cmd.size = sizeof(cmd); + nvkm_falcon_cmdq_push(cmdq, &cmd, cmd.size); + + cmdq->position = cmdq->offset; +} + +static int +nvkm_falcon_cmdq_open(struct nvkm_falcon_cmdq *cmdq, u32 size) +{ + struct nvkm_falcon *falcon = cmdq->qmgr->falcon; + bool rewind = false; + + mutex_lock(&cmdq->mutex); + + if (!nvkm_falcon_cmdq_has_room(cmdq, size, &rewind)) { + FLCNQ_DBG(cmdq, "queue full"); + mutex_unlock(&cmdq->mutex); + return -EAGAIN; + } + + cmdq->position = nvkm_falcon_rd32(falcon, cmdq->head_reg); + + if (rewind) + nvkm_falcon_cmdq_rewind(cmdq); + + return 0; +} + +static void +nvkm_falcon_cmdq_close(struct nvkm_falcon_cmdq *cmdq) +{ + nvkm_falcon_wr32(cmdq->qmgr->falcon, cmdq->head_reg, cmdq->position); + mutex_unlock(&cmdq->mutex); +} + +static int +nvkm_falcon_cmdq_write(struct nvkm_falcon_cmdq *cmdq, struct nvfw_falcon_cmd *cmd) +{ + static unsigned timeout = 2000; + unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout); + int ret = -EAGAIN; + + while (ret == -EAGAIN && time_before(jiffies, end_jiffies)) + ret = nvkm_falcon_cmdq_open(cmdq, cmd->size); + if (ret) { + FLCNQ_ERR(cmdq, "timeout waiting for queue space"); + return ret; + } + + nvkm_falcon_cmdq_push(cmdq, cmd, cmd->size); + nvkm_falcon_cmdq_close(cmdq); + return ret; +} + +/* specifies that we want to know the command status in the answer message */ +#define CMD_FLAGS_STATUS BIT(0) +/* specifies that we want an interrupt when the answer message is queued */ +#define CMD_FLAGS_INTR BIT(1) + +int +nvkm_falcon_cmdq_send(struct nvkm_falcon_cmdq *cmdq, struct nvfw_falcon_cmd *cmd, + nvkm_falcon_qmgr_callback cb, void *priv, + unsigned long timeout) +{ + struct nvkm_falcon_qmgr_seq *seq; + int ret; + + if (!wait_for_completion_timeout(&cmdq->ready, + msecs_to_jiffies(1000))) { + FLCNQ_ERR(cmdq, "timeout waiting for queue ready"); + return -ETIMEDOUT; + } + + seq = nvkm_falcon_qmgr_seq_acquire(cmdq->qmgr); + if (IS_ERR(seq)) + return PTR_ERR(seq); + + cmd->seq_id = seq->id; + cmd->ctrl_flags = CMD_FLAGS_STATUS | CMD_FLAGS_INTR; + + seq->state = SEQ_STATE_USED; + seq->async = !timeout; + seq->callback = cb; + seq->priv = priv; + + ret = nvkm_falcon_cmdq_write(cmdq, cmd); + if (ret) { + seq->state = SEQ_STATE_PENDING; + nvkm_falcon_qmgr_seq_release(cmdq->qmgr, seq); + return ret; + } + + if (!seq->async) { + if (!wait_for_completion_timeout(&seq->done, timeout)) { + FLCNQ_ERR(cmdq, "timeout waiting for reply"); + return -ETIMEDOUT; + } + ret = seq->result; + nvkm_falcon_qmgr_seq_release(cmdq->qmgr, seq); + } + + return ret; +} + +void +nvkm_falcon_cmdq_fini(struct nvkm_falcon_cmdq *cmdq) +{ + reinit_completion(&cmdq->ready); +} + +void +nvkm_falcon_cmdq_init(struct nvkm_falcon_cmdq *cmdq, + u32 index, u32 offset, u32 size) +{ + const struct nvkm_falcon_func *func = cmdq->qmgr->falcon->func; + + cmdq->head_reg = func->cmdq.head + index * func->cmdq.stride; + cmdq->tail_reg = func->cmdq.tail + index * func->cmdq.stride; + cmdq->offset = offset; + cmdq->size = size; + complete_all(&cmdq->ready); + + FLCNQ_DBG(cmdq, "initialised @ index %d offset 0x%08x size 0x%08x", + index, cmdq->offset, cmdq->size); +} + +void +nvkm_falcon_cmdq_del(struct nvkm_falcon_cmdq **pcmdq) +{ + struct nvkm_falcon_cmdq *cmdq = *pcmdq; + if (cmdq) { + kfree(*pcmdq); + *pcmdq = NULL; + } +} + +int +nvkm_falcon_cmdq_new(struct nvkm_falcon_qmgr *qmgr, const char *name, + struct nvkm_falcon_cmdq **pcmdq) +{ + struct nvkm_falcon_cmdq *cmdq = *pcmdq; + + if (!(cmdq = *pcmdq = kzalloc(sizeof(*cmdq), GFP_KERNEL))) + return -ENOMEM; + + cmdq->qmgr = qmgr; + cmdq->name = name; + mutex_init(&cmdq->mutex); + init_completion(&cmdq->ready); + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c b/drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c new file mode 100644 index 000000000000..e74371dffc76 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "qmgr.h" + +static void +nvkm_falcon_msgq_open(struct nvkm_falcon_msgq *msgq) +{ + mutex_lock(&msgq->mutex); + msgq->position = nvkm_falcon_rd32(msgq->qmgr->falcon, msgq->tail_reg); +} + +static void +nvkm_falcon_msgq_close(struct nvkm_falcon_msgq *msgq, bool commit) +{ + struct nvkm_falcon *falcon = msgq->qmgr->falcon; + + if (commit) + nvkm_falcon_wr32(falcon, msgq->tail_reg, msgq->position); + + mutex_unlock(&msgq->mutex); +} + +static bool +nvkm_falcon_msgq_empty(struct nvkm_falcon_msgq *msgq) +{ + u32 head = nvkm_falcon_rd32(msgq->qmgr->falcon, msgq->head_reg); + u32 tail = nvkm_falcon_rd32(msgq->qmgr->falcon, msgq->tail_reg); + return head == tail; +} + +static int +nvkm_falcon_msgq_pop(struct nvkm_falcon_msgq *msgq, void *data, u32 size) +{ + struct nvkm_falcon *falcon = msgq->qmgr->falcon; + u32 head, tail, available; + + head = nvkm_falcon_rd32(falcon, msgq->head_reg); + /* has the buffer looped? */ + if (head < msgq->position) + msgq->position = msgq->offset; + + tail = msgq->position; + + available = head - tail; + if (size > available) { + FLCNQ_ERR(msgq, "requested %d bytes, but only %d available", + size, available); + return -EINVAL; + } + + nvkm_falcon_read_dmem(falcon, tail, size, 0, data); + msgq->position += ALIGN(size, QUEUE_ALIGNMENT); + return 0; +} + +static int +nvkm_falcon_msgq_read(struct nvkm_falcon_msgq *msgq, struct nvfw_falcon_msg *hdr) +{ + int ret = 0; + + nvkm_falcon_msgq_open(msgq); + + if (nvkm_falcon_msgq_empty(msgq)) + goto close; + + ret = nvkm_falcon_msgq_pop(msgq, hdr, HDR_SIZE); + if (ret) { + FLCNQ_ERR(msgq, "failed to read message header"); + goto close; + } + + if (hdr->size > MSG_BUF_SIZE) { + FLCNQ_ERR(msgq, "message too big, %d bytes", hdr->size); + ret = -ENOSPC; + goto close; + } + + if (hdr->size > HDR_SIZE) { + u32 read_size = hdr->size - HDR_SIZE; + + ret = nvkm_falcon_msgq_pop(msgq, (hdr + 1), read_size); + if (ret) { + FLCNQ_ERR(msgq, "failed to read message data"); + goto close; + } + } + + ret = 1; +close: + nvkm_falcon_msgq_close(msgq, (ret >= 0)); + return ret; +} + +static int +nvkm_falcon_msgq_exec(struct nvkm_falcon_msgq *msgq, struct nvfw_falcon_msg *hdr) +{ + struct nvkm_falcon_qmgr_seq *seq; + + seq = &msgq->qmgr->seq.id[hdr->seq_id]; + if (seq->state != SEQ_STATE_USED && seq->state != SEQ_STATE_CANCELLED) { + FLCNQ_ERR(msgq, "message for unknown sequence %08x", seq->id); + return -EINVAL; + } + + if (seq->state == SEQ_STATE_USED) { + if (seq->callback) + seq->result = seq->callback(seq->priv, hdr); + } + + if (seq->async) { + nvkm_falcon_qmgr_seq_release(msgq->qmgr, seq); + return 0; + } + + complete_all(&seq->done); + return 0; +} + +void +nvkm_falcon_msgq_recv(struct nvkm_falcon_msgq *msgq) +{ + /* + * We are invoked from a worker thread, so normally we have plenty of + * stack space to work with. + */ + u8 msg_buffer[MSG_BUF_SIZE]; + struct nvfw_falcon_msg *hdr = (void *)msg_buffer; + + while (nvkm_falcon_msgq_read(msgq, hdr) > 0) + nvkm_falcon_msgq_exec(msgq, hdr); +} + +int +nvkm_falcon_msgq_recv_initmsg(struct nvkm_falcon_msgq *msgq, + void *data, u32 size) +{ + struct nvkm_falcon *falcon = msgq->qmgr->falcon; + struct nvfw_falcon_msg *hdr = data; + int ret; + + msgq->head_reg = falcon->func->msgq.head; + msgq->tail_reg = falcon->func->msgq.tail; + msgq->offset = nvkm_falcon_rd32(falcon, falcon->func->msgq.tail); + + nvkm_falcon_msgq_open(msgq); + ret = nvkm_falcon_msgq_pop(msgq, data, size); + if (ret == 0 && hdr->size != size) { + FLCN_ERR(falcon, "unexpected init message size %d vs %d", + hdr->size, size); + ret = -EINVAL; + } + nvkm_falcon_msgq_close(msgq, ret == 0); + return ret; +} + +void +nvkm_falcon_msgq_init(struct nvkm_falcon_msgq *msgq, + u32 index, u32 offset, u32 size) +{ + const struct nvkm_falcon_func *func = msgq->qmgr->falcon->func; + + msgq->head_reg = func->msgq.head + index * func->msgq.stride; + msgq->tail_reg = func->msgq.tail + index * func->msgq.stride; + msgq->offset = offset; + + FLCNQ_DBG(msgq, "initialised @ index %d offset 0x%08x size 0x%08x", + index, msgq->offset, size); +} + +void +nvkm_falcon_msgq_del(struct nvkm_falcon_msgq **pmsgq) +{ + struct nvkm_falcon_msgq *msgq = *pmsgq; + if (msgq) { + kfree(*pmsgq); + *pmsgq = NULL; + } +} + +int +nvkm_falcon_msgq_new(struct nvkm_falcon_qmgr *qmgr, const char *name, + struct nvkm_falcon_msgq **pmsgq) +{ + struct nvkm_falcon_msgq *msgq = *pmsgq; + + if (!(msgq = *pmsgq = kzalloc(sizeof(*msgq), GFP_KERNEL))) + return -ENOMEM; + + msgq->qmgr = qmgr; + msgq->name = name; + mutex_init(&msgq->mutex); + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c deleted file mode 100644 index a8bee1e046aa..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "msgqueue.h" -#include <engine/falcon.h> - -#include <subdev/secboot.h> - - -#define HDR_SIZE sizeof(struct nvkm_msgqueue_hdr) -#define QUEUE_ALIGNMENT 4 -/* max size of the messages we can receive */ -#define MSG_BUF_SIZE 128 - -static int -msg_queue_open(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue) -{ - struct nvkm_falcon *falcon = priv->falcon; - - mutex_lock(&queue->mutex); - - queue->position = nvkm_falcon_rd32(falcon, queue->tail_reg); - - return 0; -} - -static void -msg_queue_close(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue, - bool commit) -{ - struct nvkm_falcon *falcon = priv->falcon; - - if (commit) - nvkm_falcon_wr32(falcon, queue->tail_reg, queue->position); - - mutex_unlock(&queue->mutex); -} - -static bool -msg_queue_empty(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue) -{ - struct nvkm_falcon *falcon = priv->falcon; - u32 head, tail; - - head = nvkm_falcon_rd32(falcon, queue->head_reg); - tail = nvkm_falcon_rd32(falcon, queue->tail_reg); - - return head == tail; -} - -static int -msg_queue_pop(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue, - void *data, u32 size) -{ - struct nvkm_falcon *falcon = priv->falcon; - const struct nvkm_subdev *subdev = priv->falcon->owner; - u32 head, tail, available; - - head = nvkm_falcon_rd32(falcon, queue->head_reg); - /* has the buffer looped? */ - if (head < queue->position) - queue->position = queue->offset; - - tail = queue->position; - - available = head - tail; - - if (available == 0) { - nvkm_warn(subdev, "no message data available\n"); - return 0; - } - - if (size > available) { - nvkm_warn(subdev, "message data smaller than read request\n"); - size = available; - } - - nvkm_falcon_read_dmem(priv->falcon, tail, size, 0, data); - queue->position += ALIGN(size, QUEUE_ALIGNMENT); - - return size; -} - -static int -msg_queue_read(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue, - struct nvkm_msgqueue_hdr *hdr) -{ - const struct nvkm_subdev *subdev = priv->falcon->owner; - int err; - - err = msg_queue_open(priv, queue); - if (err) { - nvkm_error(subdev, "fail to open queue %d\n", queue->index); - return err; - } - - if (msg_queue_empty(priv, queue)) { - err = 0; - goto close; - } - - err = msg_queue_pop(priv, queue, hdr, HDR_SIZE); - if (err >= 0 && err != HDR_SIZE) - err = -EINVAL; - if (err < 0) { - nvkm_error(subdev, "failed to read message header: %d\n", err); - goto close; - } - - if (hdr->size > MSG_BUF_SIZE) { - nvkm_error(subdev, "message too big (%d bytes)\n", hdr->size); - err = -ENOSPC; - goto close; - } - - if (hdr->size > HDR_SIZE) { - u32 read_size = hdr->size - HDR_SIZE; - - err = msg_queue_pop(priv, queue, (hdr + 1), read_size); - if (err >= 0 && err != read_size) - err = -EINVAL; - if (err < 0) { - nvkm_error(subdev, "failed to read message: %d\n", err); - goto close; - } - } - -close: - msg_queue_close(priv, queue, (err >= 0)); - - return err; -} - -static bool -cmd_queue_has_room(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue, - u32 size, bool *rewind) -{ - struct nvkm_falcon *falcon = priv->falcon; - u32 head, tail, free; - - size = ALIGN(size, QUEUE_ALIGNMENT); - - head = nvkm_falcon_rd32(falcon, queue->head_reg); - tail = nvkm_falcon_rd32(falcon, queue->tail_reg); - - if (head >= tail) { - free = queue->offset + queue->size - head; - free -= HDR_SIZE; - - if (size > free) { - *rewind = true; - head = queue->offset; - } - } - - if (head < tail) - free = tail - head - 1; - - return size <= free; -} - -static int -cmd_queue_push(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue, - void *data, u32 size) -{ - nvkm_falcon_load_dmem(priv->falcon, data, queue->position, size, 0); - queue->position += ALIGN(size, QUEUE_ALIGNMENT); - - return 0; -} - -/* REWIND unit is always 0x00 */ -#define MSGQUEUE_UNIT_REWIND 0x00 - -static void -cmd_queue_rewind(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue) -{ - const struct nvkm_subdev *subdev = priv->falcon->owner; - struct nvkm_msgqueue_hdr cmd; - int err; - - cmd.unit_id = MSGQUEUE_UNIT_REWIND; - cmd.size = sizeof(cmd); - err = cmd_queue_push(priv, queue, &cmd, cmd.size); - if (err) - nvkm_error(subdev, "queue %d rewind failed\n", queue->index); - else - nvkm_error(subdev, "queue %d rewinded\n", queue->index); - - queue->position = queue->offset; -} - -static int -cmd_queue_open(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue, - u32 size) -{ - struct nvkm_falcon *falcon = priv->falcon; - const struct nvkm_subdev *subdev = priv->falcon->owner; - bool rewind = false; - - mutex_lock(&queue->mutex); - - if (!cmd_queue_has_room(priv, queue, size, &rewind)) { - nvkm_error(subdev, "queue full\n"); - mutex_unlock(&queue->mutex); - return -EAGAIN; - } - - queue->position = nvkm_falcon_rd32(falcon, queue->head_reg); - - if (rewind) - cmd_queue_rewind(priv, queue); - - return 0; -} - -static void -cmd_queue_close(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue, - bool commit) -{ - struct nvkm_falcon *falcon = priv->falcon; - - if (commit) - nvkm_falcon_wr32(falcon, queue->head_reg, queue->position); - - mutex_unlock(&queue->mutex); -} - -static int -cmd_write(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_hdr *cmd, - struct nvkm_msgqueue_queue *queue) -{ - const struct nvkm_subdev *subdev = priv->falcon->owner; - static unsigned timeout = 2000; - unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout); - int ret = -EAGAIN; - bool commit = true; - - while (ret == -EAGAIN && time_before(jiffies, end_jiffies)) - ret = cmd_queue_open(priv, queue, cmd->size); - if (ret) { - nvkm_error(subdev, "pmu_queue_open_write failed\n"); - return ret; - } - - ret = cmd_queue_push(priv, queue, cmd, cmd->size); - if (ret) { - nvkm_error(subdev, "pmu_queue_push failed\n"); - commit = false; - } - - cmd_queue_close(priv, queue, commit); - - return ret; -} - -static struct nvkm_msgqueue_seq * -msgqueue_seq_acquire(struct nvkm_msgqueue *priv) -{ - const struct nvkm_subdev *subdev = priv->falcon->owner; - struct nvkm_msgqueue_seq *seq; - u32 index; - - mutex_lock(&priv->seq_lock); - - index = find_first_zero_bit(priv->seq_tbl, NVKM_MSGQUEUE_NUM_SEQUENCES); - - if (index >= NVKM_MSGQUEUE_NUM_SEQUENCES) { - nvkm_error(subdev, "no free sequence available\n"); - mutex_unlock(&priv->seq_lock); - return ERR_PTR(-EAGAIN); - } - - set_bit(index, priv->seq_tbl); - - mutex_unlock(&priv->seq_lock); - - seq = &priv->seq[index]; - seq->state = SEQ_STATE_PENDING; - - return seq; -} - -static void -msgqueue_seq_release(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_seq *seq) -{ - /* no need to acquire seq_lock since clear_bit is atomic */ - seq->state = SEQ_STATE_FREE; - seq->callback = NULL; - seq->completion = NULL; - clear_bit(seq->id, priv->seq_tbl); -} - -/* specifies that we want to know the command status in the answer message */ -#define CMD_FLAGS_STATUS BIT(0) -/* specifies that we want an interrupt when the answer message is queued */ -#define CMD_FLAGS_INTR BIT(1) - -int -nvkm_msgqueue_post(struct nvkm_msgqueue *priv, enum msgqueue_msg_priority prio, - struct nvkm_msgqueue_hdr *cmd, nvkm_msgqueue_callback cb, - struct completion *completion, bool wait_init) -{ - struct nvkm_msgqueue_seq *seq; - struct nvkm_msgqueue_queue *queue; - int ret; - - if (wait_init && !wait_for_completion_timeout(&priv->init_done, - msecs_to_jiffies(1000))) - return -ETIMEDOUT; - - queue = priv->func->cmd_queue(priv, prio); - if (IS_ERR(queue)) - return PTR_ERR(queue); - - seq = msgqueue_seq_acquire(priv); - if (IS_ERR(seq)) - return PTR_ERR(seq); - - cmd->seq_id = seq->id; - cmd->ctrl_flags = CMD_FLAGS_STATUS | CMD_FLAGS_INTR; - - seq->callback = cb; - seq->state = SEQ_STATE_USED; - seq->completion = completion; - - ret = cmd_write(priv, cmd, queue); - if (ret) { - seq->state = SEQ_STATE_PENDING; - msgqueue_seq_release(priv, seq); - } - - return ret; -} - -static int -msgqueue_msg_handle(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_hdr *hdr) -{ - const struct nvkm_subdev *subdev = priv->falcon->owner; - struct nvkm_msgqueue_seq *seq; - - seq = &priv->seq[hdr->seq_id]; - if (seq->state != SEQ_STATE_USED && seq->state != SEQ_STATE_CANCELLED) { - nvkm_error(subdev, "msg for unknown sequence %d", seq->id); - return -EINVAL; - } - - if (seq->state == SEQ_STATE_USED) { - if (seq->callback) - seq->callback(priv, hdr); - } - - if (seq->completion) - complete(seq->completion); - - msgqueue_seq_release(priv, seq); - - return 0; -} - -static int -msgqueue_handle_init_msg(struct nvkm_msgqueue *priv, - struct nvkm_msgqueue_hdr *hdr) -{ - struct nvkm_falcon *falcon = priv->falcon; - const struct nvkm_subdev *subdev = falcon->owner; - u32 tail; - u32 tail_reg; - int ret; - - /* - * Of course the message queue registers vary depending on the falcon - * used... - */ - switch (falcon->owner->index) { - case NVKM_SUBDEV_PMU: - tail_reg = 0x4cc; - break; - case NVKM_ENGINE_SEC2: - tail_reg = 0xa34; - break; - default: - nvkm_error(subdev, "falcon %s unsupported for msgqueue!\n", - nvkm_subdev_name[falcon->owner->index]); - return -EINVAL; - } - - /* - * Read the message - queues are not initialized yet so we cannot rely - * on msg_queue_read() - */ - tail = nvkm_falcon_rd32(falcon, tail_reg); - nvkm_falcon_read_dmem(falcon, tail, HDR_SIZE, 0, hdr); - - if (hdr->size > MSG_BUF_SIZE) { - nvkm_error(subdev, "message too big (%d bytes)\n", hdr->size); - return -ENOSPC; - } - - nvkm_falcon_read_dmem(falcon, tail + HDR_SIZE, hdr->size - HDR_SIZE, 0, - (hdr + 1)); - - tail += ALIGN(hdr->size, QUEUE_ALIGNMENT); - nvkm_falcon_wr32(falcon, tail_reg, tail); - - ret = priv->func->init_func->init_callback(priv, hdr); - if (ret) - return ret; - - return 0; -} - -void -nvkm_msgqueue_process_msgs(struct nvkm_msgqueue *priv, - struct nvkm_msgqueue_queue *queue) -{ - /* - * We are invoked from a worker thread, so normally we have plenty of - * stack space to work with. - */ - u8 msg_buffer[MSG_BUF_SIZE]; - struct nvkm_msgqueue_hdr *hdr = (void *)msg_buffer; - int ret; - - /* the first message we receive must be the init message */ - if ((!priv->init_msg_received)) { - ret = msgqueue_handle_init_msg(priv, hdr); - if (!ret) - priv->init_msg_received = true; - } else { - while (msg_queue_read(priv, queue, hdr) > 0) - msgqueue_msg_handle(priv, hdr); - } -} - -void -nvkm_msgqueue_write_cmdline(struct nvkm_msgqueue *queue, void *buf) -{ - if (!queue || !queue->func || !queue->func->init_func) - return; - - queue->func->init_func->gen_cmdline(queue, buf); -} - -int -nvkm_msgqueue_acr_boot_falcons(struct nvkm_msgqueue *queue, - unsigned long falcon_mask) -{ - unsigned long falcon; - - if (!queue || !queue->func->acr_func) - return -ENODEV; - - /* Does the firmware support booting multiple falcons? */ - if (queue->func->acr_func->boot_multiple_falcons) - return queue->func->acr_func->boot_multiple_falcons(queue, - falcon_mask); - - /* Else boot all requested falcons individually */ - if (!queue->func->acr_func->boot_falcon) - return -ENODEV; - - for_each_set_bit(falcon, &falcon_mask, NVKM_SECBOOT_FALCON_END) { - int ret = queue->func->acr_func->boot_falcon(queue, falcon); - - if (ret) - return ret; - } - - return 0; -} - -int -nvkm_msgqueue_new(u32 version, struct nvkm_falcon *falcon, - const struct nvkm_secboot *sb, struct nvkm_msgqueue **queue) -{ - const struct nvkm_subdev *subdev = falcon->owner; - int ret = -EINVAL; - - switch (version) { - case 0x0137c63d: - ret = msgqueue_0137c63d_new(falcon, sb, queue); - break; - case 0x0137bca5: - ret = msgqueue_0137bca5_new(falcon, sb, queue); - break; - case 0x0148cdec: - case 0x015ccf3e: - case 0x0167d263: - ret = msgqueue_0148cdec_new(falcon, sb, queue); - break; - default: - nvkm_error(subdev, "unhandled firmware version 0x%08x\n", - version); - break; - } - - if (ret == 0) { - nvkm_debug(subdev, "firmware version: 0x%08x\n", version); - (*queue)->fw_version = version; - } - - return ret; -} - -void -nvkm_msgqueue_del(struct nvkm_msgqueue **queue) -{ - if (*queue) { - (*queue)->func->dtor(*queue); - *queue = NULL; - } -} - -void -nvkm_msgqueue_recv(struct nvkm_msgqueue *queue) -{ - if (!queue->func || !queue->func->recv) { - const struct nvkm_subdev *subdev = queue->falcon->owner; - - nvkm_warn(subdev, "missing msgqueue recv function\n"); - return; - } - - queue->func->recv(queue); -} - -int -nvkm_msgqueue_reinit(struct nvkm_msgqueue *queue) -{ - /* firmware not set yet... */ - if (!queue) - return 0; - - queue->init_msg_received = false; - reinit_completion(&queue->init_done); - - return 0; -} - -void -nvkm_msgqueue_ctor(const struct nvkm_msgqueue_func *func, - struct nvkm_falcon *falcon, - struct nvkm_msgqueue *queue) -{ - int i; - - queue->func = func; - queue->falcon = falcon; - mutex_init(&queue->seq_lock); - for (i = 0; i < NVKM_MSGQUEUE_NUM_SEQUENCES; i++) - queue->seq[i].id = i; - - init_completion(&queue->init_done); - - -} diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.h b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.h deleted file mode 100644 index 13b54f8d8e04..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __NVKM_CORE_FALCON_MSGQUEUE_H -#define __NVKM_CORE_FALCON_MSGQUEUE_H - -#include <core/msgqueue.h> - -/* - * The struct nvkm_msgqueue (named so for lack of better candidate) manages - * a firmware (typically, NVIDIA signed firmware) running under a given falcon. - * - * Such firmwares expect to receive commands (through one or several command - * queues) and will reply to such command by sending messages (using one - * message queue). - * - * Each firmware can support one or several units - ACR for managing secure - * falcons, PMU for power management, etc. A unit can be seen as a class to - * which command can be sent. - * - * One usage example would be to send a command to the SEC falcon to ask it to - * reset a secure falcon. The SEC falcon will receive the command, process it, - * and send a message to signal success or failure. Only when the corresponding - * message is received can the requester assume the request has been processed. - * - * Since we expect many variations between the firmwares NVIDIA will release - * across GPU generations, this library is built in a very modular way. Message - * formats and queues details (such as number of usage) are left to - * specializations of struct nvkm_msgqueue, while the functions in msgqueue.c - * take care of posting commands and processing messages in a fashion that is - * universal. - * - */ - -enum msgqueue_msg_priority { - MSGQUEUE_MSG_PRIORITY_HIGH, - MSGQUEUE_MSG_PRIORITY_LOW, -}; - -/** - * struct nvkm_msgqueue_hdr - header for all commands/messages - * @unit_id: id of firmware using receiving the command/sending the message - * @size: total size of command/message - * @ctrl_flags: type of command/message - * @seq_id: used to match a message from its corresponding command - */ -struct nvkm_msgqueue_hdr { - u8 unit_id; - u8 size; - u8 ctrl_flags; - u8 seq_id; -}; - -/** - * struct nvkm_msgqueue_msg - base message. - * - * This is just a header and a message (or command) type. Useful when - * building command-specific structures. - */ -struct nvkm_msgqueue_msg { - struct nvkm_msgqueue_hdr hdr; - u8 msg_type; -}; - -struct nvkm_msgqueue; -typedef void -(*nvkm_msgqueue_callback)(struct nvkm_msgqueue *, struct nvkm_msgqueue_hdr *); - -/** - * struct nvkm_msgqueue_init_func - msgqueue functions related to initialization - * - * @gen_cmdline: build the commandline into a pre-allocated buffer - * @init_callback: called to process the init message - */ -struct nvkm_msgqueue_init_func { - void (*gen_cmdline)(struct nvkm_msgqueue *, void *); - int (*init_callback)(struct nvkm_msgqueue *, struct nvkm_msgqueue_hdr *); -}; - -/** - * struct nvkm_msgqueue_acr_func - msgqueue functions related to ACR - * - * @boot_falcon: build and send the command to reset a given falcon - * @boot_multiple_falcons: build and send the command to reset several falcons - */ -struct nvkm_msgqueue_acr_func { - int (*boot_falcon)(struct nvkm_msgqueue *, enum nvkm_secboot_falcon); - int (*boot_multiple_falcons)(struct nvkm_msgqueue *, unsigned long); -}; - -struct nvkm_msgqueue_func { - const struct nvkm_msgqueue_init_func *init_func; - const struct nvkm_msgqueue_acr_func *acr_func; - void (*dtor)(struct nvkm_msgqueue *); - struct nvkm_msgqueue_queue *(*cmd_queue)(struct nvkm_msgqueue *, - enum msgqueue_msg_priority); - void (*recv)(struct nvkm_msgqueue *queue); -}; - -/** - * struct nvkm_msgqueue_queue - information about a command or message queue - * - * The number of queues is firmware-dependent. All queues must have their - * information filled by the init message handler. - * - * @mutex_lock: to be acquired when the queue is being used - * @index: physical queue index - * @offset: DMEM offset where this queue begins - * @size: size allocated to this queue in DMEM (in bytes) - * @position: current write position - * @head_reg: address of the HEAD register for this queue - * @tail_reg: address of the TAIL register for this queue - */ -struct nvkm_msgqueue_queue { - struct mutex mutex; - u32 index; - u32 offset; - u32 size; - u32 position; - - u32 head_reg; - u32 tail_reg; -}; - -/** - * struct nvkm_msgqueue_seq - keep track of ongoing commands - * - * Every time a command is sent, a sequence is assigned to it so the - * corresponding message can be matched. Upon receiving the message, a callback - * can be called and/or a completion signaled. - * - * @id: sequence ID - * @state: current state - * @callback: callback to call upon receiving matching message - * @completion: completion to signal after callback is called - */ -struct nvkm_msgqueue_seq { - u16 id; - enum { - SEQ_STATE_FREE = 0, - SEQ_STATE_PENDING, - SEQ_STATE_USED, - SEQ_STATE_CANCELLED - } state; - nvkm_msgqueue_callback callback; - struct completion *completion; -}; - -/* - * We can have an arbitrary number of sequences, but realistically we will - * probably not use that much simultaneously. - */ -#define NVKM_MSGQUEUE_NUM_SEQUENCES 16 - -/** - * struct nvkm_msgqueue - manage a command/message based FW on a falcon - * - * @falcon: falcon to be managed - * @func: implementation of the firmware to use - * @init_msg_received: whether the init message has already been received - * @init_done: whether all init is complete and commands can be processed - * @seq_lock: protects seq and seq_tbl - * @seq: sequences to match commands and messages - * @seq_tbl: bitmap of sequences currently in use - */ -struct nvkm_msgqueue { - struct nvkm_falcon *falcon; - const struct nvkm_msgqueue_func *func; - u32 fw_version; - bool init_msg_received; - struct completion init_done; - - struct mutex seq_lock; - struct nvkm_msgqueue_seq seq[NVKM_MSGQUEUE_NUM_SEQUENCES]; - unsigned long seq_tbl[BITS_TO_LONGS(NVKM_MSGQUEUE_NUM_SEQUENCES)]; -}; - -void nvkm_msgqueue_ctor(const struct nvkm_msgqueue_func *, struct nvkm_falcon *, - struct nvkm_msgqueue *); -int nvkm_msgqueue_post(struct nvkm_msgqueue *, enum msgqueue_msg_priority, - struct nvkm_msgqueue_hdr *, nvkm_msgqueue_callback, - struct completion *, bool); -void nvkm_msgqueue_process_msgs(struct nvkm_msgqueue *, - struct nvkm_msgqueue_queue *); - -int msgqueue_0137c63d_new(struct nvkm_falcon *, const struct nvkm_secboot *, - struct nvkm_msgqueue **); -int msgqueue_0137bca5_new(struct nvkm_falcon *, const struct nvkm_secboot *, - struct nvkm_msgqueue **); -int msgqueue_0148cdec_new(struct nvkm_falcon *, const struct nvkm_secboot *, - struct nvkm_msgqueue **); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c deleted file mode 100644 index fec0273158f6..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "msgqueue.h" -#include <engine/falcon.h> -#include <subdev/secboot.h> - -/* Queues identifiers */ -enum { - /* High Priority Command Queue for Host -> PMU communication */ - MSGQUEUE_0137C63D_COMMAND_QUEUE_HPQ = 0, - /* Low Priority Command Queue for Host -> PMU communication */ - MSGQUEUE_0137C63D_COMMAND_QUEUE_LPQ = 1, - /* Message queue for PMU -> Host communication */ - MSGQUEUE_0137C63D_MESSAGE_QUEUE = 4, - MSGQUEUE_0137C63D_NUM_QUEUES = 5, -}; - -struct msgqueue_0137c63d { - struct nvkm_msgqueue base; - - struct nvkm_msgqueue_queue queue[MSGQUEUE_0137C63D_NUM_QUEUES]; -}; -#define msgqueue_0137c63d(q) \ - container_of(q, struct msgqueue_0137c63d, base) - -struct msgqueue_0137bca5 { - struct msgqueue_0137c63d base; - - u64 wpr_addr; -}; -#define msgqueue_0137bca5(q) \ - container_of(container_of(q, struct msgqueue_0137c63d, base), \ - struct msgqueue_0137bca5, base); - -static struct nvkm_msgqueue_queue * -msgqueue_0137c63d_cmd_queue(struct nvkm_msgqueue *queue, - enum msgqueue_msg_priority priority) -{ - struct msgqueue_0137c63d *priv = msgqueue_0137c63d(queue); - const struct nvkm_subdev *subdev = priv->base.falcon->owner; - - switch (priority) { - case MSGQUEUE_MSG_PRIORITY_HIGH: - return &priv->queue[MSGQUEUE_0137C63D_COMMAND_QUEUE_HPQ]; - case MSGQUEUE_MSG_PRIORITY_LOW: - return &priv->queue[MSGQUEUE_0137C63D_COMMAND_QUEUE_LPQ]; - default: - nvkm_error(subdev, "invalid command queue!\n"); - return ERR_PTR(-EINVAL); - } -} - -static void -msgqueue_0137c63d_process_msgs(struct nvkm_msgqueue *queue) -{ - struct msgqueue_0137c63d *priv = msgqueue_0137c63d(queue); - struct nvkm_msgqueue_queue *q_queue = - &priv->queue[MSGQUEUE_0137C63D_MESSAGE_QUEUE]; - - nvkm_msgqueue_process_msgs(&priv->base, q_queue); -} - -/* Init unit */ -#define MSGQUEUE_0137C63D_UNIT_INIT 0x07 - -enum { - INIT_MSG_INIT = 0x0, -}; - -static void -init_gen_cmdline(struct nvkm_msgqueue *queue, void *buf) -{ - struct { - u32 reserved; - u32 freq_hz; - u32 trace_size; - u32 trace_dma_base; - u16 trace_dma_base1; - u8 trace_dma_offset; - u32 trace_dma_idx; - bool secure_mode; - bool raise_priv_sec; - struct { - u32 dma_base; - u16 dma_base1; - u8 dma_offset; - u16 fb_size; - u8 dma_idx; - } gc6_ctx; - u8 pad; - } *args = buf; - - args->secure_mode = 1; -} - -/* forward declaration */ -static int acr_init_wpr(struct nvkm_msgqueue *queue); - -static int -init_callback(struct nvkm_msgqueue *_queue, struct nvkm_msgqueue_hdr *hdr) -{ - struct msgqueue_0137c63d *priv = msgqueue_0137c63d(_queue); - struct { - struct nvkm_msgqueue_msg base; - - u8 pad; - u16 os_debug_entry_point; - - struct { - u16 size; - u16 offset; - u8 index; - u8 pad; - } queue_info[MSGQUEUE_0137C63D_NUM_QUEUES]; - - u16 sw_managed_area_offset; - u16 sw_managed_area_size; - } *init = (void *)hdr; - const struct nvkm_subdev *subdev = _queue->falcon->owner; - int i; - - if (init->base.hdr.unit_id != MSGQUEUE_0137C63D_UNIT_INIT) { - nvkm_error(subdev, "expected message from init unit\n"); - return -EINVAL; - } - - if (init->base.msg_type != INIT_MSG_INIT) { - nvkm_error(subdev, "expected PMU init msg\n"); - return -EINVAL; - } - - for (i = 0; i < MSGQUEUE_0137C63D_NUM_QUEUES; i++) { - struct nvkm_msgqueue_queue *queue = &priv->queue[i]; - - mutex_init(&queue->mutex); - - queue->index = init->queue_info[i].index; - queue->offset = init->queue_info[i].offset; - queue->size = init->queue_info[i].size; - - if (i != MSGQUEUE_0137C63D_MESSAGE_QUEUE) { - queue->head_reg = 0x4a0 + (queue->index * 4); - queue->tail_reg = 0x4b0 + (queue->index * 4); - } else { - queue->head_reg = 0x4c8; - queue->tail_reg = 0x4cc; - } - - nvkm_debug(subdev, - "queue %d: index %d, offset 0x%08x, size 0x%08x\n", - i, queue->index, queue->offset, queue->size); - } - - /* Complete initialization by initializing WPR region */ - return acr_init_wpr(&priv->base); -} - -static const struct nvkm_msgqueue_init_func -msgqueue_0137c63d_init_func = { - .gen_cmdline = init_gen_cmdline, - .init_callback = init_callback, -}; - - - -/* ACR unit */ -#define MSGQUEUE_0137C63D_UNIT_ACR 0x0a - -enum { - ACR_CMD_INIT_WPR_REGION = 0x00, - ACR_CMD_BOOTSTRAP_FALCON = 0x01, - ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS = 0x03, -}; - -static void -acr_init_wpr_callback(struct nvkm_msgqueue *queue, - struct nvkm_msgqueue_hdr *hdr) -{ - struct { - struct nvkm_msgqueue_msg base; - u32 error_code; - } *msg = (void *)hdr; - const struct nvkm_subdev *subdev = queue->falcon->owner; - - if (msg->error_code) { - nvkm_error(subdev, "ACR WPR init failure: %d\n", - msg->error_code); - return; - } - - nvkm_debug(subdev, "ACR WPR init complete\n"); - complete_all(&queue->init_done); -} - -static int -acr_init_wpr(struct nvkm_msgqueue *queue) -{ - /* - * region_id: region ID in WPR region - * wpr_offset: offset in WPR region - */ - struct { - struct nvkm_msgqueue_hdr hdr; - u8 cmd_type; - u32 region_id; - u32 wpr_offset; - } cmd; - memset(&cmd, 0, sizeof(cmd)); - - cmd.hdr.unit_id = MSGQUEUE_0137C63D_UNIT_ACR; - cmd.hdr.size = sizeof(cmd); - cmd.cmd_type = ACR_CMD_INIT_WPR_REGION; - cmd.region_id = 0x01; - cmd.wpr_offset = 0x00; - - nvkm_msgqueue_post(queue, MSGQUEUE_MSG_PRIORITY_HIGH, &cmd.hdr, - acr_init_wpr_callback, NULL, false); - - return 0; -} - - -static void -acr_boot_falcon_callback(struct nvkm_msgqueue *priv, - struct nvkm_msgqueue_hdr *hdr) -{ - struct acr_bootstrap_falcon_msg { - struct nvkm_msgqueue_msg base; - - u32 falcon_id; - } *msg = (void *)hdr; - const struct nvkm_subdev *subdev = priv->falcon->owner; - u32 falcon_id = msg->falcon_id; - - if (falcon_id >= NVKM_SECBOOT_FALCON_END) { - nvkm_error(subdev, "in bootstrap falcon callback:\n"); - nvkm_error(subdev, "invalid falcon ID 0x%x\n", falcon_id); - return; - } - nvkm_debug(subdev, "%s booted\n", nvkm_secboot_falcon_name[falcon_id]); -} - -enum { - ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES = 0, - ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO = 1, -}; - -static int -acr_boot_falcon(struct nvkm_msgqueue *priv, enum nvkm_secboot_falcon falcon) -{ - DECLARE_COMPLETION_ONSTACK(completed); - /* - * flags - Flag specifying RESET or no RESET. - * falcon id - Falcon id specifying falcon to bootstrap. - */ - struct { - struct nvkm_msgqueue_hdr hdr; - u8 cmd_type; - u32 flags; - u32 falcon_id; - } cmd; - - memset(&cmd, 0, sizeof(cmd)); - - cmd.hdr.unit_id = MSGQUEUE_0137C63D_UNIT_ACR; - cmd.hdr.size = sizeof(cmd); - cmd.cmd_type = ACR_CMD_BOOTSTRAP_FALCON; - cmd.flags = ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; - cmd.falcon_id = falcon; - nvkm_msgqueue_post(priv, MSGQUEUE_MSG_PRIORITY_HIGH, &cmd.hdr, - acr_boot_falcon_callback, &completed, true); - - if (!wait_for_completion_timeout(&completed, msecs_to_jiffies(1000))) - return -ETIMEDOUT; - - return 0; -} - -static void -acr_boot_multiple_falcons_callback(struct nvkm_msgqueue *priv, - struct nvkm_msgqueue_hdr *hdr) -{ - struct acr_bootstrap_falcon_msg { - struct nvkm_msgqueue_msg base; - - u32 falcon_mask; - } *msg = (void *)hdr; - const struct nvkm_subdev *subdev = priv->falcon->owner; - unsigned long falcon_mask = msg->falcon_mask; - u32 falcon_id, falcon_treated = 0; - - for_each_set_bit(falcon_id, &falcon_mask, NVKM_SECBOOT_FALCON_END) { - nvkm_debug(subdev, "%s booted\n", - nvkm_secboot_falcon_name[falcon_id]); - falcon_treated |= BIT(falcon_id); - } - - if (falcon_treated != msg->falcon_mask) { - nvkm_error(subdev, "in bootstrap falcon callback:\n"); - nvkm_error(subdev, "invalid falcon mask 0x%x\n", - msg->falcon_mask); - return; - } -} - -static int -acr_boot_multiple_falcons(struct nvkm_msgqueue *priv, unsigned long falcon_mask) -{ - DECLARE_COMPLETION_ONSTACK(completed); - /* - * flags - Flag specifying RESET or no RESET. - * falcon id - Falcon id specifying falcon to bootstrap. - */ - struct { - struct nvkm_msgqueue_hdr hdr; - u8 cmd_type; - u32 flags; - u32 falcon_mask; - u32 use_va_mask; - u32 wpr_lo; - u32 wpr_hi; - } cmd; - struct msgqueue_0137bca5 *queue = msgqueue_0137bca5(priv); - - memset(&cmd, 0, sizeof(cmd)); - - cmd.hdr.unit_id = MSGQUEUE_0137C63D_UNIT_ACR; - cmd.hdr.size = sizeof(cmd); - cmd.cmd_type = ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS; - cmd.flags = ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; - cmd.falcon_mask = falcon_mask; - cmd.wpr_lo = lower_32_bits(queue->wpr_addr); - cmd.wpr_hi = upper_32_bits(queue->wpr_addr); - nvkm_msgqueue_post(priv, MSGQUEUE_MSG_PRIORITY_HIGH, &cmd.hdr, - acr_boot_multiple_falcons_callback, &completed, true); - - if (!wait_for_completion_timeout(&completed, msecs_to_jiffies(1000))) - return -ETIMEDOUT; - - return 0; -} - -static const struct nvkm_msgqueue_acr_func -msgqueue_0137c63d_acr_func = { - .boot_falcon = acr_boot_falcon, -}; - -static const struct nvkm_msgqueue_acr_func -msgqueue_0137bca5_acr_func = { - .boot_falcon = acr_boot_falcon, - .boot_multiple_falcons = acr_boot_multiple_falcons, -}; - -static void -msgqueue_0137c63d_dtor(struct nvkm_msgqueue *queue) -{ - kfree(msgqueue_0137c63d(queue)); -} - -static const struct nvkm_msgqueue_func -msgqueue_0137c63d_func = { - .init_func = &msgqueue_0137c63d_init_func, - .acr_func = &msgqueue_0137c63d_acr_func, - .cmd_queue = msgqueue_0137c63d_cmd_queue, - .recv = msgqueue_0137c63d_process_msgs, - .dtor = msgqueue_0137c63d_dtor, -}; - -int -msgqueue_0137c63d_new(struct nvkm_falcon *falcon, const struct nvkm_secboot *sb, - struct nvkm_msgqueue **queue) -{ - struct msgqueue_0137c63d *ret; - - ret = kzalloc(sizeof(*ret), GFP_KERNEL); - if (!ret) - return -ENOMEM; - - *queue = &ret->base; - - nvkm_msgqueue_ctor(&msgqueue_0137c63d_func, falcon, &ret->base); - - return 0; -} - -static const struct nvkm_msgqueue_func -msgqueue_0137bca5_func = { - .init_func = &msgqueue_0137c63d_init_func, - .acr_func = &msgqueue_0137bca5_acr_func, - .cmd_queue = msgqueue_0137c63d_cmd_queue, - .recv = msgqueue_0137c63d_process_msgs, - .dtor = msgqueue_0137c63d_dtor, -}; - -int -msgqueue_0137bca5_new(struct nvkm_falcon *falcon, const struct nvkm_secboot *sb, - struct nvkm_msgqueue **queue) -{ - struct msgqueue_0137bca5 *ret; - - ret = kzalloc(sizeof(*ret), GFP_KERNEL); - if (!ret) - return -ENOMEM; - - *queue = &ret->base.base; - - /* - * FIXME this must be set to the address of a *GPU* mapping within the - * ACR address space! - */ - /* ret->wpr_addr = sb->wpr_addr; */ - - nvkm_msgqueue_ctor(&msgqueue_0137bca5_func, falcon, &ret->base.base); - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c deleted file mode 100644 index 9424803b9ef4..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "msgqueue.h" -#include <engine/falcon.h> -#include <subdev/secboot.h> - -/* - * This firmware runs on the SEC falcon. It only has one command and one - * message queue, and uses a different command line and init message. - */ - -enum { - MSGQUEUE_0148CDEC_COMMAND_QUEUE = 0, - MSGQUEUE_0148CDEC_MESSAGE_QUEUE = 1, - MSGQUEUE_0148CDEC_NUM_QUEUES, -}; - -struct msgqueue_0148cdec { - struct nvkm_msgqueue base; - - struct nvkm_msgqueue_queue queue[MSGQUEUE_0148CDEC_NUM_QUEUES]; -}; -#define msgqueue_0148cdec(q) \ - container_of(q, struct msgqueue_0148cdec, base) - -static struct nvkm_msgqueue_queue * -msgqueue_0148cdec_cmd_queue(struct nvkm_msgqueue *queue, - enum msgqueue_msg_priority priority) -{ - struct msgqueue_0148cdec *priv = msgqueue_0148cdec(queue); - - return &priv->queue[MSGQUEUE_0148CDEC_COMMAND_QUEUE]; -} - -static void -msgqueue_0148cdec_process_msgs(struct nvkm_msgqueue *queue) -{ - struct msgqueue_0148cdec *priv = msgqueue_0148cdec(queue); - struct nvkm_msgqueue_queue *q_queue = - &priv->queue[MSGQUEUE_0148CDEC_MESSAGE_QUEUE]; - - nvkm_msgqueue_process_msgs(&priv->base, q_queue); -} - - -/* Init unit */ -#define MSGQUEUE_0148CDEC_UNIT_INIT 0x01 - -enum { - INIT_MSG_INIT = 0x0, -}; - -static void -init_gen_cmdline(struct nvkm_msgqueue *queue, void *buf) -{ - struct { - u32 freq_hz; - u32 falc_trace_size; - u32 falc_trace_dma_base; - u32 falc_trace_dma_idx; - bool secure_mode; - } *args = buf; - - args->secure_mode = false; -} - -static int -init_callback(struct nvkm_msgqueue *_queue, struct nvkm_msgqueue_hdr *hdr) -{ - struct msgqueue_0148cdec *priv = msgqueue_0148cdec(_queue); - struct { - struct nvkm_msgqueue_msg base; - - u8 num_queues; - u16 os_debug_entry_point; - - struct { - u32 offset; - u16 size; - u8 index; - u8 id; - } queue_info[MSGQUEUE_0148CDEC_NUM_QUEUES]; - - u16 sw_managed_area_offset; - u16 sw_managed_area_size; - } *init = (void *)hdr; - const struct nvkm_subdev *subdev = _queue->falcon->owner; - int i; - - if (init->base.hdr.unit_id != MSGQUEUE_0148CDEC_UNIT_INIT) { - nvkm_error(subdev, "expected message from init unit\n"); - return -EINVAL; - } - - if (init->base.msg_type != INIT_MSG_INIT) { - nvkm_error(subdev, "expected SEC init msg\n"); - return -EINVAL; - } - - for (i = 0; i < MSGQUEUE_0148CDEC_NUM_QUEUES; i++) { - u8 id = init->queue_info[i].id; - struct nvkm_msgqueue_queue *queue = &priv->queue[id]; - - mutex_init(&queue->mutex); - - queue->index = init->queue_info[i].index; - queue->offset = init->queue_info[i].offset; - queue->size = init->queue_info[i].size; - - if (id == MSGQUEUE_0148CDEC_MESSAGE_QUEUE) { - queue->head_reg = 0xa30 + (queue->index * 8); - queue->tail_reg = 0xa34 + (queue->index * 8); - } else { - queue->head_reg = 0xa00 + (queue->index * 8); - queue->tail_reg = 0xa04 + (queue->index * 8); - } - - nvkm_debug(subdev, - "queue %d: index %d, offset 0x%08x, size 0x%08x\n", - id, queue->index, queue->offset, queue->size); - } - - complete_all(&_queue->init_done); - - return 0; -} - -static const struct nvkm_msgqueue_init_func -msgqueue_0148cdec_init_func = { - .gen_cmdline = init_gen_cmdline, - .init_callback = init_callback, -}; - - - -/* ACR unit */ -#define MSGQUEUE_0148CDEC_UNIT_ACR 0x08 - -enum { - ACR_CMD_BOOTSTRAP_FALCON = 0x00, -}; - -static void -acr_boot_falcon_callback(struct nvkm_msgqueue *priv, - struct nvkm_msgqueue_hdr *hdr) -{ - struct acr_bootstrap_falcon_msg { - struct nvkm_msgqueue_msg base; - - u32 error_code; - u32 falcon_id; - } *msg = (void *)hdr; - const struct nvkm_subdev *subdev = priv->falcon->owner; - u32 falcon_id = msg->falcon_id; - - if (msg->error_code) { - nvkm_error(subdev, "in bootstrap falcon callback:\n"); - nvkm_error(subdev, "expected error code 0x%x\n", - msg->error_code); - return; - } - - if (falcon_id >= NVKM_SECBOOT_FALCON_END) { - nvkm_error(subdev, "in bootstrap falcon callback:\n"); - nvkm_error(subdev, "invalid falcon ID 0x%x\n", falcon_id); - return; - } - - nvkm_debug(subdev, "%s booted\n", nvkm_secboot_falcon_name[falcon_id]); -} - -enum { - ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES = 0, - ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO = 1, -}; - -static int -acr_boot_falcon(struct nvkm_msgqueue *priv, enum nvkm_secboot_falcon falcon) -{ - DECLARE_COMPLETION_ONSTACK(completed); - /* - * flags - Flag specifying RESET or no RESET. - * falcon id - Falcon id specifying falcon to bootstrap. - */ - struct { - struct nvkm_msgqueue_hdr hdr; - u8 cmd_type; - u32 flags; - u32 falcon_id; - } cmd; - - memset(&cmd, 0, sizeof(cmd)); - - cmd.hdr.unit_id = MSGQUEUE_0148CDEC_UNIT_ACR; - cmd.hdr.size = sizeof(cmd); - cmd.cmd_type = ACR_CMD_BOOTSTRAP_FALCON; - cmd.flags = ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; - cmd.falcon_id = falcon; - nvkm_msgqueue_post(priv, MSGQUEUE_MSG_PRIORITY_HIGH, &cmd.hdr, - acr_boot_falcon_callback, &completed, true); - - if (!wait_for_completion_timeout(&completed, msecs_to_jiffies(1000))) - return -ETIMEDOUT; - - return 0; -} - -const struct nvkm_msgqueue_acr_func -msgqueue_0148cdec_acr_func = { - .boot_falcon = acr_boot_falcon, -}; - -static void -msgqueue_0148cdec_dtor(struct nvkm_msgqueue *queue) -{ - kfree(msgqueue_0148cdec(queue)); -} - -const struct nvkm_msgqueue_func -msgqueue_0148cdec_func = { - .init_func = &msgqueue_0148cdec_init_func, - .acr_func = &msgqueue_0148cdec_acr_func, - .cmd_queue = msgqueue_0148cdec_cmd_queue, - .recv = msgqueue_0148cdec_process_msgs, - .dtor = msgqueue_0148cdec_dtor, -}; - -int -msgqueue_0148cdec_new(struct nvkm_falcon *falcon, const struct nvkm_secboot *sb, - struct nvkm_msgqueue **queue) -{ - struct msgqueue_0148cdec *ret; - - ret = kzalloc(sizeof(*ret), GFP_KERNEL); - if (!ret) - return -ENOMEM; - - *queue = &ret->base; - - nvkm_msgqueue_ctor(&msgqueue_0148cdec_func, falcon, &ret->base); - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/priv.h b/drivers/gpu/drm/nouveau/nvkm/falcon/priv.h index 900fe1d37b4d..466188752eb0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/priv.h @@ -1,9 +1,5 @@ /* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FALCON_PRIV_H__ #define __NVKM_FALCON_PRIV_H__ -#include <engine/falcon.h> - -void -nvkm_falcon_ctor(const struct nvkm_falcon_func *, struct nvkm_subdev *, - const char *, u32, struct nvkm_falcon *); +#include <core/falcon.h> #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.c b/drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.c new file mode 100644 index 000000000000..a453de341a75 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "qmgr.h" + +struct nvkm_falcon_qmgr_seq * +nvkm_falcon_qmgr_seq_acquire(struct nvkm_falcon_qmgr *qmgr) +{ + const struct nvkm_subdev *subdev = qmgr->falcon->owner; + struct nvkm_falcon_qmgr_seq *seq; + u32 index; + + mutex_lock(&qmgr->seq.mutex); + index = find_first_zero_bit(qmgr->seq.tbl, NVKM_FALCON_QMGR_SEQ_NUM); + if (index >= NVKM_FALCON_QMGR_SEQ_NUM) { + nvkm_error(subdev, "no free sequence available\n"); + mutex_unlock(&qmgr->seq.mutex); + return ERR_PTR(-EAGAIN); + } + + set_bit(index, qmgr->seq.tbl); + mutex_unlock(&qmgr->seq.mutex); + + seq = &qmgr->seq.id[index]; + seq->state = SEQ_STATE_PENDING; + return seq; +} + +void +nvkm_falcon_qmgr_seq_release(struct nvkm_falcon_qmgr *qmgr, + struct nvkm_falcon_qmgr_seq *seq) +{ + /* no need to acquire seq.mutex since clear_bit is atomic */ + seq->state = SEQ_STATE_FREE; + seq->callback = NULL; + reinit_completion(&seq->done); + clear_bit(seq->id, qmgr->seq.tbl); +} + +void +nvkm_falcon_qmgr_del(struct nvkm_falcon_qmgr **pqmgr) +{ + struct nvkm_falcon_qmgr *qmgr = *pqmgr; + if (qmgr) { + kfree(*pqmgr); + *pqmgr = NULL; + } +} + +int +nvkm_falcon_qmgr_new(struct nvkm_falcon *falcon, + struct nvkm_falcon_qmgr **pqmgr) +{ + struct nvkm_falcon_qmgr *qmgr; + int i; + + if (!(qmgr = *pqmgr = kzalloc(sizeof(*qmgr), GFP_KERNEL))) + return -ENOMEM; + + qmgr->falcon = falcon; + mutex_init(&qmgr->seq.mutex); + for (i = 0; i < NVKM_FALCON_QMGR_SEQ_NUM; i++) { + qmgr->seq.id[i].id = i; + init_completion(&qmgr->seq.id[i].done); + } + + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.h b/drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.h new file mode 100644 index 000000000000..976cb7b7aa99 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVKM_FALCON_QMGR_H__ +#define __NVKM_FALCON_QMGR_H__ +#include <core/falcon.h> + +#define HDR_SIZE sizeof(struct nvfw_falcon_msg) +#define QUEUE_ALIGNMENT 4 +/* max size of the messages we can receive */ +#define MSG_BUF_SIZE 128 + +/** + * struct nvkm_falcon_qmgr_seq - keep track of ongoing commands + * + * Every time a command is sent, a sequence is assigned to it so the + * corresponding message can be matched. Upon receiving the message, a callback + * can be called and/or a completion signaled. + * + * @id: sequence ID + * @state: current state + * @callback: callback to call upon receiving matching message + * @completion: completion to signal after callback is called + */ +struct nvkm_falcon_qmgr_seq { + u16 id; + enum { + SEQ_STATE_FREE = 0, + SEQ_STATE_PENDING, + SEQ_STATE_USED, + SEQ_STATE_CANCELLED + } state; + bool async; + nvkm_falcon_qmgr_callback callback; + void *priv; + struct completion done; + int result; +}; + +/* + * We can have an arbitrary number of sequences, but realistically we will + * probably not use that much simultaneously. + */ +#define NVKM_FALCON_QMGR_SEQ_NUM 16 + +struct nvkm_falcon_qmgr { + struct nvkm_falcon *falcon; + + struct { + struct mutex mutex; + struct nvkm_falcon_qmgr_seq id[NVKM_FALCON_QMGR_SEQ_NUM]; + unsigned long tbl[BITS_TO_LONGS(NVKM_FALCON_QMGR_SEQ_NUM)]; + } seq; +}; + +struct nvkm_falcon_qmgr_seq * +nvkm_falcon_qmgr_seq_acquire(struct nvkm_falcon_qmgr *); +void nvkm_falcon_qmgr_seq_release(struct nvkm_falcon_qmgr *, + struct nvkm_falcon_qmgr_seq *); + +struct nvkm_falcon_cmdq { + struct nvkm_falcon_qmgr *qmgr; + const char *name; + struct mutex mutex; + struct completion ready; + + u32 head_reg; + u32 tail_reg; + u32 offset; + u32 size; + + u32 position; +}; + +struct nvkm_falcon_msgq { + struct nvkm_falcon_qmgr *qmgr; + const char *name; + struct mutex mutex; + + u32 head_reg; + u32 tail_reg; + u32 offset; + + u32 position; +}; + +#define FLCNQ_PRINTK(t,q,f,a...) \ + FLCN_PRINTK(t, (q)->qmgr->falcon, "%s: "f, (q)->name, ##a) +#define FLCNQ_DBG(q,f,a...) FLCNQ_PRINTK(debug, (q), f, ##a) +#define FLCNQ_ERR(q,f,a...) FLCNQ_PRINTK(error, (q), f, ##a) +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c b/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c index 6d978feebbd7..1ff9b9c2e651 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c @@ -25,7 +25,7 @@ #include <core/memory.h> #include <subdev/timer.h> -static void +void nvkm_falcon_v1_load_imem(struct nvkm_falcon *falcon, void *data, u32 start, u32 size, u16 tag, u8 port, bool secure) { @@ -89,18 +89,17 @@ nvkm_falcon_v1_load_emem(struct nvkm_falcon *falcon, void *data, u32 start, } } -static const u32 EMEM_START_ADDR = 0x1000000; - -static void +void nvkm_falcon_v1_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start, - u32 size, u8 port) + u32 size, u8 port) { + const struct nvkm_falcon_func *func = falcon->func; u8 rem = size % 4; int i; - if (start >= EMEM_START_ADDR && falcon->has_emem) + if (func->emem_addr && start >= func->emem_addr) return nvkm_falcon_v1_load_emem(falcon, data, - start - EMEM_START_ADDR, size, + start - func->emem_addr, size, port); size -= rem; @@ -148,15 +147,16 @@ nvkm_falcon_v1_read_emem(struct nvkm_falcon *falcon, u32 start, u32 size, } } -static void +void nvkm_falcon_v1_read_dmem(struct nvkm_falcon *falcon, u32 start, u32 size, u8 port, void *data) { + const struct nvkm_falcon_func *func = falcon->func; u8 rem = size % 4; int i; - if (start >= EMEM_START_ADDR && falcon->has_emem) - return nvkm_falcon_v1_read_emem(falcon, start - EMEM_START_ADDR, + if (func->emem_addr && start >= func->emem_addr) + return nvkm_falcon_v1_read_emem(falcon, start - func->emem_addr, size, port, data); size -= rem; @@ -179,12 +179,11 @@ nvkm_falcon_v1_read_dmem(struct nvkm_falcon *falcon, u32 start, u32 size, } } -static void +void nvkm_falcon_v1_bind_context(struct nvkm_falcon *falcon, struct nvkm_memory *ctx) { - struct nvkm_device *device = falcon->owner->device; + const u32 fbif = falcon->func->fbif; u32 inst_loc; - u32 fbif; /* disable instance block binding */ if (ctx == NULL) { @@ -192,20 +191,6 @@ nvkm_falcon_v1_bind_context(struct nvkm_falcon *falcon, struct nvkm_memory *ctx) return; } - switch (falcon->owner->index) { - case NVKM_ENGINE_NVENC0: - case NVKM_ENGINE_NVENC1: - case NVKM_ENGINE_NVENC2: - fbif = 0x800; - break; - case NVKM_SUBDEV_PMU: - fbif = 0xe00; - break; - default: - fbif = 0x600; - break; - } - nvkm_falcon_wr32(falcon, 0x10c, 0x1); /* setup apertures - virtual */ @@ -234,50 +219,15 @@ nvkm_falcon_v1_bind_context(struct nvkm_falcon *falcon, struct nvkm_memory *ctx) nvkm_falcon_mask(falcon, 0x090, 0x10000, 0x10000); nvkm_falcon_mask(falcon, 0x0a4, 0x8, 0x8); - - /* Not sure if this is a WAR for a HW issue, or some additional - * programming sequence that's needed to properly complete the - * context switch we trigger above. - * - * Fixes unreliability of booting the SEC2 RTOS on Quadro P620, - * particularly when resuming from suspend. - * - * Also removes the need for an odd workaround where we needed - * to program SEC2's FALCON_CPUCTL_ALIAS_STARTCPU twice before - * the SEC2 RTOS would begin executing. - */ - switch (falcon->owner->index) { - case NVKM_SUBDEV_GSP: - case NVKM_ENGINE_SEC2: - nvkm_msec(device, 10, - u32 irqstat = nvkm_falcon_rd32(falcon, 0x008); - u32 flcn0dc = nvkm_falcon_rd32(falcon, 0x0dc); - if ((irqstat & 0x00000008) && - (flcn0dc & 0x00007000) == 0x00005000) - break; - ); - - nvkm_falcon_mask(falcon, 0x004, 0x00000008, 0x00000008); - nvkm_falcon_mask(falcon, 0x058, 0x00000002, 0x00000002); - - nvkm_msec(device, 10, - u32 flcn0dc = nvkm_falcon_rd32(falcon, 0x0dc); - if ((flcn0dc & 0x00007000) == 0x00000000) - break; - ); - break; - default: - break; - } } -static void +void nvkm_falcon_v1_set_start_addr(struct nvkm_falcon *falcon, u32 start_addr) { nvkm_falcon_wr32(falcon, 0x104, start_addr); } -static void +void nvkm_falcon_v1_start(struct nvkm_falcon *falcon) { u32 reg = nvkm_falcon_rd32(falcon, 0x100); @@ -288,7 +238,7 @@ nvkm_falcon_v1_start(struct nvkm_falcon *falcon) nvkm_falcon_wr32(falcon, 0x100, 0x2); } -static int +int nvkm_falcon_v1_wait_for_halt(struct nvkm_falcon *falcon, u32 ms) { struct nvkm_device *device = falcon->owner->device; @@ -301,7 +251,7 @@ nvkm_falcon_v1_wait_for_halt(struct nvkm_falcon *falcon, u32 ms) return 0; } -static int +int nvkm_falcon_v1_clear_interrupt(struct nvkm_falcon *falcon, u32 mask) { struct nvkm_device *device = falcon->owner->device; @@ -330,7 +280,7 @@ falcon_v1_wait_idle(struct nvkm_falcon *falcon) return 0; } -static int +int nvkm_falcon_v1_enable(struct nvkm_falcon *falcon) { struct nvkm_device *device = falcon->owner->device; @@ -352,7 +302,7 @@ nvkm_falcon_v1_enable(struct nvkm_falcon *falcon) return 0; } -static void +void nvkm_falcon_v1_disable(struct nvkm_falcon *falcon) { /* disable IRQs and wait for any previous code to complete */ diff --git a/drivers/gpu/drm/nouveau/nvkm/nvfw/Kbuild b/drivers/gpu/drm/nouveau/nvkm/nvfw/Kbuild new file mode 100644 index 000000000000..41d75f98e603 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/nvfw/Kbuild @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: MIT +nvkm-y += nvkm/nvfw/fw.o +nvkm-y += nvkm/nvfw/hs.o +nvkm-y += nvkm/nvfw/ls.o + +nvkm-y += nvkm/nvfw/acr.o +nvkm-y += nvkm/nvfw/flcn.o diff --git a/drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c b/drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c new file mode 100644 index 000000000000..bef790ad8f2f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c @@ -0,0 +1,164 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include <core/subdev.h> +#include <nvfw/acr.h> + +void +wpr_header_dump(struct nvkm_subdev *subdev, const struct wpr_header *hdr) +{ + nvkm_debug(subdev, "wprHeader\n"); + nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id); + nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset); + nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner); + nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap); + nvkm_debug(subdev, "\tstatus : %d\n", hdr->status); +} + +void +wpr_header_v1_dump(struct nvkm_subdev *subdev, const struct wpr_header_v1 *hdr) +{ + nvkm_debug(subdev, "wprHeader\n"); + nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id); + nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset); + nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner); + nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap); + nvkm_debug(subdev, "\tbinVersion : %d\n", hdr->bin_version); + nvkm_debug(subdev, "\tstatus : %d\n", hdr->status); +} + +static void +lsb_header_tail_dump(struct nvkm_subdev *subdev, struct lsb_header_tail *hdr) +{ + nvkm_debug(subdev, "lsbHeader\n"); + nvkm_debug(subdev, "\tucodeOff : 0x%x\n", hdr->ucode_off); + nvkm_debug(subdev, "\tucodeSize : 0x%x\n", hdr->ucode_size); + nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); + nvkm_debug(subdev, "\tblCodeSize : 0x%x\n", hdr->bl_code_size); + nvkm_debug(subdev, "\tblImemOff : 0x%x\n", hdr->bl_imem_off); + nvkm_debug(subdev, "\tblDataOff : 0x%x\n", hdr->bl_data_off); + nvkm_debug(subdev, "\tblDataSize : 0x%x\n", hdr->bl_data_size); + nvkm_debug(subdev, "\tappCodeOff : 0x%x\n", hdr->app_code_off); + nvkm_debug(subdev, "\tappCodeSize : 0x%x\n", hdr->app_code_size); + nvkm_debug(subdev, "\tappDataOff : 0x%x\n", hdr->app_data_off); + nvkm_debug(subdev, "\tappDataSize : 0x%x\n", hdr->app_data_size); + nvkm_debug(subdev, "\tflags : 0x%x\n", hdr->flags); +} + +void +lsb_header_dump(struct nvkm_subdev *subdev, struct lsb_header *hdr) +{ + lsb_header_tail_dump(subdev, &hdr->tail); +} + +void +lsb_header_v1_dump(struct nvkm_subdev *subdev, struct lsb_header_v1 *hdr) +{ + lsb_header_tail_dump(subdev, &hdr->tail); +} + +void +flcn_acr_desc_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc *hdr) +{ + int i; + + nvkm_debug(subdev, "acrDesc\n"); + nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id); + nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset); + nvkm_debug(subdev, "\tmmuMemRange : 0x%x\n", + hdr->mmu_mem_range); + nvkm_debug(subdev, "\tnoRegions : %d\n", + hdr->regions.no_regions); + + for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) { + nvkm_debug(subdev, "\tregion[%d] :\n", i); + nvkm_debug(subdev, "\t startAddr : 0x%x\n", + hdr->regions.region_props[i].start_addr); + nvkm_debug(subdev, "\t endAddr : 0x%x\n", + hdr->regions.region_props[i].end_addr); + nvkm_debug(subdev, "\t regionId : %d\n", + hdr->regions.region_props[i].region_id); + nvkm_debug(subdev, "\t readMask : 0x%x\n", + hdr->regions.region_props[i].read_mask); + nvkm_debug(subdev, "\t writeMask : 0x%x\n", + hdr->regions.region_props[i].write_mask); + nvkm_debug(subdev, "\t clientMask : 0x%x\n", + hdr->regions.region_props[i].client_mask); + } + + nvkm_debug(subdev, "\tucodeBlobSize: %d\n", + hdr->ucode_blob_size); + nvkm_debug(subdev, "\tucodeBlobBase: 0x%llx\n", + hdr->ucode_blob_base); + nvkm_debug(subdev, "\tvprEnabled : %d\n", + hdr->vpr_desc.vpr_enabled); + nvkm_debug(subdev, "\tvprStart : 0x%x\n", + hdr->vpr_desc.vpr_start); + nvkm_debug(subdev, "\tvprEnd : 0x%x\n", + hdr->vpr_desc.vpr_end); + nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n", + hdr->vpr_desc.hdcp_policies); +} + +void +flcn_acr_desc_v1_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc_v1 *hdr) +{ + int i; + + nvkm_debug(subdev, "acrDesc\n"); + nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id); + nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset); + nvkm_debug(subdev, "\tmmuMemoryRange : 0x%x\n", + hdr->mmu_memory_range); + nvkm_debug(subdev, "\tnoRegions : %d\n", + hdr->regions.no_regions); + + for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) { + nvkm_debug(subdev, "\tregion[%d] :\n", i); + nvkm_debug(subdev, "\t startAddr : 0x%x\n", + hdr->regions.region_props[i].start_addr); + nvkm_debug(subdev, "\t endAddr : 0x%x\n", + hdr->regions.region_props[i].end_addr); + nvkm_debug(subdev, "\t regionId : %d\n", + hdr->regions.region_props[i].region_id); + nvkm_debug(subdev, "\t readMask : 0x%x\n", + hdr->regions.region_props[i].read_mask); + nvkm_debug(subdev, "\t writeMask : 0x%x\n", + hdr->regions.region_props[i].write_mask); + nvkm_debug(subdev, "\t clientMask : 0x%x\n", + hdr->regions.region_props[i].client_mask); + nvkm_debug(subdev, "\t shadowMemStartAddr: 0x%x\n", + hdr->regions.region_props[i].shadow_mem_start_addr); + } + + nvkm_debug(subdev, "\tucodeBlobSize : %d\n", + hdr->ucode_blob_size); + nvkm_debug(subdev, "\tucodeBlobBase : 0x%llx\n", + hdr->ucode_blob_base); + nvkm_debug(subdev, "\tvprEnabled : %d\n", + hdr->vpr_desc.vpr_enabled); + nvkm_debug(subdev, "\tvprStart : 0x%x\n", + hdr->vpr_desc.vpr_start); + nvkm_debug(subdev, "\tvprEnd : 0x%x\n", + hdr->vpr_desc.vpr_end); + nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n", + hdr->vpr_desc.hdcp_policies); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c b/drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c new file mode 100644 index 000000000000..00ec764e1aab --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c @@ -0,0 +1,115 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include <core/subdev.h> +#include <nvfw/flcn.h> + +void +loader_config_dump(struct nvkm_subdev *subdev, const struct loader_config *hdr) +{ + nvkm_debug(subdev, "loaderConfig\n"); + nvkm_debug(subdev, "\tdmaIdx : %d\n", hdr->dma_idx); + nvkm_debug(subdev, "\tcodeDmaBase : 0x%xx\n", hdr->code_dma_base); + nvkm_debug(subdev, "\tcodeSizeTotal : 0x%x\n", hdr->code_size_total); + nvkm_debug(subdev, "\tcodeSizeToLoad: 0x%x\n", hdr->code_size_to_load); + nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point); + nvkm_debug(subdev, "\tdataDmaBase : 0x%x\n", hdr->data_dma_base); + nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); + nvkm_debug(subdev, "\toverlayDmaBase: 0x%x\n", hdr->overlay_dma_base); + nvkm_debug(subdev, "\targc : 0x%08x\n", hdr->argc); + nvkm_debug(subdev, "\targv : 0x%08x\n", hdr->argv); + nvkm_debug(subdev, "\tcodeDmaBase1 : 0x%x\n", hdr->code_dma_base1); + nvkm_debug(subdev, "\tdataDmaBase1 : 0x%x\n", hdr->data_dma_base1); + nvkm_debug(subdev, "\tovlyDmaBase1 : 0x%x\n", hdr->overlay_dma_base1); +} + +void +loader_config_v1_dump(struct nvkm_subdev *subdev, + const struct loader_config_v1 *hdr) +{ + nvkm_debug(subdev, "loaderConfig\n"); + nvkm_debug(subdev, "\treserved : 0x%08x\n", hdr->reserved); + nvkm_debug(subdev, "\tdmaIdx : %d\n", hdr->dma_idx); + nvkm_debug(subdev, "\tcodeDmaBase : 0x%llxx\n", hdr->code_dma_base); + nvkm_debug(subdev, "\tcodeSizeTotal : 0x%x\n", hdr->code_size_total); + nvkm_debug(subdev, "\tcodeSizeToLoad: 0x%x\n", hdr->code_size_to_load); + nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point); + nvkm_debug(subdev, "\tdataDmaBase : 0x%llx\n", hdr->data_dma_base); + nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); + nvkm_debug(subdev, "\toverlayDmaBase: 0x%llx\n", hdr->overlay_dma_base); + nvkm_debug(subdev, "\targc : 0x%08x\n", hdr->argc); + nvkm_debug(subdev, "\targv : 0x%08x\n", hdr->argv); +} + +void +flcn_bl_dmem_desc_dump(struct nvkm_subdev *subdev, + const struct flcn_bl_dmem_desc *hdr) +{ + nvkm_debug(subdev, "flcnBlDmemDesc\n"); + nvkm_debug(subdev, "\treserved : 0x%08x 0x%08x 0x%08x 0x%08x\n", + hdr->reserved[0], hdr->reserved[1], hdr->reserved[2], + hdr->reserved[3]); + nvkm_debug(subdev, "\tsignature : 0x%08x 0x%08x 0x%08x 0x%08x\n", + hdr->signature[0], hdr->signature[1], hdr->signature[2], + hdr->signature[3]); + nvkm_debug(subdev, "\tctxDma : %d\n", hdr->ctx_dma); + nvkm_debug(subdev, "\tcodeDmaBase : 0x%x\n", hdr->code_dma_base); + nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n", hdr->non_sec_code_off); + nvkm_debug(subdev, "\tnonSecCodeSize: 0x%x\n", hdr->non_sec_code_size); + nvkm_debug(subdev, "\tsecCodeOff : 0x%x\n", hdr->sec_code_off); + nvkm_debug(subdev, "\tsecCodeSize : 0x%x\n", hdr->sec_code_size); + nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point); + nvkm_debug(subdev, "\tdataDmaBase : 0x%x\n", hdr->data_dma_base); + nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); + nvkm_debug(subdev, "\tcodeDmaBase1 : 0x%x\n", hdr->code_dma_base1); + nvkm_debug(subdev, "\tdataDmaBase1 : 0x%x\n", hdr->data_dma_base1); +} + +void +flcn_bl_dmem_desc_v1_dump(struct nvkm_subdev *subdev, + const struct flcn_bl_dmem_desc_v1 *hdr) +{ + nvkm_debug(subdev, "flcnBlDmemDesc\n"); + nvkm_debug(subdev, "\treserved : 0x%08x 0x%08x 0x%08x 0x%08x\n", + hdr->reserved[0], hdr->reserved[1], hdr->reserved[2], + hdr->reserved[3]); + nvkm_debug(subdev, "\tsignature : 0x%08x 0x%08x 0x%08x 0x%08x\n", + hdr->signature[0], hdr->signature[1], hdr->signature[2], + hdr->signature[3]); + nvkm_debug(subdev, "\tctxDma : %d\n", hdr->ctx_dma); + nvkm_debug(subdev, "\tcodeDmaBase : 0x%llx\n", hdr->code_dma_base); + nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n", hdr->non_sec_code_off); + nvkm_debug(subdev, "\tnonSecCodeSize: 0x%x\n", hdr->non_sec_code_size); + nvkm_debug(subdev, "\tsecCodeOff : 0x%x\n", hdr->sec_code_off); + nvkm_debug(subdev, "\tsecCodeSize : 0x%x\n", hdr->sec_code_size); + nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point); + nvkm_debug(subdev, "\tdataDmaBase : 0x%llx\n", hdr->data_dma_base); + nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); +} + +void +flcn_bl_dmem_desc_v2_dump(struct nvkm_subdev *subdev, + const struct flcn_bl_dmem_desc_v2 *hdr) +{ + flcn_bl_dmem_desc_v1_dump(subdev, (void *)hdr); + nvkm_debug(subdev, "\targc : 0x%08x\n", hdr->argc); + nvkm_debug(subdev, "\targv : 0x%08x\n", hdr->argv); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c b/drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c new file mode 100644 index 000000000000..746803bd5318 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c @@ -0,0 +1,51 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include <core/subdev.h> +#include <nvfw/fw.h> + +const struct nvfw_bin_hdr * +nvfw_bin_hdr(struct nvkm_subdev *subdev, const void *data) +{ + const struct nvfw_bin_hdr *hdr = data; + nvkm_debug(subdev, "binHdr:\n"); + nvkm_debug(subdev, "\tbinMagic : 0x%08x\n", hdr->bin_magic); + nvkm_debug(subdev, "\tbinVer : %d\n", hdr->bin_ver); + nvkm_debug(subdev, "\tbinSize : %d\n", hdr->bin_size); + nvkm_debug(subdev, "\theaderOffset : 0x%x\n", hdr->header_offset); + nvkm_debug(subdev, "\tdataOffset : 0x%x\n", hdr->data_offset); + nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); + return hdr; +} + +const struct nvfw_bl_desc * +nvfw_bl_desc(struct nvkm_subdev *subdev, const void *data) +{ + const struct nvfw_bl_desc *hdr = data; + nvkm_debug(subdev, "blDesc\n"); + nvkm_debug(subdev, "\tstartTag : 0x%x\n", hdr->start_tag); + nvkm_debug(subdev, "\tdmemLoadOff : 0x%x\n", hdr->dmem_load_off); + nvkm_debug(subdev, "\tcodeOff : 0x%x\n", hdr->code_off); + nvkm_debug(subdev, "\tcodeSize : 0x%x\n", hdr->code_size); + nvkm_debug(subdev, "\tdataOff : 0x%x\n", hdr->data_off); + nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); + return hdr; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c b/drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c new file mode 100644 index 000000000000..04ed77cb2eba --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c @@ -0,0 +1,62 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include <core/subdev.h> +#include <nvfw/hs.h> + +const struct nvfw_hs_header * +nvfw_hs_header(struct nvkm_subdev *subdev, const void *data) +{ + const struct nvfw_hs_header *hdr = data; + nvkm_debug(subdev, "hsHeader:\n"); + nvkm_debug(subdev, "\tsigDbgOffset : 0x%x\n", hdr->sig_dbg_offset); + nvkm_debug(subdev, "\tsigDbgSize : 0x%x\n", hdr->sig_dbg_size); + nvkm_debug(subdev, "\tsigProdOffset : 0x%x\n", hdr->sig_prod_offset); + nvkm_debug(subdev, "\tsigProdSize : 0x%x\n", hdr->sig_prod_size); + nvkm_debug(subdev, "\tpatchLoc : 0x%x\n", hdr->patch_loc); + nvkm_debug(subdev, "\tpatchSig : 0x%x\n", hdr->patch_sig); + nvkm_debug(subdev, "\thdrOffset : 0x%x\n", hdr->hdr_offset); + nvkm_debug(subdev, "\thdrSize : 0x%x\n", hdr->hdr_size); + return hdr; +} + +const struct nvfw_hs_load_header * +nvfw_hs_load_header(struct nvkm_subdev *subdev, const void *data) +{ + const struct nvfw_hs_load_header *hdr = data; + int i; + + nvkm_debug(subdev, "hsLoadHeader:\n"); + nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n", + hdr->non_sec_code_off); + nvkm_debug(subdev, "\tnonSecCodeSize : 0x%x\n", + hdr->non_sec_code_size); + nvkm_debug(subdev, "\tdataDmaBase : 0x%x\n", hdr->data_dma_base); + nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); + nvkm_debug(subdev, "\tnumApps : 0x%x\n", hdr->num_apps); + for (i = 0; i < hdr->num_apps; i++) { + nvkm_debug(subdev, + "\tApp[%d] : offset 0x%x size 0x%x\n", i, + hdr->apps[(i * 2) + 0], hdr->apps[(i * 2) + 1]); + } + + return hdr; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c b/drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c new file mode 100644 index 000000000000..b847f281ce97 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c @@ -0,0 +1,108 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include <core/subdev.h> +#include <nvfw/ls.h> + +static void +nvfw_ls_desc_head(struct nvkm_subdev *subdev, + const struct nvfw_ls_desc_head *hdr) +{ + char *date; + + nvkm_debug(subdev, "lsUcodeImgDesc:\n"); + nvkm_debug(subdev, "\tdescriptorSize : %d\n", + hdr->descriptor_size); + nvkm_debug(subdev, "\timageSize : %d\n", hdr->image_size); + nvkm_debug(subdev, "\ttoolsVersion : 0x%x\n", + hdr->tools_version); + nvkm_debug(subdev, "\tappVersion : 0x%x\n", hdr->app_version); + + date = kstrndup(hdr->date, sizeof(hdr->date), GFP_KERNEL); + nvkm_debug(subdev, "\tdate : %s\n", date); + kfree(date); + + nvkm_debug(subdev, "\tbootloaderStartOffset: 0x%x\n", + hdr->bootloader_start_offset); + nvkm_debug(subdev, "\tbootloaderSize : 0x%x\n", + hdr->bootloader_size); + nvkm_debug(subdev, "\tbootloaderImemOffset : 0x%x\n", + hdr->bootloader_imem_offset); + nvkm_debug(subdev, "\tbootloaderEntryPoint : 0x%x\n", + hdr->bootloader_entry_point); + + nvkm_debug(subdev, "\tappStartOffset : 0x%x\n", + hdr->app_start_offset); + nvkm_debug(subdev, "\tappSize : 0x%x\n", hdr->app_size); + nvkm_debug(subdev, "\tappImemOffset : 0x%x\n", + hdr->app_imem_offset); + nvkm_debug(subdev, "\tappImemEntry : 0x%x\n", + hdr->app_imem_entry); + nvkm_debug(subdev, "\tappDmemOffset : 0x%x\n", + hdr->app_dmem_offset); + nvkm_debug(subdev, "\tappResidentCodeOffset: 0x%x\n", + hdr->app_resident_code_offset); + nvkm_debug(subdev, "\tappResidentCodeSize : 0x%x\n", + hdr->app_resident_code_size); + nvkm_debug(subdev, "\tappResidentDataOffset: 0x%x\n", + hdr->app_resident_data_offset); + nvkm_debug(subdev, "\tappResidentDataSize : 0x%x\n", + hdr->app_resident_data_size); +} + +const struct nvfw_ls_desc * +nvfw_ls_desc(struct nvkm_subdev *subdev, const void *data) +{ + const struct nvfw_ls_desc *hdr = data; + int i; + + nvfw_ls_desc_head(subdev, &hdr->head); + + nvkm_debug(subdev, "\tnbOverlays : %d\n", hdr->nb_overlays); + for (i = 0; i < ARRAY_SIZE(hdr->load_ovl); i++) { + nvkm_debug(subdev, "\tloadOvl[%d] : 0x%x %d\n", i, + hdr->load_ovl[i].start, hdr->load_ovl[i].size); + } + nvkm_debug(subdev, "\tcompressed : %d\n", hdr->compressed); + + return hdr; +} + +const struct nvfw_ls_desc_v1 * +nvfw_ls_desc_v1(struct nvkm_subdev *subdev, const void *data) +{ + const struct nvfw_ls_desc_v1 *hdr = data; + int i; + + nvfw_ls_desc_head(subdev, &hdr->head); + + nvkm_debug(subdev, "\tnbImemOverlays : %d\n", + hdr->nb_imem_overlays); + nvkm_debug(subdev, "\tnbDmemOverlays : %d\n", + hdr->nb_imem_overlays); + for (i = 0; i < ARRAY_SIZE(hdr->load_ovl); i++) { + nvkm_debug(subdev, "\tloadOvl[%2d] : 0x%x %d\n", i, + hdr->load_ovl[i].start, hdr->load_ovl[i].size); + } + nvkm_debug(subdev, "\tcompressed : %d\n", hdr->compressed); + + return hdr; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild index 4e136f3d7c28..2cb24fff7e32 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild @@ -1,4 +1,5 @@ # SPDX-License-Identifier: MIT +include $(src)/nvkm/subdev/acr/Kbuild include $(src)/nvkm/subdev/bar/Kbuild include $(src)/nvkm/subdev/bios/Kbuild include $(src)/nvkm/subdev/bus/Kbuild @@ -10,7 +11,6 @@ include $(src)/nvkm/subdev/fuse/Kbuild include $(src)/nvkm/subdev/gpio/Kbuild include $(src)/nvkm/subdev/gsp/Kbuild include $(src)/nvkm/subdev/i2c/Kbuild -include $(src)/nvkm/subdev/ibus/Kbuild include $(src)/nvkm/subdev/iccsense/Kbuild include $(src)/nvkm/subdev/instmem/Kbuild include $(src)/nvkm/subdev/ltc/Kbuild @@ -19,7 +19,7 @@ include $(src)/nvkm/subdev/mmu/Kbuild include $(src)/nvkm/subdev/mxm/Kbuild include $(src)/nvkm/subdev/pci/Kbuild include $(src)/nvkm/subdev/pmu/Kbuild -include $(src)/nvkm/subdev/secboot/Kbuild +include $(src)/nvkm/subdev/privring/Kbuild include $(src)/nvkm/subdev/therm/Kbuild include $(src)/nvkm/subdev/timer/Kbuild include $(src)/nvkm/subdev/top/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/Kbuild new file mode 100644 index 000000000000..5b9f64a8957f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/Kbuild @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: MIT +nvkm-y += nvkm/subdev/acr/base.o +nvkm-y += nvkm/subdev/acr/hsfw.o +nvkm-y += nvkm/subdev/acr/lsfw.o +nvkm-y += nvkm/subdev/acr/gm200.o +nvkm-y += nvkm/subdev/acr/gm20b.o +nvkm-y += nvkm/subdev/acr/gp102.o +nvkm-y += nvkm/subdev/acr/gp108.o +nvkm-y += nvkm/subdev/acr/gp10b.o +nvkm-y += nvkm/subdev/acr/tu102.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c new file mode 100644 index 000000000000..af6cac696d43 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c @@ -0,0 +1,440 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +#include <core/firmware.h> +#include <core/memory.h> +#include <subdev/mmu.h> + +static struct nvkm_acr_hsf * +nvkm_acr_hsf_find(struct nvkm_acr *acr, const char *name) +{ + struct nvkm_acr_hsf *hsf; + list_for_each_entry(hsf, &acr->hsf, head) { + if (!strcmp(hsf->name, name)) + return hsf; + } + return NULL; +} + +int +nvkm_acr_hsf_boot(struct nvkm_acr *acr, const char *name) +{ + struct nvkm_subdev *subdev = &acr->subdev; + struct nvkm_acr_hsf *hsf; + int ret; + + hsf = nvkm_acr_hsf_find(acr, name); + if (!hsf) + return -EINVAL; + + nvkm_debug(subdev, "executing %s binary\n", hsf->name); + ret = nvkm_falcon_get(hsf->falcon, subdev); + if (ret) + return ret; + + ret = hsf->func->boot(acr, hsf); + nvkm_falcon_put(hsf->falcon, subdev); + if (ret) { + nvkm_error(subdev, "%s binary failed\n", hsf->name); + return ret; + } + + nvkm_debug(subdev, "%s binary completed successfully\n", hsf->name); + return 0; +} + +static void +nvkm_acr_unload(struct nvkm_acr *acr) +{ + if (acr->done) { + nvkm_acr_hsf_boot(acr, "unload"); + acr->done = false; + } +} + +static int +nvkm_acr_load(struct nvkm_acr *acr) +{ + struct nvkm_subdev *subdev = &acr->subdev; + struct nvkm_acr_lsf *lsf; + u64 start, limit; + int ret; + + if (list_empty(&acr->lsf)) { + nvkm_debug(subdev, "No LSF(s) present.\n"); + return 0; + } + + ret = acr->func->init(acr); + if (ret) + return ret; + + acr->func->wpr_check(acr, &start, &limit); + + if (start != acr->wpr_start || limit != acr->wpr_end) { + nvkm_error(subdev, "WPR not configured as expected: " + "%016llx-%016llx vs %016llx-%016llx\n", + acr->wpr_start, acr->wpr_end, start, limit); + return -EIO; + } + + acr->done = true; + + list_for_each_entry(lsf, &acr->lsf, head) { + if (lsf->func->boot) { + ret = lsf->func->boot(lsf->falcon); + if (ret) + break; + } + } + + return ret; +} + +static int +nvkm_acr_reload(struct nvkm_acr *acr) +{ + nvkm_acr_unload(acr); + return nvkm_acr_load(acr); +} + +static struct nvkm_acr_lsf * +nvkm_acr_falcon(struct nvkm_device *device) +{ + struct nvkm_acr *acr = device->acr; + struct nvkm_acr_lsf *lsf; + + if (acr) { + list_for_each_entry(lsf, &acr->lsf, head) { + if (lsf->func->bootstrap_falcon) + return lsf; + } + } + + return NULL; +} + +int +nvkm_acr_bootstrap_falcons(struct nvkm_device *device, unsigned long mask) +{ + struct nvkm_acr_lsf *acrflcn = nvkm_acr_falcon(device); + struct nvkm_acr *acr = device->acr; + unsigned long id; + + /* If there's no LS FW managing bootstrapping of other LS falcons, + * we depend on the HS firmware being able to do it instead. + */ + if (!acrflcn) { + /* Which isn't possible everywhere... */ + if ((mask & acr->func->bootstrap_falcons) == mask) { + int ret = nvkm_acr_reload(acr); + if (ret) + return ret; + + return acr->done ? 0 : -EINVAL; + } + return -ENOSYS; + } + + if ((mask & acrflcn->func->bootstrap_falcons) != mask) + return -ENOSYS; + + if (acrflcn->func->bootstrap_multiple_falcons) { + return acrflcn->func-> + bootstrap_multiple_falcons(acrflcn->falcon, mask); + } + + for_each_set_bit(id, &mask, NVKM_ACR_LSF_NUM) { + int ret = acrflcn->func->bootstrap_falcon(acrflcn->falcon, id); + if (ret) + return ret; + } + + return 0; +} + +bool +nvkm_acr_managed_falcon(struct nvkm_device *device, enum nvkm_acr_lsf_id id) +{ + struct nvkm_acr *acr = device->acr; + + if (acr) { + if (acr->managed_falcons & BIT_ULL(id)) + return true; + } + + return false; +} + +static int +nvkm_acr_fini(struct nvkm_subdev *subdev, bool suspend) +{ + nvkm_acr_unload(nvkm_acr(subdev)); + return 0; +} + +static int +nvkm_acr_init(struct nvkm_subdev *subdev) +{ + if (!nvkm_acr_falcon(subdev->device)) + return 0; + + return nvkm_acr_load(nvkm_acr(subdev)); +} + +static void +nvkm_acr_cleanup(struct nvkm_acr *acr) +{ + nvkm_acr_lsfw_del_all(acr); + nvkm_acr_hsfw_del_all(acr); + nvkm_firmware_put(acr->wpr_fw); + acr->wpr_fw = NULL; +} + +static int +nvkm_acr_oneinit(struct nvkm_subdev *subdev) +{ + struct nvkm_device *device = subdev->device; + struct nvkm_acr *acr = nvkm_acr(subdev); + struct nvkm_acr_hsfw *hsfw; + struct nvkm_acr_lsfw *lsfw, *lsft; + struct nvkm_acr_lsf *lsf; + u32 wpr_size = 0; + u64 falcons; + int ret, i; + + if (list_empty(&acr->hsfw)) { + nvkm_debug(subdev, "No HSFW(s)\n"); + nvkm_acr_cleanup(acr); + return 0; + } + + /* Determine layout/size of WPR image up-front, as we need to know + * it to allocate memory before we begin constructing it. + */ + list_for_each_entry_safe(lsfw, lsft, &acr->lsfw, head) { + /* Cull unknown falcons that are present in WPR image. */ + if (acr->wpr_fw) { + if (!lsfw->func) { + nvkm_acr_lsfw_del(lsfw); + continue; + } + + wpr_size = acr->wpr_fw->size; + } + + /* Ensure we've fetched falcon configuration. */ + ret = nvkm_falcon_get(lsfw->falcon, subdev); + if (ret) + return ret; + + nvkm_falcon_put(lsfw->falcon, subdev); + + if (!(lsf = kmalloc(sizeof(*lsf), GFP_KERNEL))) + return -ENOMEM; + lsf->func = lsfw->func; + lsf->falcon = lsfw->falcon; + lsf->id = lsfw->id; + list_add_tail(&lsf->head, &acr->lsf); + acr->managed_falcons |= BIT_ULL(lsf->id); + } + + /* Ensure the falcon that'll provide ACR functions is booted first. */ + lsf = nvkm_acr_falcon(device); + if (lsf) { + falcons = lsf->func->bootstrap_falcons; + list_move(&lsf->head, &acr->lsf); + } else { + falcons = acr->func->bootstrap_falcons; + } + + /* Cull falcons that can't be bootstrapped, or the HSFW can fail to + * boot and leave the GPU in a weird state. + */ + list_for_each_entry_safe(lsfw, lsft, &acr->lsfw, head) { + if (!(falcons & BIT_ULL(lsfw->id))) { + nvkm_warn(subdev, "%s falcon cannot be bootstrapped\n", + nvkm_acr_lsf_id(lsfw->id)); + nvkm_acr_lsfw_del(lsfw); + } + } + + if (!acr->wpr_fw || acr->wpr_comp) + wpr_size = acr->func->wpr_layout(acr); + + /* Allocate/Locate WPR + fill ucode blob pointer. + * + * dGPU: allocate WPR + shadow blob + * Tegra: locate WPR with regs, ensure size is sufficient, + * allocate ucode blob. + */ + ret = acr->func->wpr_alloc(acr, wpr_size); + if (ret) + return ret; + + nvkm_debug(subdev, "WPR region is from 0x%llx-0x%llx (shadow 0x%llx)\n", + acr->wpr_start, acr->wpr_end, acr->shadow_start); + + /* Write WPR to ucode blob. */ + nvkm_kmap(acr->wpr); + if (acr->wpr_fw && !acr->wpr_comp) + nvkm_wobj(acr->wpr, 0, acr->wpr_fw->data, acr->wpr_fw->size); + + if (!acr->wpr_fw || acr->wpr_comp) + acr->func->wpr_build(acr, nvkm_acr_falcon(device)); + acr->func->wpr_patch(acr, (s64)acr->wpr_start - acr->wpr_prev); + + if (acr->wpr_fw && acr->wpr_comp) { + nvkm_kmap(acr->wpr); + for (i = 0; i < acr->wpr_fw->size; i += 4) { + u32 us = nvkm_ro32(acr->wpr, i); + u32 fw = ((u32 *)acr->wpr_fw->data)[i/4]; + if (fw != us) { + nvkm_warn(subdev, "%08x: %08x %08x\n", + i, us, fw); + } + } + return -EINVAL; + } + nvkm_done(acr->wpr); + + /* Allocate instance block for ACR-related stuff. */ + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0, true, + &acr->inst); + if (ret) + return ret; + + ret = nvkm_vmm_new(device, 0, 0, NULL, 0, NULL, "acr", &acr->vmm); + if (ret) + return ret; + + acr->vmm->debug = acr->subdev.debug; + + ret = nvkm_vmm_join(acr->vmm, acr->inst); + if (ret) + return ret; + + /* Load HS firmware blobs into ACR VMM. */ + list_for_each_entry(hsfw, &acr->hsfw, head) { + nvkm_debug(subdev, "loading %s fw\n", hsfw->name); + ret = hsfw->func->load(acr, hsfw); + if (ret) + return ret; + } + + /* Kill temporary data. */ + nvkm_acr_cleanup(acr); + return 0; +} + +static void * +nvkm_acr_dtor(struct nvkm_subdev *subdev) +{ + struct nvkm_acr *acr = nvkm_acr(subdev); + struct nvkm_acr_hsf *hsf, *hst; + struct nvkm_acr_lsf *lsf, *lst; + + list_for_each_entry_safe(hsf, hst, &acr->hsf, head) { + nvkm_vmm_put(acr->vmm, &hsf->vma); + nvkm_memory_unref(&hsf->ucode); + kfree(hsf->imem); + list_del(&hsf->head); + kfree(hsf); + } + + nvkm_vmm_part(acr->vmm, acr->inst); + nvkm_vmm_unref(&acr->vmm); + nvkm_memory_unref(&acr->inst); + + nvkm_memory_unref(&acr->wpr); + + list_for_each_entry_safe(lsf, lst, &acr->lsf, head) { + list_del(&lsf->head); + kfree(lsf); + } + + nvkm_acr_cleanup(acr); + return acr; +} + +static const struct nvkm_subdev_func +nvkm_acr = { + .dtor = nvkm_acr_dtor, + .oneinit = nvkm_acr_oneinit, + .init = nvkm_acr_init, + .fini = nvkm_acr_fini, +}; + +static int +nvkm_acr_ctor_wpr(struct nvkm_acr *acr, int ver) +{ + struct nvkm_subdev *subdev = &acr->subdev; + struct nvkm_device *device = subdev->device; + int ret; + + ret = nvkm_firmware_get(subdev, "acr/wpr", ver, &acr->wpr_fw); + if (ret < 0) + return ret; + + /* Pre-add LSFs in the order they appear in the FW WPR image so that + * we're able to do a binary comparison with our own generator. + */ + ret = acr->func->wpr_parse(acr); + if (ret) + return ret; + + acr->wpr_comp = nvkm_boolopt(device->cfgopt, "NvAcrWprCompare", false); + acr->wpr_prev = nvkm_longopt(device->cfgopt, "NvAcrWprPrevAddr", 0); + return 0; +} + +int +nvkm_acr_new_(const struct nvkm_acr_fwif *fwif, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_acr **pacr) +{ + struct nvkm_acr *acr; + long wprfw; + + if (!(acr = *pacr = kzalloc(sizeof(*acr), GFP_KERNEL))) + return -ENOMEM; + nvkm_subdev_ctor(&nvkm_acr, device, type, inst, &acr->subdev); + INIT_LIST_HEAD(&acr->hsfw); + INIT_LIST_HEAD(&acr->lsfw); + INIT_LIST_HEAD(&acr->hsf); + INIT_LIST_HEAD(&acr->lsf); + + fwif = nvkm_firmware_load(&acr->subdev, fwif, "Acr", acr); + if (IS_ERR(fwif)) + return PTR_ERR(fwif); + + acr->func = fwif->func; + + wprfw = nvkm_longopt(device->cfgopt, "NvAcrWpr", -1); + if (wprfw >= 0) { + int ret = nvkm_acr_ctor_wpr(acr, wprfw); + if (ret) + return ret; + } + + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c new file mode 100644 index 000000000000..82b4c8e1457c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c @@ -0,0 +1,487 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +#include <core/falcon.h> +#include <core/firmware.h> +#include <core/memory.h> +#include <subdev/mc.h> +#include <subdev/mmu.h> +#include <subdev/pmu.h> +#include <subdev/timer.h> + +#include <nvfw/acr.h> +#include <nvfw/flcn.h> + +const struct nvkm_acr_func +gm200_acr = { +}; + +int +gm200_acr_nofw(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) +{ + nvkm_warn(&acr->subdev, "firmware unavailable\n"); + return 0; +} + +int +gm200_acr_init(struct nvkm_acr *acr) +{ + return nvkm_acr_hsf_boot(acr, "load"); +} + +void +gm200_acr_wpr_check(struct nvkm_acr *acr, u64 *start, u64 *limit) +{ + struct nvkm_device *device = acr->subdev.device; + + nvkm_wr32(device, 0x100cd4, 2); + *start = (u64)(nvkm_rd32(device, 0x100cd4) & 0xffffff00) << 8; + nvkm_wr32(device, 0x100cd4, 3); + *limit = (u64)(nvkm_rd32(device, 0x100cd4) & 0xffffff00) << 8; + *limit = *limit + 0x20000; +} + +void +gm200_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust) +{ + struct nvkm_subdev *subdev = &acr->subdev; + struct wpr_header hdr; + struct lsb_header lsb; + struct nvkm_acr_lsf *lsfw; + u32 offset = 0; + + do { + nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr)); + wpr_header_dump(subdev, &hdr); + + list_for_each_entry(lsfw, &acr->lsfw, head) { + if (lsfw->id != hdr.falcon_id) + continue; + + nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb)); + lsb_header_dump(subdev, &lsb); + + lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust); + break; + } + offset += sizeof(hdr); + } while (hdr.falcon_id != WPR_HEADER_V0_FALCON_ID_INVALID); +} + +void +gm200_acr_wpr_build_lsb_tail(struct nvkm_acr_lsfw *lsfw, + struct lsb_header_tail *hdr) +{ + hdr->ucode_off = lsfw->offset.img; + hdr->ucode_size = lsfw->ucode_size; + hdr->data_size = lsfw->data_size; + hdr->bl_code_size = lsfw->bootloader_size; + hdr->bl_imem_off = lsfw->bootloader_imem_offset; + hdr->bl_data_off = lsfw->offset.bld; + hdr->bl_data_size = lsfw->bl_data_size; + hdr->app_code_off = lsfw->app_start_offset + + lsfw->app_resident_code_offset; + hdr->app_code_size = lsfw->app_resident_code_size; + hdr->app_data_off = lsfw->app_start_offset + + lsfw->app_resident_data_offset; + hdr->app_data_size = lsfw->app_resident_data_size; + hdr->flags = lsfw->func->flags; +} + +static int +gm200_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw) +{ + struct lsb_header hdr; + + if (WARN_ON(lsfw->sig->size != sizeof(hdr.signature))) + return -EINVAL; + + memcpy(&hdr.signature, lsfw->sig->data, lsfw->sig->size); + gm200_acr_wpr_build_lsb_tail(lsfw, &hdr.tail); + + nvkm_wobj(acr->wpr, lsfw->offset.lsb, &hdr, sizeof(hdr)); + return 0; +} + +int +gm200_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos) +{ + struct nvkm_acr_lsfw *lsfw; + u32 offset = 0; + int ret; + + /* Fill per-LSF structures. */ + list_for_each_entry(lsfw, &acr->lsfw, head) { + struct wpr_header hdr = { + .falcon_id = lsfw->id, + .lsb_offset = lsfw->offset.lsb, + .bootstrap_owner = NVKM_ACR_LSF_PMU, + .lazy_bootstrap = rtos && lsfw->id != rtos->id, + .status = WPR_HEADER_V0_STATUS_COPY, + }; + + /* Write WPR header. */ + nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr)); + offset += sizeof(hdr); + + /* Write LSB header. */ + ret = gm200_acr_wpr_build_lsb(acr, lsfw); + if (ret) + return ret; + + /* Write ucode image. */ + nvkm_wobj(acr->wpr, lsfw->offset.img, + lsfw->img.data, + lsfw->img.size); + + /* Write bootloader data. */ + lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw); + } + + /* Finalise WPR. */ + nvkm_wo32(acr->wpr, offset, WPR_HEADER_V0_FALCON_ID_INVALID); + return 0; +} + +static int +gm200_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size) +{ + int ret = nvkm_memory_new(acr->subdev.device, NVKM_MEM_TARGET_INST, + ALIGN(wpr_size, 0x40000), 0x40000, true, + &acr->wpr); + if (ret) + return ret; + + acr->wpr_start = nvkm_memory_addr(acr->wpr); + acr->wpr_end = acr->wpr_start + nvkm_memory_size(acr->wpr); + return 0; +} + +u32 +gm200_acr_wpr_layout(struct nvkm_acr *acr) +{ + struct nvkm_acr_lsfw *lsfw; + u32 wpr = 0; + + wpr += 11 /* MAX_LSF */ * sizeof(struct wpr_header); + + list_for_each_entry(lsfw, &acr->lsfw, head) { + wpr = ALIGN(wpr, 256); + lsfw->offset.lsb = wpr; + wpr += sizeof(struct lsb_header); + + wpr = ALIGN(wpr, 4096); + lsfw->offset.img = wpr; + wpr += lsfw->img.size; + + wpr = ALIGN(wpr, 256); + lsfw->offset.bld = wpr; + lsfw->bl_data_size = ALIGN(lsfw->func->bld_size, 256); + wpr += lsfw->bl_data_size; + } + + return wpr; +} + +int +gm200_acr_wpr_parse(struct nvkm_acr *acr) +{ + const struct wpr_header *hdr = (void *)acr->wpr_fw->data; + struct nvkm_acr_lsfw *lsfw; + + while (hdr->falcon_id != WPR_HEADER_V0_FALCON_ID_INVALID) { + wpr_header_dump(&acr->subdev, hdr); + lsfw = nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)->falcon_id); + if (IS_ERR(lsfw)) + return PTR_ERR(lsfw); + } + + return 0; +} + +void +gm200_acr_hsfw_bld(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf) +{ + struct flcn_bl_dmem_desc_v1 hsdesc = { + .ctx_dma = FALCON_DMAIDX_VIRT, + .code_dma_base = hsf->vma->addr, + .non_sec_code_off = hsf->non_sec_addr, + .non_sec_code_size = hsf->non_sec_size, + .sec_code_off = hsf->sec_addr, + .sec_code_size = hsf->sec_size, + .code_entry_point = 0, + .data_dma_base = hsf->vma->addr + hsf->data_addr, + .data_size = hsf->data_size, + }; + + flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hsdesc); + + nvkm_falcon_load_dmem(hsf->falcon, &hsdesc, 0, sizeof(hsdesc), 0); +} + +int +gm200_acr_hsfw_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf, + u32 intr_clear, u32 mbox0_ok) +{ + struct nvkm_subdev *subdev = &acr->subdev; + struct nvkm_device *device = subdev->device; + struct nvkm_falcon *falcon = hsf->falcon; + u32 mbox0, mbox1; + int ret; + + /* Reset falcon. */ + nvkm_falcon_reset(falcon); + nvkm_falcon_bind_context(falcon, acr->inst); + + /* Load bootloader into IMEM. */ + nvkm_falcon_load_imem(falcon, hsf->imem, + falcon->code.limit - hsf->imem_size, + hsf->imem_size, + hsf->imem_tag, + 0, false); + + /* Load bootloader data into DMEM. */ + hsf->func->bld(acr, hsf); + + /* Boot the falcon. */ + nvkm_mc_intr_mask(device, falcon->owner->type, falcon->owner->inst, false); + + nvkm_falcon_wr32(falcon, 0x040, 0xdeada5a5); + nvkm_falcon_set_start_addr(falcon, hsf->imem_tag << 8); + nvkm_falcon_start(falcon); + ret = nvkm_falcon_wait_for_halt(falcon, 100); + if (ret) + return ret; + + /* Check for successful completion. */ + mbox0 = nvkm_falcon_rd32(falcon, 0x040); + mbox1 = nvkm_falcon_rd32(falcon, 0x044); + nvkm_debug(subdev, "mailbox %08x %08x\n", mbox0, mbox1); + if (mbox0 && mbox0 != mbox0_ok) + return -EIO; + + nvkm_falcon_clear_interrupt(falcon, intr_clear); + nvkm_mc_intr_mask(device, falcon->owner->type, falcon->owner->inst, true); + return ret; +} + +int +gm200_acr_hsfw_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw, + struct nvkm_falcon *falcon) +{ + struct nvkm_subdev *subdev = &acr->subdev; + struct nvkm_acr_hsf *hsf; + int ret; + + /* Patch the appropriate signature (production/debug) into the FW + * image, as determined by the mode the falcon is in. + */ + ret = nvkm_falcon_get(falcon, subdev); + if (ret) + return ret; + + if (hsfw->sig.patch_loc) { + if (!falcon->debug) { + nvkm_debug(subdev, "patching production signature\n"); + memcpy(hsfw->image + hsfw->sig.patch_loc, + hsfw->sig.prod.data, + hsfw->sig.prod.size); + } else { + nvkm_debug(subdev, "patching debug signature\n"); + memcpy(hsfw->image + hsfw->sig.patch_loc, + hsfw->sig.dbg.data, + hsfw->sig.dbg.size); + } + } + + nvkm_falcon_put(falcon, subdev); + + if (!(hsf = kzalloc(sizeof(*hsf), GFP_KERNEL))) + return -ENOMEM; + hsf->func = hsfw->func; + hsf->name = hsfw->name; + list_add_tail(&hsf->head, &acr->hsf); + + hsf->imem_size = hsfw->imem_size; + hsf->imem_tag = hsfw->imem_tag; + hsf->imem = kmemdup(hsfw->imem, hsfw->imem_size, GFP_KERNEL); + if (!hsf->imem) + return -ENOMEM; + + hsf->non_sec_addr = hsfw->non_sec_addr; + hsf->non_sec_size = hsfw->non_sec_size; + hsf->sec_addr = hsfw->sec_addr; + hsf->sec_size = hsfw->sec_size; + hsf->data_addr = hsfw->data_addr; + hsf->data_size = hsfw->data_size; + + /* Make the FW image accessible to the HS bootloader. */ + ret = nvkm_memory_new(subdev->device, NVKM_MEM_TARGET_INST, + hsfw->image_size, 0x1000, false, &hsf->ucode); + if (ret) + return ret; + + nvkm_kmap(hsf->ucode); + nvkm_wobj(hsf->ucode, 0, hsfw->image, hsfw->image_size); + nvkm_done(hsf->ucode); + + ret = nvkm_vmm_get(acr->vmm, 12, nvkm_memory_size(hsf->ucode), + &hsf->vma); + if (ret) + return ret; + + ret = nvkm_memory_map(hsf->ucode, 0, acr->vmm, hsf->vma, NULL, 0); + if (ret) + return ret; + + hsf->falcon = falcon; + return 0; +} + +int +gm200_acr_unload_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf) +{ + return gm200_acr_hsfw_boot(acr, hsf, 0, 0x1d); +} + +int +gm200_acr_unload_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw) +{ + return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->pmu->falcon); +} + +const struct nvkm_acr_hsf_func +gm200_acr_unload_0 = { + .load = gm200_acr_unload_load, + .boot = gm200_acr_unload_boot, + .bld = gm200_acr_hsfw_bld, +}; + +MODULE_FIRMWARE("nvidia/gm200/acr/ucode_unload.bin"); +MODULE_FIRMWARE("nvidia/gm204/acr/ucode_unload.bin"); +MODULE_FIRMWARE("nvidia/gm206/acr/ucode_unload.bin"); +MODULE_FIRMWARE("nvidia/gp100/acr/ucode_unload.bin"); + +static const struct nvkm_acr_hsf_fwif +gm200_acr_unload_fwif[] = { + { 0, nvkm_acr_hsfw_load, &gm200_acr_unload_0 }, + {} +}; + +int +gm200_acr_load_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf) +{ + return gm200_acr_hsfw_boot(acr, hsf, 0x10, 0); +} + +static int +gm200_acr_load_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw) +{ + struct flcn_acr_desc *desc = (void *)&hsfw->image[hsfw->data_addr]; + + desc->wpr_region_id = 1; + desc->regions.no_regions = 2; + desc->regions.region_props[0].start_addr = acr->wpr_start >> 8; + desc->regions.region_props[0].end_addr = acr->wpr_end >> 8; + desc->regions.region_props[0].region_id = 1; + desc->regions.region_props[0].read_mask = 0xf; + desc->regions.region_props[0].write_mask = 0xc; + desc->regions.region_props[0].client_mask = 0x2; + flcn_acr_desc_dump(&acr->subdev, desc); + + return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->pmu->falcon); +} + +static const struct nvkm_acr_hsf_func +gm200_acr_load_0 = { + .load = gm200_acr_load_load, + .boot = gm200_acr_load_boot, + .bld = gm200_acr_hsfw_bld, +}; + +MODULE_FIRMWARE("nvidia/gm200/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/gm200/acr/ucode_load.bin"); + +MODULE_FIRMWARE("nvidia/gm204/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/gm204/acr/ucode_load.bin"); + +MODULE_FIRMWARE("nvidia/gm206/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/gm206/acr/ucode_load.bin"); + +MODULE_FIRMWARE("nvidia/gp100/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/gp100/acr/ucode_load.bin"); + +static const struct nvkm_acr_hsf_fwif +gm200_acr_load_fwif[] = { + { 0, nvkm_acr_hsfw_load, &gm200_acr_load_0 }, + {} +}; + +static const struct nvkm_acr_func +gm200_acr_0 = { + .load = gm200_acr_load_fwif, + .unload = gm200_acr_unload_fwif, + .wpr_parse = gm200_acr_wpr_parse, + .wpr_layout = gm200_acr_wpr_layout, + .wpr_alloc = gm200_acr_wpr_alloc, + .wpr_build = gm200_acr_wpr_build, + .wpr_patch = gm200_acr_wpr_patch, + .wpr_check = gm200_acr_wpr_check, + .init = gm200_acr_init, + .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) | + BIT_ULL(NVKM_ACR_LSF_GPCCS), +}; + +static int +gm200_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) +{ + struct nvkm_subdev *subdev = &acr->subdev; + const struct nvkm_acr_hsf_fwif *hsfwif; + + hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad", + acr, "acr/bl", "acr/ucode_load", "load"); + if (IS_ERR(hsfwif)) + return PTR_ERR(hsfwif); + + hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload", + acr, "acr/bl", "acr/ucode_unload", + "unload"); + if (IS_ERR(hsfwif)) + return PTR_ERR(hsfwif); + + return 0; +} + +static const struct nvkm_acr_fwif +gm200_acr_fwif[] = { + { 0, gm200_acr_load, &gm200_acr_0 }, + { -1, gm200_acr_nofw, &gm200_acr }, + {} +}; + +int +gm200_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_acr **pacr) +{ + return nvkm_acr_new_(gm200_acr_fwif, device, type, inst, pacr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c new file mode 100644 index 000000000000..54e996f2f630 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c @@ -0,0 +1,136 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +#include <core/firmware.h> +#include <core/memory.h> +#include <subdev/mmu.h> +#include <subdev/pmu.h> + +#include <nvfw/acr.h> +#include <nvfw/flcn.h> + +int +gm20b_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size) +{ + struct nvkm_subdev *subdev = &acr->subdev; + + acr->func->wpr_check(acr, &acr->wpr_start, &acr->wpr_end); + + if ((acr->wpr_end - acr->wpr_start) < wpr_size) { + nvkm_error(subdev, "WPR image too big for WPR!\n"); + return -ENOSPC; + } + + return nvkm_memory_new(subdev->device, NVKM_MEM_TARGET_INST, + wpr_size, 0, true, &acr->wpr); +} + +static void +gm20b_acr_load_bld(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf) +{ + struct flcn_bl_dmem_desc hsdesc = { + .ctx_dma = FALCON_DMAIDX_VIRT, + .code_dma_base = hsf->vma->addr >> 8, + .non_sec_code_off = hsf->non_sec_addr, + .non_sec_code_size = hsf->non_sec_size, + .sec_code_off = hsf->sec_addr, + .sec_code_size = hsf->sec_size, + .code_entry_point = 0, + .data_dma_base = (hsf->vma->addr + hsf->data_addr) >> 8, + .data_size = hsf->data_size, + }; + + flcn_bl_dmem_desc_dump(&acr->subdev, &hsdesc); + + nvkm_falcon_load_dmem(hsf->falcon, &hsdesc, 0, sizeof(hsdesc), 0); +} + +static int +gm20b_acr_load_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw) +{ + struct flcn_acr_desc *desc = (void *)&hsfw->image[hsfw->data_addr]; + + desc->ucode_blob_base = nvkm_memory_addr(acr->wpr); + desc->ucode_blob_size = nvkm_memory_size(acr->wpr); + flcn_acr_desc_dump(&acr->subdev, desc); + + return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->pmu->falcon); +} + +const struct nvkm_acr_hsf_func +gm20b_acr_load_0 = { + .load = gm20b_acr_load_load, + .boot = gm200_acr_load_boot, + .bld = gm20b_acr_load_bld, +}; + +#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) +MODULE_FIRMWARE("nvidia/gm20b/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/gm20b/acr/ucode_load.bin"); +#endif + +static const struct nvkm_acr_hsf_fwif +gm20b_acr_load_fwif[] = { + { 0, nvkm_acr_hsfw_load, &gm20b_acr_load_0 }, + {} +}; + +static const struct nvkm_acr_func +gm20b_acr = { + .load = gm20b_acr_load_fwif, + .wpr_parse = gm200_acr_wpr_parse, + .wpr_layout = gm200_acr_wpr_layout, + .wpr_alloc = gm20b_acr_wpr_alloc, + .wpr_build = gm200_acr_wpr_build, + .wpr_patch = gm200_acr_wpr_patch, + .wpr_check = gm200_acr_wpr_check, + .init = gm200_acr_init, +}; + +int +gm20b_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) +{ + struct nvkm_subdev *subdev = &acr->subdev; + const struct nvkm_acr_hsf_fwif *hsfwif; + + hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad", + acr, "acr/bl", "acr/ucode_load", "load"); + if (IS_ERR(hsfwif)) + return PTR_ERR(hsfwif); + + return 0; +} + +static const struct nvkm_acr_fwif +gm20b_acr_fwif[] = { + { 0, gm20b_acr_load, &gm20b_acr }, + { -1, gm200_acr_nofw, &gm200_acr }, + {} +}; + +int +gm20b_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_acr **pacr) +{ + return nvkm_acr_new_(gm20b_acr_fwif, device, type, inst, pacr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c new file mode 100644 index 000000000000..fd97a935a380 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c @@ -0,0 +1,285 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +#include <core/firmware.h> +#include <core/memory.h> +#include <subdev/mmu.h> +#include <engine/sec2.h> + +#include <nvfw/acr.h> +#include <nvfw/flcn.h> + +void +gp102_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust) +{ + struct wpr_header_v1 hdr; + struct lsb_header_v1 lsb; + struct nvkm_acr_lsfw *lsfw; + u32 offset = 0; + + do { + nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr)); + wpr_header_v1_dump(&acr->subdev, &hdr); + + list_for_each_entry(lsfw, &acr->lsfw, head) { + if (lsfw->id != hdr.falcon_id) + continue; + + nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb)); + lsb_header_v1_dump(&acr->subdev, &lsb); + + lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust); + break; + } + + offset += sizeof(hdr); + } while (hdr.falcon_id != WPR_HEADER_V1_FALCON_ID_INVALID); +} + +int +gp102_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw) +{ + struct lsb_header_v1 hdr; + + if (WARN_ON(lsfw->sig->size != sizeof(hdr.signature))) + return -EINVAL; + + memcpy(&hdr.signature, lsfw->sig->data, lsfw->sig->size); + gm200_acr_wpr_build_lsb_tail(lsfw, &hdr.tail); + + nvkm_wobj(acr->wpr, lsfw->offset.lsb, &hdr, sizeof(hdr)); + return 0; +} + +int +gp102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos) +{ + struct nvkm_acr_lsfw *lsfw; + u32 offset = 0; + int ret; + + /* Fill per-LSF structures. */ + list_for_each_entry(lsfw, &acr->lsfw, head) { + struct lsf_signature_v1 *sig = (void *)lsfw->sig->data; + struct wpr_header_v1 hdr = { + .falcon_id = lsfw->id, + .lsb_offset = lsfw->offset.lsb, + .bootstrap_owner = NVKM_ACR_LSF_SEC2, + .lazy_bootstrap = rtos && lsfw->id != rtos->id, + .bin_version = sig->version, + .status = WPR_HEADER_V1_STATUS_COPY, + }; + + /* Write WPR header. */ + nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr)); + offset += sizeof(hdr); + + /* Write LSB header. */ + ret = gp102_acr_wpr_build_lsb(acr, lsfw); + if (ret) + return ret; + + /* Write ucode image. */ + nvkm_wobj(acr->wpr, lsfw->offset.img, + lsfw->img.data, + lsfw->img.size); + + /* Write bootloader data. */ + lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw); + } + + /* Finalise WPR. */ + nvkm_wo32(acr->wpr, offset, WPR_HEADER_V1_FALCON_ID_INVALID); + return 0; +} + +int +gp102_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size) +{ + int ret = nvkm_memory_new(acr->subdev.device, NVKM_MEM_TARGET_INST, + ALIGN(wpr_size, 0x40000) << 1, 0x40000, true, + &acr->wpr); + if (ret) + return ret; + + acr->shadow_start = nvkm_memory_addr(acr->wpr); + acr->wpr_start = acr->shadow_start + (nvkm_memory_size(acr->wpr) >> 1); + acr->wpr_end = acr->wpr_start + (nvkm_memory_size(acr->wpr) >> 1); + return 0; +} + +u32 +gp102_acr_wpr_layout(struct nvkm_acr *acr) +{ + struct nvkm_acr_lsfw *lsfw; + u32 wpr = 0; + + wpr += 11 /* MAX_LSF */ * sizeof(struct wpr_header_v1); + wpr = ALIGN(wpr, 256); + + wpr += 0x100; /* Shared sub-WPR headers. */ + + list_for_each_entry(lsfw, &acr->lsfw, head) { + wpr = ALIGN(wpr, 256); + lsfw->offset.lsb = wpr; + wpr += sizeof(struct lsb_header_v1); + + wpr = ALIGN(wpr, 4096); + lsfw->offset.img = wpr; + wpr += lsfw->img.size; + + wpr = ALIGN(wpr, 256); + lsfw->offset.bld = wpr; + lsfw->bl_data_size = ALIGN(lsfw->func->bld_size, 256); + wpr += lsfw->bl_data_size; + } + + return wpr; +} + +int +gp102_acr_wpr_parse(struct nvkm_acr *acr) +{ + const struct wpr_header_v1 *hdr = (void *)acr->wpr_fw->data; + struct nvkm_acr_lsfw *lsfw; + + while (hdr->falcon_id != WPR_HEADER_V1_FALCON_ID_INVALID) { + wpr_header_v1_dump(&acr->subdev, hdr); + lsfw = nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)->falcon_id); + if (IS_ERR(lsfw)) + return PTR_ERR(lsfw); + } + + return 0; +} + +MODULE_FIRMWARE("nvidia/gp102/acr/unload_bl.bin"); +MODULE_FIRMWARE("nvidia/gp102/acr/ucode_unload.bin"); + +MODULE_FIRMWARE("nvidia/gp104/acr/unload_bl.bin"); +MODULE_FIRMWARE("nvidia/gp104/acr/ucode_unload.bin"); + +MODULE_FIRMWARE("nvidia/gp106/acr/unload_bl.bin"); +MODULE_FIRMWARE("nvidia/gp106/acr/ucode_unload.bin"); + +MODULE_FIRMWARE("nvidia/gp107/acr/unload_bl.bin"); +MODULE_FIRMWARE("nvidia/gp107/acr/ucode_unload.bin"); + +static const struct nvkm_acr_hsf_fwif +gp102_acr_unload_fwif[] = { + { 0, nvkm_acr_hsfw_load, &gm200_acr_unload_0 }, + {} +}; + +int +gp102_acr_load_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw) +{ + struct flcn_acr_desc_v1 *desc = (void *)&hsfw->image[hsfw->data_addr]; + + desc->wpr_region_id = 1; + desc->regions.no_regions = 2; + desc->regions.region_props[0].start_addr = acr->wpr_start >> 8; + desc->regions.region_props[0].end_addr = acr->wpr_end >> 8; + desc->regions.region_props[0].region_id = 1; + desc->regions.region_props[0].read_mask = 0xf; + desc->regions.region_props[0].write_mask = 0xc; + desc->regions.region_props[0].client_mask = 0x2; + desc->regions.region_props[0].shadow_mem_start_addr = + acr->shadow_start >> 8; + flcn_acr_desc_v1_dump(&acr->subdev, desc); + + return gm200_acr_hsfw_load(acr, hsfw, + &acr->subdev.device->sec2->falcon); +} + +static const struct nvkm_acr_hsf_func +gp102_acr_load_0 = { + .load = gp102_acr_load_load, + .boot = gm200_acr_load_boot, + .bld = gm200_acr_hsfw_bld, +}; + +MODULE_FIRMWARE("nvidia/gp102/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/gp102/acr/ucode_load.bin"); + +MODULE_FIRMWARE("nvidia/gp104/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/gp104/acr/ucode_load.bin"); + +MODULE_FIRMWARE("nvidia/gp106/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/gp106/acr/ucode_load.bin"); + +MODULE_FIRMWARE("nvidia/gp107/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/gp107/acr/ucode_load.bin"); + +static const struct nvkm_acr_hsf_fwif +gp102_acr_load_fwif[] = { + { 0, nvkm_acr_hsfw_load, &gp102_acr_load_0 }, + {} +}; + +static const struct nvkm_acr_func +gp102_acr = { + .load = gp102_acr_load_fwif, + .unload = gp102_acr_unload_fwif, + .wpr_parse = gp102_acr_wpr_parse, + .wpr_layout = gp102_acr_wpr_layout, + .wpr_alloc = gp102_acr_wpr_alloc, + .wpr_build = gp102_acr_wpr_build, + .wpr_patch = gp102_acr_wpr_patch, + .wpr_check = gm200_acr_wpr_check, + .init = gm200_acr_init, +}; + +int +gp102_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) +{ + struct nvkm_subdev *subdev = &acr->subdev; + const struct nvkm_acr_hsf_fwif *hsfwif; + + hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad", + acr, "acr/bl", "acr/ucode_load", "load"); + if (IS_ERR(hsfwif)) + return PTR_ERR(hsfwif); + + hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload", + acr, "acr/unload_bl", "acr/ucode_unload", + "unload"); + if (IS_ERR(hsfwif)) + return PTR_ERR(hsfwif); + + return 0; +} + +static const struct nvkm_acr_fwif +gp102_acr_fwif[] = { + { 0, gp102_acr_load, &gp102_acr }, + { -1, gm200_acr_nofw, &gm200_acr }, + {} +}; + +int +gp102_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_acr **pacr) +{ + return nvkm_acr_new_(gp102_acr_fwif, device, type, inst, pacr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c new file mode 100644 index 000000000000..373d638a2177 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c @@ -0,0 +1,113 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +#include <subdev/mmu.h> + +#include <nvfw/flcn.h> + +void +gp108_acr_hsfw_bld(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf) +{ + struct flcn_bl_dmem_desc_v2 hsdesc = { + .ctx_dma = FALCON_DMAIDX_VIRT, + .code_dma_base = hsf->vma->addr, + .non_sec_code_off = hsf->non_sec_addr, + .non_sec_code_size = hsf->non_sec_size, + .sec_code_off = hsf->sec_addr, + .sec_code_size = hsf->sec_size, + .code_entry_point = 0, + .data_dma_base = hsf->vma->addr + hsf->data_addr, + .data_size = hsf->data_size, + .argc = 0, + .argv = 0, + }; + + flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hsdesc); + + nvkm_falcon_load_dmem(hsf->falcon, &hsdesc, 0, sizeof(hsdesc), 0); +} + +const struct nvkm_acr_hsf_func +gp108_acr_unload_0 = { + .load = gm200_acr_unload_load, + .boot = gm200_acr_unload_boot, + .bld = gp108_acr_hsfw_bld, +}; + +MODULE_FIRMWARE("nvidia/gp108/acr/unload_bl.bin"); +MODULE_FIRMWARE("nvidia/gp108/acr/ucode_unload.bin"); + +MODULE_FIRMWARE("nvidia/gv100/acr/unload_bl.bin"); +MODULE_FIRMWARE("nvidia/gv100/acr/ucode_unload.bin"); + +static const struct nvkm_acr_hsf_fwif +gp108_acr_unload_fwif[] = { + { 0, nvkm_acr_hsfw_load, &gp108_acr_unload_0 }, + {} +}; + +static const struct nvkm_acr_hsf_func +gp108_acr_load_0 = { + .load = gp102_acr_load_load, + .boot = gm200_acr_load_boot, + .bld = gp108_acr_hsfw_bld, +}; + +MODULE_FIRMWARE("nvidia/gp108/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/gp108/acr/ucode_load.bin"); + +MODULE_FIRMWARE("nvidia/gv100/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/gv100/acr/ucode_load.bin"); + +static const struct nvkm_acr_hsf_fwif +gp108_acr_load_fwif[] = { + { 0, nvkm_acr_hsfw_load, &gp108_acr_load_0 }, + {} +}; + +static const struct nvkm_acr_func +gp108_acr = { + .load = gp108_acr_load_fwif, + .unload = gp108_acr_unload_fwif, + .wpr_parse = gp102_acr_wpr_parse, + .wpr_layout = gp102_acr_wpr_layout, + .wpr_alloc = gp102_acr_wpr_alloc, + .wpr_build = gp102_acr_wpr_build, + .wpr_patch = gp102_acr_wpr_patch, + .wpr_check = gm200_acr_wpr_check, + .init = gm200_acr_init, +}; + +static const struct nvkm_acr_fwif +gp108_acr_fwif[] = { + { 0, gp102_acr_load, &gp108_acr }, + { -1, gm200_acr_nofw, &gm200_acr }, + {} +}; + +int +gp108_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_acr **pacr) +{ + return nvkm_acr_new_(gp108_acr_fwif, device, type, inst, pacr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c new file mode 100644 index 000000000000..f03ba028867b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c @@ -0,0 +1,59 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) +MODULE_FIRMWARE("nvidia/gp10b/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/gp10b/acr/ucode_load.bin"); +#endif + +static const struct nvkm_acr_hsf_fwif +gp10b_acr_load_fwif[] = { + { 0, nvkm_acr_hsfw_load, &gm20b_acr_load_0 }, + {} +}; + +static const struct nvkm_acr_func +gp10b_acr = { + .load = gp10b_acr_load_fwif, + .wpr_parse = gm200_acr_wpr_parse, + .wpr_layout = gm200_acr_wpr_layout, + .wpr_alloc = gm20b_acr_wpr_alloc, + .wpr_build = gm200_acr_wpr_build, + .wpr_patch = gm200_acr_wpr_patch, + .wpr_check = gm200_acr_wpr_check, + .init = gm200_acr_init, +}; + +static const struct nvkm_acr_fwif +gp10b_acr_fwif[] = { + { 0, gm20b_acr_load, &gp10b_acr }, + { -1, gm200_acr_nofw, &gm200_acr }, + {} +}; + +int +gp10b_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_acr **pacr) +{ + return nvkm_acr_new_(gp10b_acr_fwif, device, type, inst, pacr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/hsfw.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/hsfw.c new file mode 100644 index 000000000000..a6ea89a5d51a --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/hsfw.c @@ -0,0 +1,177 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +#include <core/firmware.h> + +#include <nvfw/fw.h> +#include <nvfw/hs.h> + +static void +nvkm_acr_hsfw_del(struct nvkm_acr_hsfw *hsfw) +{ + list_del(&hsfw->head); + kfree(hsfw->imem); + kfree(hsfw->image); + kfree(hsfw->sig.prod.data); + kfree(hsfw->sig.dbg.data); + kfree(hsfw); +} + +void +nvkm_acr_hsfw_del_all(struct nvkm_acr *acr) +{ + struct nvkm_acr_hsfw *hsfw, *hsft; + list_for_each_entry_safe(hsfw, hsft, &acr->hsfw, head) { + nvkm_acr_hsfw_del(hsfw); + } +} + +static int +nvkm_acr_hsfw_load_image(struct nvkm_acr *acr, const char *name, int ver, + struct nvkm_acr_hsfw *hsfw) +{ + struct nvkm_subdev *subdev = &acr->subdev; + const struct firmware *fw; + const struct nvfw_bin_hdr *hdr; + const struct nvfw_hs_header *fwhdr; + const struct nvfw_hs_load_header *lhdr; + u32 loc, sig; + int ret; + + ret = nvkm_firmware_get(subdev, name, ver, &fw); + if (ret < 0) + return ret; + + hdr = nvfw_bin_hdr(subdev, fw->data); + fwhdr = nvfw_hs_header(subdev, fw->data + hdr->header_offset); + + /* Earlier FW releases by NVIDIA for Nouveau's use aren't in NVIDIA's + * standard format, and don't have the indirection seen in the 0x10de + * case. + */ + switch (hdr->bin_magic) { + case 0x000010de: + loc = *(u32 *)(fw->data + fwhdr->patch_loc); + sig = *(u32 *)(fw->data + fwhdr->patch_sig); + break; + case 0x3b1d14f0: + loc = fwhdr->patch_loc; + sig = fwhdr->patch_sig; + break; + default: + ret = -EINVAL; + goto done; + } + + lhdr = nvfw_hs_load_header(subdev, fw->data + fwhdr->hdr_offset); + + if (!(hsfw->image = kmalloc(hdr->data_size, GFP_KERNEL))) { + ret = -ENOMEM; + goto done; + } + + memcpy(hsfw->image, fw->data + hdr->data_offset, hdr->data_size); + hsfw->image_size = hdr->data_size; + hsfw->non_sec_addr = lhdr->non_sec_code_off; + hsfw->non_sec_size = lhdr->non_sec_code_size; + hsfw->sec_addr = lhdr->apps[0]; + hsfw->sec_size = lhdr->apps[lhdr->num_apps]; + hsfw->data_addr = lhdr->data_dma_base; + hsfw->data_size = lhdr->data_size; + + hsfw->sig.prod.size = fwhdr->sig_prod_size; + hsfw->sig.prod.data = kmemdup(fw->data + fwhdr->sig_prod_offset + sig, + hsfw->sig.prod.size, GFP_KERNEL); + if (!hsfw->sig.prod.data) { + ret = -ENOMEM; + goto done; + } + + hsfw->sig.dbg.size = fwhdr->sig_dbg_size; + hsfw->sig.dbg.data = kmemdup(fw->data + fwhdr->sig_dbg_offset + sig, + hsfw->sig.dbg.size, GFP_KERNEL); + if (!hsfw->sig.dbg.data) { + ret = -ENOMEM; + goto done; + } + + hsfw->sig.patch_loc = loc; +done: + nvkm_firmware_put(fw); + return ret; +} + +static int +nvkm_acr_hsfw_load_bl(struct nvkm_acr *acr, const char *name, int ver, + struct nvkm_acr_hsfw *hsfw) +{ + struct nvkm_subdev *subdev = &acr->subdev; + const struct nvfw_bin_hdr *hdr; + const struct nvfw_bl_desc *desc; + const struct firmware *fw; + u8 *data; + int ret; + + ret = nvkm_firmware_get(subdev, name, ver, &fw); + if (ret) + return ret; + + hdr = nvfw_bin_hdr(subdev, fw->data); + desc = nvfw_bl_desc(subdev, fw->data + hdr->header_offset); + data = (void *)fw->data + hdr->data_offset; + + hsfw->imem_size = desc->code_size; + hsfw->imem_tag = desc->start_tag; + hsfw->imem = kmemdup(data + desc->code_off, desc->code_size, GFP_KERNEL); + nvkm_firmware_put(fw); + if (!hsfw->imem) + return -ENOMEM; + else + return 0; +} + +int +nvkm_acr_hsfw_load(struct nvkm_acr *acr, const char *bl, const char *fw, + const char *name, int version, + const struct nvkm_acr_hsf_fwif *fwif) +{ + struct nvkm_acr_hsfw *hsfw; + int ret; + + if (!(hsfw = kzalloc(sizeof(*hsfw), GFP_KERNEL))) + return -ENOMEM; + + hsfw->func = fwif->func; + hsfw->name = name; + list_add_tail(&hsfw->head, &acr->hsfw); + + ret = nvkm_acr_hsfw_load_bl(acr, bl, version, hsfw); + if (ret) + goto done; + + ret = nvkm_acr_hsfw_load_image(acr, fw, version, hsfw); +done: + if (ret) + nvkm_acr_hsfw_del(hsfw); + return ret; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c new file mode 100644 index 000000000000..9b1cf6711ae9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c @@ -0,0 +1,253 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" +#include <core/falcon.h> +#include <core/firmware.h> +#include <nvfw/fw.h> +#include <nvfw/ls.h> + +void +nvkm_acr_lsfw_del(struct nvkm_acr_lsfw *lsfw) +{ + nvkm_blob_dtor(&lsfw->img); + nvkm_firmware_put(lsfw->sig); + list_del(&lsfw->head); + kfree(lsfw); +} + +void +nvkm_acr_lsfw_del_all(struct nvkm_acr *acr) +{ + struct nvkm_acr_lsfw *lsfw, *lsft; + list_for_each_entry_safe(lsfw, lsft, &acr->lsfw, head) { + nvkm_acr_lsfw_del(lsfw); + } +} + +static struct nvkm_acr_lsfw * +nvkm_acr_lsfw_get(struct nvkm_acr *acr, enum nvkm_acr_lsf_id id) +{ + struct nvkm_acr_lsfw *lsfw; + list_for_each_entry(lsfw, &acr->lsfw, head) { + if (lsfw->id == id) + return lsfw; + } + return NULL; +} + +struct nvkm_acr_lsfw * +nvkm_acr_lsfw_add(const struct nvkm_acr_lsf_func *func, struct nvkm_acr *acr, + struct nvkm_falcon *falcon, enum nvkm_acr_lsf_id id) +{ + struct nvkm_acr_lsfw *lsfw; + + if (!acr || list_empty(&acr->hsfw)) + return ERR_PTR(-ENOSYS); + + lsfw = nvkm_acr_lsfw_get(acr, id); + if (lsfw && lsfw->func) { + nvkm_error(&acr->subdev, "LSFW %d redefined\n", id); + return ERR_PTR(-EEXIST); + } + + if (!lsfw) { + if (!(lsfw = kzalloc(sizeof(*lsfw), GFP_KERNEL))) + return ERR_PTR(-ENOMEM); + + lsfw->id = id; + list_add_tail(&lsfw->head, &acr->lsfw); + } + + lsfw->func = func; + lsfw->falcon = falcon; + return lsfw; +} + +static struct nvkm_acr_lsfw * +nvkm_acr_lsfw_load_sig_image_desc_(struct nvkm_subdev *subdev, + struct nvkm_falcon *falcon, + enum nvkm_acr_lsf_id id, + const char *path, int ver, + const struct nvkm_acr_lsf_func *func, + const struct firmware **pdesc) +{ + struct nvkm_acr *acr = subdev->device->acr; + struct nvkm_acr_lsfw *lsfw; + int ret; + + if (IS_ERR((lsfw = nvkm_acr_lsfw_add(func, acr, falcon, id)))) + return lsfw; + + ret = nvkm_firmware_load_name(subdev, path, "sig", ver, &lsfw->sig); + if (ret) + goto done; + + ret = nvkm_firmware_load_blob(subdev, path, "image", ver, &lsfw->img); + if (ret) + goto done; + + ret = nvkm_firmware_load_name(subdev, path, "desc", ver, pdesc); +done: + if (ret) { + nvkm_acr_lsfw_del(lsfw); + return ERR_PTR(ret); + } + + return lsfw; +} + +static void +nvkm_acr_lsfw_from_desc(const struct nvfw_ls_desc_head *desc, + struct nvkm_acr_lsfw *lsfw) +{ + lsfw->bootloader_size = ALIGN(desc->bootloader_size, 256); + lsfw->bootloader_imem_offset = desc->bootloader_imem_offset; + + lsfw->app_size = ALIGN(desc->app_size, 256); + lsfw->app_start_offset = desc->app_start_offset; + lsfw->app_imem_entry = desc->app_imem_entry; + lsfw->app_resident_code_offset = desc->app_resident_code_offset; + lsfw->app_resident_code_size = desc->app_resident_code_size; + lsfw->app_resident_data_offset = desc->app_resident_data_offset; + lsfw->app_resident_data_size = desc->app_resident_data_size; + + lsfw->ucode_size = ALIGN(lsfw->app_resident_data_offset, 256) + + lsfw->bootloader_size; + lsfw->data_size = lsfw->app_size + lsfw->bootloader_size - + lsfw->ucode_size; +} + +int +nvkm_acr_lsfw_load_sig_image_desc(struct nvkm_subdev *subdev, + struct nvkm_falcon *falcon, + enum nvkm_acr_lsf_id id, + const char *path, int ver, + const struct nvkm_acr_lsf_func *func) +{ + const struct firmware *fw; + struct nvkm_acr_lsfw *lsfw; + + lsfw = nvkm_acr_lsfw_load_sig_image_desc_(subdev, falcon, id, path, ver, + func, &fw); + if (IS_ERR(lsfw)) + return PTR_ERR(lsfw); + + nvkm_acr_lsfw_from_desc(&nvfw_ls_desc(subdev, fw->data)->head, lsfw); + nvkm_firmware_put(fw); + return 0; +} + +int +nvkm_acr_lsfw_load_sig_image_desc_v1(struct nvkm_subdev *subdev, + struct nvkm_falcon *falcon, + enum nvkm_acr_lsf_id id, + const char *path, int ver, + const struct nvkm_acr_lsf_func *func) +{ + const struct firmware *fw; + struct nvkm_acr_lsfw *lsfw; + + lsfw = nvkm_acr_lsfw_load_sig_image_desc_(subdev, falcon, id, path, ver, + func, &fw); + if (IS_ERR(lsfw)) + return PTR_ERR(lsfw); + + nvkm_acr_lsfw_from_desc(&nvfw_ls_desc_v1(subdev, fw->data)->head, lsfw); + nvkm_firmware_put(fw); + return 0; +} + +int +nvkm_acr_lsfw_load_bl_inst_data_sig(struct nvkm_subdev *subdev, + struct nvkm_falcon *falcon, + enum nvkm_acr_lsf_id id, + const char *path, int ver, + const struct nvkm_acr_lsf_func *func) +{ + struct nvkm_acr *acr = subdev->device->acr; + struct nvkm_acr_lsfw *lsfw; + const struct firmware *bl = NULL, *inst = NULL, *data = NULL; + const struct nvfw_bin_hdr *hdr; + const struct nvfw_bl_desc *desc; + u32 *bldata; + int ret; + + if (IS_ERR((lsfw = nvkm_acr_lsfw_add(func, acr, falcon, id)))) + return PTR_ERR(lsfw); + + ret = nvkm_firmware_load_name(subdev, path, "bl", ver, &bl); + if (ret) + goto done; + + hdr = nvfw_bin_hdr(subdev, bl->data); + desc = nvfw_bl_desc(subdev, bl->data + hdr->header_offset); + bldata = (void *)(bl->data + hdr->data_offset); + + ret = nvkm_firmware_load_name(subdev, path, "inst", ver, &inst); + if (ret) + goto done; + + ret = nvkm_firmware_load_name(subdev, path, "data", ver, &data); + if (ret) + goto done; + + ret = nvkm_firmware_load_name(subdev, path, "sig", ver, &lsfw->sig); + if (ret) + goto done; + + lsfw->bootloader_size = ALIGN(desc->code_size, 256); + lsfw->bootloader_imem_offset = desc->start_tag << 8; + + lsfw->app_start_offset = lsfw->bootloader_size; + lsfw->app_imem_entry = 0; + lsfw->app_resident_code_offset = 0; + lsfw->app_resident_code_size = ALIGN(inst->size, 256); + lsfw->app_resident_data_offset = lsfw->app_resident_code_size; + lsfw->app_resident_data_size = ALIGN(data->size, 256); + lsfw->app_size = lsfw->app_resident_code_size + + lsfw->app_resident_data_size; + + lsfw->img.size = lsfw->bootloader_size + lsfw->app_size; + if (!(lsfw->img.data = kzalloc(lsfw->img.size, GFP_KERNEL))) { + ret = -ENOMEM; + goto done; + } + + memcpy(lsfw->img.data, bldata, lsfw->bootloader_size); + memcpy(lsfw->img.data + lsfw->app_start_offset + + lsfw->app_resident_code_offset, inst->data, inst->size); + memcpy(lsfw->img.data + lsfw->app_start_offset + + lsfw->app_resident_data_offset, data->data, data->size); + + lsfw->ucode_size = ALIGN(lsfw->app_resident_data_offset, 256) + + lsfw->bootloader_size; + lsfw->data_size = lsfw->app_size + lsfw->bootloader_size - + lsfw->ucode_size; + +done: + if (ret) + nvkm_acr_lsfw_del(lsfw); + nvkm_firmware_put(data); + nvkm_firmware_put(inst); + nvkm_firmware_put(bl); + return ret; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h new file mode 100644 index 000000000000..c30b841c9d35 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h @@ -0,0 +1,154 @@ +#ifndef __NVKM_ACR_PRIV_H__ +#define __NVKM_ACR_PRIV_H__ +#include <subdev/acr.h> +struct lsb_header_tail; + +struct nvkm_acr_fwif { + int version; + int (*load)(struct nvkm_acr *, int version, + const struct nvkm_acr_fwif *); + const struct nvkm_acr_func *func; +}; + +int gm200_acr_nofw(struct nvkm_acr *, int, const struct nvkm_acr_fwif *); +int gm20b_acr_load(struct nvkm_acr *, int, const struct nvkm_acr_fwif *); +int gp102_acr_load(struct nvkm_acr *, int, const struct nvkm_acr_fwif *); + +struct nvkm_acr_lsf; +struct nvkm_acr_func { + const struct nvkm_acr_hsf_fwif *load; + const struct nvkm_acr_hsf_fwif *ahesasc; + const struct nvkm_acr_hsf_fwif *asb; + const struct nvkm_acr_hsf_fwif *unload; + int (*wpr_parse)(struct nvkm_acr *); + u32 (*wpr_layout)(struct nvkm_acr *); + int (*wpr_alloc)(struct nvkm_acr *, u32 wpr_size); + int (*wpr_build)(struct nvkm_acr *, struct nvkm_acr_lsf *rtos); + void (*wpr_patch)(struct nvkm_acr *, s64 adjust); + void (*wpr_check)(struct nvkm_acr *, u64 *start, u64 *limit); + int (*init)(struct nvkm_acr *); + void (*fini)(struct nvkm_acr *); + u64 bootstrap_falcons; +}; + +extern const struct nvkm_acr_func gm200_acr; +int gm200_acr_wpr_parse(struct nvkm_acr *); +u32 gm200_acr_wpr_layout(struct nvkm_acr *); +int gm200_acr_wpr_build(struct nvkm_acr *, struct nvkm_acr_lsf *); +void gm200_acr_wpr_patch(struct nvkm_acr *, s64); +void gm200_acr_wpr_check(struct nvkm_acr *, u64 *, u64 *); +void gm200_acr_wpr_build_lsb_tail(struct nvkm_acr_lsfw *, + struct lsb_header_tail *); +int gm200_acr_init(struct nvkm_acr *); + +int gm20b_acr_wpr_alloc(struct nvkm_acr *, u32 wpr_size); + +int gp102_acr_wpr_parse(struct nvkm_acr *); +u32 gp102_acr_wpr_layout(struct nvkm_acr *); +int gp102_acr_wpr_alloc(struct nvkm_acr *, u32 wpr_size); +int gp102_acr_wpr_build(struct nvkm_acr *, struct nvkm_acr_lsf *); +int gp102_acr_wpr_build_lsb(struct nvkm_acr *, struct nvkm_acr_lsfw *); +void gp102_acr_wpr_patch(struct nvkm_acr *, s64); + +struct nvkm_acr_hsfw { + const struct nvkm_acr_hsf_func *func; + const char *name; + struct list_head head; + + u32 imem_size; + u32 imem_tag; + u32 *imem; + + u8 *image; + u32 image_size; + u32 non_sec_addr; + u32 non_sec_size; + u32 sec_addr; + u32 sec_size; + u32 data_addr; + u32 data_size; + + struct { + struct { + void *data; + u32 size; + } prod, dbg; + u32 patch_loc; + } sig; +}; + +struct nvkm_acr_hsf_fwif { + int version; + int (*load)(struct nvkm_acr *, const char *bl, const char *fw, + const char *name, int version, + const struct nvkm_acr_hsf_fwif *); + const struct nvkm_acr_hsf_func *func; +}; + +int nvkm_acr_hsfw_load(struct nvkm_acr *, const char *, const char *, + const char *, int, const struct nvkm_acr_hsf_fwif *); +void nvkm_acr_hsfw_del_all(struct nvkm_acr *); + +struct nvkm_acr_hsf { + const struct nvkm_acr_hsf_func *func; + const char *name; + struct list_head head; + + u32 imem_size; + u32 imem_tag; + u32 *imem; + + u32 non_sec_addr; + u32 non_sec_size; + u32 sec_addr; + u32 sec_size; + u32 data_addr; + u32 data_size; + + struct nvkm_memory *ucode; + struct nvkm_vma *vma; + struct nvkm_falcon *falcon; +}; + +struct nvkm_acr_hsf_func { + int (*load)(struct nvkm_acr *, struct nvkm_acr_hsfw *); + int (*boot)(struct nvkm_acr *, struct nvkm_acr_hsf *); + void (*bld)(struct nvkm_acr *, struct nvkm_acr_hsf *); +}; + +int gm200_acr_hsfw_load(struct nvkm_acr *, struct nvkm_acr_hsfw *, + struct nvkm_falcon *); +int gm200_acr_hsfw_boot(struct nvkm_acr *, struct nvkm_acr_hsf *, + u32 clear_intr, u32 mbox0_ok); + +int gm200_acr_load_boot(struct nvkm_acr *, struct nvkm_acr_hsf *); + +extern const struct nvkm_acr_hsf_func gm200_acr_unload_0; +int gm200_acr_unload_load(struct nvkm_acr *, struct nvkm_acr_hsfw *); +int gm200_acr_unload_boot(struct nvkm_acr *, struct nvkm_acr_hsf *); +void gm200_acr_hsfw_bld(struct nvkm_acr *, struct nvkm_acr_hsf *); + +extern const struct nvkm_acr_hsf_func gm20b_acr_load_0; + +int gp102_acr_load_load(struct nvkm_acr *, struct nvkm_acr_hsfw *); + +extern const struct nvkm_acr_hsf_func gp108_acr_unload_0; +void gp108_acr_hsfw_bld(struct nvkm_acr *, struct nvkm_acr_hsf *); + +int nvkm_acr_new_(const struct nvkm_acr_fwif *, struct nvkm_device *, enum nvkm_subdev_type, + int inst, struct nvkm_acr **); +int nvkm_acr_hsf_boot(struct nvkm_acr *, const char *name); + +struct nvkm_acr_lsf { + const struct nvkm_acr_lsf_func *func; + struct nvkm_falcon *falcon; + enum nvkm_acr_lsf_id id; + struct list_head head; +}; + +struct nvkm_acr_lsfw *nvkm_acr_lsfw_add(const struct nvkm_acr_lsf_func *, + struct nvkm_acr *, struct nvkm_falcon *, + enum nvkm_acr_lsf_id); +void nvkm_acr_lsfw_del(struct nvkm_acr_lsfw *); +void nvkm_acr_lsfw_del_all(struct nvkm_acr *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c new file mode 100644 index 000000000000..05a87e77525f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c @@ -0,0 +1,231 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +#include <core/firmware.h> +#include <core/memory.h> +#include <subdev/gsp.h> +#include <subdev/pmu.h> +#include <engine/sec2.h> + +#include <nvfw/acr.h> + +static int +tu102_acr_init(struct nvkm_acr *acr) +{ + int ret = nvkm_acr_hsf_boot(acr, "AHESASC"); + if (ret) + return ret; + + return nvkm_acr_hsf_boot(acr, "ASB"); +} + +static int +tu102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos) +{ + struct nvkm_acr_lsfw *lsfw; + u32 offset = 0; + int ret; + + /*XXX: shared sub-WPR headers, fill terminator for now. */ + nvkm_wo32(acr->wpr, 0x200, 0xffffffff); + + /* Fill per-LSF structures. */ + list_for_each_entry(lsfw, &acr->lsfw, head) { + struct lsf_signature_v1 *sig = (void *)lsfw->sig->data; + struct wpr_header_v1 hdr = { + .falcon_id = lsfw->id, + .lsb_offset = lsfw->offset.lsb, + .bootstrap_owner = NVKM_ACR_LSF_GSPLITE, + .lazy_bootstrap = 1, + .bin_version = sig->version, + .status = WPR_HEADER_V1_STATUS_COPY, + }; + + /* Write WPR header. */ + nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr)); + offset += sizeof(hdr); + + /* Write LSB header. */ + ret = gp102_acr_wpr_build_lsb(acr, lsfw); + if (ret) + return ret; + + /* Write ucode image. */ + nvkm_wobj(acr->wpr, lsfw->offset.img, + lsfw->img.data, + lsfw->img.size); + + /* Write bootloader data. */ + lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw); + } + + /* Finalise WPR. */ + nvkm_wo32(acr->wpr, offset, WPR_HEADER_V1_FALCON_ID_INVALID); + return 0; +} + +static int +tu102_acr_hsfw_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf) +{ + return gm200_acr_hsfw_boot(acr, hsf, 0, 0); +} + +static int +tu102_acr_hsfw_nofw(struct nvkm_acr *acr, const char *bl, const char *fw, + const char *name, int version, + const struct nvkm_acr_hsf_fwif *fwif) +{ + return 0; +} + +MODULE_FIRMWARE("nvidia/tu102/acr/unload_bl.bin"); +MODULE_FIRMWARE("nvidia/tu102/acr/ucode_unload.bin"); + +MODULE_FIRMWARE("nvidia/tu104/acr/unload_bl.bin"); +MODULE_FIRMWARE("nvidia/tu104/acr/ucode_unload.bin"); + +MODULE_FIRMWARE("nvidia/tu106/acr/unload_bl.bin"); +MODULE_FIRMWARE("nvidia/tu106/acr/ucode_unload.bin"); + +MODULE_FIRMWARE("nvidia/tu116/acr/unload_bl.bin"); +MODULE_FIRMWARE("nvidia/tu116/acr/ucode_unload.bin"); + +MODULE_FIRMWARE("nvidia/tu117/acr/unload_bl.bin"); +MODULE_FIRMWARE("nvidia/tu117/acr/ucode_unload.bin"); + +static const struct nvkm_acr_hsf_fwif +tu102_acr_unload_fwif[] = { + { 0, nvkm_acr_hsfw_load, &gp108_acr_unload_0 }, + { -1, tu102_acr_hsfw_nofw }, + {} +}; + +static int +tu102_acr_asb_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw) +{ + return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->gsp->falcon); +} + +static const struct nvkm_acr_hsf_func +tu102_acr_asb_0 = { + .load = tu102_acr_asb_load, + .boot = tu102_acr_hsfw_boot, + .bld = gp108_acr_hsfw_bld, +}; + +MODULE_FIRMWARE("nvidia/tu102/acr/ucode_asb.bin"); +MODULE_FIRMWARE("nvidia/tu104/acr/ucode_asb.bin"); +MODULE_FIRMWARE("nvidia/tu106/acr/ucode_asb.bin"); +MODULE_FIRMWARE("nvidia/tu116/acr/ucode_asb.bin"); +MODULE_FIRMWARE("nvidia/tu117/acr/ucode_asb.bin"); + +static const struct nvkm_acr_hsf_fwif +tu102_acr_asb_fwif[] = { + { 0, nvkm_acr_hsfw_load, &tu102_acr_asb_0 }, + { -1, tu102_acr_hsfw_nofw }, + {} +}; + +static const struct nvkm_acr_hsf_func +tu102_acr_ahesasc_0 = { + .load = gp102_acr_load_load, + .boot = tu102_acr_hsfw_boot, + .bld = gp108_acr_hsfw_bld, +}; + +MODULE_FIRMWARE("nvidia/tu102/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/tu102/acr/ucode_ahesasc.bin"); + +MODULE_FIRMWARE("nvidia/tu104/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/tu104/acr/ucode_ahesasc.bin"); + +MODULE_FIRMWARE("nvidia/tu106/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/tu106/acr/ucode_ahesasc.bin"); + +MODULE_FIRMWARE("nvidia/tu116/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/tu116/acr/ucode_ahesasc.bin"); + +MODULE_FIRMWARE("nvidia/tu117/acr/bl.bin"); +MODULE_FIRMWARE("nvidia/tu117/acr/ucode_ahesasc.bin"); + +static const struct nvkm_acr_hsf_fwif +tu102_acr_ahesasc_fwif[] = { + { 0, nvkm_acr_hsfw_load, &tu102_acr_ahesasc_0 }, + { -1, tu102_acr_hsfw_nofw }, + {} +}; + +static const struct nvkm_acr_func +tu102_acr = { + .ahesasc = tu102_acr_ahesasc_fwif, + .asb = tu102_acr_asb_fwif, + .unload = tu102_acr_unload_fwif, + .wpr_parse = gp102_acr_wpr_parse, + .wpr_layout = gp102_acr_wpr_layout, + .wpr_alloc = gp102_acr_wpr_alloc, + .wpr_patch = gp102_acr_wpr_patch, + .wpr_build = tu102_acr_wpr_build, + .wpr_check = gm200_acr_wpr_check, + .init = tu102_acr_init, +}; + +static int +tu102_acr_load(struct nvkm_acr *acr, int version, + const struct nvkm_acr_fwif *fwif) +{ + struct nvkm_subdev *subdev = &acr->subdev; + const struct nvkm_acr_hsf_fwif *hsfwif; + + hsfwif = nvkm_firmware_load(subdev, fwif->func->ahesasc, "AcrAHESASC", + acr, "acr/bl", "acr/ucode_ahesasc", + "AHESASC"); + if (IS_ERR(hsfwif)) + return PTR_ERR(hsfwif); + + hsfwif = nvkm_firmware_load(subdev, fwif->func->asb, "AcrASB", + acr, "acr/bl", "acr/ucode_asb", "ASB"); + if (IS_ERR(hsfwif)) + return PTR_ERR(hsfwif); + + hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload", + acr, "acr/unload_bl", "acr/ucode_unload", + "unload"); + if (IS_ERR(hsfwif)) + return PTR_ERR(hsfwif); + + return 0; +} + +static const struct nvkm_acr_fwif +tu102_acr_fwif[] = { + { 0, tu102_acr_load, &tu102_acr }, + { -1, gm200_acr_nofw, &gm200_acr }, + {} +}; + +int +tu102_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_acr **pacr) +{ + return nvkm_acr_new_(tu102_acr_fwif, device, type, inst, pacr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c index 209a6a40834a..d017a1b5e5dd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c @@ -134,9 +134,9 @@ nvkm_bar = { void nvkm_bar_ctor(const struct nvkm_bar_func *func, struct nvkm_device *device, - int index, struct nvkm_bar *bar) + enum nvkm_subdev_type type, int inst, struct nvkm_bar *bar) { - nvkm_subdev_ctor(&nvkm_bar, device, index, &bar->subdev); + nvkm_subdev_ctor(&nvkm_bar, device, type, inst, &bar->subdev); bar->func = func; spin_lock_init(&bar->lock); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c index 87f26f54b481..77a41bcf860e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c @@ -56,7 +56,8 @@ g84_bar_func = { }; int -g84_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +g84_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - return nv50_bar_new_(&g84_bar_func, device, index, 0x200, pbar); + return nv50_bar_new_(&g84_bar_func, device, type, inst, 0x200, pbar); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c index a3dcb09a40ee..51070b7dda85 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c @@ -162,12 +162,12 @@ gf100_bar_dtor(struct nvkm_bar *base) int gf100_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device, - int index, struct nvkm_bar **pbar) + enum nvkm_subdev_type type, int inst, struct nvkm_bar **pbar) { struct gf100_bar *bar; if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL))) return -ENOMEM; - nvkm_bar_ctor(func, device, index, &bar->base); + nvkm_bar_ctor(func, device, type, inst, &bar->base); bar->bar2_halve = nvkm_boolopt(device->cfgopt, "NvBar2Halve", false); *pbar = &bar->base; return 0; @@ -189,7 +189,8 @@ gf100_bar_func = { }; int -gf100_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +gf100_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - return gf100_bar_new_(&gf100_bar_func, device, index, pbar); + return gf100_bar_new_(&gf100_bar_func, device, type, inst, pbar); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h index 4ae4c7145712..328a68b418d9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h @@ -15,7 +15,7 @@ struct gf100_bar { struct gf100_barN bar[2]; }; -int gf100_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *, +int gf100_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_bar **); void *gf100_bar_dtor(struct nvkm_bar *); int gf100_bar_oneinit(struct nvkm_bar *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c index 35878fb538f2..eead8ab88393 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c @@ -32,9 +32,10 @@ gk20a_bar_func = { }; int -gk20a_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +gk20a_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - int ret = gf100_bar_new_(&gk20a_bar_func, device, index, pbar); + int ret = gf100_bar_new_(&gk20a_bar_func, device, type, inst, pbar); if (ret == 0) (*pbar)->iomap_uncached = true; return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c index 3ddf9222d935..da95307a7912 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c @@ -59,7 +59,8 @@ gm107_bar_func = { }; int -gm107_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +gm107_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - return gf100_bar_new_(&gm107_bar_func, device, index, pbar); + return gf100_bar_new_(&gm107_bar_func, device, type, inst, pbar); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c index 950bff1955ad..4acdb4fb0107 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c @@ -26,16 +26,16 @@ gm20b_bar_func = { .dtor = gf100_bar_dtor, .oneinit = gf100_bar_oneinit, .bar1.init = gf100_bar_bar1_init, - .bar1.fini = gf100_bar_bar1_fini, .bar1.wait = gm107_bar_bar1_wait, .bar1.vmm = gf100_bar_bar1_vmm, .flush = g84_bar_flush, }; int -gm20b_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +gm20b_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - int ret = gf100_bar_new_(&gm20b_bar_func, device, index, pbar); + int ret = gf100_bar_new_(&gm20b_bar_func, device, type, inst, pbar); if (ret == 0) (*pbar)->iomap_uncached = true; return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c index f23a0ccc2bec..27d8a1be43e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c @@ -220,12 +220,12 @@ nv50_bar_dtor(struct nvkm_bar *base) int nv50_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device, - int index, u32 pgd_addr, struct nvkm_bar **pbar) + enum nvkm_subdev_type type, int inst, u32 pgd_addr, struct nvkm_bar **pbar) { struct nv50_bar *bar; if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL))) return -ENOMEM; - nvkm_bar_ctor(func, device, index, &bar->base); + nvkm_bar_ctor(func, device, type, inst, &bar->base); bar->pgd_addr = pgd_addr; *pbar = &bar->base; return 0; @@ -248,7 +248,8 @@ nv50_bar_func = { }; int -nv50_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +nv50_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - return nv50_bar_new_(&nv50_bar_func, device, index, 0x1400, pbar); + return nv50_bar_new_(&nv50_bar_func, device, type, inst, 0x1400, pbar); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h index e4193deb2e51..dedee9394079 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h @@ -16,7 +16,7 @@ struct nv50_bar { struct nvkm_gpuobj *bar2; }; -int nv50_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *, +int nv50_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *, enum nvkm_subdev_type, int, u32 pgd_addr, struct nvkm_bar **); void *nv50_bar_dtor(struct nvkm_bar *); int nv50_bar_oneinit(struct nvkm_bar *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h index 869ad184f923..daebfc991c76 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h @@ -5,7 +5,7 @@ #include <subdev/bar.h> void nvkm_bar_ctor(const struct nvkm_bar_func *, struct nvkm_device *, - int, struct nvkm_bar *); + enum nvkm_subdev_type, int, struct nvkm_bar *); struct nvkm_bar_func { void *(*dtor)(struct nvkm_bar *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c index 798f65ec3a86..c25ab407b85d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c @@ -92,7 +92,8 @@ tu102_bar = { }; int -tu102_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +tu102_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - return gf100_bar_new_(&tu102_bar, device, index, pbar); + return gf100_bar_new_(&tu102_bar, device, type, inst, pbar); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c index f3c30b2a788e..64e423dddd9e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c @@ -38,7 +38,7 @@ nvbios_addr(struct nvkm_bios *bios, u32 *addr, u8 size) *addr += bios->imaged_addr; } - if (unlikely(*addr + size >= bios->size)) { + if (unlikely(*addr + size > bios->size)) { nvkm_error(&bios->subdev, "OOB %d %08x %08x\n", size, p, *addr); return false; } @@ -140,7 +140,8 @@ nvkm_bios = { }; int -nvkm_bios_new(struct nvkm_device *device, int index, struct nvkm_bios **pbios) +nvkm_bios_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bios **pbios) { struct nvkm_bios *bios; struct nvbios_image image; @@ -149,7 +150,7 @@ nvkm_bios_new(struct nvkm_device *device, int index, struct nvkm_bios **pbios) if (!(bios = *pbios = kzalloc(sizeof(*bios), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_bios, device, index, &bios->subdev); + nvkm_subdev_ctor(&nvkm_bios, device, type, inst, &bios->subdev); ret = nvbios_shadow(bios); if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c index a8d5d67feeaf..8698f260b988 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c @@ -172,8 +172,8 @@ dcb_outp_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len, outp->dpconf.link_nr = 1; break; } + fallthrough; - /* fall-through... */ case DCB_OUTPUT_TMDS: case DCB_OUTPUT_LVDS: outp->link = (conf & 0x00000030) >> 4; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c index b099d1209be8..c694501ae206 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c @@ -100,7 +100,7 @@ nvbios_dpout_parse(struct nvkm_bios *bios, u8 idx, switch (*ver) { case 0x20: info->mask |= 0x00c0; /* match any link */ - /* fall-through */ + fallthrough; case 0x21: case 0x30: info->flags = nvbios_rd08(bios, data + 0x05); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c index b8578359e61b..118e33174cbe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c @@ -46,6 +46,19 @@ extdev_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) return extdev + *hdr; } +bool +nvbios_extdev_skip_probe(struct nvkm_bios *bios) +{ + u8 ver, hdr, len, cnt; + u16 data = extdev_table(bios, &ver, &hdr, &len, &cnt); + if (data && ver == 0x40 && hdr >= 5) { + u8 flags = nvbios_rd08(bios, data - hdr + 4); + if (flags & 1) + return true; + } + return false; +} + static u16 nvbios_extdev_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c index ec0e9f7224b5..142079403864 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c @@ -401,7 +401,7 @@ init_table_(struct nvbios_init *init, u16 offset, const char *name) #define init_macro_table(b) init_table_((b), 0x04, "macro table") #define init_condition_table(b) init_table_((b), 0x06, "condition table") #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table") -#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table") +#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag condition table") #define init_function_table(b) init_table_((b), 0x0c, "function table") #define init_xlat_table(b) init_table_((b), 0x10, "xlat table"); @@ -834,7 +834,7 @@ init_generic_condition(struct nvbios_init *init) init_exec_set(init, false); break; default: - warn("INIT_GENERIC_CONDITON: unknown 0x%02x\n", cond); + warn("INIT_GENERIC_CONDITION: unknown 0x%02x\n", cond); init->offset += size; break; } @@ -1935,6 +1935,28 @@ init_ram_restrict_pll(struct nvbios_init *init) } /** + * INIT_RESET_BEGUN - opcode 0x8c + * + */ +static void +init_reset_begun(struct nvbios_init *init) +{ + trace("RESET_BEGUN\n"); + init->offset += 1; +} + +/** + * INIT_RESET_END - opcode 0x8d + * + */ +static void +init_reset_end(struct nvbios_init *init) +{ + trace("RESET_END\n"); + init->offset += 1; +} + +/** * INIT_GPIO - opcode 0x8e * */ @@ -2260,8 +2282,8 @@ static struct nvbios_init_opcode { [0x79] = { init_pll }, [0x7a] = { init_zm_reg }, [0x87] = { init_ram_restrict_pll }, - [0x8c] = { init_reserved }, - [0x8d] = { init_reserved }, + [0x8c] = { init_reset_begun }, + [0x8d] = { init_reset_end }, [0x8e] = { init_gpio }, [0x8f] = { init_ram_restrict_zm_reg_group }, [0x90] = { init_copy_zm_reg }, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c index 7112992e0e38..f039388f0676 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c @@ -135,7 +135,7 @@ nvbios_perfEp(struct nvkm_bios *bios, int idx, break; case 0x30: info->script = nvbios_rd16(bios, perf + 0x02); - /* fall through */ + fallthrough; case 0x35: info->fanspeed = nvbios_rd08(bios, perf + 0x06); info->voltage = nvbios_rd08(bios, perf + 0x07); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c index bda6cc9a7aaf..2ec84b8a3b3a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c @@ -123,7 +123,6 @@ pll_map(struct nvkm_bios *bios) case NV_20: case NV_30: return nv04_pll_mapping; - break; case NV_40: return nv40_pll_mapping; case NV_50: @@ -134,7 +133,7 @@ pll_map(struct nvkm_bios *bios) device->chipset == 0xaa || device->chipset == 0xac) return g84_pll_mapping; - /* fall through */ + fallthrough; default: return NULL; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c index 7deb81b6dbac..4b571cc6bc70 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c @@ -75,7 +75,7 @@ shadow_image(struct nvkm_bios *bios, int idx, u32 offset, struct shadow *mthd) nvkm_debug(subdev, "%08x: type %02x, %d bytes\n", image.base, image.type, image.size); - if (!shadow_fetch(bios, mthd, image.size)) { + if (!shadow_fetch(bios, mthd, image.base + image.size)) { nvkm_debug(subdev, "%08x: fetch failed\n", image.base); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c index 06572f8ce914..f9c427559538 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c @@ -22,22 +22,39 @@ */ #include "priv.h" -#if defined(CONFIG_ACPI) && defined(CONFIG_X86) -int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); -bool nouveau_acpi_rom_supported(struct device *); -#else -static inline bool -nouveau_acpi_rom_supported(struct device *dev) +static int +acpi_read_bios(acpi_handle rom_handle, u8 *bios, u32 offset, u32 length) { - return false; -} +#if defined(CONFIG_ACPI) && defined(CONFIG_X86) + acpi_status status; + union acpi_object rom_arg_elements[2], *obj; + struct acpi_object_list rom_arg; + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; -static inline int -nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) -{ + rom_arg.count = 2; + rom_arg.pointer = &rom_arg_elements[0]; + + rom_arg_elements[0].type = ACPI_TYPE_INTEGER; + rom_arg_elements[0].integer.value = offset; + + rom_arg_elements[1].type = ACPI_TYPE_INTEGER; + rom_arg_elements[1].integer.value = length; + + status = acpi_evaluate_object(rom_handle, NULL, &rom_arg, &buffer); + if (ACPI_FAILURE(status)) { + pr_info("failed to evaluate ROM got %s\n", + acpi_format_exception(status)); + return -ENODEV; + } + obj = (union acpi_object *)buffer.pointer; + length = min(length, obj->buffer.length); + memcpy(bios+offset, obj->buffer.pointer, length); + kfree(buffer.pointer); + return length; +#else return -EINVAL; -} #endif +} /* This version of the shadow function disobeys the ACPI spec and tries * to fetch in units of more than 4KiB at a time. This is a LOT faster @@ -51,7 +68,7 @@ acpi_read_fast(void *data, u32 offset, u32 length, struct nvkm_bios *bios) u32 fetch = limit - start; if (nvbios_extend(bios, limit) >= 0) { - int ret = nouveau_acpi_get_bios_chunk(bios->data, start, fetch); + int ret = acpi_read_bios(data, bios->data, start, fetch); if (ret == fetch) return fetch; } @@ -73,9 +90,8 @@ acpi_read_slow(void *data, u32 offset, u32 length, struct nvkm_bios *bios) if (nvbios_extend(bios, limit) >= 0) { while (start + fetch < limit) { - int ret = nouveau_acpi_get_bios_chunk(bios->data, - start + fetch, - 0x1000); + int ret = acpi_read_bios(data, bios->data, + start + fetch, 0x1000); if (ret != 0x1000) break; fetch += 0x1000; @@ -88,9 +104,22 @@ acpi_read_slow(void *data, u32 offset, u32 length, struct nvkm_bios *bios) static void * acpi_init(struct nvkm_bios *bios, const char *name) { - if (!nouveau_acpi_rom_supported(bios->subdev.device->dev)) +#if defined(CONFIG_ACPI) && defined(CONFIG_X86) + acpi_status status; + acpi_handle dhandle, rom_handle; + + dhandle = ACPI_HANDLE(bios->subdev.device->dev); + if (!dhandle) return ERR_PTR(-ENODEV); - return NULL; + + status = acpi_get_handle(dhandle, "_ROM", &rom_handle); + if (ACPI_FAILURE(status)) + return ERR_PTR(-ENODEV); + + return rom_handle; +#else + return ERR_PTR(-ENODEV); +#endif } const struct nvbios_source diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c index 9b91da09dc5f..8d9812a51ef6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c @@ -101,9 +101,13 @@ platform_init(struct nvkm_bios *bios, const char *name) else return ERR_PTR(-ENODEV); + if (!pdev->rom || pdev->romlen == 0) + return ERR_PTR(-ENODEV); + if ((priv = kmalloc(sizeof(*priv), GFP_KERNEL))) { + priv->size = pdev->romlen; if (ret = -ENODEV, - (priv->rom = pci_platform_rom(pdev, &priv->size))) + (priv->rom = ioremap(pdev->rom, pdev->romlen))) return priv; kfree(priv); } @@ -111,11 +115,20 @@ platform_init(struct nvkm_bios *bios, const char *name) return ERR_PTR(ret); } +static void +platform_fini(void *data) +{ + struct priv *priv = data; + + iounmap(priv->rom); + kfree(priv); +} + const struct nvbios_source nvbios_platform = { .name = "PLATFORM", .init = platform_init, - .fini = (void(*)(void *))kfree, + .fini = platform_fini, .read = pcirom_read, .rw = true, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c index 3634cd0630b8..023ddc7c5399 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c @@ -64,6 +64,9 @@ pramin_init(struct nvkm_bios *bios, const char *name) return NULL; /* we can't get the bios image pointer without PDISP */ + if (device->card_type >= GA100) + addr = device->chipset == 0x170; /*XXX: find the fuse reg for this */ + else if (device->card_type >= GM100) addr = nvkm_rd32(device, 0x021c04); else diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c index 20ff5173cf8f..2da45e29f68b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c @@ -115,21 +115,21 @@ nvbios_timingEp(struct nvkm_bios *bios, int idx, switch (min_t(u8, *hdr, 25)) { case 25: p->timing_10_24 = nvbios_rd08(bios, data + 0x18); - /* fall through */ + fallthrough; case 24: case 23: case 22: p->timing_10_21 = nvbios_rd08(bios, data + 0x15); - /* fall through */ + fallthrough; case 21: p->timing_10_20 = nvbios_rd08(bios, data + 0x14); - /* fall through */ + fallthrough; case 20: p->timing_10_CWL = nvbios_rd08(bios, data + 0x13); - /* fall through */ + fallthrough; case 19: p->timing_10_18 = nvbios_rd08(bios, data + 0x12); - /* fall through */ + fallthrough; case 18: case 17: p->timing_10_16 = nvbios_rd08(bios, data + 0x10); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c index 7143ea4611aa..33a9fb5ac558 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c @@ -96,6 +96,8 @@ nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, info->min = min(info->base, info->base + info->step * info->vidmask); info->max = nvbios_rd32(bios, volt + 0x0e); + if (!info->max) + info->max = max(info->base, info->base + info->step * info->vidmask); break; case 0x50: info->min = nvbios_rd32(bios, volt + 0x0a); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.c index 52ad73bce5fe..0e5a46db52ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.c @@ -53,12 +53,12 @@ nvkm_bus = { int nvkm_bus_new_(const struct nvkm_bus_func *func, struct nvkm_device *device, - int index, struct nvkm_bus **pbus) + enum nvkm_subdev_type type, int inst, struct nvkm_bus **pbus) { struct nvkm_bus *bus; if (!(bus = *pbus = kzalloc(sizeof(*bus), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_bus, device, index, &bus->subdev); + nvkm_subdev_ctor(&nvkm_bus, device, type, inst, &bus->subdev); bus->func = func; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c index 9700b5c01cc6..a0d6e2d3f804 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c @@ -58,7 +58,8 @@ g94_bus = { }; int -g94_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus) +g94_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bus **pbus) { - return nvkm_bus_new_(&g94_bus, device, index, pbus); + return nvkm_bus_new_(&g94_bus, device, type, inst, pbus); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c index e0930d5fdfb1..80b5aaceeaad 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c @@ -35,13 +35,13 @@ gf100_bus_intr(struct nvkm_bus *bus) u32 addr = nvkm_rd32(device, 0x009084); u32 data = nvkm_rd32(device, 0x009088); - nvkm_error(subdev, - "MMIO %s of %08x FAULT at %06x [ %s%s%s]\n", - (addr & 0x00000002) ? "write" : "read", data, - (addr & 0x00fffffc), - (stat & 0x00000002) ? "!ENGINE " : "", - (stat & 0x00000004) ? "IBUS " : "", - (stat & 0x00000008) ? "TIMEOUT " : ""); + nvkm_error_ratelimited(subdev, + "MMIO %s of %08x FAULT at %06x [ %s%s%s]\n", + (addr & 0x00000002) ? "write" : "read", data, + (addr & 0x00fffffc), + (stat & 0x00000002) ? "!ENGINE " : "", + (stat & 0x00000004) ? "PRIVRING " : "", + (stat & 0x00000008) ? "TIMEOUT " : ""); nvkm_wr32(device, 0x009084, 0x00000000); nvkm_wr32(device, 0x001100, (stat & 0x0000000e)); @@ -69,7 +69,8 @@ gf100_bus = { }; int -gf100_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus) +gf100_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bus **pbus) { - return nvkm_bus_new_(&gf100_bus, device, index, pbus); + return nvkm_bus_new_(&gf100_bus, device, type, inst, pbus); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c index 2b44ba5cf4b0..cfed17c062ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c @@ -68,7 +68,8 @@ nv04_bus = { }; int -nv04_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus) +nv04_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bus **pbus) { - return nvkm_bus_new_(&nv04_bus, device, index, pbus); + return nvkm_bus_new_(&nv04_bus, device, type, inst, pbus); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c index 5153d89e1f0b..c75e463f3501 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c @@ -45,9 +45,9 @@ nv31_bus_intr(struct nvkm_bus *bus) u32 addr = nvkm_rd32(device, 0x009084); u32 data = nvkm_rd32(device, 0x009088); - nvkm_error(subdev, "MMIO %s of %08x FAULT at %06x\n", - (addr & 0x00000002) ? "write" : "read", data, - (addr & 0x00fffffc)); + nvkm_error_ratelimited(subdev, "MMIO %s of %08x FAULT at %06x\n", + (addr & 0x00000002) ? "write" : "read", data, + (addr & 0x00fffffc)); stat &= ~0x00000008; nvkm_wr32(device, 0x001100, 0x00000008); @@ -82,7 +82,8 @@ nv31_bus = { }; int -nv31_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus) +nv31_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bus **pbus) { - return nvkm_bus_new_(&nv31_bus, device, index, pbus); + return nvkm_bus_new_(&nv31_bus, device, type, inst, pbus); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c index 19e10fdc9291..2055d0b100d3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c @@ -60,9 +60,9 @@ nv50_bus_intr(struct nvkm_bus *bus) u32 addr = nvkm_rd32(device, 0x009084); u32 data = nvkm_rd32(device, 0x009088); - nvkm_error(subdev, "MMIO %s of %08x FAULT at %06x\n", - (addr & 0x00000002) ? "write" : "read", data, - (addr & 0x00fffffc)); + nvkm_error_ratelimited(subdev, "MMIO %s of %08x FAULT at %06x\n", + (addr & 0x00000002) ? "write" : "read", data, + (addr & 0x00fffffc)); stat &= ~0x00000008; nvkm_wr32(device, 0x001100, 0x00000008); @@ -99,7 +99,8 @@ nv50_bus = { }; int -nv50_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus) +nv50_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bus **pbus) { - return nvkm_bus_new_(&nv50_bus, device, index, pbus); + return nvkm_bus_new_(&nv50_bus, device, type, inst, pbus); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h index 76f7ba1c6494..2e9345b17cf8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h @@ -11,7 +11,7 @@ struct nvkm_bus_func { u32 hwsq_size; }; -int nvkm_bus_new_(const struct nvkm_bus_func *, struct nvkm_device *, int, +int nvkm_bus_new_(const struct nvkm_bus_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_bus **); void nv50_bus_init(struct nvkm_bus *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c index 40e564524b7a..c2b5cc5f97ed 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c @@ -90,7 +90,7 @@ nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate, case NVKM_CLK_BOOST_NONE: if (clk->base_khz && freq > clk->base_khz) return false; - /* fall through */ + fallthrough; case NVKM_CLK_BOOST_BIOS: if (clk->boost_khz && freq > clk->boost_khz) return false; @@ -135,10 +135,10 @@ nvkm_cstate_find_best(struct nvkm_clk *clk, struct nvkm_pstate *pstate, list_for_each_entry_from_reverse(cstate, &pstate->list, head) { if (nvkm_cstate_valid(clk, cstate, max_volt, clk->temp)) - break; + return cstate; } - return cstate; + return NULL; } static struct nvkm_cstate * @@ -169,6 +169,8 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) if (!list_empty(&pstate->list)) { cstate = nvkm_cstate_get(clk, pstate, cstatei); cstate = nvkm_cstate_find_best(clk, pstate, cstate); + if (!cstate) + return -EINVAL; } else { cstate = &pstate->base; } @@ -649,7 +651,7 @@ nvkm_clk = { int nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device, - int index, bool allow_reclock, struct nvkm_clk *clk) + enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk *clk) { struct nvkm_subdev *subdev = &clk->subdev; struct nvkm_bios *bios = device->bios; @@ -657,7 +659,7 @@ nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device, const char *mode; struct nvbios_vpstate_header h; - nvkm_subdev_ctor(&nvkm_clk, device, index, subdev); + nvkm_subdev_ctor(&nvkm_clk, device, type, inst, subdev); if (bios && !nvbios_vpstate_parse(bios, &h)) { struct nvbios_vpstate_entry base, boost; @@ -716,9 +718,9 @@ nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device, int nvkm_clk_new_(const struct nvkm_clk_func *func, struct nvkm_device *device, - int index, bool allow_reclock, struct nvkm_clk **pclk) + enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk **pclk) { if (!(*pclk = kzalloc(sizeof(**pclk), GFP_KERNEL))) return -ENOMEM; - return nvkm_clk_ctor(func, device, index, allow_reclock, *pclk); + return nvkm_clk_ctor(func, device, type, inst, allow_reclock, *pclk); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c index f97e3ec196bb..07157cf53c9e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c @@ -41,8 +41,8 @@ g84_clk = { }; int -g84_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +g84_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { - return nv50_clk_new_(&g84_clk, device, index, - (device->chipset >= 0x94), pclk); + return nv50_clk_new_(&g84_clk, device, type, inst, (device->chipset >= 0x94), pclk); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c index 7f67f9f5a550..6eea11aefb70 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -468,7 +468,8 @@ gf100_clk = { }; int -gf100_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +gf100_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct gf100_clk *clk; @@ -476,5 +477,5 @@ gf100_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) return -ENOMEM; *pclk = &clk->base; - return nvkm_clk_ctor(&gf100_clk, device, index, false, &clk->base); + return nvkm_clk_ctor(&gf100_clk, device, type, inst, false, &clk->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c index 0b37e3da7feb..0d8e2ddcc5ee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c @@ -504,7 +504,8 @@ gk104_clk = { }; int -gk104_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +gk104_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct gk104_clk *clk; @@ -512,5 +513,5 @@ gk104_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) return -ENOMEM; *pclk = &clk->base; - return nvkm_clk_ctor(&gk104_clk, device, index, true, &clk->base); + return nvkm_clk_ctor(&gk104_clk, device, type, inst, true, &clk->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c index 218893e3e5f9..d573fb0917fc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c @@ -610,10 +610,9 @@ gk20a_clk = { }; int -gk20a_clk_ctor(struct nvkm_device *device, int index, - const struct nvkm_clk_func *func, - const struct gk20a_clk_pllg_params *params, - struct gk20a_clk *clk) +gk20a_clk_ctor(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + const struct nvkm_clk_func *func, const struct gk20a_clk_pllg_params *params, + struct gk20a_clk *clk) { struct nvkm_device_tegra *tdev = device->func->tegra(device); int ret; @@ -628,7 +627,7 @@ gk20a_clk_ctor(struct nvkm_device *device, int index, clk->params = params; clk->parent_rate = clk_get_rate(tdev->clk); - ret = nvkm_clk_ctor(func, device, index, true, &clk->base); + ret = nvkm_clk_ctor(func, device, type, inst, true, &clk->base); if (ret) return ret; @@ -639,7 +638,8 @@ gk20a_clk_ctor(struct nvkm_device *device, int index, } int -gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +gk20a_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct gk20a_clk *clk; int ret; @@ -649,11 +649,9 @@ gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) return -ENOMEM; *pclk = &clk->base; - ret = gk20a_clk_ctor(device, index, &gk20a_clk, &gk20a_pllg_params, - clk); + ret = gk20a_clk_ctor(device, type, inst, &gk20a_clk, &gk20a_pllg_params, clk); clk->pl_to_div = pl_to_div; clk->div_to_pl = div_to_pl; - return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h index 0d1450972162..286413ff4a9e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h @@ -146,8 +146,8 @@ gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll) clk->parent_rate / KHZ); } -int gk20a_clk_ctor(struct nvkm_device *, int, const struct nvkm_clk_func *, - const struct gk20a_clk_pllg_params *, struct gk20a_clk *); +int gk20a_clk_ctor(struct nvkm_device *, enum nvkm_subdev_type, int, const struct nvkm_clk_func *, + const struct gk20a_clk_pllg_params *, struct gk20a_clk *); void gk20a_clk_fini(struct nvkm_clk *); int gk20a_clk_read(struct nvkm_clk *, enum nv_clk_src); int gk20a_clk_calc(struct nvkm_clk *, struct nvkm_cstate *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c index b284e949f732..a139dafffe06 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c @@ -908,7 +908,7 @@ gm20b_clk = { }; static int -gm20b_clk_new_speedo0(struct nvkm_device *device, int index, +gm20b_clk_new_speedo0(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_clk **pclk) { struct gk20a_clk *clk; @@ -919,12 +919,9 @@ gm20b_clk_new_speedo0(struct nvkm_device *device, int index, return -ENOMEM; *pclk = &clk->base; - ret = gk20a_clk_ctor(device, index, &gm20b_clk_speedo0, - &gm20b_pllg_params, clk); - + ret = gk20a_clk_ctor(device, type, inst, &gm20b_clk_speedo0, &gm20b_pllg_params, clk); clk->pl_to_div = pl_to_div; clk->div_to_pl = div_to_pl; - return ret; } @@ -1014,7 +1011,8 @@ gm20b_clk_init_safe_fmax(struct gm20b_clk *clk) } int -gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +gm20b_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct nvkm_device_tegra *tdev = device->func->tegra(device); struct gm20b_clk *clk; @@ -1024,7 +1022,7 @@ gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) /* Speedo 0 GPUs cannot use noise-aware PLL */ if (tdev->gpu_speedo_id == 0) - return gm20b_clk_new_speedo0(device, index, pclk); + return gm20b_clk_new_speedo0(device, type, inst, pclk); /* Speedo >= 1, use NAPLL */ clk = kzalloc(sizeof(*clk) + sizeof(*clk_params), GFP_KERNEL); @@ -1036,8 +1034,7 @@ gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) /* duplicate the clock parameters since we will patch them below */ clk_params = (void *) (clk + 1); *clk_params = gm20b_pllg_params; - ret = gk20a_clk_ctor(device, index, &gm20b_clk, clk_params, - &clk->base); + ret = gk20a_clk_ctor(device, type, inst, &gm20b_clk, clk_params, &clk->base); if (ret) return ret; @@ -1050,7 +1047,7 @@ gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) if (clk_params->max_m == 0) { nvkm_warn(subdev, "cannot use NAPLL, using legacy clock...\n"); kfree(clk); - return gm20b_clk_new_speedo0(device, index, pclk); + return gm20b_clk_new_speedo0(device, type, inst, pclk); } clk->base.pl_to_div = pl_to_div; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c index f0a26881d9b9..b5f3969727a2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c @@ -537,7 +537,8 @@ gt215_clk = { }; int -gt215_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +gt215_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct gt215_clk *clk; @@ -545,5 +546,5 @@ gt215_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) return -ENOMEM; *pclk = &clk->base; - return nvkm_clk_ctor(>215_clk, device, index, true, &clk->base); + return nvkm_clk_ctor(>215_clk, device, type, inst, true, &clk->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c index 4f000237796f..81f103f88dc8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c @@ -140,17 +140,14 @@ mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src) break; case nv_clk_src_mem: return 0; - break; case nv_clk_src_vdec: P = (read_div(clk) & 0x00000700) >> 8; switch (mast & 0x00400000) { case 0x00400000: return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; - break; default: return 500000 >> P; - break; } break; default: @@ -363,7 +360,7 @@ mcp77_clk_prog(struct nvkm_clk *base) switch (clk->vsrc) { case nv_clk_src_cclk: mast |= 0x00400000; - /* fall through */ + fallthrough; default: nvkm_wr32(device, 0x4600, clk->vdiv); } @@ -412,7 +409,8 @@ mcp77_clk = { }; int -mcp77_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +mcp77_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct mcp77_clk *clk; @@ -420,5 +418,5 @@ mcp77_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) return -ENOMEM; *pclk = &clk->base; - return nvkm_clk_ctor(&mcp77_clk, device, index, true, &clk->base); + return nvkm_clk_ctor(&mcp77_clk, device, type, inst, true, &clk->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c index b280f85e8827..ca13598c2caa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c @@ -72,9 +72,10 @@ nv04_clk = { }; int -nv04_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +nv04_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { - int ret = nvkm_clk_new_(&nv04_clk, device, index, false, pclk); + int ret = nvkm_clk_new_(&nv04_clk, device, type, inst, false, pclk); if (ret == 0) { (*pclk)->pll_calc = nv04_clk_pll_calc; (*pclk)->pll_prog = nv04_clk_pll_prog; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c index 2ab9b9b84018..7ddd8cecb805 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c @@ -218,7 +218,8 @@ nv40_clk = { }; int -nv40_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +nv40_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct nv40_clk *clk; @@ -228,5 +229,5 @@ nv40_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) clk->base.pll_prog = nv04_clk_pll_prog; *pclk = &clk->base; - return nvkm_clk_ctor(&nv40_clk, device, index, true, &clk->base); + return nvkm_clk_ctor(&nv40_clk, device, type, inst, true, &clk->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c index da1770e47490..e1d31c62f9ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c @@ -313,6 +313,7 @@ nv50_clk_read(struct nvkm_clk *base, enum nv_clk_src src) default: break; } + break; default: break; } @@ -507,14 +508,14 @@ nv50_clk_tidy(struct nvkm_clk *base) int nv50_clk_new_(const struct nvkm_clk_func *func, struct nvkm_device *device, - int index, bool allow_reclock, struct nvkm_clk **pclk) + enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk **pclk) { struct nv50_clk *clk; int ret; if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) return -ENOMEM; - ret = nvkm_clk_ctor(func, device, index, allow_reclock, &clk->base); + ret = nvkm_clk_ctor(func, device, type, inst, allow_reclock, &clk->base); *pclk = &clk->base; if (ret) return ret; @@ -555,7 +556,8 @@ nv50_clk = { }; int -nv50_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +nv50_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { - return nv50_clk_new_(&nv50_clk, device, index, false, pclk); + return nv50_clk_new_(&nv50_clk, device, type, inst, false, pclk); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h index 7c7713238ec4..5b4cb7e5cff6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h @@ -20,7 +20,7 @@ struct nv50_clk { struct nv50_clk_hwsq hwsq; }; -int nv50_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, int, +int nv50_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, enum nvkm_subdev_type, int, bool, struct nvkm_clk **); int nv50_clk_read(struct nvkm_clk *, enum nv_clk_src); int nv50_clk_calc(struct nvkm_clk *, struct nvkm_cstate *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h index 81dfb37480ae..810cc572cd30 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h @@ -16,9 +16,9 @@ struct nvkm_clk_func { struct nvkm_domain domains[]; }; -int nvkm_clk_ctor(const struct nvkm_clk_func *, struct nvkm_device *, int, +int nvkm_clk_ctor(const struct nvkm_clk_func *, struct nvkm_device *, enum nvkm_subdev_type, int, bool allow_reclock, struct nvkm_clk *); -int nvkm_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, int, +int nvkm_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, enum nvkm_subdev_type, int, bool allow_reclock, struct nvkm_clk **); int nv04_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, int clk, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild index b3429371ed82..d1abb64841da 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild @@ -15,3 +15,4 @@ nvkm-y += nvkm/subdev/devinit/gm107.o nvkm-y += nvkm/subdev/devinit/gm200.o nvkm-y += nvkm/subdev/devinit/gv100.o nvkm-y += nvkm/subdev/devinit/tu102.o +nvkm-y += nvkm/subdev/devinit/ga100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c index 4756019ddf3f..dd4981708fe4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c @@ -56,12 +56,12 @@ nvkm_devinit_disable(struct nvkm_devinit *init) } int -nvkm_devinit_post(struct nvkm_devinit *init, u64 *disable) +nvkm_devinit_post(struct nvkm_devinit *init) { int ret = 0; if (init && init->func->post) ret = init->func->post(init, init->post); - *disable = nvkm_devinit_disable(init); + nvkm_devinit_disable(init); return ret; } @@ -126,11 +126,10 @@ nvkm_devinit = { }; void -nvkm_devinit_ctor(const struct nvkm_devinit_func *func, - struct nvkm_device *device, int index, - struct nvkm_devinit *init) +nvkm_devinit_ctor(const struct nvkm_devinit_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_devinit *init) { - nvkm_subdev_ctor(&nvkm_devinit, device, index, &init->subdev); + nvkm_subdev_ctor(&nvkm_devinit, device, type, inst, &init->subdev); init->func = func; init->force_post = nvkm_boolopt(device->cfgopt, "NvForcePost", false); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c index e895289bf3c1..c224702b7bed 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c @@ -35,18 +35,18 @@ g84_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVKM_ENGINE_MPEG); - disable |= (1ULL << NVKM_ENGINE_VP); - disable |= (1ULL << NVKM_ENGINE_BSP); - disable |= (1ULL << NVKM_ENGINE_CIPHER); + nvkm_subdev_disable(device, NVKM_ENGINE_MPEG, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_VP, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_BSP, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_CIPHER, 0); } if (!(r00154c & 0x00000004)) - disable |= (1ULL << NVKM_ENGINE_DISP); + nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVKM_ENGINE_BSP); + nvkm_subdev_disable(device, NVKM_ENGINE_BSP, 0); if (!(r00154c & 0x00000040)) - disable |= (1ULL << NVKM_ENGINE_CIPHER); + nvkm_subdev_disable(device, NVKM_ENGINE_CIPHER, 0); return disable; } @@ -61,8 +61,8 @@ g84_devinit = { }; int -g84_devinit_new(struct nvkm_device *device, int index, +g84_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&g84_devinit, device, index, pinit); + return nv50_devinit_new_(&g84_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c index a9d45844df5a..8977483a9f42 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c @@ -32,22 +32,21 @@ g98_devinit_disable(struct nvkm_devinit *init) struct nvkm_device *device = init->subdev.device; u32 r001540 = nvkm_rd32(device, 0x001540); u32 r00154c = nvkm_rd32(device, 0x00154c); - u64 disable = 0ULL; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVKM_ENGINE_MSPDEC); - disable |= (1ULL << NVKM_ENGINE_MSVLD); - disable |= (1ULL << NVKM_ENGINE_MSPPP); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0); } if (!(r00154c & 0x00000004)) - disable |= (1ULL << NVKM_ENGINE_DISP); + nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVKM_ENGINE_MSVLD); + nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0); if (!(r00154c & 0x00000040)) - disable |= (1ULL << NVKM_ENGINE_SEC); + nvkm_subdev_disable(device, NVKM_ENGINE_SEC, 0); - return disable; + return 0ULL; } static const struct nvkm_devinit_func @@ -60,8 +59,8 @@ g98_devinit = { }; int -g98_devinit_new(struct nvkm_device *device, int index, +g98_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&g98_devinit, device, index, pinit); + return nv50_devinit_new_(&g98_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c new file mode 100644 index 000000000000..6b280b05c4ca --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c @@ -0,0 +1,77 @@ +/* + * Copyright 2021 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "nv50.h" + +#include <subdev/bios.h> +#include <subdev/bios/pll.h> +#include <subdev/clk/pll.h> + +static int +ga100_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq) +{ + struct nvkm_subdev *subdev = &init->subdev; + struct nvkm_device *device = subdev->device; + struct nvbios_pll info; + int head = type - PLL_VPLL0; + int N, fN, M, P; + int ret; + + ret = nvbios_pll_parse(device->bios, type, &info); + if (ret) + return ret; + + ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P); + if (ret < 0) + return ret; + + switch (info.type) { + case PLL_VPLL0: + case PLL_VPLL1: + case PLL_VPLL2: + case PLL_VPLL3: + nvkm_wr32(device, 0x00ef00 + (head * 0x40), 0x02080004); + nvkm_wr32(device, 0x00ef18 + (head * 0x40), (N << 16) | fN); + nvkm_wr32(device, 0x00ef04 + (head * 0x40), (P << 16) | M); + nvkm_wr32(device, 0x00e9c0 + (head * 0x04), 0x00000001); + break; + default: + nvkm_warn(subdev, "%08x/%dKhz unimplemented\n", type, freq); + ret = -EINVAL; + break; + } + + return ret; +} + +static const struct nvkm_devinit_func +ga100_devinit = { + .init = nv50_devinit_init, + .post = tu102_devinit_post, + .pll_set = ga100_devinit_pll_set, +}; + +int +ga100_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) +{ + return nv50_devinit_new_(&ga100_devinit, device, type, inst, pinit); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c index 8b1b34c3ad26..5b7cb1fe7897 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c @@ -68,26 +68,25 @@ gf100_devinit_disable(struct nvkm_devinit *init) { struct nvkm_device *device = init->subdev.device; u32 r022500 = nvkm_rd32(device, 0x022500); - u64 disable = 0ULL; if (r022500 & 0x00000001) - disable |= (1ULL << NVKM_ENGINE_DISP); + nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0); if (r022500 & 0x00000002) { - disable |= (1ULL << NVKM_ENGINE_MSPDEC); - disable |= (1ULL << NVKM_ENGINE_MSPPP); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0); } if (r022500 & 0x00000004) - disable |= (1ULL << NVKM_ENGINE_MSVLD); + nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0); if (r022500 & 0x00000008) - disable |= (1ULL << NVKM_ENGINE_MSENC); + nvkm_subdev_disable(device, NVKM_ENGINE_MSENC, 0); if (r022500 & 0x00000100) - disable |= (1ULL << NVKM_ENGINE_CE0); + nvkm_subdev_disable(device, NVKM_ENGINE_CE, 0); if (r022500 & 0x00000200) - disable |= (1ULL << NVKM_ENGINE_CE1); + nvkm_subdev_disable(device, NVKM_ENGINE_CE, 1); - return disable; + return 0ULL; } void @@ -114,8 +113,8 @@ gf100_devinit = { }; int -gf100_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +gf100_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&gf100_devinit, device, index, pinit); + return nv50_devinit_new_(&gf100_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c index 28ca01be3d38..8955af2704c7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c @@ -32,16 +32,15 @@ gm107_devinit_disable(struct nvkm_devinit *init) struct nvkm_device *device = init->subdev.device; u32 r021c00 = nvkm_rd32(device, 0x021c00); u32 r021c04 = nvkm_rd32(device, 0x021c04); - u64 disable = 0ULL; if (r021c00 & 0x00000001) - disable |= (1ULL << NVKM_ENGINE_CE0); + nvkm_subdev_disable(device, NVKM_ENGINE_CE, 0); if (r021c00 & 0x00000004) - disable |= (1ULL << NVKM_ENGINE_CE2); + nvkm_subdev_disable(device, NVKM_ENGINE_CE, 2); if (r021c04 & 0x00000001) - disable |= (1ULL << NVKM_ENGINE_DISP); + nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0); - return disable; + return 0ULL; } static const struct nvkm_devinit_func @@ -54,8 +53,8 @@ gm107_devinit = { }; int -gm107_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +gm107_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&gm107_devinit, device, index, pinit); + return nv50_devinit_new_(&gm107_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c index 59940dacc2ba..a308b9bde449 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c @@ -179,8 +179,8 @@ gm200_devinit = { }; int -gm200_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +gm200_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&gm200_devinit, device, index, pinit); + return nv50_devinit_new_(&gm200_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c index 9a8522fa9c65..3d0ab86c3115 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c @@ -68,21 +68,20 @@ gt215_devinit_disable(struct nvkm_devinit *init) struct nvkm_device *device = init->subdev.device; u32 r001540 = nvkm_rd32(device, 0x001540); u32 r00154c = nvkm_rd32(device, 0x00154c); - u64 disable = 0ULL; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVKM_ENGINE_MSPDEC); - disable |= (1ULL << NVKM_ENGINE_MSPPP); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0); } if (!(r00154c & 0x00000004)) - disable |= (1ULL << NVKM_ENGINE_DISP); + nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVKM_ENGINE_MSVLD); + nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0); if (!(r00154c & 0x00000200)) - disable |= (1ULL << NVKM_ENGINE_CE0); + nvkm_subdev_disable(device, NVKM_ENGINE_CE, 0); - return disable; + return 0ULL; } static u32 @@ -146,8 +145,8 @@ gt215_devinit = { }; int -gt215_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +gt215_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(>215_devinit, device, index, pinit); + return nv50_devinit_new_(>215_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.c index fbde6828bd38..b4d1688517d5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.c @@ -72,8 +72,8 @@ gv100_devinit = { }; int -gv100_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +gv100_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&gv100_devinit, device, index, pinit); + return nv50_devinit_new_(&gv100_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c index ce4f718e98a1..a9cdf2411187 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c @@ -32,23 +32,22 @@ mcp89_devinit_disable(struct nvkm_devinit *init) struct nvkm_device *device = init->subdev.device; u32 r001540 = nvkm_rd32(device, 0x001540); u32 r00154c = nvkm_rd32(device, 0x00154c); - u64 disable = 0; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVKM_ENGINE_MSPDEC); - disable |= (1ULL << NVKM_ENGINE_MSPPP); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0); } if (!(r00154c & 0x00000004)) - disable |= (1ULL << NVKM_ENGINE_DISP); + nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVKM_ENGINE_MSVLD); + nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0); if (!(r00154c & 0x00000040)) - disable |= (1ULL << NVKM_ENGINE_VIC); + nvkm_subdev_disable(device, NVKM_ENGINE_VIC, 0); if (!(r00154c & 0x00000200)) - disable |= (1ULL << NVKM_ENGINE_CE0); + nvkm_subdev_disable(device, NVKM_ENGINE_CE, 0); - return disable; + return 0; } static const struct nvkm_devinit_func @@ -61,8 +60,8 @@ mcp89_devinit = { }; int -mcp89_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +mcp89_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&mcp89_devinit, device, index, pinit); + return nv50_devinit_new_(&mcp89_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c index c3dae05348eb..88bc890f89a2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c @@ -119,11 +119,11 @@ powerctrl_1_shift(int chip_version, int reg) switch (reg) { case 0x680520: - shift += 4; /* fall through */ + shift += 4; fallthrough; case 0x680508: - shift += 4; /* fall through */ + shift += 4; fallthrough; case 0x680504: - shift += 4; /* fall through */ + shift += 4; fallthrough; case 0x680500: shift += 4; } @@ -245,11 +245,11 @@ setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1, switch (reg1) { case 0x680504: - shift_c040 += 2; /* fall through */ + shift_c040 += 2; fallthrough; case 0x680500: - shift_c040 += 2; /* fall through */ + shift_c040 += 2; fallthrough; case 0x680520: - shift_c040 += 2; /* fall through */ + shift_c040 += 2; fallthrough; case 0x680508: shift_c040 += 2; } @@ -434,9 +434,8 @@ nv04_devinit_dtor(struct nvkm_devinit *base) } int -nv04_devinit_new_(const struct nvkm_devinit_func *func, - struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +nv04_devinit_new_(const struct nvkm_devinit_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { struct nv04_devinit *init; @@ -444,7 +443,7 @@ nv04_devinit_new_(const struct nvkm_devinit_func *func, return -ENOMEM; *pinit = &init->base; - nvkm_devinit_ctor(func, device, index, &init->base); + nvkm_devinit_ctor(func, device, type, inst, &init->base); init->owner = -1; return 0; } @@ -459,8 +458,8 @@ nv04_devinit = { }; int -nv04_devinit_new(struct nvkm_device *device, int index, +nv04_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv04_devinit_new_(&nv04_devinit, device, index, pinit); + return nv04_devinit_new_(&nv04_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h index 15b029ddf6df..06ad8a606bb8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h @@ -11,7 +11,7 @@ struct nv04_devinit { }; int nv04_devinit_new_(const struct nvkm_devinit_func *, struct nvkm_device *, - int, struct nvkm_devinit **); + enum nvkm_subdev_type, int, struct nvkm_devinit **); void *nv04_devinit_dtor(struct nvkm_devinit *); void nv04_devinit_preinit(struct nvkm_devinit *); void nv04_devinit_fini(struct nvkm_devinit *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c index 9891eadca1ce..1410befd2285 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c @@ -136,8 +136,8 @@ nv05_devinit = { }; int -nv05_devinit_new(struct nvkm_device *device, int index, +nv05_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv04_devinit_new_(&nv05_devinit, device, index, pinit); + return nv04_devinit_new_(&nv05_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c index 570822f83acf..a6aa8786d610 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c @@ -106,8 +106,8 @@ nv10_devinit = { }; int -nv10_devinit_new(struct nvkm_device *device, int index, +nv10_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv04_devinit_new_(&nv10_devinit, device, index, pinit); + return nv04_devinit_new_(&nv10_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c index fefafec7e2a7..4cc5ef9a5a63 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c @@ -35,8 +35,8 @@ nv1a_devinit = { }; int -nv1a_devinit_new(struct nvkm_device *device, int index, +nv1a_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv04_devinit_new_(&nv1a_devinit, device, index, pinit); + return nv04_devinit_new_(&nv1a_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c index 4ef04e0d8826..67f46df723e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c @@ -72,8 +72,8 @@ nv20_devinit = { }; int -nv20_devinit_new(struct nvkm_device *device, int index, +nv20_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv04_devinit_new_(&nv20_devinit, device, index, pinit); + return nv04_devinit_new_(&nv20_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c index d7947c4391dc..380995d398b1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c @@ -85,7 +85,7 @@ nv50_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (!(r001540 & 0x40000000)) - disable |= (1ULL << NVKM_ENGINE_MPEG); + nvkm_subdev_disable(device, NVKM_ENGINE_MPEG, 0); return disable; } @@ -101,8 +101,8 @@ nv50_devinit_preinit(struct nvkm_devinit *base) * missing, assume it's a secondary gpu which requires post */ if (!base->post) { - u64 disable = nvkm_devinit_disable(base); - if (disable & (1ULL << NVKM_ENGINE_DISP)) + nvkm_devinit_disable(base); + if (!device->disp) base->post = true; } @@ -148,9 +148,8 @@ nv50_devinit_init(struct nvkm_devinit *base) } int -nv50_devinit_new_(const struct nvkm_devinit_func *func, - struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +nv50_devinit_new_(const struct nvkm_devinit_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { struct nv50_devinit *init; @@ -158,7 +157,7 @@ nv50_devinit_new_(const struct nvkm_devinit_func *func, return -ENOMEM; *pinit = &init->base; - nvkm_devinit_ctor(func, device, index, &init->base); + nvkm_devinit_ctor(func, device, type, inst, &init->base); return 0; } @@ -172,8 +171,8 @@ nv50_devinit = { }; int -nv50_devinit_new(struct nvkm_device *device, int index, +nv50_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&nv50_devinit, device, index, pinit); + return nv50_devinit_new_(&nv50_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h index e8d37a6145a2..987a7f478b84 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h @@ -9,7 +9,7 @@ struct nv50_devinit { u32 r001540; }; -int nv50_devinit_new_(const struct nvkm_devinit_func *, struct nvkm_device *, +int nv50_devinit_new_(const struct nvkm_devinit_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); void nv50_devinit_preinit(struct nvkm_devinit *); void nv50_devinit_init(struct nvkm_devinit *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h index 94723352137a..dd8b038a8cee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h @@ -16,7 +16,9 @@ struct nvkm_devinit_func { }; void nvkm_devinit_ctor(const struct nvkm_devinit_func *, struct nvkm_device *, - int index, struct nvkm_devinit *); + enum nvkm_subdev_type, int inst, struct nvkm_devinit *); +u64 nvkm_devinit_disable(struct nvkm_devinit *); int nv04_devinit_post(struct nvkm_devinit *, bool); +int tu102_devinit_post(struct nvkm_devinit *, bool); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c index 397670e72fff..634f64f88fc8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c @@ -65,7 +65,7 @@ tu102_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq) return ret; } -static int +int tu102_devinit_post(struct nvkm_devinit *base, bool post) { struct nv50_devinit *init = nv50_devinit(base); @@ -82,8 +82,8 @@ tu102_devinit = { }; int -tu102_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +tu102_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&tu102_devinit, device, index, pinit); + return nv50_devinit_new_(&tu102_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild index 53b9d638f2c8..d65ec719f153 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild @@ -2,5 +2,6 @@ nvkm-y += nvkm/subdev/fault/base.o nvkm-y += nvkm/subdev/fault/user.o nvkm-y += nvkm/subdev/fault/gp100.o +nvkm-y += nvkm/subdev/fault/gp10b.o nvkm-y += nvkm/subdev/fault/gv100.o nvkm-y += nvkm/subdev/fault/tu102.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c index ca251560d3e0..fd54fa504efa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c @@ -108,7 +108,7 @@ nvkm_fault_oneinit_buffer(struct nvkm_fault *fault, int id) return ret; /* Pin fault buffer in BAR2. */ - buffer->addr = nvkm_memory_bar2(buffer->mem); + buffer->addr = fault->func->buffer.pin(buffer); if (buffer->addr == ~0ULL) return -EFAULT; @@ -146,6 +146,7 @@ nvkm_fault_dtor(struct nvkm_subdev *subdev) struct nvkm_fault *fault = nvkm_fault(subdev); int i; + nvkm_notify_fini(&fault->nrpfb); nvkm_event_fini(&fault->event); for (i = 0; i < fault->buffer_nr; i++) { @@ -169,12 +170,12 @@ nvkm_fault = { int nvkm_fault_new_(const struct nvkm_fault_func *func, struct nvkm_device *device, - int index, struct nvkm_fault **pfault) + enum nvkm_subdev_type type, int inst, struct nvkm_fault **pfault) { struct nvkm_fault *fault; if (!(fault = *pfault = kzalloc(sizeof(*fault), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_fault, device, index, &fault->subdev); + nvkm_subdev_ctor(&nvkm_fault, device, type, inst, &fault->subdev); fault->func = func; fault->user.ctor = nvkm_ufault_new; fault->user.base = func->user.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c index 4f3c4e091117..6af7959e02ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c @@ -21,25 +21,26 @@ */ #include "priv.h" +#include <core/memory.h> #include <subdev/mc.h> #include <nvif/class.h> -static void +void gp100_fault_buffer_intr(struct nvkm_fault_buffer *buffer, bool enable) { struct nvkm_device *device = buffer->fault->subdev.device; - nvkm_mc_intr_mask(device, NVKM_SUBDEV_FAULT, enable); + nvkm_mc_intr_mask(device, NVKM_SUBDEV_FAULT, 0, enable); } -static void +void gp100_fault_buffer_fini(struct nvkm_fault_buffer *buffer) { struct nvkm_device *device = buffer->fault->subdev.device; nvkm_mask(device, 0x002a70, 0x00000001, 0x00000000); } -static void +void gp100_fault_buffer_init(struct nvkm_fault_buffer *buffer) { struct nvkm_device *device = buffer->fault->subdev.device; @@ -48,7 +49,12 @@ gp100_fault_buffer_init(struct nvkm_fault_buffer *buffer) nvkm_mask(device, 0x002a70, 0x00000001, 0x00000001); } -static void +u64 gp100_fault_buffer_pin(struct nvkm_fault_buffer *buffer) +{ + return nvkm_memory_bar2(buffer->mem); +} + +void gp100_fault_buffer_info(struct nvkm_fault_buffer *buffer) { buffer->entries = nvkm_rd32(buffer->fault->subdev.device, 0x002a78); @@ -56,7 +62,7 @@ gp100_fault_buffer_info(struct nvkm_fault_buffer *buffer) buffer->put = 0x002a80; } -static void +void gp100_fault_intr(struct nvkm_fault *fault) { nvkm_event_send(&fault->event, 1, 0, NULL, 0); @@ -68,6 +74,7 @@ gp100_fault = { .buffer.nr = 1, .buffer.entry_size = 32, .buffer.info = gp100_fault_buffer_info, + .buffer.pin = gp100_fault_buffer_pin, .buffer.init = gp100_fault_buffer_init, .buffer.fini = gp100_fault_buffer_fini, .buffer.intr = gp100_fault_buffer_intr, @@ -75,8 +82,8 @@ gp100_fault = { }; int -gp100_fault_new(struct nvkm_device *device, int index, +gp100_fault_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fault **pfault) { - return nvkm_fault_new_(&gp100_fault, device, index, pfault); + return nvkm_fault_new_(&gp100_fault, device, type, inst, pfault); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c new file mode 100644 index 000000000000..89e0bc96fb92 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2019 NVIDIA Corporation. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "priv.h" + +#include <core/memory.h> + +#include <nvif/class.h> + +u64 +gp10b_fault_buffer_pin(struct nvkm_fault_buffer *buffer) +{ + return nvkm_memory_addr(buffer->mem); +} + +static const struct nvkm_fault_func +gp10b_fault = { + .intr = gp100_fault_intr, + .buffer.nr = 1, + .buffer.entry_size = 32, + .buffer.info = gp100_fault_buffer_info, + .buffer.pin = gp10b_fault_buffer_pin, + .buffer.init = gp100_fault_buffer_init, + .buffer.fini = gp100_fault_buffer_fini, + .buffer.intr = gp100_fault_buffer_intr, + .user = { { 0, 0, MAXWELL_FAULT_BUFFER_A }, 0 }, +}; + +int +gp10b_fault_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fault **pfault) +{ + return nvkm_fault_new_(&gp10b_fault, device, type, inst, pfault); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c index 6747f09c2dc3..cd9d2ade5ac7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c @@ -214,6 +214,7 @@ gv100_fault = { .buffer.nr = 2, .buffer.entry_size = 32, .buffer.info = gv100_fault_buffer_info, + .buffer.pin = gp100_fault_buffer_pin, .buffer.init = gv100_fault_buffer_init, .buffer.fini = gv100_fault_buffer_fini, .buffer.intr = gv100_fault_buffer_intr, @@ -227,8 +228,8 @@ gv100_fault = { }; int -gv100_fault_new(struct nvkm_device *device, int index, +gv100_fault_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fault **pfault) { - return nvkm_fault_new_(&gv100_fault, device, index, pfault); + return nvkm_fault_new_(&gv100_fault, device, type, inst, pfault); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h index 975e66ac6344..36681c347fb5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h @@ -18,8 +18,8 @@ struct nvkm_fault_buffer { u64 addr; }; -int nvkm_fault_new_(const struct nvkm_fault_func *, struct nvkm_device *, - int index, struct nvkm_fault **); +int nvkm_fault_new_(const struct nvkm_fault_func *, struct nvkm_device *, enum nvkm_subdev_type, + int inst, struct nvkm_fault **); struct nvkm_fault_func { int (*oneinit)(struct nvkm_fault *); @@ -30,6 +30,7 @@ struct nvkm_fault_func { int nr; u32 entry_size; void (*info)(struct nvkm_fault_buffer *); + u64 (*pin)(struct nvkm_fault_buffer *); void (*init)(struct nvkm_fault_buffer *); void (*fini)(struct nvkm_fault_buffer *); void (*intr)(struct nvkm_fault_buffer *, bool enable); @@ -40,6 +41,15 @@ struct nvkm_fault_func { } user; }; +void gp100_fault_buffer_intr(struct nvkm_fault_buffer *, bool enable); +void gp100_fault_buffer_fini(struct nvkm_fault_buffer *); +void gp100_fault_buffer_init(struct nvkm_fault_buffer *); +u64 gp100_fault_buffer_pin(struct nvkm_fault_buffer *); +void gp100_fault_buffer_info(struct nvkm_fault_buffer *); +void gp100_fault_intr(struct nvkm_fault *); + +u64 gp10b_fault_buffer_pin(struct nvkm_fault_buffer *); + int gv100_fault_oneinit(struct nvkm_fault *); int nvkm_ufault_new(struct nvkm_device *, const struct nvkm_oclass *, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c index fa1dfe5692b0..91eb6729c84d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c @@ -22,6 +22,7 @@ #include "priv.h" #include <core/memory.h> +#include <subdev/mc.h> #include <subdev/mmu.h> #include <engine/fifo.h> @@ -34,6 +35,9 @@ tu102_fault_buffer_intr(struct nvkm_fault_buffer *buffer, bool enable) * which don't appear to actually work anymore, but newer * versions of RM don't appear to touch anything at all.. */ + struct nvkm_device *device = buffer->fault->subdev.device; + + nvkm_mc_intr_mask(device, NVKM_SUBDEV_FAULT, 0, enable); } static void @@ -41,6 +45,11 @@ tu102_fault_buffer_fini(struct nvkm_fault_buffer *buffer) { struct nvkm_device *device = buffer->fault->subdev.device; const u32 foff = buffer->id * 0x20; + + /* Disable the fault interrupts */ + nvkm_wr32(device, 0xb81408, 0x1); + nvkm_wr32(device, 0xb81410, 0x10); + nvkm_mask(device, 0xb83010 + foff, 0x80000000, 0x00000000); } @@ -50,6 +59,10 @@ tu102_fault_buffer_init(struct nvkm_fault_buffer *buffer) struct nvkm_device *device = buffer->fault->subdev.device; const u32 foff = buffer->id * 0x20; + /* Enable the fault interrupts */ + nvkm_wr32(device, 0xb81208, 0x1); + nvkm_wr32(device, 0xb81210, 0x10); + nvkm_mask(device, 0xb83010 + foff, 0xc0000000, 0x40000000); nvkm_wr32(device, 0xb83004 + foff, upper_32_bits(buffer->addr)); nvkm_wr32(device, 0xb83000 + foff, lower_32_bits(buffer->addr)); @@ -109,14 +122,20 @@ tu102_fault_intr(struct nvkm_fault *fault) } if (stat & 0x00000200) { + /* Clear the associated interrupt flag */ + nvkm_wr32(device, 0xb81010, 0x10); + if (fault->buffer[0]) { nvkm_event_send(&fault->event, 1, 0, NULL, 0); stat &= ~0x00000200; } } - /*XXX: guess, can't confirm until we get fw... */ + /* Replayable MMU fault */ if (stat & 0x00000100) { + /* Clear the associated interrupt flag */ + nvkm_wr32(device, 0xb81008, 0x1); + if (fault->buffer[1]) { nvkm_event_send(&fault->event, 1, 1, NULL, 0); stat &= ~0x00000100; @@ -154,6 +173,7 @@ tu102_fault = { .buffer.nr = 2, .buffer.entry_size = 32, .buffer.info = tu102_fault_buffer_info, + .buffer.pin = gp100_fault_buffer_pin, .buffer.init = tu102_fault_buffer_init, .buffer.fini = tu102_fault_buffer_fini, .buffer.intr = tu102_fault_buffer_intr, @@ -161,8 +181,8 @@ tu102_fault = { }; int -tu102_fault_new(struct nvkm_device *device, int index, +tu102_fault_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fault **pfault) { - return nvkm_fault_new_(&tu102_fault, device, index, pfault); + return nvkm_fault_new_(&tu102_fault, device, type, inst, pfault); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild index 43a42159a3d0..5d0bab8ecb43 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild @@ -32,6 +32,8 @@ nvkm-y += nvkm/subdev/fb/gp100.o nvkm-y += nvkm/subdev/fb/gp102.o nvkm-y += nvkm/subdev/fb/gp10b.o nvkm-y += nvkm/subdev/fb/gv100.o +nvkm-y += nvkm/subdev/fb/ga100.o +nvkm-y += nvkm/subdev/fb/ga102.o nvkm-y += nvkm/subdev/fb/ram.o nvkm-y += nvkm/subdev/fb/ramnv04.o @@ -52,6 +54,7 @@ nvkm-y += nvkm/subdev/fb/ramgk104.o nvkm-y += nvkm/subdev/fb/ramgm107.o nvkm-y += nvkm/subdev/fb/ramgm200.o nvkm-y += nvkm/subdev/fb/ramgp100.o +nvkm-y += nvkm/subdev/fb/ramga102.o nvkm-y += nvkm/subdev/fb/sddr2.o nvkm-y += nvkm/subdev/fb/sddr3.o nvkm-y += nvkm/subdev/fb/gddr3.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c index b2bb5a3ccb02..6faaea948fc4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c @@ -122,7 +122,35 @@ nvkm_fb_oneinit(struct nvkm_subdev *subdev) nvkm_debug(subdev, "%d comptags\n", tags); } - return nvkm_mm_init(&fb->tags, 0, 0, tags, 1); + return nvkm_mm_init(&fb->tags.mm, 0, 0, tags, 1); +} + +static int +nvkm_fb_init_scrub_vpr(struct nvkm_fb *fb) +{ + struct nvkm_subdev *subdev = &fb->subdev; + int ret; + + nvkm_debug(subdev, "VPR locked, running scrubber binary\n"); + + if (!fb->vpr_scrubber.size) { + nvkm_warn(subdev, "VPR locked, but no scrubber binary!\n"); + return 0; + } + + ret = fb->func->vpr.scrub(fb); + if (ret) { + nvkm_error(subdev, "VPR scrubber binary failed\n"); + return ret; + } + + if (fb->func->vpr.scrub_required(fb)) { + nvkm_error(subdev, "VPR still locked after scrub!\n"); + return -EIO; + } + + nvkm_debug(subdev, "VPR scrubber binary successful\n"); + return 0; } static int @@ -154,6 +182,14 @@ nvkm_fb_init(struct nvkm_subdev *subdev) if (fb->func->init_unkn) fb->func->init_unkn(fb); + + if (fb->func->vpr.scrub_required && + fb->func->vpr.scrub_required(fb)) { + ret = nvkm_fb_init_scrub_vpr(fb); + if (ret) + return ret; + } + return 0; } @@ -169,9 +205,13 @@ nvkm_fb_dtor(struct nvkm_subdev *subdev) for (i = 0; i < fb->tile.regions; i++) fb->func->tile.fini(fb, i, &fb->tile.region[i]); - nvkm_mm_fini(&fb->tags); + nvkm_mm_fini(&fb->tags.mm); + mutex_destroy(&fb->tags.mutex); + nvkm_ram_del(&fb->ram); + nvkm_blob_dtor(&fb->vpr_scrubber); + if (fb->func->dtor) return fb->func->dtor(fb); return fb; @@ -187,21 +227,21 @@ nvkm_fb = { void nvkm_fb_ctor(const struct nvkm_fb_func *func, struct nvkm_device *device, - int index, struct nvkm_fb *fb) + enum nvkm_subdev_type type, int inst, struct nvkm_fb *fb) { - nvkm_subdev_ctor(&nvkm_fb, device, index, &fb->subdev); + nvkm_subdev_ctor(&nvkm_fb, device, type, inst, &fb->subdev); fb->func = func; fb->tile.regions = fb->func->tile.regions; - fb->page = nvkm_longopt(device->cfgopt, "NvFbBigPage", - fb->func->default_bigpage); + fb->page = nvkm_longopt(device->cfgopt, "NvFbBigPage", fb->func->default_bigpage); + mutex_init(&fb->tags.mutex); } int nvkm_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device, - int index, struct nvkm_fb **pfb) + enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { if (!(*pfb = kzalloc(sizeof(**pfb), GFP_KERNEL))) return -ENOMEM; - nvkm_fb_ctor(func, device, index, *pfb); + nvkm_fb_ctor(func, device, type, inst, *pfb); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c index 06bf95c0c549..770a4ad39122 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c @@ -32,7 +32,7 @@ g84_fb = { }; int -g84_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +g84_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nv50_fb_new_(&g84_fb, device, index, pfb); + return nv50_fb_new_(&g84_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c new file mode 100644 index 000000000000..b47bebfbc26f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c @@ -0,0 +1,40 @@ +/* + * Copyright 2021 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "gf100.h" +#include "ram.h" + +static const struct nvkm_fb_func +ga100_fb = { + .dtor = gf100_fb_dtor, + .oneinit = gf100_fb_oneinit, + .init = gp100_fb_init, + .init_page = gv100_fb_init_page, + .init_unkn = gp100_fb_init_unkn, + .ram_new = gp100_ram_new, + .default_bigpage = 16, +}; + +int +ga100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) +{ + return gp102_fb_new_(&ga100_fb, device, type, inst, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c new file mode 100644 index 000000000000..6ea7908f0563 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c @@ -0,0 +1,40 @@ +/* + * Copyright 2021 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "gf100.h" +#include "ram.h" + +static const struct nvkm_fb_func +ga102_fb = { + .dtor = gf100_fb_dtor, + .oneinit = gf100_fb_oneinit, + .init = gp100_fb_init, + .init_page = gv100_fb_init_page, + .init_unkn = gp100_fb_init_unkn, + .ram_new = ga102_ram_new, + .default_bigpage = 16, +}; + +int +ga102_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) +{ + return gp102_fb_new_(&ga102_fb, device, type, inst, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c index e8dc4e913494..9dcc40f9ef79 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c @@ -117,13 +117,13 @@ gf100_fb_dtor(struct nvkm_fb *base) int gf100_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device, - int index, struct nvkm_fb **pfb) + enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { struct gf100_fb *fb; if (!(fb = kzalloc(sizeof(*fb), GFP_KERNEL))) return -ENOMEM; - nvkm_fb_ctor(func, device, index, &fb->base); + nvkm_fb_ctor(func, device, type, inst, &fb->base); *pfb = &fb->base; return 0; @@ -141,7 +141,7 @@ gf100_fb = { }; int -gf100_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gf100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gf100_fb, device, index, pfb); + return gf100_fb_new_(&gf100_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h index 2ed7cdaab37c..0cac7b06acc8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h @@ -10,8 +10,8 @@ struct gf100_fb { dma_addr_t r100c10; }; -int gf100_fb_new_(const struct nvkm_fb_func *, struct nvkm_device *, - int index, struct nvkm_fb **); +int gf100_fb_new_(const struct nvkm_fb_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_fb **); void *gf100_fb_dtor(struct nvkm_fb *); void gf100_fb_init(struct nvkm_fb *); void gf100_fb_intr(struct nvkm_fb *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.c index 4a9f463745b5..76678dd60f93 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.c @@ -36,7 +36,7 @@ gf108_fb = { }; int -gf108_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gf108_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gf108_fb, device, index, pfb); + return gf100_fb_new_(&gf108_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c index 48fd98e08baa..f73442ccb424 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c @@ -83,7 +83,7 @@ gk104_fb = { }; int -gk104_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gk104_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gk104_fb, device, index, pfb); + return gf100_fb_new_(&gk104_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.c index 0695e5dd360e..45d6cdffafee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.c @@ -65,7 +65,7 @@ gk110_fb = { }; int -gk110_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gk110_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gk110_fb, device, index, pfb); + return gf100_fb_new_(&gk110_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c index a7e29b125094..6bc42f89d8c4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c @@ -34,7 +34,7 @@ gk20a_fb = { }; int -gk20a_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gk20a_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gk20a_fb, device, index, pfb); + return gf100_fb_new_(&gk20a_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c index 69c876d5d1c1..de52462a92bf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c @@ -36,7 +36,7 @@ gm107_fb = { }; int -gm107_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gm107_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gm107_fb, device, index, pfb); + return gf100_fb_new_(&gm107_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c index d3b8c3367152..5acf8d15d06f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c @@ -67,7 +67,7 @@ gm200_fb = { }; int -gm200_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gm200_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gm200_fb, device, index, pfb); + return gf100_fb_new_(&gm200_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.c index 12db61e31128..86f61a3f2fea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.c @@ -34,7 +34,7 @@ gm20b_fb = { }; int -gm20b_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gm20b_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gm20b_fb, device, index, pfb); + return gf100_fb_new_(&gm20b_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c index 8205ce436b3e..09e943edc362 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c @@ -71,7 +71,7 @@ gp100_fb = { }; int -gp100_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gp100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gp100_fb, device, index, pfb); + return gf100_fb_new_(&gp100_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c index b4d74e815674..0e78b3d734a0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c @@ -24,7 +24,81 @@ #include "gf100.h" #include "ram.h" +#include <core/firmware.h> #include <core/memory.h> +#include <nvfw/fw.h> +#include <nvfw/hs.h> +#include <engine/nvdec.h> + +int +gp102_fb_vpr_scrub(struct nvkm_fb *fb) +{ + struct nvkm_subdev *subdev = &fb->subdev; + struct nvkm_device *device = subdev->device; + struct nvkm_falcon *falcon = &device->nvdec[0]->falcon; + struct nvkm_blob *blob = &fb->vpr_scrubber; + const struct nvfw_bin_hdr *hsbin_hdr; + const struct nvfw_hs_header *fw_hdr; + const struct nvfw_hs_load_header *lhdr; + void *scrub_data; + u32 patch_loc, patch_sig; + int ret; + + nvkm_falcon_get(falcon, subdev); + + hsbin_hdr = nvfw_bin_hdr(subdev, blob->data); + fw_hdr = nvfw_hs_header(subdev, blob->data + hsbin_hdr->header_offset); + lhdr = nvfw_hs_load_header(subdev, blob->data + fw_hdr->hdr_offset); + scrub_data = blob->data + hsbin_hdr->data_offset; + + patch_loc = *(u32 *)(blob->data + fw_hdr->patch_loc); + patch_sig = *(u32 *)(blob->data + fw_hdr->patch_sig); + if (falcon->debug) { + memcpy(scrub_data + patch_loc, + blob->data + fw_hdr->sig_dbg_offset + patch_sig, + fw_hdr->sig_dbg_size); + } else { + memcpy(scrub_data + patch_loc, + blob->data + fw_hdr->sig_prod_offset + patch_sig, + fw_hdr->sig_prod_size); + } + + nvkm_falcon_reset(falcon); + nvkm_falcon_bind_context(falcon, NULL); + + nvkm_falcon_load_imem(falcon, scrub_data, lhdr->non_sec_code_off, + lhdr->non_sec_code_size, + lhdr->non_sec_code_off >> 8, 0, false); + nvkm_falcon_load_imem(falcon, scrub_data + lhdr->apps[0], + ALIGN(lhdr->apps[0], 0x100), + lhdr->apps[1], + lhdr->apps[0] >> 8, 0, true); + nvkm_falcon_load_dmem(falcon, scrub_data + lhdr->data_dma_base, 0, + lhdr->data_size, 0); + + nvkm_falcon_set_start_addr(falcon, 0x0); + nvkm_falcon_start(falcon); + + ret = nvkm_falcon_wait_for_halt(falcon, 500); + if (ret < 0) { + ret = -ETIMEDOUT; + goto end; + } + + /* put nvdec in clean state - without reset it will remain in HS mode */ + nvkm_falcon_reset(falcon); +end: + nvkm_falcon_put(falcon, subdev); + return ret; +} + +bool +gp102_fb_vpr_scrub_required(struct nvkm_fb *fb) +{ + struct nvkm_device *device = fb->subdev.device; + nvkm_wr32(device, 0x100cd0, 0x2); + return (nvkm_rd32(device, 0x100cd0) & 0x00000010) != 0; +} static const struct nvkm_fb_func gp102_fb = { @@ -33,11 +107,32 @@ gp102_fb = { .init = gp100_fb_init, .init_remapper = gp100_fb_init_remapper, .init_page = gm200_fb_init_page, + .vpr.scrub_required = gp102_fb_vpr_scrub_required, + .vpr.scrub = gp102_fb_vpr_scrub, .ram_new = gp100_ram_new, }; int -gp102_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gp102_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) +{ + int ret = gf100_fb_new_(func, device, type, inst, pfb); + if (ret) + return ret; + + nvkm_firmware_load_blob(&(*pfb)->subdev, "nvdec/scrubber", "", 0, + &(*pfb)->vpr_scrubber); + return 0; +} + +int +gp102_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gp102_fb, device, index, pfb); + return gp102_fb_new_(&gp102_fb, device, type, inst, pfb); } + +MODULE_FIRMWARE("nvidia/gp102/nvdec/scrubber.bin"); +MODULE_FIRMWARE("nvidia/gp104/nvdec/scrubber.bin"); +MODULE_FIRMWARE("nvidia/gp106/nvdec/scrubber.bin"); +MODULE_FIRMWARE("nvidia/gp107/nvdec/scrubber.bin"); +MODULE_FIRMWARE("nvidia/gp108/nvdec/scrubber.bin"); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.c index af8e43979dc1..84c9815a6d48 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.c @@ -31,7 +31,7 @@ gp10b_fb = { }; int -gp10b_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gp10b_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gp10b_fb, device, index, pfb); + return gf100_fb_new_(&gp10b_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c index 9266559b45f9..c1ec9758617c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c @@ -32,7 +32,7 @@ gt215_fb = { }; int -gt215_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gt215_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nv50_fb_new_(>215_fb, device, index, pfb); + return nv50_fb_new_(>215_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c index 3c5e02e9794a..63daa83ae12d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c @@ -22,7 +22,7 @@ #include "gf100.h" #include "ram.h" -static int +int gv100_fb_init_page(struct nvkm_fb *fb) { return (fb->page == 16) ? 0 : -EINVAL; @@ -35,12 +35,21 @@ gv100_fb = { .init = gp100_fb_init, .init_page = gv100_fb_init_page, .init_unkn = gp100_fb_init_unkn, + .vpr.scrub_required = gp102_fb_vpr_scrub_required, + .vpr.scrub = gp102_fb_vpr_scrub, .ram_new = gp100_ram_new, .default_bigpage = 16, }; int -gv100_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gv100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gv100_fb, device, index, pfb); + return gp102_fb_new_(&gv100_fb, device, type, inst, pfb); } + +MODULE_FIRMWARE("nvidia/gv100/nvdec/scrubber.bin"); +MODULE_FIRMWARE("nvidia/tu102/nvdec/scrubber.bin"); +MODULE_FIRMWARE("nvidia/tu104/nvdec/scrubber.bin"); +MODULE_FIRMWARE("nvidia/tu106/nvdec/scrubber.bin"); +MODULE_FIRMWARE("nvidia/tu116/nvdec/scrubber.bin"); +MODULE_FIRMWARE("nvidia/tu117/nvdec/scrubber.bin"); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c index 73b3b86a2826..70c7b08ee0a6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c @@ -31,7 +31,7 @@ mcp77_fb = { }; int -mcp77_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +mcp77_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nv50_fb_new_(&mcp77_fb, device, index, pfb); + return nv50_fb_new_(&mcp77_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c index 6d11e32ec7ad..308d955168e8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c @@ -31,7 +31,7 @@ mcp89_fb = { }; int -mcp89_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +mcp89_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nv50_fb_new_(&mcp89_fb, device, index, pfb); + return nv50_fb_new_(&mcp89_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c index c886664533c8..8d5a007ecc47 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c @@ -44,7 +44,7 @@ nv04_fb = { }; int -nv04_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv04_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv04_fb, device, index, pfb); + return nvkm_fb_new_(&nv04_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c index c998b7e96aa3..7d2c16b27032 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c @@ -64,7 +64,7 @@ nv10_fb = { }; int -nv10_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv10_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv10_fb, device, index, pfb); + return nvkm_fb_new_(&nv10_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c index 7b9f04f44af8..4bdad2abd56f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c @@ -36,7 +36,7 @@ nv1a_fb = { }; int -nv1a_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv1a_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv1a_fb, device, index, pfb); + return nvkm_fb_new_(&nv1a_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c index a021d21ff153..d254f27f9b37 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c @@ -45,7 +45,7 @@ nv20_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ else tile->zcomp = 0x04000000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; @@ -63,7 +63,7 @@ nv20_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) tile->limit = 0; tile->pitch = 0; tile->zcomp = 0; - nvkm_mm_free(&fb->tags, &tile->tag); + nvkm_mm_free(&fb->tags.mm, &tile->tag); } void @@ -96,7 +96,7 @@ nv20_fb = { }; int -nv20_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv20_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv20_fb, device, index, pfb); + return nvkm_fb_new_(&nv20_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c index 7709f5fe9a45..47da66dea6e6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c @@ -32,7 +32,7 @@ nv25_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ else tile->zcomp = 0x00200000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; @@ -54,7 +54,7 @@ nv25_fb = { }; int -nv25_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv25_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv25_fb, device, index, pfb); + return nvkm_fb_new_(&nv25_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c index 8aa782666507..0f87efb636d5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c @@ -51,7 +51,7 @@ nv30_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */ else tile->zcomp |= 0x02000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -127,7 +127,7 @@ nv30_fb = { }; int -nv30_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv30_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv30_fb, device, index, pfb); + return nvkm_fb_new_(&nv30_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c index 6e83dcff72e0..0694dcfd107e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c @@ -32,7 +32,7 @@ nv35_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ else tile->zcomp |= 0x08000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -56,7 +56,7 @@ nv35_fb = { }; int -nv35_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv35_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv35_fb, device, index, pfb); + return nvkm_fb_new_(&nv35_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c index 2a07617bb44c..1a39770372f1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c @@ -32,7 +32,7 @@ nv36_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ else tile->zcomp |= 0x20000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -56,7 +56,7 @@ nv36_fb = { }; int -nv36_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv36_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv36_fb, device, index, pfb); + return nvkm_fb_new_(&nv36_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c index 955160778b5b..77dbb9d6ba48 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c @@ -33,7 +33,7 @@ nv40_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, u32 tiles = DIV_ROUND_UP(size, 0x80); u32 tags = round_up(tiles / fb->ram->parts, 0x100); if ( (flags & 2) && - !nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ tile->zcomp |= ((tile->tag->offset ) >> 8); tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; @@ -62,7 +62,7 @@ nv40_fb = { }; int -nv40_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv40_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv40_fb, device, index, pfb); + return nvkm_fb_new_(&nv40_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c index b77f08d34cc3..0f9d9e48e7ad 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c @@ -56,7 +56,7 @@ nv41_fb = { }; int -nv41_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv41_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv41_fb, device, index, pfb); + return nvkm_fb_new_(&nv41_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c index b59dc486083d..b1046ee9f0ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c @@ -65,7 +65,7 @@ nv44_fb = { }; int -nv44_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv44_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv44_fb, device, index, pfb); + return nvkm_fb_new_(&nv44_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c index cab7d20fa039..0d78de422dfa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c @@ -51,7 +51,7 @@ nv46_fb = { }; int -nv46_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv46_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv46_fb, device, index, pfb); + return nvkm_fb_new_(&nv46_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c index a8b0ad4c871d..5cedde29c8ee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c @@ -39,7 +39,7 @@ nv47_fb = { }; int -nv47_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv47_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv47_fb, device, index, pfb); + return nvkm_fb_new_(&nv47_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c index d0b317bb0252..95cc099603d8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c @@ -39,7 +39,7 @@ nv49_fb = { }; int -nv49_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv49_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv49_fb, device, index, pfb); + return nvkm_fb_new_(&nv49_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c index 6a6f0c086071..c9f3148f4e75 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c @@ -37,7 +37,7 @@ nv4e_fb = { }; int -nv4e_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv4e_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv4e_fb, device, index, pfb); + return nvkm_fb_new_(&nv4e_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index b2f5bf8144ea..95fd8f834010 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -262,16 +262,15 @@ nv50_fb_ = { int nv50_fb_new_(const struct nv50_fb_func *func, struct nvkm_device *device, - int index, struct nvkm_fb **pfb) + enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { struct nv50_fb *fb; if (!(fb = kzalloc(sizeof(*fb), GFP_KERNEL))) return -ENOMEM; - nvkm_fb_ctor(&nv50_fb_, device, index, &fb->base); + nvkm_fb_ctor(&nv50_fb_, device, type, inst, &fb->base); fb->func = func; *pfb = &fb->base; - return 0; } @@ -283,7 +282,7 @@ nv50_fb = { }; int -nv50_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv50_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nv50_fb_new_(&nv50_fb, device, index, pfb); + return nv50_fb_new_(&nv50_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h index 5e2b0c9539ed..a5e673859a90 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h @@ -17,6 +17,6 @@ struct nv50_fb_func { u32 trap; }; -int nv50_fb_new_(const struct nv50_fb_func *, struct nvkm_device *, int index, +int nv50_fb_new_(const struct nv50_fb_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_fb **pfb); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h index c4e9f55af283..3f1be9780c65 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h @@ -17,6 +17,11 @@ struct nvkm_fb_func { void (*intr)(struct nvkm_fb *); struct { + bool (*scrub_required)(struct nvkm_fb *); + int (*scrub)(struct nvkm_fb *); + } vpr; + + struct { int regions; void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *); @@ -33,9 +38,9 @@ struct nvkm_fb_func { }; void nvkm_fb_ctor(const struct nvkm_fb_func *, struct nvkm_device *device, - int index, struct nvkm_fb *); + enum nvkm_subdev_type type, int inst, struct nvkm_fb *); int nvkm_fb_new_(const struct nvkm_fb_func *, struct nvkm_device *device, - int index, struct nvkm_fb **); + enum nvkm_subdev_type type, int inst, struct nvkm_fb **); int nvkm_fb_bios_memtype(struct nvkm_bios *); void nv10_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, @@ -72,4 +77,11 @@ int gm200_fb_init_page(struct nvkm_fb *); void gp100_fb_init_remapper(struct nvkm_fb *); void gp100_fb_init_unkn(struct nvkm_fb *); + +int gp102_fb_new_(const struct nvkm_fb_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_fb **); +bool gp102_fb_vpr_scrub_required(struct nvkm_fb *); +int gp102_fb_vpr_scrub(struct nvkm_fb *); + +int gv100_fb_init_page(struct nvkm_fb *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.c index b11867f682cb..03b1bdb27770 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.c @@ -81,12 +81,12 @@ nvkm_vram_dtor(struct nvkm_memory *memory) struct nvkm_vram *vram = nvkm_vram(memory); struct nvkm_mm_node *next = vram->mn; struct nvkm_mm_node *node; - mutex_lock(&vram->ram->fb->subdev.mutex); + mutex_lock(&vram->ram->mutex); while ((node = next)) { next = node->next; nvkm_mm_free(&vram->ram->vram, &node); } - mutex_unlock(&vram->ram->fb->subdev.mutex); + mutex_unlock(&vram->ram->mutex); return vram; } @@ -126,7 +126,7 @@ nvkm_ram_get(struct nvkm_device *device, u8 heap, u8 type, u8 rpage, u64 size, vram->page = page; *pmemory = &vram->memory; - mutex_lock(&ram->fb->subdev.mutex); + mutex_lock(&ram->mutex); node = &vram->mn; do { if (back) @@ -134,7 +134,7 @@ nvkm_ram_get(struct nvkm_device *device, u8 heap, u8 type, u8 rpage, u64 size, else ret = nvkm_mm_head(mm, heap, type, max, min, align, &r); if (ret) { - mutex_unlock(&ram->fb->subdev.mutex); + mutex_unlock(&ram->mutex); nvkm_memory_unref(pmemory); return ret; } @@ -143,7 +143,7 @@ nvkm_ram_get(struct nvkm_device *device, u8 heap, u8 type, u8 rpage, u64 size, node = &r->next; max -= r->length; } while (max); - mutex_unlock(&ram->fb->subdev.mutex); + mutex_unlock(&ram->mutex); return 0; } @@ -163,6 +163,7 @@ nvkm_ram_del(struct nvkm_ram **pram) if (ram->func->dtor) *pram = ram->func->dtor(ram); nvkm_mm_fini(&ram->vram); + mutex_destroy(&ram->mutex); kfree(*pram); *pram = NULL; } @@ -196,6 +197,7 @@ nvkm_ram_ctor(const struct nvkm_ram_func *func, struct nvkm_fb *fb, ram->fb = fb; ram->type = type; ram->size = size; + mutex_init(&ram->mutex); if (!nvkm_mm_initialised(&ram->vram)) { ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL, 0, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h index d723a9b4e3c4..ea7d66f3dd82 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h @@ -70,4 +70,5 @@ int gk104_ram_new(struct nvkm_fb *, struct nvkm_ram **); int gm107_ram_new(struct nvkm_fb *, struct nvkm_ram **); int gm200_ram_new(struct nvkm_fb *, struct nvkm_ram **); int gp100_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int ga102_ram_new(struct nvkm_fb *, struct nvkm_ram **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramga102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramga102.c new file mode 100644 index 000000000000..298c136cefe0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramga102.c @@ -0,0 +1,40 @@ +/* + * Copyright 2021 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "ram.h" + +#include <subdev/bios.h> +#include <subdev/bios/init.h> +#include <subdev/bios/rammap.h> + +static const struct nvkm_ram_func +ga102_ram = { +}; + +int +ga102_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) +{ + struct nvkm_device *device = fb->subdev.device; + enum nvkm_ram_type type = nvkm_fb_bios_memtype(device->bios); + u32 size = nvkm_rd32(device, 0x1183a4); + + return nvkm_ram_new_(&ga102_ram, fb, type, (u64)size << 20, pram); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index ac87a3b6b7c9..ba43fe158b22 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -655,7 +655,7 @@ gf100_ram_new_(const struct nvkm_ram_func *func, static const struct nvkm_ram_func gf100_ram = { - .upper = 0x0200000000, + .upper = 0x0200000000ULL, .probe_fbp = gf100_ram_probe_fbp, .probe_fbp_amount = gf100_ram_probe_fbp_amount, .probe_fbpa_amount = gf100_ram_probe_fbpa_amount, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.c index 70a06e3cd55a..d97fa43efb91 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.c @@ -43,7 +43,7 @@ gf108_ram_probe_fbp_amount(const struct nvkm_ram_func *func, u32 fbpao, static const struct nvkm_ram_func gf108_ram = { - .upper = 0x0200000000, + .upper = 0x0200000000ULL, .probe_fbp = gf100_ram_probe_fbp, .probe_fbp_amount = gf108_ram_probe_fbp_amount, .probe_fbpa_amount = gf100_ram_probe_fbpa_amount, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c index 456aed1f2a02..2b678b60b4d3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c @@ -260,7 +260,7 @@ gk104_ram_calc_gddr5(struct gk104_ram *ram, u32 freq) ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); ram_block(fuc); - if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) + if (ram->base.fb->subdev.device->disp) ram_wr32(fuc, 0x62c000, 0x0f0f0000); /* MR1: turn termination on early, for some reason.. */ @@ -661,7 +661,7 @@ gk104_ram_calc_gddr5(struct gk104_ram *ram, u32 freq) ram_unblock(fuc); - if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) + if (ram->base.fb->subdev.device->disp) ram_wr32(fuc, 0x62c000, 0x0f0f0f00); if (next->bios.rammap_11_08_01) @@ -711,7 +711,7 @@ gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq) ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); ram_block(fuc); - if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) + if (ram->base.fb->subdev.device->disp) ram_wr32(fuc, 0x62c000, 0x0f0f0000); if (vc == 1 && ram_have(fuc, gpio2E)) { @@ -943,7 +943,7 @@ gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq) ram_unblock(fuc); - if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) + if (ram->base.fb->subdev.device->disp) ram_wr32(fuc, 0x62c000, 0x0f0f0f00); if (next->bios.rammap_11_08_01) @@ -1698,7 +1698,7 @@ gk104_ram_new_(const struct nvkm_ram_func *func, struct nvkm_fb *fb, static const struct nvkm_ram_func gk104_ram = { - .upper = 0x0200000000, + .upper = 0x0200000000ULL, .probe_fbp = gf100_ram_probe_fbp, .probe_fbp_amount = gf108_ram_probe_fbp_amount, .probe_fbpa_amount = gf100_ram_probe_fbpa_amount, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c index 27c68e3f9772..be91da854dca 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c @@ -33,7 +33,7 @@ gm107_ram_probe_fbp(const struct nvkm_ram_func *func, static const struct nvkm_ram_func gm107_ram = { - .upper = 0x1000000000, + .upper = 0x1000000000ULL, .probe_fbp = gm107_ram_probe_fbp, .probe_fbp_amount = gf108_ram_probe_fbp_amount, .probe_fbpa_amount = gf100_ram_probe_fbpa_amount, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.c index 6b0cac1fe7b4..8f91ea91ee25 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.c @@ -48,7 +48,7 @@ gm200_ram_probe_fbp_amount(const struct nvkm_ram_func *func, u32 fbpao, static const struct nvkm_ram_func gm200_ram = { - .upper = 0x1000000000, + .upper = 0x1000000000ULL, .probe_fbp = gm107_ram_probe_fbp, .probe_fbp_amount = gm200_ram_probe_fbp_amount, .probe_fbpa_amount = gf100_ram_probe_fbpa_amount, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c index adb62a6beb63..378f6fb70990 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c @@ -79,7 +79,7 @@ gp100_ram_probe_fbpa(struct nvkm_device *device, int fbpa) static const struct nvkm_ram_func gp100_ram = { - .upper = 0x1000000000, + .upper = 0x1000000000ULL, .probe_fbp = gm107_ram_probe_fbp, .probe_fbp_amount = gm200_ram_probe_fbp_amount, .probe_fbpa_amount = gp100_ram_probe_fbpa, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c index 5f4c287d7943..97b3a28ca5c0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c @@ -131,13 +131,13 @@ nv40_ram_prog(struct nvkm_ram *base) nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl); nvkm_wr32(device, 0x004048, ram->coef); nvkm_wr32(device, 0x004030, ram->coef); - /* fall through */ + fallthrough; case 0x43: case 0x49: case 0x4b: nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl); nvkm_wr32(device, 0x00403c, ram->coef); - /* fall through */ + fallthrough; default: nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl); nvkm_wr32(device, 0x004024, ram->coef); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c index 2ccb4b6be153..7b1eb44ff3da 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c @@ -171,7 +171,6 @@ nv50_ram_timing_read(struct nv50_ram *ram, u32 *timing) break; default: return -ENOSYS; - break; } T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c index 1c3c18ea8ced..375dfce09f84 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c @@ -42,12 +42,12 @@ nvkm_fuse = { int nvkm_fuse_new_(const struct nvkm_fuse_func *func, struct nvkm_device *device, - int index, struct nvkm_fuse **pfuse) + enum nvkm_subdev_type type, int inst, struct nvkm_fuse **pfuse) { struct nvkm_fuse *fuse; if (!(fuse = *pfuse = kzalloc(sizeof(*fuse), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_fuse, device, index, &fuse->subdev); + nvkm_subdev_ctor(&nvkm_fuse, device, type, inst, &fuse->subdev); fuse->func = func; spin_lock_init(&fuse->lock); return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c index 13671fedc805..01f770654b1d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c @@ -47,7 +47,8 @@ gf100_fuse = { }; int -gf100_fuse_new(struct nvkm_device *device, int index, struct nvkm_fuse **pfuse) +gf100_fuse_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fuse **pfuse) { - return nvkm_fuse_new_(&gf100_fuse, device, index, pfuse); + return nvkm_fuse_new_(&gf100_fuse, device, type, inst, pfuse); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c index 9aff4ea04506..7dc99492f536 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c @@ -36,7 +36,8 @@ gm107_fuse = { }; int -gm107_fuse_new(struct nvkm_device *device, int index, struct nvkm_fuse **pfuse) +gm107_fuse_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fuse **pfuse) { - return nvkm_fuse_new_(&gm107_fuse, device, index, pfuse); + return nvkm_fuse_new_(&gm107_fuse, device, type, inst, pfuse); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c index 514c193db25d..2505e8e1c1d3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c @@ -45,7 +45,8 @@ nv50_fuse = { }; int -nv50_fuse_new(struct nvkm_device *device, int index, struct nvkm_fuse **pfuse) +nv50_fuse_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fuse **pfuse) { - return nvkm_fuse_new_(&nv50_fuse, device, index, pfuse); + return nvkm_fuse_new_(&nv50_fuse, device, type, inst, pfuse); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h index 2edc612408dd..e83d0c30dff6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h @@ -8,6 +8,6 @@ struct nvkm_fuse_func { u32 (*read)(struct nvkm_fuse *, u32 addr); }; -int nvkm_fuse_new_(const struct nvkm_fuse_func *, struct nvkm_device *, - int index, struct nvkm_fuse **); +int nvkm_fuse_new_(const struct nvkm_fuse_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_fuse **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild index b2ad5922a1c2..efbbaa080de5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild @@ -5,3 +5,4 @@ nvkm-y += nvkm/subdev/gpio/nv50.o nvkm-y += nvkm/subdev/gpio/g94.o nvkm-y += nvkm/subdev/gpio/gf119.o nvkm-y += nvkm/subdev/gpio/gk104.o +nvkm-y += nvkm/subdev/gpio/ga102.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c index 1399d923d446..048bcc70c3f4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c @@ -23,6 +23,7 @@ */ #include "priv.h" +#include <core/option.h> #include <core/notify.h> static int @@ -182,12 +183,43 @@ static const struct dmi_system_id gpio_reset_ids[] = { { } }; +static enum dcb_gpio_func_name power_checks[] = { + DCB_GPIO_THERM_EXT_POWER_EVENT, + DCB_GPIO_POWER_ALERT, + DCB_GPIO_EXT_POWER_LOW, +}; + static int nvkm_gpio_init(struct nvkm_subdev *subdev) { struct nvkm_gpio *gpio = nvkm_gpio(subdev); + struct dcb_gpio_func func; + int ret; + int i; + if (dmi_check_system(gpio_reset_ids)) nvkm_gpio_reset(gpio, DCB_GPIO_UNUSED); + + if (nvkm_boolopt(subdev->device->cfgopt, "NvPowerChecks", true)) { + for (i = 0; i < ARRAY_SIZE(power_checks); ++i) { + ret = nvkm_gpio_find(gpio, 0, power_checks[i], + DCB_GPIO_UNUSED, &func); + if (ret) + continue; + + ret = nvkm_gpio_get(gpio, 0, func.func, func.line); + if (!ret) + continue; + + nvkm_error(&gpio->subdev, + "GPU is missing power, check its power " + "cables. Boot with " + "nouveau.config=NvPowerChecks=0 to " + "disable.\n"); + return -EINVAL; + } + } + return 0; } @@ -209,14 +241,14 @@ nvkm_gpio = { int nvkm_gpio_new_(const struct nvkm_gpio_func *func, struct nvkm_device *device, - int index, struct nvkm_gpio **pgpio) + enum nvkm_subdev_type type, int inst, struct nvkm_gpio **pgpio) { struct nvkm_gpio *gpio; if (!(gpio = *pgpio = kzalloc(sizeof(*gpio), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_gpio, device, index, &gpio->subdev); + nvkm_subdev_ctor(&nvkm_gpio, device, type, inst, &gpio->subdev); gpio->func = func; return nvkm_event_init(&nvkm_gpio_intr_func, 2, func->lines, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c index 6dcda55fb865..114728ccdf8e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c @@ -68,7 +68,8 @@ g94_gpio = { }; int -g94_gpio_new(struct nvkm_device *device, int index, struct nvkm_gpio **pgpio) +g94_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gpio **pgpio) { - return nvkm_gpio_new_(&g94_gpio, device, index, pgpio); + return nvkm_gpio_new_(&g94_gpio, device, type, inst, pgpio); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c new file mode 100644 index 000000000000..4a96f926b66d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c @@ -0,0 +1,119 @@ +/* + * Copyright 2021 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +static void +ga102_gpio_reset(struct nvkm_gpio *gpio, u8 match) +{ + struct nvkm_device *device = gpio->subdev.device; + struct nvkm_bios *bios = device->bios; + u8 ver, len; + u16 entry; + int ent = -1; + + while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) { + u32 data = nvbios_rd32(bios, entry); + u8 line = (data & 0x0000003f); + u8 defs = !!(data & 0x00000080); + u8 func = (data & 0x0000ff00) >> 8; + u8 unk0 = (data & 0x00ff0000) >> 16; + u8 unk1 = (data & 0x1f000000) >> 24; + + if ( func == DCB_GPIO_UNUSED || + (match != DCB_GPIO_UNUSED && match != func)) + continue; + + nvkm_gpio_set(gpio, 0, func, line, defs); + + nvkm_mask(device, 0x021200 + (line * 4), 0xff, unk0); + if (unk1--) + nvkm_mask(device, 0x00d740 + (unk1 * 4), 0xff, line); + } +} + +static int +ga102_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out) +{ + struct nvkm_device *device = gpio->subdev.device; + u32 data = ((dir ^ 1) << 13) | (out << 12); + nvkm_mask(device, 0x021200 + (line * 4), 0x00003000, data); + nvkm_mask(device, 0x00d604, 0x00000001, 0x00000001); /* update? */ + return 0; +} + +static int +ga102_gpio_sense(struct nvkm_gpio *gpio, int line) +{ + struct nvkm_device *device = gpio->subdev.device; + return !!(nvkm_rd32(device, 0x021200 + (line * 4)) & 0x00004000); +} + +static void +ga102_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo) +{ + struct nvkm_device *device = gpio->subdev.device; + u32 intr0 = nvkm_rd32(device, 0x021640); + u32 intr1 = nvkm_rd32(device, 0x02164c); + u32 stat0 = nvkm_rd32(device, 0x021648) & intr0; + u32 stat1 = nvkm_rd32(device, 0x021654) & intr1; + *lo = (stat1 & 0xffff0000) | (stat0 >> 16); + *hi = (stat1 << 16) | (stat0 & 0x0000ffff); + nvkm_wr32(device, 0x021640, intr0); + nvkm_wr32(device, 0x02164c, intr1); +} + +static void +ga102_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) +{ + struct nvkm_device *device = gpio->subdev.device; + u32 inte0 = nvkm_rd32(device, 0x021648); + u32 inte1 = nvkm_rd32(device, 0x021654); + if (type & NVKM_GPIO_LO) + inte0 = (inte0 & ~(mask << 16)) | (data << 16); + if (type & NVKM_GPIO_HI) + inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff); + mask >>= 16; + data >>= 16; + if (type & NVKM_GPIO_LO) + inte1 = (inte1 & ~(mask << 16)) | (data << 16); + if (type & NVKM_GPIO_HI) + inte1 = (inte1 & ~mask) | data; + nvkm_wr32(device, 0x021648, inte0); + nvkm_wr32(device, 0x021654, inte1); +} + +static const struct nvkm_gpio_func +ga102_gpio = { + .lines = 32, + .intr_stat = ga102_gpio_intr_stat, + .intr_mask = ga102_gpio_intr_mask, + .drive = ga102_gpio_drive, + .sense = ga102_gpio_sense, + .reset = ga102_gpio_reset, +}; + +int +ga102_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gpio **pgpio) +{ + return nvkm_gpio_new_(&ga102_gpio, device, type, inst, pgpio); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.c index bb7400dfaef8..ecb19e4f5c48 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.c @@ -80,7 +80,8 @@ gf119_gpio = { }; int -gf119_gpio_new(struct nvkm_device *device, int index, struct nvkm_gpio **pgpio) +gf119_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gpio **pgpio) { - return nvkm_gpio_new_(&gf119_gpio, device, index, pgpio); + return nvkm_gpio_new_(&gf119_gpio, device, type, inst, pgpio); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c index 2ead515b8530..c0e4cdb45520 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c @@ -68,7 +68,8 @@ gk104_gpio = { }; int -gk104_gpio_new(struct nvkm_device *device, int index, struct nvkm_gpio **pgpio) +gk104_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gpio **pgpio) { - return nvkm_gpio_new_(&gk104_gpio, device, index, pgpio); + return nvkm_gpio_new_(&gk104_gpio, device, type, inst, pgpio); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c index ae3499b48330..48ad29b5638f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c @@ -112,7 +112,8 @@ nv10_gpio = { }; int -nv10_gpio_new(struct nvkm_device *device, int index, struct nvkm_gpio **pgpio) +nv10_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gpio **pgpio) { - return nvkm_gpio_new_(&nv10_gpio, device, index, pgpio); + return nvkm_gpio_new_(&nv10_gpio, device, type, inst, pgpio); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c index 73923fd5f7f2..b86c49762f11 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c @@ -126,7 +126,8 @@ nv50_gpio = { }; int -nv50_gpio_new(struct nvkm_device *device, int index, struct nvkm_gpio **pgpio) +nv50_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gpio **pgpio) { - return nvkm_gpio_new_(&nv50_gpio, device, index, pgpio); + return nvkm_gpio_new_(&nv50_gpio, device, type, inst, pgpio); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h index 59e39affe2a0..6590d81164e7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h @@ -28,8 +28,8 @@ struct nvkm_gpio_func { void (*reset)(struct nvkm_gpio *, u8); }; -int nvkm_gpio_new_(const struct nvkm_gpio_func *, struct nvkm_device *, - int index, struct nvkm_gpio **); +int nvkm_gpio_new_(const struct nvkm_gpio_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_gpio **); void nv50_gpio_reset(struct nvkm_gpio *, u8); int nv50_gpio_drive(struct nvkm_gpio *, int, int, int); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/Kbuild index e7c4f068936e..67cc3b320169 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/Kbuild @@ -1,2 +1,3 @@ # SPDX-License-Identifier: MIT +nvkm-y += nvkm/subdev/gsp/base.o nvkm-y += nvkm/subdev/gsp/gv100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c new file mode 100644 index 000000000000..22574886b819 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c @@ -0,0 +1,57 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" +#include <core/falcon.h> +#include <core/firmware.h> +#include <subdev/acr.h> +#include <subdev/top.h> + +static void * +nvkm_gsp_dtor(struct nvkm_subdev *subdev) +{ + struct nvkm_gsp *gsp = nvkm_gsp(subdev); + nvkm_falcon_dtor(&gsp->falcon); + return gsp; +} + +static const struct nvkm_subdev_func +nvkm_gsp = { + .dtor = nvkm_gsp_dtor, +}; + +int +nvkm_gsp_new_(const struct nvkm_gsp_fwif *fwif, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_gsp **pgsp) +{ + struct nvkm_gsp *gsp; + + if (!(gsp = *pgsp = kzalloc(sizeof(*gsp), GFP_KERNEL))) + return -ENOMEM; + + nvkm_subdev_ctor(&nvkm_gsp, device, type, inst, &gsp->subdev); + + fwif = nvkm_firmware_load(&gsp->subdev, fwif, "Gsp", gsp); + if (IS_ERR(fwif)) + return PTR_ERR(fwif); + + return nvkm_falcon_ctor(fwif->flcn, &gsp->subdev, gsp->subdev.name, 0, &gsp->falcon); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c index dccfaf1162e2..6c4ef62a746a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c @@ -19,44 +19,38 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ -#include <subdev/gsp.h> -#include <subdev/top.h> -#include <engine/falcon.h> +#include "priv.h" + +static const struct nvkm_falcon_func +gv100_gsp_flcn = { + .fbif = 0x600, + .load_imem = nvkm_falcon_v1_load_imem, + .load_dmem = nvkm_falcon_v1_load_dmem, + .read_dmem = nvkm_falcon_v1_read_dmem, + .bind_context = gp102_sec2_flcn_bind_context, + .wait_for_halt = nvkm_falcon_v1_wait_for_halt, + .clear_interrupt = nvkm_falcon_v1_clear_interrupt, + .set_start_addr = nvkm_falcon_v1_set_start_addr, + .start = nvkm_falcon_v1_start, + .enable = gp102_sec2_flcn_enable, + .disable = nvkm_falcon_v1_disable, +}; static int -gv100_gsp_oneinit(struct nvkm_subdev *subdev) -{ - struct nvkm_gsp *gsp = nvkm_gsp(subdev); - - gsp->addr = nvkm_top_addr(subdev->device, subdev->index); - if (!gsp->addr) - return -EINVAL; - - return nvkm_falcon_v1_new(subdev, "GSP", gsp->addr, &gsp->falcon); -} - -static void * -gv100_gsp_dtor(struct nvkm_subdev *subdev) +gv100_gsp_nofw(struct nvkm_gsp *gsp, int ver, const struct nvkm_gsp_fwif *fwif) { - struct nvkm_gsp *gsp = nvkm_gsp(subdev); - nvkm_falcon_del(&gsp->falcon); - return gsp; + return 0; } -static const struct nvkm_subdev_func -gv100_gsp = { - .dtor = gv100_gsp_dtor, - .oneinit = gv100_gsp_oneinit, +static struct nvkm_gsp_fwif +gv100_gsp[] = { + { -1, gv100_gsp_nofw, &gv100_gsp_flcn }, + {} }; int -gv100_gsp_new(struct nvkm_device *device, int index, struct nvkm_gsp **pgsp) +gv100_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gsp **pgsp) { - struct nvkm_gsp *gsp; - - if (!(gsp = *pgsp = kzalloc(sizeof(*gsp), GFP_KERNEL))) - return -ENOMEM; - - nvkm_subdev_ctor(&gv100_gsp, device, index, &gsp->subdev); - return 0; + return nvkm_gsp_new_(gv100_gsp, device, type, inst, pgsp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/priv.h new file mode 100644 index 000000000000..19381ddd38d4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/priv.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVKM_GSP_PRIV_H__ +#define __NVKM_GSP_PRIV_H__ +#include <subdev/gsp.h> +enum nvkm_acr_lsf_id; + +struct nvkm_gsp_fwif { + int version; + int (*load)(struct nvkm_gsp *, int ver, const struct nvkm_gsp_fwif *); + const struct nvkm_falcon_func *flcn; +}; + +int nvkm_gsp_new_(const struct nvkm_gsp_fwif *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_gsp **); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild index 723d0284caef..819703913a00 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild @@ -7,6 +7,7 @@ nvkm-y += nvkm/subdev/i2c/g94.o nvkm-y += nvkm/subdev/i2c/gf117.o nvkm-y += nvkm/subdev/i2c/gf119.o nvkm-y += nvkm/subdev/i2c/gk104.o +nvkm-y += nvkm/subdev/i2c/gk110.o nvkm-y += nvkm/subdev/i2c/gm200.o nvkm-y += nvkm/subdev/i2c/pad.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c index b4e7404fe660..d063d0dc13c5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c @@ -21,6 +21,9 @@ * * Authors: Ben Skeggs */ + +#include <linux/string_helpers.h> + #include "aux.h" #include "pad.h" @@ -40,8 +43,7 @@ nvkm_i2c_aux_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) u8 *ptr = msg->buf; while (remaining) { - u8 cnt = (remaining > 16) ? 16 : remaining; - u8 cmd; + u8 cnt, retries, cmd; if (msg->flags & I2C_M_RD) cmd = 1; @@ -51,10 +53,19 @@ nvkm_i2c_aux_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) if (mcnt || remaining > 16) cmd |= 4; /* MOT */ - ret = aux->func->xfer(aux, true, cmd, msg->addr, ptr, &cnt); - if (ret < 0) { - nvkm_i2c_aux_release(aux); - return ret; + for (retries = 0, cnt = 0; + retries < 32 && !cnt; + retries++) { + cnt = min_t(u8, remaining, 16); + ret = aux->func->xfer(aux, true, cmd, + msg->addr, ptr, &cnt); + if (ret < 0) + goto out; + } + if (!cnt) { + AUX_TRACE(aux, "no data after 32 retries"); + ret = -EIO; + goto out; } ptr += cnt; @@ -64,8 +75,10 @@ nvkm_i2c_aux_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) msg++; } + ret = num; +out: nvkm_i2c_aux_release(aux); - return num; + return ret; } static u32 @@ -84,7 +97,7 @@ void nvkm_i2c_aux_monitor(struct nvkm_i2c_aux *aux, bool monitor) { struct nvkm_i2c_pad *pad = aux->pad; - AUX_TRACE(aux, "monitor: %s", monitor ? "yes" : "no"); + AUX_TRACE(aux, "monitor: %s", str_yes_no(monitor)); if (monitor) nvkm_i2c_pad_mode(pad, NVKM_I2C_PAD_AUX); else diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.h index 30b48896965e..f920eabf8628 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.h @@ -3,6 +3,13 @@ #define __NVKM_I2C_AUX_H__ #include "pad.h" +static inline void +nvkm_i2c_aux_autodpcd(struct nvkm_i2c *i2c, int aux, bool enable) +{ + if (i2c->func->aux_autodpcd) + i2c->func->aux_autodpcd(i2c, aux, false); +} + struct nvkm_i2c_aux_func { bool address_only; int (*xfer)(struct nvkm_i2c_aux *, bool retry, u8 type, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c index c8ab1b5741a3..47068f6f9c55 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c @@ -77,7 +77,8 @@ g94_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, u8 type, u32 addr, u8 *data, u8 *size) { struct g94_i2c_aux *aux = g94_i2c_aux(obj); - struct nvkm_device *device = aux->base.pad->i2c->subdev.device; + struct nvkm_i2c *i2c = aux->base.pad->i2c; + struct nvkm_device *device = i2c->subdev.device; const u32 base = aux->ch * 0x50; u32 ctrl, stat, timeout, retries = 0; u32 xbuf[4] = {}; @@ -96,6 +97,8 @@ g94_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, goto out; } + nvkm_i2c_aux_autodpcd(i2c, aux->ch, false); + if (!(type & 1)) { memcpy(xbuf, data, *size); for (i = 0; i < 16; i += 4) { @@ -118,17 +121,17 @@ g94_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, if (retries) udelay(400); - /* transaction request, wait up to 1ms for it to complete */ + /* transaction request, wait up to 2ms for it to complete */ nvkm_wr32(device, 0x00e4e4 + base, 0x00010000 | ctrl); - timeout = 1000; + timeout = 2000; do { ctrl = nvkm_rd32(device, 0x00e4e4 + base); udelay(1); if (!timeout--) { AUX_ERR(&aux->base, "timeout %08x", ctrl); ret = -EIO; - goto out; + goto out_err; } } while (ctrl & 0x00010000); ret = 0; @@ -154,7 +157,8 @@ g94_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, memcpy(data, xbuf, *size); *size = stat & 0x0000001f; } - +out_err: + nvkm_i2c_aux_autodpcd(i2c, aux->ch, true); out: g94_i2c_aux_fini(aux); return ret < 0 ? ret : (stat & 0x000f0000) >> 16; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c index 7ef60895f43a..8bd1d442e465 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c @@ -33,7 +33,7 @@ static void gm200_i2c_aux_fini(struct gm200_i2c_aux *aux) { struct nvkm_device *device = aux->base.pad->i2c->subdev.device; - nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00310000, 0x00000000); + nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00710000, 0x00000000); } static int @@ -54,10 +54,10 @@ gm200_i2c_aux_init(struct gm200_i2c_aux *aux) AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl); return -EBUSY; } - } while (ctrl & 0x03010000); + } while (ctrl & 0x07010000); /* set some magic, and wait up to 1ms for it to appear */ - nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00300000, ureq); + nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00700000, ureq); timeout = 1000; do { ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50)); @@ -67,7 +67,7 @@ gm200_i2c_aux_init(struct gm200_i2c_aux *aux) gm200_i2c_aux_fini(aux); return -EBUSY; } - } while ((ctrl & 0x03000000) != urep); + } while ((ctrl & 0x07000000) != urep); return 0; } @@ -77,7 +77,8 @@ gm200_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, u8 type, u32 addr, u8 *data, u8 *size) { struct gm200_i2c_aux *aux = gm200_i2c_aux(obj); - struct nvkm_device *device = aux->base.pad->i2c->subdev.device; + struct nvkm_i2c *i2c = aux->base.pad->i2c; + struct nvkm_device *device = i2c->subdev.device; const u32 base = aux->ch * 0x50; u32 ctrl, stat, timeout, retries = 0; u32 xbuf[4] = {}; @@ -96,6 +97,8 @@ gm200_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, goto out; } + nvkm_i2c_aux_autodpcd(i2c, aux->ch, false); + if (!(type & 1)) { memcpy(xbuf, data, *size); for (i = 0; i < 16; i += 4) { @@ -118,17 +121,17 @@ gm200_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, if (retries) udelay(400); - /* transaction request, wait up to 1ms for it to complete */ + /* transaction request, wait up to 2ms for it to complete */ nvkm_wr32(device, 0x00d954 + base, 0x00010000 | ctrl); - timeout = 1000; + timeout = 2000; do { ctrl = nvkm_rd32(device, 0x00d954 + base); udelay(1); if (!timeout--) { AUX_ERR(&aux->base, "timeout %08x", ctrl); ret = -EIO; - goto out; + goto out_err; } } while (ctrl & 0x00010000); ret = 0; @@ -155,6 +158,8 @@ gm200_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, *size = stat & 0x0000001f; } +out_err: + nvkm_i2c_aux_autodpcd(i2c, aux->ch, true); out: gm200_i2c_aux_fini(aux); return ret < 0 ? ret : (stat & 0x000f0000) >> 16; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c index 719345074711..cb5cb533d91c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c @@ -277,7 +277,7 @@ nvkm_i2c_drv[] = { int nvkm_i2c_new_(const struct nvkm_i2c_func *func, struct nvkm_device *device, - int index, struct nvkm_i2c **pi2c) + enum nvkm_subdev_type type, int inst, struct nvkm_i2c **pi2c) { struct nvkm_bios *bios = device->bios; struct nvkm_i2c *i2c; @@ -289,7 +289,7 @@ nvkm_i2c_new_(const struct nvkm_i2c_func *func, struct nvkm_device *device, if (!(i2c = *pi2c = kzalloc(sizeof(*i2c), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_i2c, device, index, &i2c->subdev); + nvkm_subdev_ctor(&nvkm_i2c, device, type, inst, &i2c->subdev); i2c->func = func; INIT_LIST_HEAD(&i2c->pad); INIT_LIST_HEAD(&i2c->bus); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c index bb2a31d88161..e5bad085c06f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c @@ -66,7 +66,8 @@ g94_i2c = { }; int -g94_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +g94_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&g94_i2c, device, index, pi2c); + return nvkm_i2c_new_(&g94_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c index ae4aad3fcd2e..cda30ee6767d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c @@ -30,7 +30,8 @@ gf117_i2c = { }; int -gf117_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +gf117_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&gf117_i2c, device, index, pi2c); + return nvkm_i2c_new_(&gf117_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.c index 6f2b02af42c8..e9c6a6cca09d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.c @@ -34,7 +34,8 @@ gf119_i2c = { }; int -gf119_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +gf119_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&gf119_i2c, device, index, pi2c); + return nvkm_i2c_new_(&gf119_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c index f9f6bf4b66c9..d35aa6fe3015 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c @@ -66,7 +66,8 @@ gk104_i2c = { }; int -gk104_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +gk104_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&gk104_i2c, device, index, pi2c); + return nvkm_i2c_new_(&gk104_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.c new file mode 100644 index 000000000000..9fec6af56e07 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.c @@ -0,0 +1,46 @@ +/* + * Copyright 2021 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" +#include "pad.h" + +static void +gk110_aux_autodpcd(struct nvkm_i2c *i2c, int aux, bool enable) +{ + nvkm_mask(i2c->subdev.device, 0x00e4f8 + (aux * 0x50), 0x00010000, enable << 16); +} + +static const struct nvkm_i2c_func +gk110_i2c = { + .pad_x_new = gf119_i2c_pad_x_new, + .pad_s_new = gf119_i2c_pad_s_new, + .aux = 4, + .aux_stat = gk104_aux_stat, + .aux_mask = gk104_aux_mask, + .aux_autodpcd = gk110_aux_autodpcd, +}; + +int +gk110_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) +{ + return nvkm_i2c_new_(&gk110_i2c, device, type, inst, pi2c); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.c index a23c5f315221..46917eb600f9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.c @@ -24,6 +24,12 @@ #include "priv.h" #include "pad.h" +static void +gm200_aux_autodpcd(struct nvkm_i2c *i2c, int aux, bool enable) +{ + nvkm_mask(i2c->subdev.device, 0x00d968 + (aux * 0x50), 0x00010000, enable << 16); +} + static const struct nvkm_i2c_func gm200_i2c = { .pad_x_new = gf119_i2c_pad_x_new, @@ -31,10 +37,12 @@ gm200_i2c = { .aux = 8, .aux_stat = gk104_aux_stat, .aux_mask = gk104_aux_mask, + .aux_autodpcd = gm200_aux_autodpcd, }; int -gm200_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +gm200_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&gm200_i2c, device, index, pi2c); + return nvkm_i2c_new_(&gm200_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c index 18776f49355c..ecfcf147c789 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c @@ -30,7 +30,8 @@ nv04_i2c = { }; int -nv04_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +nv04_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&nv04_i2c, device, index, pi2c); + return nvkm_i2c_new_(&nv04_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c index 6b762f7cee9e..ad1d3fd2bcbc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c @@ -30,7 +30,8 @@ nv4e_i2c = { }; int -nv4e_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +nv4e_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&nv4e_i2c, device, index, pi2c); + return nvkm_i2c_new_(&nv4e_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c index 75640ab97d6a..2f94bed2c056 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c @@ -30,7 +30,8 @@ nv50_i2c = { }; int -nv50_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +nv50_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&nv50_i2c, device, index, pi2c); + return nvkm_i2c_new_(&nv50_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h index 461016814f4f..44b7bb7d4777 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: MIT */ #ifndef __NVKM_I2C_PAD_H__ #define __NVKM_I2C_PAD_H__ -#include <subdev/i2c.h> +#include "priv.h" struct nvkm_i2c_pad { const struct nvkm_i2c_pad_func *func; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h index bd86bc298ebe..f9d79f72f7e7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h @@ -4,8 +4,8 @@ #define nvkm_i2c(p) container_of((p), struct nvkm_i2c, subdev) #include <subdev/i2c.h> -int nvkm_i2c_new_(const struct nvkm_i2c_func *, struct nvkm_device *, - int index, struct nvkm_i2c **); +int nvkm_i2c_new_(const struct nvkm_i2c_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_i2c **); struct nvkm_i2c_func { int (*pad_x_new)(struct nvkm_i2c *, int id, struct nvkm_i2c_pad **); @@ -23,6 +23,10 @@ struct nvkm_i2c_func { /* mask on/off interrupt types for a given set of auxch */ void (*aux_mask)(struct nvkm_i2c *, u32, u32, u32); + + /* enable/disable HW-initiated DPCD reads + */ + void (*aux_autodpcd)(struct nvkm_i2c *, int aux, bool enable); }; void g94_aux_stat(struct nvkm_i2c *, u32 *, u32 *, u32 *, u32 *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild deleted file mode 100644 index 127efb51f67d..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: MIT -nvkm-y += nvkm/subdev/ibus/gf100.o -nvkm-y += nvkm/subdev/ibus/gf117.o -nvkm-y += nvkm/subdev/ibus/gk104.o -nvkm-y += nvkm/subdev/ibus/gk20a.o -nvkm-y += nvkm/subdev/ibus/gm200.o -nvkm-y += nvkm/subdev/ibus/gp10b.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h deleted file mode 100644 index 302d69e384d8..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef __NVKM_IBUS_PRIV_H__ -#define __NVKM_IBUS_PRIV_H__ - -#include <subdev/ibus.h> - -void gf100_ibus_intr(struct nvkm_subdev *); -void gk104_ibus_intr(struct nvkm_subdev *); -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c index fecfa6afcf54..8f0ccd3664eb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c @@ -312,20 +312,20 @@ iccsense_func = { }; void -nvkm_iccsense_ctor(struct nvkm_device *device, int index, +nvkm_iccsense_ctor(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_iccsense *iccsense) { - nvkm_subdev_ctor(&iccsense_func, device, index, &iccsense->subdev); + nvkm_subdev_ctor(&iccsense_func, device, type, inst, &iccsense->subdev); } int -nvkm_iccsense_new_(struct nvkm_device *device, int index, +nvkm_iccsense_new_(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_iccsense **iccsense) { if (!(*iccsense = kzalloc(sizeof(**iccsense), GFP_KERNEL))) return -ENOMEM; INIT_LIST_HEAD(&(*iccsense)->sensors); INIT_LIST_HEAD(&(*iccsense)->rails); - nvkm_iccsense_ctor(device, index, *iccsense); + nvkm_iccsense_ctor(device, type, inst, *iccsense); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.c index cccff1c8a409..3eabf4944395 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.c @@ -24,8 +24,8 @@ #include "priv.h" int -gf100_iccsense_new(struct nvkm_device *device, int index, +gf100_iccsense_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_iccsense **piccsense) { - return nvkm_iccsense_new_(device, index, piccsense); + return nvkm_iccsense_new_(device, type, inst, piccsense); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h index cc09c6c504af..c33441124241 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h @@ -22,6 +22,6 @@ struct nvkm_iccsense_rail { u8 mohm; }; -void nvkm_iccsense_ctor(struct nvkm_device *, int, struct nvkm_iccsense *); -int nvkm_iccsense_new_(struct nvkm_device *, int, struct nvkm_iccsense **); +void nvkm_iccsense_ctor(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_iccsense *); +int nvkm_iccsense_new_(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_iccsense **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c index 364ea4492acc..cd8163a52bb6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c @@ -218,9 +218,11 @@ static void * nvkm_instmem_dtor(struct nvkm_subdev *subdev) { struct nvkm_instmem *imem = nvkm_instmem(subdev); + void *data = imem; if (imem->func->dtor) - return imem->func->dtor(imem); - return imem; + data = imem->func->dtor(imem); + mutex_destroy(&imem->mutex); + return data; } static const struct nvkm_subdev_func @@ -232,13 +234,13 @@ nvkm_instmem = { }; void -nvkm_instmem_ctor(const struct nvkm_instmem_func *func, - struct nvkm_device *device, int index, - struct nvkm_instmem *imem) +nvkm_instmem_ctor(const struct nvkm_instmem_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_instmem *imem) { - nvkm_subdev_ctor(&nvkm_instmem, device, index, &imem->subdev); + nvkm_subdev_ctor(&nvkm_instmem, device, type, inst, &imem->subdev); imem->func = func; spin_lock_init(&imem->lock); INIT_LIST_HEAD(&imem->list); INIT_LIST_HEAD(&imem->boot); + mutex_init(&imem->mutex); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c index 985f2990ab0d..648ecf5a8fbc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c @@ -568,7 +568,7 @@ gk20a_instmem = { }; int -gk20a_instmem_new(struct nvkm_device *device, int index, +gk20a_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_instmem **pimem) { struct nvkm_device_tegra *tdev = device->func->tegra(device); @@ -576,7 +576,7 @@ gk20a_instmem_new(struct nvkm_device *device, int index, if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) return -ENOMEM; - nvkm_instmem_ctor(&gk20a_instmem, device, index, &imem->base); + nvkm_instmem_ctor(&gk20a_instmem, device, type, inst, &imem->base); mutex_init(&imem->lock); *pimem = &imem->base; @@ -594,8 +594,7 @@ gk20a_instmem_new(struct nvkm_device *device, int index, nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { - imem->attrs = DMA_ATTR_NON_CONSISTENT | - DMA_ATTR_WEAK_ORDERING | + imem->attrs = DMA_ATTR_WEAK_ORDERING | DMA_ATTR_WRITE_COMBINE; nvkm_info(&imem->base.subdev, "using DMA API\n"); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c index 6bf0dad46919..25603b01d6f8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c @@ -99,9 +99,9 @@ static void * nv04_instobj_dtor(struct nvkm_memory *memory) { struct nv04_instobj *iobj = nv04_instobj(memory); - mutex_lock(&iobj->imem->base.subdev.mutex); + mutex_lock(&iobj->imem->base.mutex); nvkm_mm_free(&iobj->imem->heap, &iobj->node); - mutex_unlock(&iobj->imem->base.subdev.mutex); + mutex_unlock(&iobj->imem->base.mutex); nvkm_instobj_dtor(&iobj->imem->base, &iobj->base); return iobj; } @@ -132,10 +132,9 @@ nv04_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, iobj->base.memory.ptrs = &nv04_instobj_ptrs; iobj->imem = imem; - mutex_lock(&imem->base.subdev.mutex); - ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, - align ? align : 1, &iobj->node); - mutex_unlock(&imem->base.subdev.mutex); + mutex_lock(&imem->base.mutex); + ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, align ? align : 1, &iobj->node); + mutex_unlock(&imem->base.mutex); return ret; } @@ -218,14 +217,14 @@ nv04_instmem = { }; int -nv04_instmem_new(struct nvkm_device *device, int index, +nv04_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_instmem **pimem) { struct nv04_instmem *imem; if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) return -ENOMEM; - nvkm_instmem_ctor(&nv04_instmem, device, index, &imem->base); + nvkm_instmem_ctor(&nv04_instmem, device, type, inst, &imem->base); *pimem = &imem->base; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c index 086c118488ef..6b462f960922 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c @@ -99,9 +99,9 @@ static void * nv40_instobj_dtor(struct nvkm_memory *memory) { struct nv40_instobj *iobj = nv40_instobj(memory); - mutex_lock(&iobj->imem->base.subdev.mutex); + mutex_lock(&iobj->imem->base.mutex); nvkm_mm_free(&iobj->imem->heap, &iobj->node); - mutex_unlock(&iobj->imem->base.subdev.mutex); + mutex_unlock(&iobj->imem->base.mutex); nvkm_instobj_dtor(&iobj->imem->base, &iobj->base); return iobj; } @@ -132,10 +132,9 @@ nv40_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, iobj->base.memory.ptrs = &nv40_instobj_ptrs; iobj->imem = imem; - mutex_lock(&imem->base.subdev.mutex); - ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, - align ? align : 1, &iobj->node); - mutex_unlock(&imem->base.subdev.mutex); + mutex_lock(&imem->base.mutex); + ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, align ? align : 1, &iobj->node); + mutex_unlock(&imem->base.mutex); return ret; } @@ -236,7 +235,7 @@ nv40_instmem = { }; int -nv40_instmem_new(struct nvkm_device *device, int index, +nv40_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_instmem **pimem) { struct nv40_instmem *imem; @@ -244,7 +243,7 @@ nv40_instmem_new(struct nvkm_device *device, int index, if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) return -ENOMEM; - nvkm_instmem_ctor(&nv40_instmem, device, index, &imem->base); + nvkm_instmem_ctor(&nv40_instmem, device, type, inst, &imem->base); *pimem = &imem->base; /* map bar */ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c index 02c4eb28cef4..c51bac76174c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c @@ -133,12 +133,12 @@ nv50_instobj_kmap(struct nv50_instobj *iobj, struct nvkm_vmm *vmm) * into it. The lock has to be dropped while doing this due * to the possibility of recursion for page table allocation. */ - mutex_unlock(&subdev->mutex); + mutex_unlock(&imem->base.mutex); while ((ret = nvkm_vmm_get(vmm, 12, size, &bar))) { /* Evict unused mappings, and keep retrying until we either * succeed,or there's no more objects left on the LRU. */ - mutex_lock(&subdev->mutex); + mutex_lock(&imem->base.mutex); eobj = list_first_entry_or_null(&imem->lru, typeof(*eobj), lru); if (eobj) { nvkm_debug(subdev, "evict %016llx %016llx @ %016llx\n", @@ -151,7 +151,7 @@ nv50_instobj_kmap(struct nv50_instobj *iobj, struct nvkm_vmm *vmm) emap = eobj->map; eobj->map = NULL; } - mutex_unlock(&subdev->mutex); + mutex_unlock(&imem->base.mutex); if (!eobj) break; iounmap(emap); @@ -160,12 +160,12 @@ nv50_instobj_kmap(struct nv50_instobj *iobj, struct nvkm_vmm *vmm) if (ret == 0) ret = nvkm_memory_map(memory, 0, vmm, bar, NULL, 0); - mutex_lock(&subdev->mutex); + mutex_lock(&imem->base.mutex); if (ret || iobj->bar) { /* We either failed, or another thread beat us. */ - mutex_unlock(&subdev->mutex); + mutex_unlock(&imem->base.mutex); nvkm_vmm_put(vmm, &bar); - mutex_lock(&subdev->mutex); + mutex_lock(&imem->base.mutex); return; } @@ -197,7 +197,7 @@ nv50_instobj_release(struct nvkm_memory *memory) wmb(); nvkm_bar_flush(subdev->device->bar); - if (refcount_dec_and_mutex_lock(&iobj->maps, &subdev->mutex)) { + if (refcount_dec_and_mutex_lock(&iobj->maps, &imem->base.mutex)) { /* Add the now-unused mapping to the LRU instead of directly * unmapping it here, in case we need to map it again later. */ @@ -208,7 +208,7 @@ nv50_instobj_release(struct nvkm_memory *memory) /* Switch back to NULL accessors when last map is gone. */ iobj->base.memory.ptrs = NULL; - mutex_unlock(&subdev->mutex); + mutex_unlock(&imem->base.mutex); } } @@ -227,9 +227,9 @@ nv50_instobj_acquire(struct nvkm_memory *memory) /* Take the lock, and re-check that another thread hasn't * already mapped the object in the meantime. */ - mutex_lock(&imem->subdev.mutex); + mutex_lock(&imem->mutex); if (refcount_inc_not_zero(&iobj->maps)) { - mutex_unlock(&imem->subdev.mutex); + mutex_unlock(&imem->mutex); return iobj->map; } @@ -252,7 +252,7 @@ nv50_instobj_acquire(struct nvkm_memory *memory) refcount_set(&iobj->maps, 1); } - mutex_unlock(&imem->subdev.mutex); + mutex_unlock(&imem->mutex); return map; } @@ -265,7 +265,7 @@ nv50_instobj_boot(struct nvkm_memory *memory, struct nvkm_vmm *vmm) /* Exclude bootstrapped objects (ie. the page tables for the * instmem BAR itself) from eviction. */ - mutex_lock(&imem->subdev.mutex); + mutex_lock(&imem->mutex); if (likely(iobj->lru.next)) { list_del_init(&iobj->lru); iobj->lru.next = NULL; @@ -273,7 +273,7 @@ nv50_instobj_boot(struct nvkm_memory *memory, struct nvkm_vmm *vmm) nv50_instobj_kmap(iobj, vmm); nvkm_instmem_boot(imem); - mutex_unlock(&imem->subdev.mutex); + mutex_unlock(&imem->mutex); } static u64 @@ -313,14 +313,14 @@ nv50_instobj_dtor(struct nvkm_memory *memory) struct nv50_instobj *iobj = nv50_instobj(memory); struct nvkm_instmem *imem = &iobj->imem->base; struct nvkm_vma *bar; - void *map = map; + void *map; - mutex_lock(&imem->subdev.mutex); + mutex_lock(&imem->mutex); if (likely(iobj->lru.next)) list_del(&iobj->lru); map = iobj->map; bar = iobj->bar; - mutex_unlock(&imem->subdev.mutex); + mutex_unlock(&imem->mutex); if (map) { struct nvkm_vmm *vmm = nvkm_bar_bar2_vmm(imem->subdev.device); @@ -386,14 +386,14 @@ nv50_instmem = { }; int -nv50_instmem_new(struct nvkm_device *device, int index, +nv50_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_instmem **pimem) { struct nv50_instmem *imem; if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) return -ENOMEM; - nvkm_instmem_ctor(&nv50_instmem, device, index, &imem->base); + nvkm_instmem_ctor(&nv50_instmem, device, type, inst, &imem->base); INIT_LIST_HEAD(&imem->lru); *pimem = &imem->base; return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h index f5da8fcbdde3..56c15e30a5dd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h @@ -16,7 +16,7 @@ struct nvkm_instmem_func { }; void nvkm_instmem_ctor(const struct nvkm_instmem_func *, struct nvkm_device *, - int index, struct nvkm_instmem *); + enum nvkm_subdev_type, int, struct nvkm_instmem *); void nvkm_instmem_boot(struct nvkm_instmem *); #include <core/memory.h> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild index 2b6d36ea7067..728d75010847 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild @@ -6,3 +6,4 @@ nvkm-y += nvkm/subdev/ltc/gm107.o nvkm-y += nvkm/subdev/ltc/gm200.o nvkm-y += nvkm/subdev/ltc/gp100.o nvkm-y += nvkm/subdev/ltc/gp102.o +nvkm-y += nvkm/subdev/ltc/gp10b.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c index 23242179e600..fa683c190795 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c @@ -33,10 +33,10 @@ nvkm_ltc_tags_clear(struct nvkm_device *device, u32 first, u32 count) BUG_ON((first > limit) || (limit >= ltc->num_tags)); - mutex_lock(<c->subdev.mutex); + mutex_lock(<c->mutex); ltc->func->cbc_clear(ltc, first, limit); ltc->func->cbc_wait(ltc); - mutex_unlock(<c->subdev.mutex); + mutex_unlock(<c->mutex); } int @@ -113,6 +113,7 @@ nvkm_ltc_dtor(struct nvkm_subdev *subdev) { struct nvkm_ltc *ltc = nvkm_ltc(subdev); nvkm_memory_unref(<c->tag_ram); + mutex_destroy(<c->mutex); return ltc; } @@ -126,15 +127,16 @@ nvkm_ltc = { int nvkm_ltc_new_(const struct nvkm_ltc_func *func, struct nvkm_device *device, - int index, struct nvkm_ltc **pltc) + enum nvkm_subdev_type type, int inst, struct nvkm_ltc **pltc) { struct nvkm_ltc *ltc; if (!(ltc = *pltc = kzalloc(sizeof(*ltc), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_ltc, device, index, <c->subdev); + nvkm_subdev_ctor(&nvkm_ltc, device, type, inst, <c->subdev); ltc->func = func; + mutex_init(<c->mutex); ltc->zbc_min = 1; /* reserve 0 for disabled */ ltc->zbc_max = min(func->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1; return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c index a21ef45b8572..fd8aeafc812d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c @@ -200,8 +200,8 @@ gf100_ltc_oneinit_tag_ram(struct nvkm_ltc *ltc) } mm_init: - nvkm_mm_fini(&fb->tags); - return nvkm_mm_init(&fb->tags, 0, 0, ltc->num_tags, 1); + nvkm_mm_fini(&fb->tags.mm); + return nvkm_mm_init(&fb->tags.mm, 0, 0, ltc->num_tags, 1); } int @@ -249,7 +249,8 @@ gf100_ltc = { }; int -gf100_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +gf100_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) { - return nvkm_ltc_new_(&gf100_ltc, device, index, pltc); + return nvkm_ltc_new_(&gf100_ltc, device, type, inst, pltc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c index b4f6e0034d58..94aa09244d67 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c @@ -50,7 +50,8 @@ gk104_ltc = { }; int -gk104_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +gk104_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) { - return nvkm_ltc_new_(&gk104_ltc, device, index, pltc); + return nvkm_ltc_new_(&gk104_ltc, device, type, inst, pltc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c index ec0a3844b2d1..54d1d65d5a85 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c @@ -145,7 +145,8 @@ gm107_ltc = { }; int -gm107_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +gm107_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) { - return nvkm_ltc_new_(&gm107_ltc, device, index, pltc); + return nvkm_ltc_new_(&gm107_ltc, device, type, inst, pltc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c index e18e0dc19ec8..8cfdbbdd8e8d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c @@ -57,7 +57,8 @@ gm200_ltc = { }; int -gm200_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +gm200_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) { - return nvkm_ltc_new_(&gm200_ltc, device, index, pltc); + return nvkm_ltc_new_(&gm200_ltc, device, type, inst, pltc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c index e923ed76d37a..a4a6cd9b435a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c @@ -69,7 +69,8 @@ gp100_ltc = { }; int -gp100_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +gp100_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) { - return nvkm_ltc_new_(&gp100_ltc, device, index, pltc); + return nvkm_ltc_new_(&gp100_ltc, device, type, inst, pltc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.c index 601747ada655..ff05d617e7f4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.c @@ -45,7 +45,8 @@ gp102_ltc = { }; int -gp102_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +gp102_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) { - return nvkm_ltc_new_(&gp102_ltc, device, index, pltc); + return nvkm_ltc_new_(&gp102_ltc, device, type, inst, pltc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c new file mode 100644 index 000000000000..dfebd796cb4b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2019 NVIDIA Corporation. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Thierry Reding + */ + +#include "priv.h" + +static void +gp10b_ltc_init(struct nvkm_ltc *ltc) +{ + struct nvkm_device *device = ltc->subdev.device; + struct iommu_fwspec *spec; + + nvkm_wr32(device, 0x17e27c, ltc->ltc_nr); + nvkm_wr32(device, 0x17e000, ltc->ltc_nr); + nvkm_wr32(device, 0x100800, ltc->ltc_nr); + + spec = dev_iommu_fwspec_get(device->dev); + if (spec) { + u32 sid = spec->ids[0] & 0xffff; + + /* stream ID */ + nvkm_wr32(device, 0x160000, sid << 2); + } +} + +static const struct nvkm_ltc_func +gp10b_ltc = { + .oneinit = gp100_ltc_oneinit, + .init = gp10b_ltc_init, + .intr = gp100_ltc_intr, + .cbc_clear = gm107_ltc_cbc_clear, + .cbc_wait = gm107_ltc_cbc_wait, + .zbc = 16, + .zbc_clear_color = gm107_ltc_zbc_clear_color, + .zbc_clear_depth = gm107_ltc_zbc_clear_depth, + .zbc_clear_stencil = gp102_ltc_zbc_clear_stencil, + .invalidate = gf100_ltc_invalidate, + .flush = gf100_ltc_flush, +}; + +int +gp10b_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) +{ + return nvkm_ltc_new_(&gp10b_ltc, device, type, inst, pltc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h index 2fcf18e46ce3..2bebe139005d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h @@ -5,8 +5,8 @@ #include <subdev/ltc.h> #include <core/enum.h> -int nvkm_ltc_new_(const struct nvkm_ltc_func *, struct nvkm_device *, - int index, struct nvkm_ltc **); +int nvkm_ltc_new_(const struct nvkm_ltc_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_ltc **); struct nvkm_ltc_func { int (*oneinit)(struct nvkm_ltc *); @@ -46,4 +46,6 @@ void gm107_ltc_zbc_clear_depth(struct nvkm_ltc *, int, const u32); int gp100_ltc_oneinit(struct nvkm_ltc *); void gp100_ltc_init(struct nvkm_ltc *); void gp100_ltc_intr(struct nvkm_ltc *); + +void gp102_ltc_zbc_clear_stencil(struct nvkm_ltc *, int, const u32); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild index 2585ef07532a..ac2b34e9ac6a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild @@ -14,3 +14,4 @@ nvkm-y += nvkm/subdev/mc/gk20a.o nvkm-y += nvkm/subdev/mc/gp100.o nvkm-y += nvkm/subdev/mc/gp10b.o nvkm-y += nvkm/subdev/mc/tu102.o +nvkm-y += nvkm/subdev/mc/ga100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c index 0e57ab2a709f..21c4af3f81d5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c @@ -35,14 +35,14 @@ nvkm_mc_unk260(struct nvkm_device *device, u32 data) } void -nvkm_mc_intr_mask(struct nvkm_device *device, enum nvkm_devidx devidx, bool en) +nvkm_mc_intr_mask(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, bool en) { struct nvkm_mc *mc = device->mc; const struct nvkm_mc_map *map; if (likely(mc) && mc->func->intr_mask) { - u32 mask = nvkm_top_intr_mask(device, devidx); + u32 mask = nvkm_top_intr_mask(device, type, inst); for (map = mc->func->intr; !mask && map->stat; map++) { - if (map->unit == devidx) + if (map->type == type && map->inst == inst) mask = map->stat; } mc->func->intr_mask(mc, mask, en ? mask : 0); @@ -78,27 +78,34 @@ void nvkm_mc_intr(struct nvkm_device *device, bool *handled) { struct nvkm_mc *mc = device->mc; + struct nvkm_top *top = device->top; + struct nvkm_top_device *tdev; struct nvkm_subdev *subdev; const struct nvkm_mc_map *map; u32 stat, intr; - u64 subdevs; if (unlikely(!mc)) return; - intr = nvkm_mc_intr_stat(mc); - stat = nvkm_top_intr(device, intr, &subdevs); - while (subdevs) { - enum nvkm_devidx subidx = __ffs64(subdevs); - subdev = nvkm_device_subdev(device, subidx); - if (subdev) - nvkm_subdev_intr(subdev); - subdevs &= ~BIT_ULL(subidx); + stat = intr = nvkm_mc_intr_stat(mc); + + if (top) { + list_for_each_entry(tdev, &top->device, head) { + if (tdev->intr >= 0 && (stat & BIT(tdev->intr))) { + subdev = nvkm_device_subdev(device, tdev->type, tdev->inst); + if (subdev) { + nvkm_subdev_intr(subdev); + stat &= ~BIT(tdev->intr); + if (!stat) + break; + } + } + } } for (map = mc->func->intr; map->stat; map++) { if (intr & map->stat) { - subdev = nvkm_device_subdev(device, map->unit); + subdev = nvkm_device_subdev(device, map->type, map->inst); if (subdev) nvkm_subdev_intr(subdev); stat &= ~map->stat; @@ -108,23 +115,19 @@ nvkm_mc_intr(struct nvkm_device *device, bool *handled) if (stat) nvkm_error(&mc->subdev, "intr %08x\n", stat); *handled = intr != 0; - - if (mc->func->intr_hack) - mc->func->intr_hack(mc, handled); } static u32 -nvkm_mc_reset_mask(struct nvkm_device *device, bool isauto, - enum nvkm_devidx devidx) +nvkm_mc_reset_mask(struct nvkm_device *device, bool isauto, enum nvkm_subdev_type type, int inst) { struct nvkm_mc *mc = device->mc; const struct nvkm_mc_map *map; u64 pmc_enable = 0; if (likely(mc)) { - if (!(pmc_enable = nvkm_top_reset(device, devidx))) { + if (!(pmc_enable = nvkm_top_reset(device, type, inst))) { for (map = mc->func->reset; map && map->stat; map++) { if (!isauto || !map->noauto) { - if (map->unit == devidx) { + if (map->type == type && map->inst == inst) { pmc_enable = map->stat; break; } @@ -136,9 +139,9 @@ nvkm_mc_reset_mask(struct nvkm_device *device, bool isauto, } void -nvkm_mc_reset(struct nvkm_device *device, enum nvkm_devidx devidx) +nvkm_mc_reset(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { - u64 pmc_enable = nvkm_mc_reset_mask(device, true, devidx); + u64 pmc_enable = nvkm_mc_reset_mask(device, true, type, inst); if (pmc_enable) { nvkm_mask(device, 0x000200, pmc_enable, 0x00000000); nvkm_mask(device, 0x000200, pmc_enable, pmc_enable); @@ -147,17 +150,17 @@ nvkm_mc_reset(struct nvkm_device *device, enum nvkm_devidx devidx) } void -nvkm_mc_disable(struct nvkm_device *device, enum nvkm_devidx devidx) +nvkm_mc_disable(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { - u64 pmc_enable = nvkm_mc_reset_mask(device, false, devidx); + u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst); if (pmc_enable) nvkm_mask(device, 0x000200, pmc_enable, 0x00000000); } void -nvkm_mc_enable(struct nvkm_device *device, enum nvkm_devidx devidx) +nvkm_mc_enable(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { - u64 pmc_enable = nvkm_mc_reset_mask(device, false, devidx); + u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst); if (pmc_enable) { nvkm_mask(device, 0x000200, pmc_enable, pmc_enable); nvkm_rd32(device, 0x000200); @@ -165,9 +168,9 @@ nvkm_mc_enable(struct nvkm_device *device, enum nvkm_devidx devidx) } bool -nvkm_mc_enabled(struct nvkm_device *device, enum nvkm_devidx devidx) +nvkm_mc_enabled(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { - u64 pmc_enable = nvkm_mc_reset_mask(device, false, devidx); + u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst); return (pmc_enable != 0) && ((nvkm_rd32(device, 0x000200) & pmc_enable) == pmc_enable); @@ -206,19 +209,19 @@ nvkm_mc = { void nvkm_mc_ctor(const struct nvkm_mc_func *func, struct nvkm_device *device, - int index, struct nvkm_mc *mc) + enum nvkm_subdev_type type, int inst, struct nvkm_mc *mc) { - nvkm_subdev_ctor(&nvkm_mc, device, index, &mc->subdev); + nvkm_subdev_ctor(&nvkm_mc, device, type, inst, &mc->subdev); mc->func = func; } int nvkm_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device, - int index, struct nvkm_mc **pmc) + enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { struct nvkm_mc *mc; if (!(mc = *pmc = kzalloc(sizeof(*mc), GFP_KERNEL))) return -ENOMEM; - nvkm_mc_ctor(func, device, index, *pmc); + nvkm_mc_ctor(func, device, type, inst, *pmc); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.c index 430a61c3df44..4cfc1c984006 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.c @@ -62,7 +62,7 @@ g84_mc = { }; int -g84_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +g84_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&g84_mc, device, index, pmc); + return nvkm_mc_new_(&g84_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c index 93ad4982ce5f..b7e58d75d894 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c @@ -62,7 +62,7 @@ g98_mc = { }; int -g98_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +g98_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&g98_mc, device, index, pmc); + return nvkm_mc_new_(&g98_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c new file mode 100644 index 000000000000..4105175dfccd --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c @@ -0,0 +1,74 @@ +/* + * Copyright 2021 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +static void +ga100_mc_intr_unarm(struct nvkm_mc *mc) +{ + nvkm_wr32(mc->subdev.device, 0xb81610, 0x00000004); +} + +static void +ga100_mc_intr_rearm(struct nvkm_mc *mc) +{ + nvkm_wr32(mc->subdev.device, 0xb81608, 0x00000004); +} + +static void +ga100_mc_intr_mask(struct nvkm_mc *mc, u32 mask, u32 intr) +{ + nvkm_wr32(mc->subdev.device, 0xb81210, mask & intr ); + nvkm_wr32(mc->subdev.device, 0xb81410, mask & ~(mask & intr)); +} + +static u32 +ga100_mc_intr_stat(struct nvkm_mc *mc) +{ + u32 intr_top = nvkm_rd32(mc->subdev.device, 0xb81600), intr = 0x00000000; + if (intr_top & 0x00000004) + intr = nvkm_mask(mc->subdev.device, 0xb81010, 0x00000000, 0x00000000); + return intr; +} + +static void +ga100_mc_init(struct nvkm_mc *mc) +{ + nv50_mc_init(mc); + nvkm_wr32(mc->subdev.device, 0xb81210, 0xffffffff); +} + +static const struct nvkm_mc_func +ga100_mc = { + .init = ga100_mc_init, + .intr = gp100_mc_intr, + .intr_unarm = ga100_mc_intr_unarm, + .intr_rearm = ga100_mc_intr_rearm, + .intr_mask = ga100_mc_intr_mask, + .intr_stat = ga100_mc_intr_stat, + .reset = gk104_mc_reset, +}; + +int +ga100_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) +{ + return nvkm_mc_new_(&ga100_mc, device, type, inst, pmc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c index f93766418056..3a589c6f7fad 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c @@ -27,11 +27,11 @@ static const struct nvkm_mc_map gf100_mc_reset[] = { { 0x00020000, NVKM_ENGINE_MSPDEC }, { 0x00008000, NVKM_ENGINE_MSVLD }, - { 0x00002000, NVKM_SUBDEV_PMU, true }, + { 0x00002000, NVKM_SUBDEV_PMU, 0, true }, { 0x00001000, NVKM_ENGINE_GR }, { 0x00000100, NVKM_ENGINE_FIFO }, - { 0x00000080, NVKM_ENGINE_CE1 }, - { 0x00000040, NVKM_ENGINE_CE0 }, + { 0x00000080, NVKM_ENGINE_CE, 1 }, + { 0x00000040, NVKM_ENGINE_CE, 0 }, { 0x00000002, NVKM_ENGINE_MSPPP }, {} }; @@ -43,10 +43,10 @@ gf100_mc_intr[] = { { 0x00008000, NVKM_ENGINE_MSVLD }, { 0x00001000, NVKM_ENGINE_GR }, { 0x00000100, NVKM_ENGINE_FIFO }, - { 0x00000040, NVKM_ENGINE_CE1 }, - { 0x00000020, NVKM_ENGINE_CE0 }, + { 0x00000040, NVKM_ENGINE_CE, 1 }, + { 0x00000020, NVKM_ENGINE_CE, 0 }, { 0x00000001, NVKM_ENGINE_MSPPP }, - { 0x40000000, NVKM_SUBDEV_IBUS }, + { 0x40000000, NVKM_SUBDEV_PRIVRING }, { 0x10000000, NVKM_SUBDEV_BUS }, { 0x08000000, NVKM_SUBDEV_FB }, { 0x02000000, NVKM_SUBDEV_LTC }, @@ -112,7 +112,7 @@ gf100_mc = { }; int -gf100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +gf100_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&gf100_mc, device, index, pmc); + return nvkm_mc_new_(&gf100_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c index 7b8c6ecad1a5..d9b9067fa93f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c @@ -26,7 +26,7 @@ const struct nvkm_mc_map gk104_mc_reset[] = { { 0x00000100, NVKM_ENGINE_FIFO }, - { 0x00002000, NVKM_SUBDEV_PMU, true }, + { 0x00002000, NVKM_SUBDEV_PMU, 0, true }, {} }; @@ -34,7 +34,7 @@ const struct nvkm_mc_map gk104_mc_intr[] = { { 0x04000000, NVKM_ENGINE_DISP }, { 0x00000100, NVKM_ENGINE_FIFO }, - { 0x40000000, NVKM_SUBDEV_IBUS }, + { 0x40000000, NVKM_SUBDEV_PRIVRING }, { 0x10000000, NVKM_SUBDEV_BUS }, { 0x08000000, NVKM_SUBDEV_FB }, { 0x02000000, NVKM_SUBDEV_LTC }, @@ -60,7 +60,7 @@ gk104_mc = { }; int -gk104_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +gk104_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&gk104_mc, device, index, pmc); + return nvkm_mc_new_(&gk104_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c index ca1bf3279dbe..03590292749a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c @@ -35,7 +35,7 @@ gk20a_mc = { }; int -gk20a_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +gk20a_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&gk20a_mc, device, index, pmc); + return nvkm_mc_new_(&gk20a_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c index 43db245eec9a..5fd1a0595c33 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c @@ -80,7 +80,7 @@ gp100_mc_intr[] = { { 0x04000000, NVKM_ENGINE_DISP }, { 0x00000100, NVKM_ENGINE_FIFO }, { 0x00000200, NVKM_SUBDEV_FAULT }, - { 0x40000000, NVKM_SUBDEV_IBUS }, + { 0x40000000, NVKM_SUBDEV_PRIVRING }, { 0x10000000, NVKM_SUBDEV_BUS }, { 0x08000000, NVKM_SUBDEV_FB }, { 0x02000000, NVKM_SUBDEV_LTC }, @@ -106,13 +106,13 @@ gp100_mc = { int gp100_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device, - int index, struct nvkm_mc **pmc) + enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { struct gp100_mc *mc; if (!(mc = kzalloc(sizeof(*mc), GFP_KERNEL))) return -ENOMEM; - nvkm_mc_ctor(func, device, index, &mc->base); + nvkm_mc_ctor(func, device, type, inst, &mc->base); *pmc = &mc->base; spin_lock_init(&mc->lock); @@ -122,7 +122,7 @@ gp100_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device, } int -gp100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +gp100_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return gp100_mc_new_(&gp100_mc, device, index, pmc); + return gp100_mc_new_(&gp100_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c index ff8629de97d6..dd581d030ced 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c @@ -23,7 +23,7 @@ #include "priv.h" -void +static void gp10b_mc_init(struct nvkm_mc *mc) { struct nvkm_device *device = mc->subdev.device; @@ -43,7 +43,7 @@ gp10b_mc = { }; int -gp10b_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +gp10b_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return gp100_mc_new_(&gp10b_mc, device, index, pmc); + return gp100_mc_new_(&gp10b_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c index 99d50a3d956f..1b4d43531dba 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c @@ -27,7 +27,7 @@ static const struct nvkm_mc_map gt215_mc_reset[] = { { 0x04008000, NVKM_ENGINE_MSVLD }, { 0x01020000, NVKM_ENGINE_MSPDEC }, - { 0x00802000, NVKM_ENGINE_CE0 }, + { 0x00802000, NVKM_ENGINE_CE, 0 }, { 0x00400002, NVKM_ENGINE_MSPPP }, { 0x00201000, NVKM_ENGINE_GR }, { 0x00000100, NVKM_ENGINE_FIFO }, @@ -37,7 +37,7 @@ gt215_mc_reset[] = { static const struct nvkm_mc_map gt215_mc_intr[] = { { 0x04000000, NVKM_ENGINE_DISP }, - { 0x00400000, NVKM_ENGINE_CE0 }, + { 0x00400000, NVKM_ENGINE_CE, 0 }, { 0x00020000, NVKM_ENGINE_MSPDEC }, { 0x00008000, NVKM_ENGINE_MSVLD }, { 0x00001000, NVKM_ENGINE_GR }, @@ -71,7 +71,7 @@ gt215_mc = { }; int -gt215_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +gt215_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(>215_mc, device, index, pmc); + return nvkm_mc_new_(>215_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c index 6509defd1460..bc0d09bafa99 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c @@ -80,7 +80,7 @@ nv04_mc = { }; int -nv04_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +nv04_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&nv04_mc, device, index, pmc); + return nvkm_mc_new_(&nv04_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.c index 9213107901e6..ab59ca1ee068 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.c @@ -44,7 +44,7 @@ nv11_mc = { }; int -nv11_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +nv11_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&nv11_mc, device, index, pmc); + return nvkm_mc_new_(&nv11_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c index 64bf5bbf8146..03d756e26e57 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c @@ -53,7 +53,7 @@ nv17_mc = { }; int -nv17_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +nv17_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&nv17_mc, device, index, pmc); + return nvkm_mc_new_(&nv17_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c index 65fa44a64b98..95f65766e8b0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c @@ -48,7 +48,7 @@ nv44_mc = { }; int -nv44_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +nv44_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&nv44_mc, device, index, pmc); + return nvkm_mc_new_(&nv44_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c index fe93b4fd7100..fce3613cdfa5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c @@ -55,7 +55,7 @@ nv50_mc = { }; int -nv50_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +nv50_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&nv50_mc, device, index, pmc); + return nvkm_mc_new_(&nv50_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h index 4aab753a6040..c8bcabb98f99 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h @@ -4,14 +4,15 @@ #define nvkm_mc(p) container_of((p), struct nvkm_mc, subdev) #include <subdev/mc.h> -void nvkm_mc_ctor(const struct nvkm_mc_func *, struct nvkm_device *, - int index, struct nvkm_mc *); -int nvkm_mc_new_(const struct nvkm_mc_func *, struct nvkm_device *, - int index, struct nvkm_mc **); +void nvkm_mc_ctor(const struct nvkm_mc_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_mc *); +int nvkm_mc_new_(const struct nvkm_mc_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_mc **); struct nvkm_mc_map { u32 stat; - u32 unit; + enum nvkm_subdev_type type; + int inst; bool noauto; }; @@ -26,7 +27,6 @@ struct nvkm_mc_func { void (*intr_mask)(struct nvkm_mc *, u32 mask, u32 stat); /* retrieve pending interrupt mask (NV_PMC_INTR) */ u32 (*intr_stat)(struct nvkm_mc *); - void (*intr_hack)(struct nvkm_mc *, bool *handled); const struct nvkm_mc_map *reset; void (*unk260)(struct nvkm_mc *, u32); }; @@ -53,7 +53,7 @@ void gf100_mc_unk260(struct nvkm_mc *, u32); void gp100_mc_intr_unarm(struct nvkm_mc *); void gp100_mc_intr_rearm(struct nvkm_mc *); void gp100_mc_intr_mask(struct nvkm_mc *, u32, u32); -int gp100_mc_new_(const struct nvkm_mc_func *, struct nvkm_device *, int, +int gp100_mc_new_(const struct nvkm_mc_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_mc **); extern const struct nvkm_mc_map gk104_mc_intr[]; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c index d098c44a4fcb..a96084b34a78 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c @@ -19,37 +19,118 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ +#define tu102_mc(p) container_of((p), struct tu102_mc, base) #include "priv.h" +struct tu102_mc { + struct nvkm_mc base; + spinlock_t lock; + bool intr; + u32 mask; +}; + static void -tu102_mc_intr_hack(struct nvkm_mc *mc, bool *handled) +tu102_mc_intr_update(struct tu102_mc *mc) { - struct nvkm_device *device = mc->subdev.device; - u32 stat = nvkm_rd32(device, 0xb81010); - if (stat & 0x00000050) { - struct nvkm_subdev *subdev = - nvkm_device_subdev(device, NVKM_SUBDEV_FAULT); - nvkm_wr32(device, 0xb81010, stat & 0x00000050); - if (subdev) - nvkm_subdev_intr(subdev); - *handled = true; + struct nvkm_device *device = mc->base.subdev.device; + u32 mask = mc->intr ? mc->mask : 0, i; + + for (i = 0; i < 2; i++) { + nvkm_wr32(device, 0x000180 + (i * 0x04), ~mask); + nvkm_wr32(device, 0x000160 + (i * 0x04), mask); } + + if (mask & 0x00000200) + nvkm_wr32(device, 0xb81608, 0x6); + else + nvkm_wr32(device, 0xb81610, 0x6); +} + +static void +tu102_mc_intr_unarm(struct nvkm_mc *base) +{ + struct tu102_mc *mc = tu102_mc(base); + unsigned long flags; + + spin_lock_irqsave(&mc->lock, flags); + mc->intr = false; + tu102_mc_intr_update(mc); + spin_unlock_irqrestore(&mc->lock, flags); +} + +static void +tu102_mc_intr_rearm(struct nvkm_mc *base) +{ + struct tu102_mc *mc = tu102_mc(base); + unsigned long flags; + + spin_lock_irqsave(&mc->lock, flags); + mc->intr = true; + tu102_mc_intr_update(mc); + spin_unlock_irqrestore(&mc->lock, flags); +} + +static void +tu102_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr) +{ + struct tu102_mc *mc = tu102_mc(base); + unsigned long flags; + + spin_lock_irqsave(&mc->lock, flags); + mc->mask = (mc->mask & ~mask) | intr; + tu102_mc_intr_update(mc); + spin_unlock_irqrestore(&mc->lock, flags); +} + +static u32 +tu102_mc_intr_stat(struct nvkm_mc *mc) +{ + struct nvkm_device *device = mc->subdev.device; + u32 intr0 = nvkm_rd32(device, 0x000100); + u32 intr1 = nvkm_rd32(device, 0x000104); + u32 intr_top = nvkm_rd32(device, 0xb81600); + + /* Turing and above route the MMU fault interrupts via a different + * interrupt tree with different control registers. For the moment remap + * them back to the old PMC vector. + */ + if (intr_top & 0x00000006) + intr0 |= 0x00000200; + + return intr0 | intr1; } + static const struct nvkm_mc_func tu102_mc = { .init = nv50_mc_init, .intr = gp100_mc_intr, - .intr_unarm = gp100_mc_intr_unarm, - .intr_rearm = gp100_mc_intr_rearm, - .intr_mask = gp100_mc_intr_mask, - .intr_stat = gf100_mc_intr_stat, - .intr_hack = tu102_mc_intr_hack, + .intr_unarm = tu102_mc_intr_unarm, + .intr_rearm = tu102_mc_intr_rearm, + .intr_mask = tu102_mc_intr_mask, + .intr_stat = tu102_mc_intr_stat, .reset = gk104_mc_reset, }; +static int +tu102_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) +{ + struct tu102_mc *mc; + + if (!(mc = kzalloc(sizeof(*mc), GFP_KERNEL))) + return -ENOMEM; + nvkm_mc_ctor(func, device, type, inst, &mc->base); + *pmc = &mc->base; + + spin_lock_init(&mc->lock); + mc->intr = false; + mc->mask = 0x7fffffff; + return 0; +} + int -tu102_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +tu102_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return gp100_mc_new_(&tu102_mc, device, index, pmc); + return tu102_mc_new_(&tu102_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c index ee11ccaf0563..ad3b44a9e0e7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c @@ -61,7 +61,7 @@ nvkm_mmu_ptp_put(struct nvkm_mmu *mmu, bool force, struct nvkm_mmu_pt *pt) kfree(pt); } -struct nvkm_mmu_pt * +static struct nvkm_mmu_pt * nvkm_mmu_ptp_get(struct nvkm_mmu *mmu, u32 size, bool zero) { struct nvkm_mmu_pt *pt; @@ -316,9 +316,9 @@ nvkm_mmu_vram(struct nvkm_mmu *mmu) { struct nvkm_device *device = mmu->subdev.device; struct nvkm_mm *mm = &device->fb->ram->vram; - const u32 sizeN = nvkm_mm_heap_size(mm, NVKM_RAM_MM_NORMAL); - const u32 sizeU = nvkm_mm_heap_size(mm, NVKM_RAM_MM_NOMAP); - const u32 sizeM = nvkm_mm_heap_size(mm, NVKM_RAM_MM_MIXED); + const u64 sizeN = nvkm_mm_heap_size(mm, NVKM_RAM_MM_NORMAL); + const u64 sizeU = nvkm_mm_heap_size(mm, NVKM_RAM_MM_NOMAP); + const u64 sizeM = nvkm_mm_heap_size(mm, NVKM_RAM_MM_MIXED); u8 type = NVKM_MEM_KIND * !!mmu->func->kind; u8 heap = NVKM_MEM_VRAM; int heapM, heapN, heapU; @@ -402,6 +402,7 @@ nvkm_mmu_dtor(struct nvkm_subdev *subdev) nvkm_vmm_unref(&mmu->vmm); nvkm_mmu_ptc_fini(mmu); + mutex_destroy(&mmu->mutex); return mmu; } @@ -414,22 +415,23 @@ nvkm_mmu = { void nvkm_mmu_ctor(const struct nvkm_mmu_func *func, struct nvkm_device *device, - int index, struct nvkm_mmu *mmu) + enum nvkm_subdev_type type, int inst, struct nvkm_mmu *mmu) { - nvkm_subdev_ctor(&nvkm_mmu, device, index, &mmu->subdev); + nvkm_subdev_ctor(&nvkm_mmu, device, type, inst, &mmu->subdev); mmu->func = func; mmu->dma_bits = func->dma_bits; nvkm_mmu_ptc_init(mmu); + mutex_init(&mmu->mutex); mmu->user.ctor = nvkm_ummu_new; mmu->user.base = func->mmu.user; } int nvkm_mmu_new_(const struct nvkm_mmu_func *func, struct nvkm_device *device, - int index, struct nvkm_mmu **pmmu) + enum nvkm_subdev_type type, int inst, struct nvkm_mmu **pmmu) { if (!(*pmmu = kzalloc(sizeof(**pmmu), GFP_KERNEL))) return -ENOMEM; - nvkm_mmu_ctor(func, device, index, *pmmu); + nvkm_mmu_ctor(func, device, type, inst, *pmmu); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.c index 8accda5a772b..ce47a3b97be9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.c @@ -35,7 +35,8 @@ g84_mmu = { }; int -g84_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +g84_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&g84_mmu, device, index, pmmu); + return nvkm_mmu_new_(&g84_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c index 2d075246dc46..7a28b1d49f7c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c @@ -30,7 +30,7 @@ * The value 0xff represents an invalid storage type. */ const u8 * -gf100_mmu_kind(struct nvkm_mmu *mmu, int *count) +gf100_mmu_kind(struct nvkm_mmu *mmu, int *count, u8 *invalid) { static const u8 kind[256] = { @@ -69,6 +69,7 @@ gf100_mmu_kind(struct nvkm_mmu *mmu, int *count) }; *count = ARRAY_SIZE(kind); + *invalid = 0xff; return kind; } @@ -83,7 +84,8 @@ gf100_mmu = { }; int -gf100_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gf100_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&gf100_mmu, device, index, pmmu); + return nvkm_mmu_new_(&gf100_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.c index 3d7d1eb1cff9..34c9b2b821f6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.c @@ -35,7 +35,8 @@ gk104_mmu = { }; int -gk104_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gk104_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&gk104_mmu, device, index, pmmu); + return nvkm_mmu_new_(&gk104_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c index ac74965a60d4..a7db29c429ee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c @@ -35,7 +35,8 @@ gk20a_mmu = { }; int -gk20a_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gk20a_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&gk20a_mmu, device, index, pmmu); + return nvkm_mmu_new_(&gk20a_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.c index dbf644ebac97..e1696f637a68 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.c @@ -27,7 +27,7 @@ #include <nvif/class.h> const u8 * -gm200_mmu_kind(struct nvkm_mmu *mmu, int *count) +gm200_mmu_kind(struct nvkm_mmu *mmu, int *count, u8 *invalid) { static const u8 kind[256] = { @@ -65,6 +65,7 @@ gm200_mmu_kind(struct nvkm_mmu *mmu, int *count) 0xfe, 0xfe, 0xfe, 0xfe, 0xff, 0xfd, 0xfe, 0xff }; *count = ARRAY_SIZE(kind); + *invalid = 0xff; return kind; } @@ -89,9 +90,10 @@ gm200_mmu_fixed = { }; int -gm200_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gm200_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { if (device->fb->page) - return nvkm_mmu_new_(&gm200_mmu_fixed, device, index, pmmu); - return nvkm_mmu_new_(&gm200_mmu, device, index, pmmu); + return nvkm_mmu_new_(&gm200_mmu_fixed, device, type, inst, pmmu); + return nvkm_mmu_new_(&gm200_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c index 7353a94b4091..e6e1a8ad701e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c @@ -47,9 +47,10 @@ gm20b_mmu_fixed = { }; int -gm20b_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gm20b_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { if (device->fb->page) - return nvkm_mmu_new_(&gm20b_mmu_fixed, device, index, pmmu); - return nvkm_mmu_new_(&gm20b_mmu, device, index, pmmu); + return nvkm_mmu_new_(&gm20b_mmu_fixed, device, type, inst, pmmu); + return nvkm_mmu_new_(&gm20b_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.c index 65cb9d28e60e..daa5ab0f8711 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.c @@ -37,9 +37,10 @@ gp100_mmu = { }; int -gp100_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gp100_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { if (!nvkm_boolopt(device->cfgopt, "GP100MmuLayout", true)) - return gm200_mmu_new(device, index, pmmu); - return nvkm_mmu_new_(&gp100_mmu, device, index, pmmu); + return gm200_mmu_new(device, type, inst, pmmu); + return nvkm_mmu_new_(&gp100_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c index 0a50be9a785a..edd0bf9a5cd8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c @@ -37,9 +37,10 @@ gp10b_mmu = { }; int -gp10b_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gp10b_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { if (!nvkm_boolopt(device->cfgopt, "GP100MmuLayout", true)) - return gm20b_mmu_new(device, index, pmmu); - return nvkm_mmu_new_(&gp10b_mmu, device, index, pmmu); + return gm20b_mmu_new(device, type, inst, pmmu); + return nvkm_mmu_new_(&gp10b_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.c index e0997eedd6d9..fb8bdc88d566 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.c @@ -37,7 +37,8 @@ gv100_mmu = { }; int -gv100_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gv100_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&gv100_mmu, device, index, pmmu); + return nvkm_mmu_new_(&gv100_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.c index 0527b50730d9..514876d6411b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.c @@ -35,7 +35,8 @@ mcp77_mmu = { }; int -mcp77_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +mcp77_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&mcp77_mmu, device, index, pmmu); + return nvkm_mmu_new_(&mcp77_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c index d201c887c2cd..0674aa8f68c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c @@ -35,7 +35,8 @@ nv04_mmu = { }; int -nv04_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +nv04_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&nv04_mmu, device, index, pmmu); + return nvkm_mmu_new_(&nv04_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c index adca81895c09..909f92b72847 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c @@ -47,11 +47,12 @@ nv41_mmu = { }; int -nv41_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +nv41_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { if (device->type == NVKM_DEVICE_AGP || !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) - return nv04_mmu_new(device, index, pmmu); + return nv04_mmu_new(device, type, inst, pmmu); - return nvkm_mmu_new_(&nv41_mmu, device, index, pmmu); + return nvkm_mmu_new_(&nv41_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c index 598c53a27bde..dd2a8d461da3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c @@ -62,11 +62,12 @@ nv44_mmu = { }; int -nv44_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +nv44_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { if (device->type == NVKM_DEVICE_AGP || !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) - return nv04_mmu_new(device, index, pmmu); + return nv04_mmu_new(device, type, inst, pmmu); - return nvkm_mmu_new_(&nv44_mmu, device, index, pmmu); + return nvkm_mmu_new_(&nv44_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c index db3dfbbb2aa0..78d46e35d0a9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c @@ -27,7 +27,7 @@ #include <nvif/class.h> const u8 * -nv50_mmu_kind(struct nvkm_mmu *base, int *count) +nv50_mmu_kind(struct nvkm_mmu *base, int *count, u8 *invalid) { /* 0x01: no bank swizzle * 0x02: bank swizzled @@ -57,6 +57,7 @@ nv50_mmu_kind(struct nvkm_mmu *base, int *count) 0x01, 0x01, 0x02, 0x02, 0x01, 0x01, 0x7f, 0x7f }; *count = ARRAY_SIZE(kind); + *invalid = 0x7f; return kind; } @@ -70,7 +71,8 @@ nv50_mmu = { }; int -nv50_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +nv50_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&nv50_mmu, device, index, pmmu); + return nvkm_mmu_new_(&nv50_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h index 07f2fcd18f3d..5265bf4d8366 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h @@ -4,10 +4,10 @@ #define nvkm_mmu(p) container_of((p), struct nvkm_mmu, subdev) #include <subdev/mmu.h> -void nvkm_mmu_ctor(const struct nvkm_mmu_func *, struct nvkm_device *, - int index, struct nvkm_mmu *); -int nvkm_mmu_new_(const struct nvkm_mmu_func *, struct nvkm_device *, - int index, struct nvkm_mmu **); +void nvkm_mmu_ctor(const struct nvkm_mmu_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_mmu *); +int nvkm_mmu_new_(const struct nvkm_mmu_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_mmu **); struct nvkm_mmu_func { void (*init)(struct nvkm_mmu *); @@ -35,17 +35,17 @@ struct nvkm_mmu_func { u32 pd_offset; } vmm; - const u8 *(*kind)(struct nvkm_mmu *, int *count); + const u8 *(*kind)(struct nvkm_mmu *, int *count, u8 *invalid); bool kind_sys; }; extern const struct nvkm_mmu_func nv04_mmu; -const u8 *nv50_mmu_kind(struct nvkm_mmu *, int *count); +const u8 *nv50_mmu_kind(struct nvkm_mmu *, int *count, u8 *invalid); -const u8 *gf100_mmu_kind(struct nvkm_mmu *, int *count); +const u8 *gf100_mmu_kind(struct nvkm_mmu *, int *count, u8 *invalid); -const u8 *gm200_mmu_kind(struct nvkm_mmu *, int *); +const u8 *gm200_mmu_kind(struct nvkm_mmu *, int *, u8 *); struct nvkm_mmu_pt { union { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c index c0db0ce10cba..8d060ce47f86 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c @@ -1,5 +1,6 @@ /* * Copyright 2018 Red Hat Inc. + * Copyright 2019 NVIDIA Corporation. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -26,18 +27,32 @@ #include <nvif/class.h> +static const u8 * +tu102_mmu_kind(struct nvkm_mmu *mmu, int *count, u8 *invalid) +{ + static const u8 + kind[16] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* 0x00 */ + 0x06, 0x06, 0x02, 0x01, 0x03, 0x04, 0x05, 0x07, + }; + *count = ARRAY_SIZE(kind); + *invalid = 0x07; + return kind; +} + static const struct nvkm_mmu_func tu102_mmu = { .dma_bits = 47, .mmu = {{ -1, -1, NVIF_CLASS_MMU_GF100}}, .mem = {{ -1, 0, NVIF_CLASS_MEM_GF100}, gf100_mem_new, gf100_mem_map }, .vmm = {{ -1, 0, NVIF_CLASS_VMM_GP100}, tu102_vmm_new }, - .kind = gm200_mmu_kind, + .kind = tu102_mmu_kind, .kind_sys = true, }; int -tu102_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +tu102_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&tu102_mmu, device, index, pmmu); + return nvkm_mmu_new_(&tu102_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c index fac2f9a45ea6..e530bb8b3b17 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c @@ -41,7 +41,7 @@ nvkm_umem_search(struct nvkm_client *client, u64 handle) object = nvkm_object_search(client, handle, &nvkm_umem); if (IS_ERR(object)) { - if (client->super && client != master) { + if (client != master) { spin_lock(&master->lock); list_for_each_entry(umem, &master->umem, head) { if (umem->object.object == handle) { @@ -53,8 +53,7 @@ nvkm_umem_search(struct nvkm_client *client, u64 handle) } } else { umem = nvkm_umem(object); - if (!umem->priv || client->super) - memory = nvkm_memory_ref(umem->memory); + memory = nvkm_memory_ref(umem->memory); } return memory ? memory : ERR_PTR(-ENOENT); @@ -167,7 +166,6 @@ nvkm_umem_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, nvkm_object_ctor(&nvkm_umem, oclass, &umem->object); umem->mmu = mmu; umem->type = mmu->type[type].type; - umem->priv = oclass->client->super; INIT_LIST_HEAD(&umem->head); *pobject = &umem->object; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.h index 85cf692d620a..d56a594016cc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.h @@ -8,7 +8,6 @@ struct nvkm_umem { struct nvkm_object object; struct nvkm_mmu *mmu; u8 type:8; - bool priv:1; bool mappable:1; bool io:1; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c index 353f10f92b77..6870fda4b188 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c @@ -34,7 +34,7 @@ nvkm_ummu_sclass(struct nvkm_object *object, int index, { struct nvkm_mmu *mmu = nvkm_ummu(object)->mmu; - if (mmu->func->mem.user.oclass && oclass->client->super) { + if (mmu->func->mem.user.oclass) { if (index-- == 0) { oclass->base = mmu->func->mem.user; oclass->ctor = nvkm_umem_new; @@ -111,15 +111,17 @@ nvkm_ummu_kind(struct nvkm_ummu *ummu, void *argv, u32 argc) } *args = argv; const u8 *kind = NULL; int ret = -ENOSYS, count = 0; + u8 kind_inv = 0; if (mmu->func->kind) - kind = mmu->func->kind(mmu, &count); + kind = mmu->func->kind(mmu, &count, &kind_inv); if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, true))) { if (argc != args->v0.count * sizeof(*args->v0.data)) return -EINVAL; if (args->v0.count > count) return -EINVAL; + args->v0.kind_inv = kind_inv; memcpy(args->v0.data, kind, args->v0.count); } else return ret; @@ -157,9 +159,10 @@ nvkm_ummu_new(struct nvkm_device *device, const struct nvkm_oclass *oclass, struct nvkm_mmu *mmu = device->mmu; struct nvkm_ummu *ummu; int ret = -ENOSYS, kinds = 0; + u8 unused = 0; if (mmu->func->kind) - mmu->func->kind(mmu, &kinds); + mmu->func->kind(mmu, &kinds, &unused); if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) { args->v0.dmabits = mmu->dma_bits; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c index c43b8248c682..186b4e63e559 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c @@ -45,7 +45,6 @@ nvkm_uvmm_search(struct nvkm_client *client, u64 handle) static int nvkm_uvmm_mthd_pfnclr(struct nvkm_uvmm *uvmm, void *argv, u32 argc) { - struct nvkm_client *client = uvmm->object.client; union { struct nvif_vmm_pfnclr_v0 v0; } *args = argv; @@ -59,9 +58,6 @@ nvkm_uvmm_mthd_pfnclr(struct nvkm_uvmm *uvmm, void *argv, u32 argc) } else return ret; - if (!client->super) - return -ENOENT; - if (size) { mutex_lock(&vmm->mutex); ret = nvkm_vmm_pfn_unmap(vmm, addr, size); @@ -74,7 +70,6 @@ nvkm_uvmm_mthd_pfnclr(struct nvkm_uvmm *uvmm, void *argv, u32 argc) static int nvkm_uvmm_mthd_pfnmap(struct nvkm_uvmm *uvmm, void *argv, u32 argc) { - struct nvkm_client *client = uvmm->object.client; union { struct nvif_vmm_pfnmap_v0 v0; } *args = argv; @@ -93,9 +88,6 @@ nvkm_uvmm_mthd_pfnmap(struct nvkm_uvmm *uvmm, void *argv, u32 argc) } else return ret; - if (!client->super) - return -ENOENT; - if (size) { mutex_lock(&vmm->mutex); ret = nvkm_vmm_pfn_map(vmm, page, addr, size, phys); @@ -108,7 +100,6 @@ nvkm_uvmm_mthd_pfnmap(struct nvkm_uvmm *uvmm, void *argv, u32 argc) static int nvkm_uvmm_mthd_unmap(struct nvkm_uvmm *uvmm, void *argv, u32 argc) { - struct nvkm_client *client = uvmm->object.client; union { struct nvif_vmm_unmap_v0 v0; } *args = argv; @@ -130,9 +121,8 @@ nvkm_uvmm_mthd_unmap(struct nvkm_uvmm *uvmm, void *argv, u32 argc) goto done; } - if (ret = -ENOENT, (!vma->user && !client->super) || vma->busy) { - VMM_DEBUG(vmm, "denied %016llx: %d %d %d", addr, - vma->user, !client->super, vma->busy); + if (ret = -ENOENT, vma->busy) { + VMM_DEBUG(vmm, "denied %016llx: %d", addr, vma->busy); goto done; } @@ -181,9 +171,8 @@ nvkm_uvmm_mthd_map(struct nvkm_uvmm *uvmm, void *argv, u32 argc) goto fail; } - if (ret = -ENOENT, (!vma->user && !client->super) || vma->busy) { - VMM_DEBUG(vmm, "denied %016llx: %d %d %d", addr, - vma->user, !client->super, vma->busy); + if (ret = -ENOENT, vma->busy) { + VMM_DEBUG(vmm, "denied %016llx: %d", addr, vma->busy); goto fail; } @@ -230,7 +219,6 @@ fail: static int nvkm_uvmm_mthd_put(struct nvkm_uvmm *uvmm, void *argv, u32 argc) { - struct nvkm_client *client = uvmm->object.client; union { struct nvif_vmm_put_v0 v0; } *args = argv; @@ -252,9 +240,8 @@ nvkm_uvmm_mthd_put(struct nvkm_uvmm *uvmm, void *argv, u32 argc) goto done; } - if (ret = -ENOENT, (!vma->user && !client->super) || vma->busy) { - VMM_DEBUG(vmm, "denied %016llx: %d %d %d", addr, - vma->user, !client->super, vma->busy); + if (ret = -ENOENT, vma->busy) { + VMM_DEBUG(vmm, "denied %016llx: %d", addr, vma->busy); goto done; } @@ -268,7 +255,6 @@ done: static int nvkm_uvmm_mthd_get(struct nvkm_uvmm *uvmm, void *argv, u32 argc) { - struct nvkm_client *client = uvmm->object.client; union { struct nvif_vmm_get_v0 v0; } *args = argv; @@ -297,7 +283,6 @@ nvkm_uvmm_mthd_get(struct nvkm_uvmm *uvmm, void *argv, u32 argc) return ret; args->v0.addr = vma->addr; - vma->user = !client->super; return ret; } @@ -314,7 +299,7 @@ nvkm_uvmm_mthd_page(struct nvkm_uvmm *uvmm, void *argv, u32 argc) page = uvmm->vmm->func->page; for (nr = 0; page[nr].shift; nr++); - if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) { + if (!(nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) { if ((index = args->v0.index) >= nr) return -EINVAL; type = page[index].type; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c index 41640e0584ac..8bf00b396ec1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c @@ -580,7 +580,7 @@ nvkm_vmm_iter(struct nvkm_vmm *vmm, const struct nvkm_vmm_page *page, it.pte[it.lvl]++; } } - }; + } nvkm_vmm_flush(&it); return ~0ULL; @@ -774,7 +774,6 @@ nvkm_vma_tail(struct nvkm_vma *vma, u64 tail) new->refd = vma->refd; new->used = vma->used; new->part = vma->part; - new->user = vma->user; new->busy = vma->busy; new->mapped = vma->mapped; list_add(&new->head, &vma->head); @@ -951,7 +950,7 @@ nvkm_vmm_node_split(struct nvkm_vmm *vmm, static void nvkm_vma_dump(struct nvkm_vma *vma) { - printk(KERN_ERR "%016llx %016llx %c%c%c%c%c%c%c%c%c %p\n", + printk(KERN_ERR "%016llx %016llx %c%c%c%c%c%c%c%c %p\n", vma->addr, (u64)vma->size, vma->used ? '-' : 'F', vma->mapref ? 'R' : '-', @@ -959,7 +958,6 @@ nvkm_vma_dump(struct nvkm_vma *vma) vma->page != NVKM_VMA_PAGE_NONE ? '0' + vma->page : '-', vma->refd != NVKM_VMA_PAGE_NONE ? '0' + vma->refd : '-', vma->part ? 'P' : '-', - vma->user ? 'U' : '-', vma->busy ? 'B' : '-', vma->mapped ? 'M' : '-', vma->memory); @@ -1024,13 +1022,12 @@ nvkm_vmm_ctor_managed(struct nvkm_vmm *vmm, u64 addr, u64 size) vma->mapref = true; vma->sparse = false; vma->used = true; - vma->user = true; nvkm_vmm_node_insert(vmm, vma); list_add_tail(&vma->head, &vmm->list); return 0; } -int +static int nvkm_vmm_ctor(const struct nvkm_vmm_func *func, struct nvkm_mmu *mmu, u32 pd_header, bool managed, u64 addr, u64 size, struct lock_class_key *key, const char *name, @@ -1204,7 +1201,6 @@ nvkm_vmm_pfn_unmap(struct nvkm_vmm *vmm, u64 addr, u64 size) /*TODO: * - Avoid PT readback (for dma_unmap etc), this might end up being dealt * with inside HMM, which would be a lot nicer for us to deal with. - * - Multiple page sizes (particularly for huge page support). * - Support for systems without a 4KiB page size. */ int @@ -1220,8 +1216,8 @@ nvkm_vmm_pfn_map(struct nvkm_vmm *vmm, u8 shift, u64 addr, u64 size, u64 *pfn) /* Only support mapping where the page size of the incoming page * array matches a page size available for direct mapping. */ - while (page->shift && page->shift != shift && - page->desc->func->pfn == NULL) + while (page->shift && (page->shift != shift || + page->desc->func->pfn == NULL)) page++; if (!page->shift || !IS_ALIGNED(addr, 1ULL << shift) || @@ -1616,7 +1612,6 @@ nvkm_vmm_put_locked(struct nvkm_vmm *vmm, struct nvkm_vma *vma) vma->page = NVKM_VMA_PAGE_NONE; vma->refd = NVKM_VMA_PAGE_NONE; vma->used = false; - vma->user = false; nvkm_vmm_put_region(vmm, vma); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h index 5e55ecbd8005..f6188aa9171c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h @@ -163,9 +163,6 @@ int nvkm_vmm_new_(const struct nvkm_vmm_func *, struct nvkm_mmu *, u32 pd_header, bool managed, u64 addr, u64 size, struct lock_class_key *, const char *name, struct nvkm_vmm **); -int nvkm_vmm_ctor(const struct nvkm_vmm_func *, struct nvkm_mmu *, - u32 pd_header, bool managed, u64 addr, u64 size, - struct lock_class_key *, const char *name, struct nvkm_vmm *); struct nvkm_vma *nvkm_vmm_node_search(struct nvkm_vmm *, u64 addr); struct nvkm_vma *nvkm_vmm_node_split(struct nvkm_vmm *, struct nvkm_vma *, u64 addr, u64 size); @@ -181,6 +178,7 @@ void nvkm_vmm_unmap_region(struct nvkm_vmm *, struct nvkm_vma *); #define NVKM_VMM_PFN_APER 0x00000000000000f0ULL #define NVKM_VMM_PFN_HOST 0x0000000000000000ULL #define NVKM_VMM_PFN_VRAM 0x0000000000000010ULL +#define NVKM_VMM_PFN_A 0x0000000000000004ULL #define NVKM_VMM_PFN_W 0x0000000000000002ULL #define NVKM_VMM_PFN_V 0x0000000000000001ULL #define NVKM_VMM_PFN_NONE 0x0000000000000000ULL @@ -304,7 +302,7 @@ int tu102_vmm_new(struct nvkm_mmu *, bool, u64, u64, void *, u32, FILL(VMM, PT, PTEI, _ptes, MAP, _addr); \ PTEI += _ptes; \ PTEN -= _ptes; \ - }; \ + } \ nvkm_done((PT)->memory); \ } while(0) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c index ab6424faf84c..5438384d9a67 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c @@ -187,12 +187,11 @@ gf100_vmm_invalidate_pdb(struct nvkm_vmm *vmm, u64 addr) void gf100_vmm_invalidate(struct nvkm_vmm *vmm, u32 type) { - struct nvkm_subdev *subdev = &vmm->mmu->subdev; - struct nvkm_device *device = subdev->device; + struct nvkm_device *device = vmm->mmu->subdev.device; struct nvkm_mmu_pt *pd = vmm->pd->pt[0]; u64 addr = 0; - mutex_lock(&subdev->mutex); + mutex_lock(&vmm->mmu->mutex); /* Looks like maybe a "free flush slots" counter, the * faster you write to 0x100cbc to more it decreases. */ @@ -222,7 +221,7 @@ gf100_vmm_invalidate(struct nvkm_vmm *vmm, u32 type) if (nvkm_rd32(device, 0x100c80) & 0x00008000) break; ); - mutex_unlock(&subdev->mutex); + mutex_unlock(&vmm->mmu->mutex); } void @@ -247,7 +246,7 @@ gf100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc, } *args = argv; struct nvkm_device *device = vmm->mmu->subdev.device; struct nvkm_memory *memory = map->memory; - u8 kind, priv, ro, vol; + u8 kind, kind_inv, priv, ro, vol; int kindn, aper, ret = -ENOSYS; const u8 *kindm; @@ -274,8 +273,8 @@ gf100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc, if (WARN_ON(aper < 0)) return aper; - kindm = vmm->mmu->func->kind(vmm->mmu, &kindn); - if (kind >= kindn || kindm[kind] == 0xff) { + kindm = vmm->mmu->func->kind(vmm->mmu, &kindn, &kind_inv); + if (kind >= kindn || kindm[kind] == kind_inv) { VMM_DEBUG(vmm, "kind %02x", kind); return -EINVAL; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c index b4f519768d5e..17899fc95b2d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c @@ -79,11 +79,18 @@ gp100_vmm_pgt_pfn(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt, dma_addr_t addr; nvkm_kmap(pt->memory); - while (ptes--) { + for (; ptes; ptes--, map->pfn++) { u64 data = 0; + + if (!(*map->pfn & NVKM_VMM_PFN_V)) + continue; + if (!(*map->pfn & NVKM_VMM_PFN_W)) data |= BIT_ULL(6); /* RO. */ + if (!(*map->pfn & NVKM_VMM_PFN_A)) + data |= BIT_ULL(7); /* Atomic disable. */ + if (!(*map->pfn & NVKM_VMM_PFN_VRAM)) { addr = *map->pfn >> NVKM_VMM_PFN_ADDR_SHIFT; addr = dma_map_page(dev, pfn_to_page(addr), 0, @@ -100,7 +107,6 @@ gp100_vmm_pgt_pfn(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt, } VMM_WO064(pt, vmm, ptei++ * 8, data); - map->pfn++; } nvkm_done(pt->memory); } @@ -258,12 +264,99 @@ gp100_vmm_pd0_unmap(struct nvkm_vmm *vmm, VMM_FO128(pt, vmm, pdei * 0x10, 0ULL, 0ULL, pdes); } +static void +gp100_vmm_pd0_pfn_unmap(struct nvkm_vmm *vmm, + struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes) +{ + struct device *dev = vmm->mmu->subdev.device->dev; + dma_addr_t addr; + + nvkm_kmap(pt->memory); + while (ptes--) { + u32 datalo = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 0); + u32 datahi = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 4); + u64 data = (u64)datahi << 32 | datalo; + + if ((data & (3ULL << 1)) != 0) { + addr = (data >> 8) << 12; + dma_unmap_page(dev, addr, 1UL << 21, DMA_BIDIRECTIONAL); + } + ptei++; + } + nvkm_done(pt->memory); +} + +static bool +gp100_vmm_pd0_pfn_clear(struct nvkm_vmm *vmm, + struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes) +{ + bool dma = false; + + nvkm_kmap(pt->memory); + while (ptes--) { + u32 datalo = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 0); + u32 datahi = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 4); + u64 data = (u64)datahi << 32 | datalo; + + if ((data & BIT_ULL(0)) && (data & (3ULL << 1)) != 0) { + VMM_WO064(pt, vmm, ptei * 16, data & ~BIT_ULL(0)); + dma = true; + } + ptei++; + } + nvkm_done(pt->memory); + return dma; +} + +static void +gp100_vmm_pd0_pfn(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt, + u32 ptei, u32 ptes, struct nvkm_vmm_map *map) +{ + struct device *dev = vmm->mmu->subdev.device->dev; + dma_addr_t addr; + + nvkm_kmap(pt->memory); + for (; ptes; ptes--, map->pfn++) { + u64 data = 0; + + if (!(*map->pfn & NVKM_VMM_PFN_V)) + continue; + + if (!(*map->pfn & NVKM_VMM_PFN_W)) + data |= BIT_ULL(6); /* RO. */ + + if (!(*map->pfn & NVKM_VMM_PFN_A)) + data |= BIT_ULL(7); /* Atomic disable. */ + + if (!(*map->pfn & NVKM_VMM_PFN_VRAM)) { + addr = *map->pfn >> NVKM_VMM_PFN_ADDR_SHIFT; + addr = dma_map_page(dev, pfn_to_page(addr), 0, + 1UL << 21, DMA_BIDIRECTIONAL); + if (!WARN_ON(dma_mapping_error(dev, addr))) { + data |= addr >> 4; + data |= 2ULL << 1; /* SYSTEM_COHERENT_MEMORY. */ + data |= BIT_ULL(3); /* VOL. */ + data |= BIT_ULL(0); /* VALID. */ + } + } else { + data |= (*map->pfn & NVKM_VMM_PFN_ADDR) >> 4; + data |= BIT_ULL(0); /* VALID. */ + } + + VMM_WO064(pt, vmm, ptei++ * 16, data); + } + nvkm_done(pt->memory); +} + static const struct nvkm_vmm_desc_func gp100_vmm_desc_pd0 = { .unmap = gp100_vmm_pd0_unmap, .sparse = gp100_vmm_pd0_sparse, .pde = gp100_vmm_pd0_pde, .mem = gp100_vmm_pd0_mem, + .pfn = gp100_vmm_pd0_pfn, + .pfn_clear = gp100_vmm_pd0_pfn_clear, + .pfn_unmap = gp100_vmm_pd0_pfn_unmap, }; static void @@ -320,7 +413,7 @@ gp100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc, } *args = argv; struct nvkm_device *device = vmm->mmu->subdev.device; struct nvkm_memory *memory = map->memory; - u8 kind, priv, ro, vol; + u8 kind, kind_inv, priv, ro, vol; int kindn, aper, ret = -ENOSYS; const u8 *kindm; @@ -347,8 +440,8 @@ gp100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc, if (WARN_ON(aper < 0)) return aper; - kindm = vmm->mmu->func->kind(vmm->mmu, &kindn); - if (kind >= kindn || kindm[kind] == 0xff) { + kindm = vmm->mmu->func->kind(vmm->mmu, &kindn, &kind_inv); + if (kind >= kindn || kindm[kind] == kind_inv) { VMM_DEBUG(vmm, "kind %02x", kind); return -EINVAL; } @@ -395,7 +488,7 @@ gp100_vmm_fault_cancel(struct nvkm_vmm *vmm, void *argv, u32 argc) struct gp100_vmm_fault_cancel_v0 v0; } *args = argv; int ret = -ENOSYS; - u32 inst, aper; + u32 aper; if ((ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) return ret; @@ -409,7 +502,7 @@ gp100_vmm_fault_cancel(struct nvkm_vmm *vmm, void *argv, u32 argc) args->v0.inst |= 0x80000000; if (!WARN_ON(nvkm_gr_ctxsw_pause(device))) { - if ((inst = nvkm_gr_ctxsw_inst(device)) == args->v0.inst) { + if (nvkm_gr_ctxsw_inst(device) == args->v0.inst) { gf100_vmm_invalidate(vmm, 0x0000001b /* CANCEL_TARGETED. */ | (args->v0.hub << 20) | @@ -441,15 +534,13 @@ int gp100_vmm_mthd(struct nvkm_vmm *vmm, struct nvkm_client *client, u32 mthd, void *argv, u32 argc) { - if (client->super) { - switch (mthd) { - case GP100_VMM_VN_FAULT_REPLAY: - return gp100_vmm_fault_replay(vmm, argv, argc); - case GP100_VMM_VN_FAULT_CANCEL: - return gp100_vmm_fault_cancel(vmm, argv, argc); - default: - break; - } + switch (mthd) { + case GP100_VMM_VN_FAULT_REPLAY: + return gp100_vmm_fault_replay(vmm, argv, argc); + case GP100_VMM_VN_FAULT_CANCEL: + return gp100_vmm_fault_cancel(vmm, argv, argc); + default: + break; } return -EINVAL; } @@ -466,7 +557,6 @@ void gp100_vmm_flush(struct nvkm_vmm *vmm, int depth) { u32 type = (5 /* CACHE_LEVEL_UP_TO_PDE3 */ - depth) << 24; - type = 0; /*XXX: need to confirm stuff works with depth enabled... */ if (atomic_read(&vmm->engref[NVKM_SUBDEV_BAR])) type |= 0x00000004; /* HUB_ONLY */ type |= 0x00000001; /* PAGE_ALL */ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c index 1d3369683a21..31984671daf8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c @@ -80,17 +80,16 @@ nv41_vmm_desc_12[] = { static void nv41_vmm_flush(struct nvkm_vmm *vmm, int level) { - struct nvkm_subdev *subdev = &vmm->mmu->subdev; - struct nvkm_device *device = subdev->device; + struct nvkm_device *device = vmm->mmu->subdev.device; - mutex_lock(&subdev->mutex); + mutex_lock(&vmm->mmu->mutex); nvkm_wr32(device, 0x100810, 0x00000022); nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x100810) & 0x00000020) break; ); nvkm_wr32(device, 0x100810, 0x00000000); - mutex_unlock(&subdev->mutex); + mutex_unlock(&vmm->mmu->mutex); } static const struct nvkm_vmm_func diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c index c98afe3134ee..b7548dcd72c7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c @@ -184,7 +184,7 @@ nv50_vmm_flush(struct nvkm_vmm *vmm, int level) struct nvkm_device *device = subdev->device; int i, id; - mutex_lock(&subdev->mutex); + mutex_lock(&vmm->mmu->mutex); for (i = 0; i < NVKM_SUBDEV_NR; i++) { if (!atomic_read(&vmm->engref[i])) continue; @@ -207,7 +207,7 @@ nv50_vmm_flush(struct nvkm_vmm *vmm, int level) case NVKM_ENGINE_MSVLD : id = 0x09; break; case NVKM_ENGINE_CIPHER: case NVKM_ENGINE_SEC : id = 0x0a; break; - case NVKM_ENGINE_CE0 : id = 0x0d; break; + case NVKM_ENGINE_CE : id = 0x0d; break; default: continue; } @@ -217,10 +217,9 @@ nv50_vmm_flush(struct nvkm_vmm *vmm, int level) if (!(nvkm_rd32(device, 0x100c80) & 0x00000001)) break; ) < 0) - nvkm_error(subdev, "%s mmu invalidate timeout\n", - nvkm_subdev_name[i]); + nvkm_error(subdev, "%s mmu invalidate timeout\n", nvkm_subdev_type[i]); } - mutex_unlock(&subdev->mutex); + mutex_unlock(&vmm->mmu->mutex); } int @@ -235,7 +234,7 @@ nv50_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc, struct nvkm_device *device = vmm->mmu->subdev.device; struct nvkm_ram *ram = device->fb->ram; struct nvkm_memory *memory = map->memory; - u8 aper, kind, comp, priv, ro; + u8 aper, kind, kind_inv, comp, priv, ro; int kindn, ret = -ENOSYS; const u8 *kindm; @@ -278,8 +277,8 @@ nv50_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc, return -EINVAL; } - kindm = vmm->mmu->func->kind(vmm->mmu, &kindn); - if (kind >= kindn || kindm[kind] == 0x7f) { + kindm = vmm->mmu->func->kind(vmm->mmu, &kindn, &kind_inv); + if (kind >= kindn || kindm[kind] == kind_inv) { VMM_DEBUG(vmm, "kind %02x", kind); return -EINVAL; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c index be91cffc3b52..6cb5eefa45e9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c @@ -26,15 +26,14 @@ static void tu102_vmm_flush(struct nvkm_vmm *vmm, int depth) { - struct nvkm_subdev *subdev = &vmm->mmu->subdev; - struct nvkm_device *device = subdev->device; - u32 type = depth << 24; /*XXX: not confirmed */ + struct nvkm_device *device = vmm->mmu->subdev.device; + u32 type = (5 /* CACHE_LEVEL_UP_TO_PDE3 */ - depth) << 24; - type = 0x00000001; /* PAGE_ALL */ + type |= 0x00000001; /* PAGE_ALL */ if (atomic_read(&vmm->engref[NVKM_SUBDEV_BAR])) type |= 0x00000004; /* HUB_ONLY */ - mutex_lock(&subdev->mutex); + mutex_lock(&vmm->mmu->mutex); nvkm_wr32(device, 0xb830a0, vmm->pd->pt[0]->addr >> 8); nvkm_wr32(device, 0xb830a4, 0x00000000); @@ -46,7 +45,7 @@ tu102_vmm_flush(struct nvkm_vmm *vmm, int depth) break; ); - mutex_unlock(&subdev->mutex); + mutex_unlock(&vmm->mmu->mutex); } static const struct nvkm_vmm_func diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c index f44682d62f75..c1acfe642da3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c @@ -230,7 +230,8 @@ nvkm_mxm = { }; int -nvkm_mxm_new_(struct nvkm_device *device, int index, struct nvkm_mxm **pmxm) +nvkm_mxm_new_(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mxm **pmxm) { struct nvkm_bios *bios = device->bios; struct nvkm_mxm *mxm; @@ -240,7 +241,7 @@ nvkm_mxm_new_(struct nvkm_device *device, int index, struct nvkm_mxm **pmxm) if (!(mxm = *pmxm = kzalloc(sizeof(*mxm), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_mxm, device, index, &mxm->subdev); + nvkm_subdev_ctor(&nvkm_mxm, device, type, inst, &mxm->subdev); data = mxm_table(bios, &ver, &len); if (!data || !(ver = nvbios_rd08(bios, data))) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c index 2a6150ab5611..f3167904dcb0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c @@ -159,7 +159,7 @@ mxm_dcb_sanitise_entry(struct nvkm_bios *bios, void *data, int idx, u16 pdcb) break; case 0x0e: /* eDP, falls through to DPint */ ctx.outp[1] |= 0x00010000; - /* fall through */ + fallthrough; case 0x07: /* DP internal, wtf is this?? HP8670w */ ctx.outp[1] |= 0x00000004; /* use_power_scripts? */ type = DCB_CONNECTOR_eDP; @@ -201,12 +201,13 @@ mxm_dcb_sanitise(struct nvkm_mxm *mxm) } int -nv50_mxm_new(struct nvkm_device *device, int index, struct nvkm_subdev **pmxm) +nv50_mxm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pmxm) { struct nvkm_mxm *mxm; int ret; - ret = nvkm_mxm_new_(device, index, &mxm); + ret = nvkm_mxm_new_(device, type, inst, &mxm); if (mxm) *pmxm = &mxm->subdev; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h index fc8f69e6fc64..fcacb6c6a7f7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h @@ -12,5 +12,5 @@ struct nvkm_mxm { u8 *mxms; }; -int nvkm_mxm_new_(struct nvkm_device *, int index, struct nvkm_mxm **); +int nvkm_mxm_new_(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_mxm **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c index ee2431a7804e..a7d42ea8ba28 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c @@ -183,13 +183,13 @@ nvkm_pci_func = { int nvkm_pci_new_(const struct nvkm_pci_func *func, struct nvkm_device *device, - int index, struct nvkm_pci **ppci) + enum nvkm_subdev_type type, int inst, struct nvkm_pci **ppci) { struct nvkm_pci *pci; if (!(pci = *ppci = kzalloc(sizeof(**ppci), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_pci_func, device, index, &pci->subdev); + nvkm_subdev_ctor(&nvkm_pci_func, device, type, inst, &pci->subdev); pci->func = func; pci->pdev = device->func->pci(device)->pdev; pci->irq = -1; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c index 62438d892f42..5b29aacedef3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c @@ -150,7 +150,8 @@ g84_pci_func = { }; int -g84_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +g84_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&g84_pci_func, device, index, ppci); + return nvkm_pci_new_(&g84_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c index 48874359d5f6..a9e0674009c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c @@ -51,7 +51,8 @@ g92_pci_func = { }; int -g92_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +g92_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&g92_pci_func, device, index, ppci); + return nvkm_pci_new_(&g92_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c index 09adb37a5664..7bacd0693283 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c @@ -43,7 +43,8 @@ g94_pci_func = { }; int -g94_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +g94_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&g94_pci_func, device, index, ppci); + return nvkm_pci_new_(&g94_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c index 00a5e7d3ee9d..099906092fe1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c @@ -96,7 +96,8 @@ gf100_pci_func = { }; int -gf100_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +gf100_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&gf100_pci_func, device, index, ppci); + return nvkm_pci_new_(&gf100_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c index 11bf419afe3f..bcde609ba866 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c @@ -43,7 +43,8 @@ gf106_pci_func = { }; int -gf106_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +gf106_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&gf106_pci_func, device, index, ppci); + return nvkm_pci_new_(&gf106_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c index e68030507d88..6be87ecffc89 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c @@ -222,7 +222,8 @@ gk104_pci_func = { }; int -gk104_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +gk104_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&gk104_pci_func, device, index, ppci); + return nvkm_pci_new_(&gk104_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.c index 82c5234a06ff..a5fafda0014d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.c @@ -38,7 +38,8 @@ gp100_pci_func = { }; int -gp100_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +gp100_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&gp100_pci_func, device, index, ppci); + return nvkm_pci_new_(&gp100_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.c index 5b1ed42cb90b..9ab64194b185 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.c @@ -52,7 +52,8 @@ nv04_pci_func = { }; int -nv04_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +nv04_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&nv04_pci_func, device, index, ppci); + return nvkm_pci_new_(&nv04_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c index 6eb417765802..6a3c31cf0200 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c @@ -59,7 +59,8 @@ nv40_pci_func = { }; int -nv40_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +nv40_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&nv40_pci_func, device, index, ppci); + return nvkm_pci_new_(&nv40_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c index fc617e4c0ab6..9cad17f178ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c @@ -45,7 +45,8 @@ nv46_pci_func = { }; int -nv46_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +nv46_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&nv46_pci_func, device, index, ppci); + return nvkm_pci_new_(&nv46_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.c index 1f1b26b5fa72..741e34bf307c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.c @@ -31,7 +31,8 @@ nv4c_pci_func = { }; int -nv4c_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +nv4c_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&nv4c_pci_func, device, index, ppci); + return nvkm_pci_new_(&nv4c_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h index 7009aad86b6e..9b7583532962 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h @@ -4,8 +4,8 @@ #define nvkm_pci(p) container_of((p), struct nvkm_pci, subdev) #include <subdev/pci.h> -int nvkm_pci_new_(const struct nvkm_pci_func *, struct nvkm_device *, - int index, struct nvkm_pci **); +int nvkm_pci_new_(const struct nvkm_pci_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_pci **); struct nvkm_pci_func { void (*init)(struct nvkm_pci *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild index e37b6e45eaa2..eafc9321a08a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild @@ -9,6 +9,7 @@ nvkm-y += nvkm/subdev/pmu/gk110.o nvkm-y += nvkm/subdev/pmu/gk208.o nvkm-y += nvkm/subdev/pmu/gk20a.o nvkm-y += nvkm/subdev/pmu/gm107.o +nvkm-y += nvkm/subdev/pmu/gm200.o nvkm-y += nvkm/subdev/pmu/gm20b.o -nvkm-y += nvkm/subdev/pmu/gp100.o nvkm-y += nvkm/subdev/pmu/gp102.o +nvkm-y += nvkm/subdev/pmu/gp10b.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c index ce70a193caa7..455e95a89259 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c @@ -23,9 +23,27 @@ */ #include "priv.h" -#include <core/msgqueue.h> +#include <core/firmware.h> #include <subdev/timer.h> +bool +nvkm_pmu_fan_controlled(struct nvkm_device *device) +{ + struct nvkm_pmu *pmu = device->pmu; + + /* Internal PMU FW does not currently control fans in any way, + * allow SW control of fans instead. + */ + if (pmu && pmu->func->code.size) + return false; + + /* Default (board-loaded, or VBIOS PMU/PREOS) PMU FW on Fermi + * and newer automatically control the fan speed, which would + * interfere with SW control. + */ + return (device->chipset >= 0xc0); +} + void nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable) { @@ -67,23 +85,22 @@ nvkm_pmu_fini(struct nvkm_subdev *subdev, bool suspend) pmu->func->fini(pmu); flush_work(&pmu->recv.work); + + reinit_completion(&pmu->wpr_ready); + + nvkm_falcon_cmdq_fini(pmu->lpq); + nvkm_falcon_cmdq_fini(pmu->hpq); + pmu->initmsg_received = false; return 0; } -static int +static void nvkm_pmu_reset(struct nvkm_pmu *pmu) { struct nvkm_device *device = pmu->subdev.device; if (!pmu->func->enabled(pmu)) - return 0; - - /* Inhibit interrupts, and wait for idle. */ - nvkm_wr32(device, 0x10a014, 0x0000ffff); - nvkm_msec(device, 2000, - if (!nvkm_rd32(device, 0x10a04c)) - break; - ); + return; /* Reset. */ if (pmu->func->reset) @@ -94,40 +111,49 @@ nvkm_pmu_reset(struct nvkm_pmu *pmu) if (!(nvkm_rd32(device, 0x10a10c) & 0x00000006)) break; ); - - return 0; } static int nvkm_pmu_preinit(struct nvkm_subdev *subdev) { struct nvkm_pmu *pmu = nvkm_pmu(subdev); - return nvkm_pmu_reset(pmu); + nvkm_pmu_reset(pmu); + return 0; } static int nvkm_pmu_init(struct nvkm_subdev *subdev) { struct nvkm_pmu *pmu = nvkm_pmu(subdev); - int ret = nvkm_pmu_reset(pmu); - if (ret == 0 && pmu->func->init) - ret = pmu->func->init(pmu); - return ret; -} + struct nvkm_device *device = pmu->subdev.device; -static int -nvkm_pmu_oneinit(struct nvkm_subdev *subdev) -{ - struct nvkm_pmu *pmu = nvkm_pmu(subdev); - return nvkm_falcon_v1_new(&pmu->subdev, "PMU", 0x10a000, &pmu->falcon); + if (!pmu->func->init) + return 0; + + if (pmu->func->enabled(pmu)) { + /* Inhibit interrupts, and wait for idle. */ + nvkm_wr32(device, 0x10a014, 0x0000ffff); + nvkm_msec(device, 2000, + if (!nvkm_rd32(device, 0x10a04c)) + break; + ); + + nvkm_pmu_reset(pmu); + } + + return pmu->func->init(pmu); } static void * nvkm_pmu_dtor(struct nvkm_subdev *subdev) { struct nvkm_pmu *pmu = nvkm_pmu(subdev); - nvkm_msgqueue_del(&pmu->queue); - nvkm_falcon_del(&pmu->falcon); + nvkm_falcon_msgq_del(&pmu->msgq); + nvkm_falcon_cmdq_del(&pmu->lpq); + nvkm_falcon_cmdq_del(&pmu->hpq); + nvkm_falcon_qmgr_del(&pmu->qmgr); + nvkm_falcon_dtor(&pmu->falcon); + mutex_destroy(&pmu->send.mutex); return nvkm_pmu(subdev); } @@ -135,29 +161,51 @@ static const struct nvkm_subdev_func nvkm_pmu = { .dtor = nvkm_pmu_dtor, .preinit = nvkm_pmu_preinit, - .oneinit = nvkm_pmu_oneinit, .init = nvkm_pmu_init, .fini = nvkm_pmu_fini, .intr = nvkm_pmu_intr, }; int -nvkm_pmu_ctor(const struct nvkm_pmu_func *func, struct nvkm_device *device, - int index, struct nvkm_pmu *pmu) +nvkm_pmu_ctor(const struct nvkm_pmu_fwif *fwif, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_pmu *pmu) { - nvkm_subdev_ctor(&nvkm_pmu, device, index, &pmu->subdev); - pmu->func = func; + int ret; + + nvkm_subdev_ctor(&nvkm_pmu, device, type, inst, &pmu->subdev); + + mutex_init(&pmu->send.mutex); + INIT_WORK(&pmu->recv.work, nvkm_pmu_recv); init_waitqueue_head(&pmu->recv.wait); + + fwif = nvkm_firmware_load(&pmu->subdev, fwif, "Pmu", pmu); + if (IS_ERR(fwif)) + return PTR_ERR(fwif); + + pmu->func = fwif->func; + + ret = nvkm_falcon_ctor(pmu->func->flcn, &pmu->subdev, pmu->subdev.name, + 0x10a000, &pmu->falcon); + if (ret) + return ret; + + if ((ret = nvkm_falcon_qmgr_new(&pmu->falcon, &pmu->qmgr)) || + (ret = nvkm_falcon_cmdq_new(pmu->qmgr, "hpq", &pmu->hpq)) || + (ret = nvkm_falcon_cmdq_new(pmu->qmgr, "lpq", &pmu->lpq)) || + (ret = nvkm_falcon_msgq_new(pmu->qmgr, "msgq", &pmu->msgq))) + return ret; + + init_completion(&pmu->wpr_ready); return 0; } int -nvkm_pmu_new_(const struct nvkm_pmu_func *func, struct nvkm_device *device, - int index, struct nvkm_pmu **ppmu) +nvkm_pmu_new_(const struct nvkm_pmu_fwif *fwif, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_pmu **ppmu) { struct nvkm_pmu *pmu; if (!(pmu = *ppmu = kzalloc(sizeof(*pmu), GFP_KERNEL))) return -ENOMEM; - return nvkm_pmu_ctor(func, device, index, *ppmu); + return nvkm_pmu_ctor(fwif, device, type, inst, *ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c index 0b458656e870..f725a3ec5479 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c @@ -30,18 +30,19 @@ void gf100_pmu_reset(struct nvkm_pmu *pmu) { struct nvkm_device *device = pmu->subdev.device; - nvkm_mc_disable(device, NVKM_SUBDEV_PMU); - nvkm_mc_enable(device, NVKM_SUBDEV_PMU); + nvkm_mc_disable(device, NVKM_SUBDEV_PMU, 0); + nvkm_mc_enable(device, NVKM_SUBDEV_PMU, 0); } bool gf100_pmu_enabled(struct nvkm_pmu *pmu) { - return nvkm_mc_enabled(pmu->subdev.device, NVKM_SUBDEV_PMU); + return nvkm_mc_enabled(pmu->subdev.device, NVKM_SUBDEV_PMU, 0); } static const struct nvkm_pmu_func gf100_pmu = { + .flcn = >215_pmu_flcn, .code.data = gf100_pmu_code, .code.size = sizeof(gf100_pmu_code), .data.data = gf100_pmu_data, @@ -56,7 +57,20 @@ gf100_pmu = { }; int -gf100_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gf100_pmu_nofw(struct nvkm_pmu *pmu, int ver, const struct nvkm_pmu_fwif *fwif) { - return nvkm_pmu_new_(&gf100_pmu, device, index, ppmu); + return 0; +} + +static const struct nvkm_pmu_fwif +gf100_pmu_fwif[] = { + { -1, gf100_pmu_nofw, &gf100_pmu }, + {} +}; + +int +gf100_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) +{ + return nvkm_pmu_new_(gf100_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c index 3dfa79d4fb13..0f4b6697a4e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c @@ -26,6 +26,7 @@ static const struct nvkm_pmu_func gf119_pmu = { + .flcn = >215_pmu_flcn, .code.data = gf119_pmu_code, .code.size = sizeof(gf119_pmu_code), .data.data = gf119_pmu_data, @@ -39,8 +40,15 @@ gf119_pmu = { .recv = gt215_pmu_recv, }; +static const struct nvkm_pmu_fwif +gf119_pmu_fwif[] = { + { -1, gf100_pmu_nofw, &gf119_pmu }, + {} +}; + int -gf119_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gf119_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(&gf119_pmu, device, index, ppmu); + return nvkm_pmu_new_(gf119_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c index 8f7ec10fd2a4..9e7631d7aa41 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c @@ -105,6 +105,7 @@ gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable) static const struct nvkm_pmu_func gk104_pmu = { + .flcn = >215_pmu_flcn, .code.data = gk104_pmu_code, .code.size = sizeof(gk104_pmu_code), .data.data = gk104_pmu_data, @@ -119,8 +120,15 @@ gk104_pmu = { .pgob = gk104_pmu_pgob, }; +static const struct nvkm_pmu_fwif +gk104_pmu_fwif[] = { + { -1, gf100_pmu_nofw, &gk104_pmu }, + {} +}; + int -gk104_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gk104_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(&gk104_pmu, device, index, ppmu); + return nvkm_pmu_new_(gk104_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c index 345741d55a56..dbaefee53e1f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c @@ -84,6 +84,7 @@ gk110_pmu_pgob(struct nvkm_pmu *pmu, bool enable) static const struct nvkm_pmu_func gk110_pmu = { + .flcn = >215_pmu_flcn, .code.data = gk110_pmu_code, .code.size = sizeof(gk110_pmu_code), .data.data = gk110_pmu_data, @@ -98,8 +99,15 @@ gk110_pmu = { .pgob = gk110_pmu_pgob, }; +static const struct nvkm_pmu_fwif +gk110_pmu_fwif[] = { + { -1, gf100_pmu_nofw, &gk110_pmu }, + {} +}; + int -gk110_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gk110_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(&gk110_pmu, device, index, ppmu); + return nvkm_pmu_new_(gk110_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c index e4acf7876ea1..a08fb049e6d6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c @@ -26,6 +26,7 @@ static const struct nvkm_pmu_func gk208_pmu = { + .flcn = >215_pmu_flcn, .code.data = gk208_pmu_code, .code.size = sizeof(gk208_pmu_code), .data.data = gk208_pmu_data, @@ -40,8 +41,15 @@ gk208_pmu = { .pgob = gk110_pmu_pgob, }; +static const struct nvkm_pmu_fwif +gk208_pmu_fwif[] = { + { -1, gf100_pmu_nofw, &gk208_pmu }, + {} +}; + int -gk208_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gk208_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(&gk208_pmu, device, index, ppmu); + return nvkm_pmu_new_(gk208_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c index 05e81855c367..a67a42e73f08 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c @@ -95,7 +95,7 @@ static void gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu *pmu, struct gk20a_pmu_dvfs_dev_status *status) { - struct nvkm_falcon *falcon = pmu->base.falcon; + struct nvkm_falcon *falcon = &pmu->base.falcon; status->busy = nvkm_falcon_rd32(falcon, 0x508 + (BUSY_SLOT * 0x10)); status->total= nvkm_falcon_rd32(falcon, 0x508 + (CLK_SLOT * 0x10)); @@ -104,7 +104,7 @@ gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu *pmu, static void gk20a_pmu_dvfs_reset_dev_status(struct gk20a_pmu *pmu) { - struct nvkm_falcon *falcon = pmu->base.falcon; + struct nvkm_falcon *falcon = &pmu->base.falcon; nvkm_falcon_wr32(falcon, 0x508 + (BUSY_SLOT * 0x10), 0x80000000); nvkm_falcon_wr32(falcon, 0x508 + (CLK_SLOT * 0x10), 0x80000000); @@ -160,7 +160,7 @@ gk20a_pmu_fini(struct nvkm_pmu *pmu) struct gk20a_pmu *gpmu = gk20a_pmu(pmu); nvkm_timer_alarm(pmu->subdev.device->timer, 0, &gpmu->alarm); - nvkm_falcon_put(pmu->falcon, &pmu->subdev); + nvkm_falcon_put(&pmu->falcon, &pmu->subdev); } static int @@ -169,7 +169,7 @@ gk20a_pmu_init(struct nvkm_pmu *pmu) struct gk20a_pmu *gpmu = gk20a_pmu(pmu); struct nvkm_subdev *subdev = &pmu->subdev; struct nvkm_device *device = pmu->subdev.device; - struct nvkm_falcon *falcon = pmu->falcon; + struct nvkm_falcon *falcon = &pmu->falcon; int ret; ret = nvkm_falcon_get(falcon, subdev); @@ -196,25 +196,35 @@ gk20a_dvfs_data= { static const struct nvkm_pmu_func gk20a_pmu = { + .flcn = >215_pmu_flcn, .enabled = gf100_pmu_enabled, .init = gk20a_pmu_init, .fini = gk20a_pmu_fini, .reset = gf100_pmu_reset, }; +static const struct nvkm_pmu_fwif +gk20a_pmu_fwif[] = { + { -1, gf100_pmu_nofw, &gk20a_pmu }, + {} +}; + int -gk20a_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gk20a_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { struct gk20a_pmu *pmu; + int ret; if (!(pmu = kzalloc(sizeof(*pmu), GFP_KERNEL))) return -ENOMEM; *ppmu = &pmu->base; - nvkm_pmu_ctor(&gk20a_pmu, device, index, &pmu->base); + ret = nvkm_pmu_ctor(gk20a_pmu_fwif, device, type, inst, &pmu->base); + if (ret) + return ret; pmu->data = &gk20a_dvfs_data; nvkm_alarm_init(&pmu->alarm, gk20a_pmu_dvfs_work); - return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c index 459df1ef9e70..622ee637f97b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c @@ -28,6 +28,7 @@ static const struct nvkm_pmu_func gm107_pmu = { + .flcn = >215_pmu_flcn, .code.data = gm107_pmu_code, .code.size = sizeof(gm107_pmu_code), .data.data = gm107_pmu_data, @@ -41,8 +42,15 @@ gm107_pmu = { .recv = gt215_pmu_recv, }; +static const struct nvkm_pmu_fwif +gm107_pmu_fwif[] = { + { -1, gf100_pmu_nofw, &gm107_pmu }, + {} +}; + int -gm107_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gm107_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(&gm107_pmu, device, index, ppmu); + return nvkm_pmu_new_(gm107_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c new file mode 100644 index 000000000000..40439e329aa9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c @@ -0,0 +1,81 @@ +/* + * Copyright 2016 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ +#include "priv.h" + +static int +gm200_pmu_flcn_reset(struct nvkm_falcon *falcon) +{ + struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon); + + nvkm_falcon_wr32(falcon, 0x014, 0x0000ffff); + pmu->func->reset(pmu); + return nvkm_falcon_enable(falcon); +} + +const struct nvkm_falcon_func +gm200_pmu_flcn = { + .debug = 0xc08, + .fbif = 0xe00, + .load_imem = nvkm_falcon_v1_load_imem, + .load_dmem = nvkm_falcon_v1_load_dmem, + .read_dmem = nvkm_falcon_v1_read_dmem, + .bind_context = nvkm_falcon_v1_bind_context, + .wait_for_halt = nvkm_falcon_v1_wait_for_halt, + .clear_interrupt = nvkm_falcon_v1_clear_interrupt, + .set_start_addr = nvkm_falcon_v1_set_start_addr, + .start = nvkm_falcon_v1_start, + .enable = nvkm_falcon_v1_enable, + .disable = nvkm_falcon_v1_disable, + .reset = gm200_pmu_flcn_reset, + .cmdq = { 0x4a0, 0x4b0, 4 }, + .msgq = { 0x4c8, 0x4cc, 0 }, +}; + +static const struct nvkm_pmu_func +gm200_pmu = { + .flcn = &gm200_pmu_flcn, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, +}; + + +int +gm200_pmu_nofw(struct nvkm_pmu *pmu, int ver, const struct nvkm_pmu_fwif *fwif) +{ + nvkm_warn(&pmu->subdev, "firmware unavailable\n"); + return 0; +} + +static const struct nvkm_pmu_fwif +gm200_pmu_fwif[] = { + { -1, gm200_pmu_nofw, &gm200_pmu }, + {} +}; + +int +gm200_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) +{ + return nvkm_pmu_new_(gm200_pmu_fwif, device, type, inst, ppmu); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c index 31c843145c7a..612310d5d481 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c @@ -19,38 +19,230 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - -#include <engine/falcon.h> -#include <core/msgqueue.h> #include "priv.h" -static void +#include <core/memory.h> +#include <subdev/acr.h> + +#include <nvfw/flcn.h> +#include <nvfw/pmu.h> + +static int +gm20b_pmu_acr_bootstrap_falcon_cb(void *priv, struct nvfw_falcon_msg *hdr) +{ + struct nv_pmu_acr_bootstrap_falcon_msg *msg = + container_of(hdr, typeof(*msg), msg.hdr); + return msg->falcon_id; +} + +int +gm20b_pmu_acr_bootstrap_falcon(struct nvkm_falcon *falcon, + enum nvkm_acr_lsf_id id) +{ + struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon); + struct nv_pmu_acr_bootstrap_falcon_cmd cmd = { + .cmd.hdr.unit_id = NV_PMU_UNIT_ACR, + .cmd.hdr.size = sizeof(cmd), + .cmd.cmd_type = NV_PMU_ACR_CMD_BOOTSTRAP_FALCON, + .flags = NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES, + .falcon_id = id, + }; + int ret; + + ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr, + gm20b_pmu_acr_bootstrap_falcon_cb, + &pmu->subdev, msecs_to_jiffies(1000)); + if (ret >= 0) { + if (ret != cmd.falcon_id) + ret = -EIO; + else + ret = 0; + } + + return ret; +} + +int +gm20b_pmu_acr_boot(struct nvkm_falcon *falcon) +{ + struct nv_pmu_args args = { .secure_mode = true }; + const u32 addr_args = falcon->data.limit - sizeof(struct nv_pmu_args); + nvkm_falcon_load_dmem(falcon, &args, addr_args, sizeof(args), 0); + nvkm_falcon_start(falcon); + return 0; +} + +void +gm20b_pmu_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) +{ + struct loader_config hdr; + u64 addr; + + nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); + addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8); + hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); + hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); + addr = ((u64)hdr.data_dma_base1 << 40 | hdr.data_dma_base << 8); + hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); + hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); + addr = ((u64)hdr.overlay_dma_base1 << 40 | hdr.overlay_dma_base << 8); + hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8); + hdr.overlay_dma_base1 = upper_32_bits((addr + adjust) << 8); + nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); + + loader_config_dump(&acr->subdev, &hdr); +} + +void +gm20b_pmu_acr_bld_write(struct nvkm_acr *acr, u32 bld, + struct nvkm_acr_lsfw *lsfw) +{ + const u64 base = lsfw->offset.img + lsfw->app_start_offset; + const u64 code = (base + lsfw->app_resident_code_offset) >> 8; + const u64 data = (base + lsfw->app_resident_data_offset) >> 8; + const struct loader_config hdr = { + .dma_idx = FALCON_DMAIDX_UCODE, + .code_dma_base = lower_32_bits(code), + .code_size_total = lsfw->app_size, + .code_size_to_load = lsfw->app_resident_code_size, + .code_entry_point = lsfw->app_imem_entry, + .data_dma_base = lower_32_bits(data), + .data_size = lsfw->app_resident_data_size, + .overlay_dma_base = lower_32_bits(code), + .argc = 1, + .argv = lsfw->falcon->data.limit - sizeof(struct nv_pmu_args), + .code_dma_base1 = upper_32_bits(code), + .data_dma_base1 = upper_32_bits(data), + .overlay_dma_base1 = upper_32_bits(code), + }; + + nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); +} + +static const struct nvkm_acr_lsf_func +gm20b_pmu_acr = { + .flags = NVKM_ACR_LSF_DMACTL_REQ_CTX, + .bld_size = sizeof(struct loader_config), + .bld_write = gm20b_pmu_acr_bld_write, + .bld_patch = gm20b_pmu_acr_bld_patch, + .boot = gm20b_pmu_acr_boot, + .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_PMU) | + BIT_ULL(NVKM_ACR_LSF_FECS) | + BIT_ULL(NVKM_ACR_LSF_GPCCS), + .bootstrap_falcon = gm20b_pmu_acr_bootstrap_falcon, +}; + +static int +gm20b_pmu_acr_init_wpr_callback(void *priv, struct nvfw_falcon_msg *hdr) +{ + struct nv_pmu_acr_init_wpr_region_msg *msg = + container_of(hdr, typeof(*msg), msg.hdr); + struct nvkm_pmu *pmu = priv; + struct nvkm_subdev *subdev = &pmu->subdev; + + if (msg->error_code) { + nvkm_error(subdev, "ACR WPR init failure: %d\n", + msg->error_code); + return -EINVAL; + } + + nvkm_debug(subdev, "ACR WPR init complete\n"); + complete_all(&pmu->wpr_ready); + return 0; +} + +static int +gm20b_pmu_acr_init_wpr(struct nvkm_pmu *pmu) +{ + struct nv_pmu_acr_init_wpr_region_cmd cmd = { + .cmd.hdr.unit_id = NV_PMU_UNIT_ACR, + .cmd.hdr.size = sizeof(cmd), + .cmd.cmd_type = NV_PMU_ACR_CMD_INIT_WPR_REGION, + .region_id = 1, + .wpr_offset = 0, + }; + + return nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr, + gm20b_pmu_acr_init_wpr_callback, pmu, 0); +} + +int +gm20b_pmu_initmsg(struct nvkm_pmu *pmu) +{ + struct nv_pmu_init_msg msg; + int ret; + + ret = nvkm_falcon_msgq_recv_initmsg(pmu->msgq, &msg, sizeof(msg)); + if (ret) + return ret; + + if (msg.hdr.unit_id != NV_PMU_UNIT_INIT || + msg.msg_type != NV_PMU_INIT_MSG_INIT) + return -EINVAL; + + nvkm_falcon_cmdq_init(pmu->hpq, msg.queue_info[0].index, + msg.queue_info[0].offset, + msg.queue_info[0].size); + nvkm_falcon_cmdq_init(pmu->lpq, msg.queue_info[1].index, + msg.queue_info[1].offset, + msg.queue_info[1].size); + nvkm_falcon_msgq_init(pmu->msgq, msg.queue_info[4].index, + msg.queue_info[4].offset, + msg.queue_info[4].size); + return gm20b_pmu_acr_init_wpr(pmu); +} + +void gm20b_pmu_recv(struct nvkm_pmu *pmu) { - if (!pmu->queue) { - nvkm_warn(&pmu->subdev, - "recv function called while no firmware set!\n"); - return; + if (!pmu->initmsg_received) { + int ret = pmu->func->initmsg(pmu); + if (ret) { + nvkm_error(&pmu->subdev, + "error parsing init message: %d\n", ret); + return; + } + + pmu->initmsg_received = true; } - nvkm_msgqueue_recv(pmu->queue); + nvkm_falcon_msgq_recv(pmu->msgq); } static const struct nvkm_pmu_func gm20b_pmu = { + .flcn = &gm200_pmu_flcn, .enabled = gf100_pmu_enabled, .intr = gt215_pmu_intr, .recv = gm20b_pmu_recv, + .initmsg = gm20b_pmu_initmsg, + .reset = gf100_pmu_reset, }; +#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) +MODULE_FIRMWARE("nvidia/gm20b/pmu/desc.bin"); +MODULE_FIRMWARE("nvidia/gm20b/pmu/image.bin"); +MODULE_FIRMWARE("nvidia/gm20b/pmu/sig.bin"); +#endif + int -gm20b_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gm20b_pmu_load(struct nvkm_pmu *pmu, int ver, const struct nvkm_pmu_fwif *fwif) { - int ret; + return nvkm_acr_lsfw_load_sig_image_desc(&pmu->subdev, &pmu->falcon, + NVKM_ACR_LSF_PMU, "pmu/", + ver, fwif->acr); +} - ret = nvkm_pmu_new_(&gm20b_pmu, device, index, ppmu); - if (ret) - return ret; +static const struct nvkm_pmu_fwif +gm20b_pmu_fwif[] = { + { 0, gm20b_pmu_load, &gm20b_pmu, &gm20b_pmu_acr }, + { -1, gm200_pmu_nofw, &gm20b_pmu }, + {} +}; - return 0; +int +gm20b_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) +{ + return nvkm_pmu_new_(gm20b_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c index 98c7a2a8afc4..1a6f9c3af5ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c @@ -23,7 +23,7 @@ */ #include "priv.h" -static void +void gp102_pmu_reset(struct nvkm_pmu *pmu) { struct nvkm_device *device = pmu->subdev.device; @@ -39,12 +39,20 @@ gp102_pmu_enabled(struct nvkm_pmu *pmu) static const struct nvkm_pmu_func gp102_pmu = { + .flcn = &gm200_pmu_flcn, .enabled = gp102_pmu_enabled, .reset = gp102_pmu_reset, }; +static const struct nvkm_pmu_fwif +gp102_pmu_fwif[] = { + { -1, gm200_pmu_nofw, &gp102_pmu }, + {} +}; + int -gp102_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gp102_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(&gp102_pmu, device, index, ppmu); + return nvkm_pmu_new_(gp102_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c new file mode 100644 index 000000000000..94cfb1791af6 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +#include <subdev/acr.h> + +#include <nvfw/flcn.h> +#include <nvfw/pmu.h> + +static int +gp10b_pmu_acr_bootstrap_multiple_falcons_cb(void *priv, + struct nvfw_falcon_msg *hdr) +{ + struct nv_pmu_acr_bootstrap_multiple_falcons_msg *msg = + container_of(hdr, typeof(*msg), msg.hdr); + return msg->falcon_mask; +} +static int +gp10b_pmu_acr_bootstrap_multiple_falcons(struct nvkm_falcon *falcon, u32 mask) +{ + struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon); + struct nv_pmu_acr_bootstrap_multiple_falcons_cmd cmd = { + .cmd.hdr.unit_id = NV_PMU_UNIT_ACR, + .cmd.hdr.size = sizeof(cmd), + .cmd.cmd_type = NV_PMU_ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS, + .flags = NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_YES, + .falcon_mask = mask, + .wpr_lo = 0, /*XXX*/ + .wpr_hi = 0, /*XXX*/ + }; + int ret; + + ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr, + gp10b_pmu_acr_bootstrap_multiple_falcons_cb, + &pmu->subdev, msecs_to_jiffies(1000)); + if (ret >= 0) { + if (ret != cmd.falcon_mask) + ret = -EIO; + else + ret = 0; + } + + return ret; +} + +static const struct nvkm_acr_lsf_func +gp10b_pmu_acr = { + .flags = NVKM_ACR_LSF_DMACTL_REQ_CTX, + .bld_size = sizeof(struct loader_config), + .bld_write = gm20b_pmu_acr_bld_write, + .bld_patch = gm20b_pmu_acr_bld_patch, + .boot = gm20b_pmu_acr_boot, + .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_PMU) | + BIT_ULL(NVKM_ACR_LSF_FECS) | + BIT_ULL(NVKM_ACR_LSF_GPCCS), + .bootstrap_falcon = gm20b_pmu_acr_bootstrap_falcon, + .bootstrap_multiple_falcons = gp10b_pmu_acr_bootstrap_multiple_falcons, +}; + +static const struct nvkm_pmu_func +gp10b_pmu = { + .flcn = &gm200_pmu_flcn, + .enabled = gf100_pmu_enabled, + .intr = gt215_pmu_intr, + .recv = gm20b_pmu_recv, + .initmsg = gm20b_pmu_initmsg, + .reset = gp102_pmu_reset, +}; + +#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) +MODULE_FIRMWARE("nvidia/gp10b/pmu/desc.bin"); +MODULE_FIRMWARE("nvidia/gp10b/pmu/image.bin"); +MODULE_FIRMWARE("nvidia/gp10b/pmu/sig.bin"); +#endif + +static const struct nvkm_pmu_fwif +gp10b_pmu_fwif[] = { + { 0, gm20b_pmu_load, &gp10b_pmu, &gp10b_pmu_acr }, + { -1, gm200_pmu_nofw, &gp10b_pmu }, + {} +}; + +int +gp10b_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) +{ + return nvkm_pmu_new_(gp10b_pmu_fwif, device, type, inst, ppmu); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c index e04216daea58..b0407b86bc10 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c @@ -34,7 +34,7 @@ gt215_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], struct nvkm_device *device = subdev->device; u32 addr; - mutex_lock(&subdev->mutex); + mutex_lock(&pmu->send.mutex); /* wait for a free slot in the fifo */ addr = nvkm_rd32(device, 0x10a4a0); if (nvkm_msec(device, 2000, @@ -42,7 +42,7 @@ gt215_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], if (tmp != (addr ^ 8)) break; ) < 0) { - mutex_unlock(&subdev->mutex); + mutex_unlock(&pmu->send.mutex); return -EBUSY; } @@ -79,7 +79,7 @@ gt215_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], reply[1] = pmu->recv.data[1]; } - mutex_unlock(&subdev->mutex); + mutex_unlock(&pmu->send.mutex); return 0; } @@ -241,8 +241,27 @@ gt215_pmu_init(struct nvkm_pmu *pmu) return 0; } +const struct nvkm_falcon_func +gt215_pmu_flcn = { + .debug = 0xc08, + .fbif = 0xe00, + .load_imem = nvkm_falcon_v1_load_imem, + .load_dmem = nvkm_falcon_v1_load_dmem, + .read_dmem = nvkm_falcon_v1_read_dmem, + .bind_context = nvkm_falcon_v1_bind_context, + .wait_for_halt = nvkm_falcon_v1_wait_for_halt, + .clear_interrupt = nvkm_falcon_v1_clear_interrupt, + .set_start_addr = nvkm_falcon_v1_set_start_addr, + .start = nvkm_falcon_v1_start, + .enable = nvkm_falcon_v1_enable, + .disable = nvkm_falcon_v1_disable, + .cmdq = { 0x4a0, 0x4b0, 4 }, + .msgq = { 0x4c8, 0x4cc, 0 }, +}; + static const struct nvkm_pmu_func gt215_pmu = { + .flcn = >215_pmu_flcn, .code.data = gt215_pmu_code, .code.size = sizeof(gt215_pmu_code), .data.data = gt215_pmu_data, @@ -256,8 +275,15 @@ gt215_pmu = { .recv = gt215_pmu_recv, }; +static const struct nvkm_pmu_fwif +gt215_pmu_fwif[] = { + { -1, gf100_pmu_nofw, >215_pmu }, + {} +}; + int -gt215_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gt215_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(>215_pmu, device, index, ppmu); + return nvkm_pmu_new_(gt215_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h index 26d73f9cd6d3..21abf31f4442 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h @@ -4,13 +4,12 @@ #define nvkm_pmu(p) container_of((p), struct nvkm_pmu, subdev) #include <subdev/pmu.h> #include <subdev/pmu/fuc/os.h> - -int nvkm_pmu_ctor(const struct nvkm_pmu_func *, struct nvkm_device *, - int index, struct nvkm_pmu *); -int nvkm_pmu_new_(const struct nvkm_pmu_func *, struct nvkm_device *, - int index, struct nvkm_pmu **); +enum nvkm_acr_lsf_id; +struct nvkm_acr_lsfw; struct nvkm_pmu_func { + const struct nvkm_falcon_func *flcn; + struct { u32 *data; u32 size; @@ -29,9 +28,11 @@ struct nvkm_pmu_func { int (*send)(struct nvkm_pmu *, u32 reply[2], u32 process, u32 message, u32 data0, u32 data1); void (*recv)(struct nvkm_pmu *); + int (*initmsg)(struct nvkm_pmu *); void (*pgob)(struct nvkm_pmu *, bool); }; +extern const struct nvkm_falcon_func gt215_pmu_flcn; int gt215_pmu_init(struct nvkm_pmu *); void gt215_pmu_fini(struct nvkm_pmu *); void gt215_pmu_intr(struct nvkm_pmu *); @@ -40,6 +41,32 @@ int gt215_pmu_send(struct nvkm_pmu *, u32[2], u32, u32, u32, u32); bool gf100_pmu_enabled(struct nvkm_pmu *); void gf100_pmu_reset(struct nvkm_pmu *); +void gp102_pmu_reset(struct nvkm_pmu *pmu); void gk110_pmu_pgob(struct nvkm_pmu *, bool); + +extern const struct nvkm_falcon_func gm200_pmu_flcn; + +void gm20b_pmu_acr_bld_patch(struct nvkm_acr *, u32, s64); +void gm20b_pmu_acr_bld_write(struct nvkm_acr *, u32, struct nvkm_acr_lsfw *); +int gm20b_pmu_acr_boot(struct nvkm_falcon *); +int gm20b_pmu_acr_bootstrap_falcon(struct nvkm_falcon *, enum nvkm_acr_lsf_id); +void gm20b_pmu_recv(struct nvkm_pmu *); +int gm20b_pmu_initmsg(struct nvkm_pmu *); + +struct nvkm_pmu_fwif { + int version; + int (*load)(struct nvkm_pmu *, int ver, const struct nvkm_pmu_fwif *); + const struct nvkm_pmu_func *func; + const struct nvkm_acr_lsf_func *acr; +}; + +int gf100_pmu_nofw(struct nvkm_pmu *, int, const struct nvkm_pmu_fwif *); +int gm200_pmu_nofw(struct nvkm_pmu *, int, const struct nvkm_pmu_fwif *); +int gm20b_pmu_load(struct nvkm_pmu *, int, const struct nvkm_pmu_fwif *); + +int nvkm_pmu_ctor(const struct nvkm_pmu_fwif *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_pmu *); +int nvkm_pmu_new_(const struct nvkm_pmu_fwif *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_pmu **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/privring/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/Kbuild new file mode 100644 index 000000000000..d47d1bdd0f2b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/Kbuild @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: MIT +nvkm-y += nvkm/subdev/privring/gf100.o +nvkm-y += nvkm/subdev/privring/gf117.o +nvkm-y += nvkm/subdev/privring/gk104.o +nvkm-y += nvkm/subdev/privring/gk20a.o +nvkm-y += nvkm/subdev/privring/gm200.o +nvkm-y += nvkm/subdev/privring/gp10b.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.c index d80dbc8f09b2..ef7caca70372 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.c @@ -22,44 +22,42 @@ * Authors: Ben Skeggs */ #include "priv.h" +#include <subdev/timer.h> static void -gf100_ibus_intr_hub(struct nvkm_subdev *ibus, int i) +gf100_privring_intr_hub(struct nvkm_subdev *privring, int i) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0400)); u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0400)); u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0400)); - nvkm_debug(ibus, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat); - nvkm_mask(device, 0x122128 + (i * 0x0400), 0x00000200, 0x00000000); + nvkm_debug(privring, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat); } static void -gf100_ibus_intr_rop(struct nvkm_subdev *ibus, int i) +gf100_privring_intr_rop(struct nvkm_subdev *privring, int i) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0400)); u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0400)); u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0400)); - nvkm_debug(ibus, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat); - nvkm_mask(device, 0x124128 + (i * 0x0400), 0x00000200, 0x00000000); + nvkm_debug(privring, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat); } static void -gf100_ibus_intr_gpc(struct nvkm_subdev *ibus, int i) +gf100_privring_intr_gpc(struct nvkm_subdev *privring, int i) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0400)); u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0400)); u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0400)); - nvkm_debug(ibus, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat); - nvkm_mask(device, 0x128128 + (i * 0x0400), 0x00000200, 0x00000000); + nvkm_debug(privring, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat); } void -gf100_ibus_intr(struct nvkm_subdev *ibus) +gf100_privring_intr(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 intr0 = nvkm_rd32(device, 0x121c58); u32 intr1 = nvkm_rd32(device, 0x121c5c); u32 hubnr = nvkm_rd32(device, 0x121c70); @@ -70,7 +68,7 @@ gf100_ibus_intr(struct nvkm_subdev *ibus) for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) { u32 stat = 0x00000100 << i; if (intr0 & stat) { - gf100_ibus_intr_hub(ibus, i); + gf100_privring_intr_hub(privring, i); intr0 &= ~stat; } } @@ -78,7 +76,7 @@ gf100_ibus_intr(struct nvkm_subdev *ibus) for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) { u32 stat = 0x00010000 << i; if (intr0 & stat) { - gf100_ibus_intr_rop(ibus, i); + gf100_privring_intr_rop(privring, i); intr0 &= ~stat; } } @@ -86,16 +84,22 @@ gf100_ibus_intr(struct nvkm_subdev *ibus) for (i = 0; intr1 && i < gpcnr; i++) { u32 stat = 0x00000001 << i; if (intr1 & stat) { - gf100_ibus_intr_gpc(ibus, i); + gf100_privring_intr_gpc(privring, i); intr1 &= ~stat; } } + + nvkm_mask(device, 0x121c4c, 0x0000003f, 0x00000002); + nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x121c4c) & 0x0000003f)) + break; + ); } static int -gf100_ibus_init(struct nvkm_subdev *ibus) +gf100_privring_init(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); nvkm_wr32(device, 0x12232c, 0x00100064); nvkm_wr32(device, 0x122330, 0x00100064); @@ -105,18 +109,14 @@ gf100_ibus_init(struct nvkm_subdev *ibus) } static const struct nvkm_subdev_func -gf100_ibus = { - .init = gf100_ibus_init, - .intr = gf100_ibus_intr, +gf100_privring = { + .init = gf100_privring_init, + .intr = gf100_privring_intr, }; int -gf100_ibus_new(struct nvkm_device *device, int index, - struct nvkm_subdev **pibus) +gf100_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pprivring) { - struct nvkm_subdev *ibus; - if (!(ibus = *pibus = kzalloc(sizeof(*ibus), GFP_KERNEL))) - return -ENOMEM; - nvkm_subdev_ctor(&gf100_ibus, device, index, ibus); - return 0; + return nvkm_subdev_new_(&gf100_privring, device, type, inst, pprivring); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf117.c b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf117.c index 3905a80da811..c78721fcd729 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf117.c @@ -24,9 +24,9 @@ #include "priv.h" static int -gf117_ibus_init(struct nvkm_subdev *ibus) +gf117_privring_init(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); nvkm_mask(device, 0x122348, 0x0003ffff, 0x00000100); nvkm_mask(device, 0x1223b0, 0x0003ffff, 0x00000fff); @@ -34,18 +34,14 @@ gf117_ibus_init(struct nvkm_subdev *ibus) } static const struct nvkm_subdev_func -gf117_ibus = { - .init = gf117_ibus_init, - .intr = gf100_ibus_intr, +gf117_privring = { + .init = gf117_privring_init, + .intr = gf100_privring_intr, }; int -gf117_ibus_new(struct nvkm_device *device, int index, - struct nvkm_subdev **pibus) +gf117_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pprivring) { - struct nvkm_subdev *ibus; - if (!(ibus = *pibus = kzalloc(sizeof(*ibus), GFP_KERNEL))) - return -ENOMEM; - nvkm_subdev_ctor(&gf117_ibus, device, index, ibus); - return 0; + return nvkm_subdev_new_(&gf117_privring, device, type, inst, pprivring); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.c index 9025ed1bd2a9..568a4c0997bd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.c @@ -22,44 +22,42 @@ * Authors: Ben Skeggs */ #include "priv.h" +#include <subdev/timer.h> static void -gk104_ibus_intr_hub(struct nvkm_subdev *ibus, int i) +gk104_privring_intr_hub(struct nvkm_subdev *privring, int i) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0800)); u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0800)); u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0800)); - nvkm_debug(ibus, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat); - nvkm_mask(device, 0x122128 + (i * 0x0800), 0x00000200, 0x00000000); + nvkm_debug(privring, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat); } static void -gk104_ibus_intr_rop(struct nvkm_subdev *ibus, int i) +gk104_privring_intr_rop(struct nvkm_subdev *privring, int i) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0800)); u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0800)); u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0800)); - nvkm_debug(ibus, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat); - nvkm_mask(device, 0x124128 + (i * 0x0800), 0x00000200, 0x00000000); + nvkm_debug(privring, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat); } static void -gk104_ibus_intr_gpc(struct nvkm_subdev *ibus, int i) +gk104_privring_intr_gpc(struct nvkm_subdev *privring, int i) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0800)); u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0800)); u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0800)); - nvkm_debug(ibus, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat); - nvkm_mask(device, 0x128128 + (i * 0x0800), 0x00000200, 0x00000000); + nvkm_debug(privring, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat); } void -gk104_ibus_intr(struct nvkm_subdev *ibus) +gk104_privring_intr(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 intr0 = nvkm_rd32(device, 0x120058); u32 intr1 = nvkm_rd32(device, 0x12005c); u32 hubnr = nvkm_rd32(device, 0x120070); @@ -70,7 +68,7 @@ gk104_ibus_intr(struct nvkm_subdev *ibus) for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) { u32 stat = 0x00000100 << i; if (intr0 & stat) { - gk104_ibus_intr_hub(ibus, i); + gk104_privring_intr_hub(privring, i); intr0 &= ~stat; } } @@ -78,7 +76,7 @@ gk104_ibus_intr(struct nvkm_subdev *ibus) for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) { u32 stat = 0x00010000 << i; if (intr0 & stat) { - gk104_ibus_intr_rop(ibus, i); + gk104_privring_intr_rop(privring, i); intr0 &= ~stat; } } @@ -86,16 +84,22 @@ gk104_ibus_intr(struct nvkm_subdev *ibus) for (i = 0; intr1 && i < gpcnr; i++) { u32 stat = 0x00000001 << i; if (intr1 & stat) { - gk104_ibus_intr_gpc(ibus, i); + gk104_privring_intr_gpc(privring, i); intr1 &= ~stat; } } + + nvkm_mask(device, 0x12004c, 0x0000003f, 0x00000002); + nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x12004c) & 0x0000003f)) + break; + ); } static int -gk104_ibus_init(struct nvkm_subdev *ibus) +gk104_privring_init(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; nvkm_mask(device, 0x122318, 0x0003ffff, 0x00001000); nvkm_mask(device, 0x12231c, 0x0003ffff, 0x00000200); nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); @@ -107,19 +111,15 @@ gk104_ibus_init(struct nvkm_subdev *ibus) } static const struct nvkm_subdev_func -gk104_ibus = { - .preinit = gk104_ibus_init, - .init = gk104_ibus_init, - .intr = gk104_ibus_intr, +gk104_privring = { + .preinit = gk104_privring_init, + .init = gk104_privring_init, + .intr = gk104_privring_intr, }; int -gk104_ibus_new(struct nvkm_device *device, int index, - struct nvkm_subdev **pibus) +gk104_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pprivring) { - struct nvkm_subdev *ibus; - if (!(ibus = *pibus = kzalloc(sizeof(*ibus), GFP_KERNEL))) - return -ENOMEM; - nvkm_subdev_ctor(&gk104_ibus, device, index, ibus); - return 0; + return nvkm_subdev_new_(&gk104_privring, device, type, inst, pprivring); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.c index 1a4ab825852c..55e4a60d8770 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.c @@ -19,13 +19,13 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#include <subdev/ibus.h> +#include <subdev/privring.h> #include <subdev/timer.h> static void -gk20a_ibus_init_ibus_ring(struct nvkm_subdev *ibus) +gk20a_privring_init_privring_ring(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; nvkm_mask(device, 0x137250, 0x3f, 0); nvkm_mask(device, 0x000200, 0x20, 0); @@ -46,14 +46,14 @@ gk20a_ibus_init_ibus_ring(struct nvkm_subdev *ibus) } static void -gk20a_ibus_intr(struct nvkm_subdev *ibus) +gk20a_privring_intr(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 status0 = nvkm_rd32(device, 0x120058); if (status0 & 0x7) { - nvkm_debug(ibus, "resetting ibus ring\n"); - gk20a_ibus_init_ibus_ring(ibus); + nvkm_debug(privring, "resetting privring ring\n"); + gk20a_privring_init_privring_ring(privring); } /* Acknowledge interrupt */ @@ -65,25 +65,21 @@ gk20a_ibus_intr(struct nvkm_subdev *ibus) } static int -gk20a_ibus_init(struct nvkm_subdev *ibus) +gk20a_privring_init(struct nvkm_subdev *privring) { - gk20a_ibus_init_ibus_ring(ibus); + gk20a_privring_init_privring_ring(privring); return 0; } static const struct nvkm_subdev_func -gk20a_ibus = { - .init = gk20a_ibus_init, - .intr = gk20a_ibus_intr, +gk20a_privring = { + .init = gk20a_privring_init, + .intr = gk20a_privring_intr, }; int -gk20a_ibus_new(struct nvkm_device *device, int index, - struct nvkm_subdev **pibus) +gk20a_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pprivring) { - struct nvkm_subdev *ibus; - if (!(ibus = *pibus = kzalloc(sizeof(*ibus), GFP_KERNEL))) - return -ENOMEM; - nvkm_subdev_ctor(&gk20a_ibus, device, index, ibus); - return 0; + return nvkm_subdev_new_(&gk20a_privring, device, type, inst, pprivring); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gm200.c index c63328152bfa..b4eaf6db36d7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gm200.c @@ -24,17 +24,13 @@ #include "priv.h" static const struct nvkm_subdev_func -gm200_ibus = { - .intr = gk104_ibus_intr, +gm200_privring = { + .intr = gk104_privring_intr, }; int -gm200_ibus_new(struct nvkm_device *device, int index, - struct nvkm_subdev **pibus) +gm200_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pprivring) { - struct nvkm_subdev *ibus; - if (!(ibus = *pibus = kzalloc(sizeof(*ibus), GFP_KERNEL))) - return -ENOMEM; - nvkm_subdev_ctor(&gm200_ibus, device, index, ibus); - return 0; + return nvkm_subdev_new_(&gm200_privring, device, type, inst, pprivring); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gp10b.c index 39db90aa2c80..4534111cf907 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gp10b.c @@ -19,14 +19,14 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#include <subdev/ibus.h> +#include <subdev/privring.h> #include "priv.h" static int -gp10b_ibus_init(struct nvkm_subdev *ibus) +gp10b_privring_init(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; nvkm_wr32(device, 0x1200a8, 0x0); @@ -42,18 +42,14 @@ gp10b_ibus_init(struct nvkm_subdev *ibus) } static const struct nvkm_subdev_func -gp10b_ibus = { - .init = gp10b_ibus_init, - .intr = gk104_ibus_intr, +gp10b_privring = { + .init = gp10b_privring_init, + .intr = gk104_privring_intr, }; int -gp10b_ibus_new(struct nvkm_device *device, int index, - struct nvkm_subdev **pibus) +gp10b_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pprivring) { - struct nvkm_subdev *ibus; - if (!(ibus = *pibus = kzalloc(sizeof(*ibus), GFP_KERNEL))) - return -ENOMEM; - nvkm_subdev_ctor(&gp10b_ibus, device, index, ibus); - return 0; + return nvkm_subdev_new_(&gp10b_privring, device, type, inst, pprivring); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/privring/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/priv.h new file mode 100644 index 000000000000..b378c14bc8dc --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/priv.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVKM_PRIVRING_PRIV_H__ +#define __NVKM_PRIVRING_PRIV_H__ +#include <subdev/privring.h> + +void gf100_privring_intr(struct nvkm_subdev *); +void gk104_privring_intr(struct nvkm_subdev *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild deleted file mode 100644 index f3dee2693c79..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: MIT -nvkm-y += nvkm/subdev/secboot/base.o -nvkm-y += nvkm/subdev/secboot/hs_ucode.o -nvkm-y += nvkm/subdev/secboot/ls_ucode_gr.o -nvkm-y += nvkm/subdev/secboot/ls_ucode_msgqueue.o -nvkm-y += nvkm/subdev/secboot/acr.o -nvkm-y += nvkm/subdev/secboot/acr_r352.o -nvkm-y += nvkm/subdev/secboot/acr_r361.o -nvkm-y += nvkm/subdev/secboot/acr_r364.o -nvkm-y += nvkm/subdev/secboot/acr_r367.o -nvkm-y += nvkm/subdev/secboot/acr_r370.o -nvkm-y += nvkm/subdev/secboot/acr_r375.o -nvkm-y += nvkm/subdev/secboot/gm200.o -nvkm-y += nvkm/subdev/secboot/gm20b.o -nvkm-y += nvkm/subdev/secboot/gp102.o -nvkm-y += nvkm/subdev/secboot/gp108.o -nvkm-y += nvkm/subdev/secboot/gp10b.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.c deleted file mode 100644 index dc80985cf093..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "acr.h" - -#include <core/firmware.h> - -/** - * Convenience function to duplicate a firmware file in memory and check that - * it has the required minimum size. - */ -void * -nvkm_acr_load_firmware(const struct nvkm_subdev *subdev, const char *name, - size_t min_size) -{ - const struct firmware *fw; - void *blob; - int ret; - - ret = nvkm_firmware_get(subdev, name, &fw); - if (ret) - return ERR_PTR(ret); - if (fw->size < min_size) { - nvkm_error(subdev, "%s is smaller than expected size %zu\n", - name, min_size); - nvkm_firmware_put(fw); - return ERR_PTR(-EINVAL); - } - blob = kmemdup(fw->data, fw->size, GFP_KERNEL); - nvkm_firmware_put(fw); - if (!blob) - return ERR_PTR(-ENOMEM); - - return blob; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.h deleted file mode 100644 index 73a2ac81ac69..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef __NVKM_SECBOOT_ACR_H__ -#define __NVKM_SECBOOT_ACR_H__ - -#include "priv.h" - -struct nvkm_acr; - -/** - * struct nvkm_acr_func - properties and functions specific to an ACR - * - * @load: make the ACR ready to run on the given secboot device - * @reset: reset the specified falcon - * @start: start the specified falcon (assumed to have been reset) - */ -struct nvkm_acr_func { - void (*dtor)(struct nvkm_acr *); - int (*oneinit)(struct nvkm_acr *, struct nvkm_secboot *); - int (*fini)(struct nvkm_acr *, struct nvkm_secboot *, bool); - int (*load)(struct nvkm_acr *, struct nvkm_falcon *, - struct nvkm_gpuobj *, u64); - int (*reset)(struct nvkm_acr *, struct nvkm_secboot *, unsigned long); -}; - -/** - * struct nvkm_acr - instance of an ACR - * - * @boot_falcon: ID of the falcon that will perform secure boot - * @managed_falcons: bitfield of falcons managed by this ACR - * @optional_falcons: bitfield of falcons we can live without - */ -struct nvkm_acr { - const struct nvkm_acr_func *func; - const struct nvkm_subdev *subdev; - - enum nvkm_secboot_falcon boot_falcon; - unsigned long managed_falcons; - unsigned long optional_falcons; -}; - -void *nvkm_acr_load_firmware(const struct nvkm_subdev *, const char *, size_t); - -struct nvkm_acr *acr_r352_new(unsigned long); -struct nvkm_acr *acr_r361_new(unsigned long); -struct nvkm_acr *acr_r364_new(unsigned long); -struct nvkm_acr *acr_r367_new(enum nvkm_secboot_falcon, unsigned long); -struct nvkm_acr *acr_r370_new(enum nvkm_secboot_falcon, unsigned long); -struct nvkm_acr *acr_r375_new(enum nvkm_secboot_falcon, unsigned long); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c deleted file mode 100644 index 4fd4cfe459b8..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ /dev/null @@ -1,1241 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "acr_r352.h" -#include "hs_ucode.h" - -#include <core/gpuobj.h> -#include <core/firmware.h> -#include <engine/falcon.h> -#include <subdev/pmu.h> -#include <core/msgqueue.h> -#include <engine/sec2.h> - -/** - * struct acr_r352_flcn_bl_desc - DMEM bootloader descriptor - * @signature: 16B signature for secure code. 0s if no secure code - * @ctx_dma: DMA context to be used by BL while loading code/data - * @code_dma_base: 256B-aligned Physical FB Address where code is located - * (falcon's $xcbase register) - * @non_sec_code_off: offset from code_dma_base where the non-secure code is - * located. The offset must be multiple of 256 to help perf - * @non_sec_code_size: the size of the nonSecure code part. - * @sec_code_off: offset from code_dma_base where the secure code is - * located. The offset must be multiple of 256 to help perf - * @sec_code_size: offset from code_dma_base where the secure code is - * located. The offset must be multiple of 256 to help perf - * @code_entry_point: code entry point which will be invoked by BL after - * code is loaded. - * @data_dma_base: 256B aligned Physical FB Address where data is located. - * (falcon's $xdbase register) - * @data_size: size of data block. Should be multiple of 256B - * - * Structure used by the bootloader to load the rest of the code. This has - * to be filled by host and copied into DMEM at offset provided in the - * hsflcn_bl_desc.bl_desc_dmem_load_off. - */ -struct acr_r352_flcn_bl_desc { - u32 reserved[4]; - u32 signature[4]; - u32 ctx_dma; - u32 code_dma_base; - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - u32 data_dma_base; - u32 data_size; - u32 code_dma_base1; - u32 data_dma_base1; -}; - -/** - * acr_r352_generate_flcn_bl_desc - generate generic BL descriptor for LS image - */ -static void -acr_r352_generate_flcn_bl_desc(const struct nvkm_acr *acr, - const struct ls_ucode_img *img, u64 wpr_addr, - void *_desc) -{ - struct acr_r352_flcn_bl_desc *desc = _desc; - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; - u64 base, addr_code, addr_data; - - base = wpr_addr + img->ucode_off + pdesc->app_start_offset; - addr_code = (base + pdesc->app_resident_code_offset) >> 8; - addr_data = (base + pdesc->app_resident_data_offset) >> 8; - - desc->ctx_dma = FALCON_DMAIDX_UCODE; - desc->code_dma_base = lower_32_bits(addr_code); - desc->code_dma_base1 = upper_32_bits(addr_code); - desc->non_sec_code_off = pdesc->app_resident_code_offset; - desc->non_sec_code_size = pdesc->app_resident_code_size; - desc->code_entry_point = pdesc->app_imem_entry; - desc->data_dma_base = lower_32_bits(addr_data); - desc->data_dma_base1 = upper_32_bits(addr_data); - desc->data_size = pdesc->app_resident_data_size; -} - - -/** - * struct hsflcn_acr_desc - data section of the HS firmware - * - * This header is to be copied at the beginning of DMEM by the HS bootloader. - * - * @signature: signature of ACR ucode - * @wpr_region_id: region ID holding the WPR header and its details - * @wpr_offset: offset from the WPR region holding the wpr header - * @regions: region descriptors - * @nonwpr_ucode_blob_size: size of LS blob - * @nonwpr_ucode_blob_start: FB location of LS blob is - */ -struct hsflcn_acr_desc { - union { - u8 reserved_dmem[0x200]; - u32 signatures[4]; - } ucode_reserved_space; - u32 wpr_region_id; - u32 wpr_offset; - u32 mmu_mem_range; -#define FLCN_ACR_MAX_REGIONS 2 - struct { - u32 no_regions; - struct { - u32 start_addr; - u32 end_addr; - u32 region_id; - u32 read_mask; - u32 write_mask; - u32 client_mask; - } region_props[FLCN_ACR_MAX_REGIONS]; - } regions; - u32 ucode_blob_size; - u64 ucode_blob_base __aligned(8); - struct { - u32 vpr_enabled; - u32 vpr_start; - u32 vpr_end; - u32 hdcp_policies; - } vpr_desc; -}; - - -/* - * Low-secure blob creation - */ - -/** - * struct acr_r352_lsf_lsb_header - LS firmware header - * @signature: signature to verify the firmware against - * @ucode_off: offset of the ucode blob in the WPR region. The ucode - * blob contains the bootloader, code and data of the - * LS falcon - * @ucode_size: size of the ucode blob, including bootloader - * @data_size: size of the ucode blob data - * @bl_code_size: size of the bootloader code - * @bl_imem_off: offset in imem of the bootloader - * @bl_data_off: offset of the bootloader data in WPR region - * @bl_data_size: size of the bootloader data - * @app_code_off: offset of the app code relative to ucode_off - * @app_code_size: size of the app code - * @app_data_off: offset of the app data relative to ucode_off - * @app_data_size: size of the app data - * @flags: flags for the secure bootloader - * - * This structure is written into the WPR region for each managed falcon. Each - * instance is referenced by the lsb_offset member of the corresponding - * lsf_wpr_header. - */ -struct acr_r352_lsf_lsb_header { - /** - * LS falcon signatures - * @prd_keys: signature to use in production mode - * @dgb_keys: signature to use in debug mode - * @b_prd_present: whether the production key is present - * @b_dgb_present: whether the debug key is present - * @falcon_id: ID of the falcon the ucode applies to - */ - struct { - u8 prd_keys[2][16]; - u8 dbg_keys[2][16]; - u32 b_prd_present; - u32 b_dbg_present; - u32 falcon_id; - } signature; - u32 ucode_off; - u32 ucode_size; - u32 data_size; - u32 bl_code_size; - u32 bl_imem_off; - u32 bl_data_off; - u32 bl_data_size; - u32 app_code_off; - u32 app_code_size; - u32 app_data_off; - u32 app_data_size; - u32 flags; -}; - -/** - * struct acr_r352_lsf_wpr_header - LS blob WPR Header - * @falcon_id: LS falcon ID - * @lsb_offset: offset of the lsb_lsf_header in the WPR region - * @bootstrap_owner: secure falcon reponsible for bootstrapping the LS falcon - * @lazy_bootstrap: skip bootstrapping by ACR - * @status: bootstrapping status - * - * An array of these is written at the beginning of the WPR region, one for - * each managed falcon. The array is terminated by an instance which falcon_id - * is LSF_FALCON_ID_INVALID. - */ -struct acr_r352_lsf_wpr_header { - u32 falcon_id; - u32 lsb_offset; - u32 bootstrap_owner; - u32 lazy_bootstrap; - u32 status; -#define LSF_IMAGE_STATUS_NONE 0 -#define LSF_IMAGE_STATUS_COPY 1 -#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2 -#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3 -#define LSF_IMAGE_STATUS_VALIDATION_DONE 4 -#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5 -#define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6 -}; - -/** - * struct ls_ucode_img_r352 - ucode image augmented with r352 headers - */ -struct ls_ucode_img_r352 { - struct ls_ucode_img base; - - const struct acr_r352_lsf_func *func; - - struct acr_r352_lsf_wpr_header wpr_header; - struct acr_r352_lsf_lsb_header lsb_header; -}; -#define ls_ucode_img_r352(i) container_of(i, struct ls_ucode_img_r352, base) - -/** - * ls_ucode_img_load() - create a lsf_ucode_img and load it - */ -struct ls_ucode_img * -acr_r352_ls_ucode_img_load(const struct acr_r352 *acr, - const struct nvkm_secboot *sb, - enum nvkm_secboot_falcon falcon_id) -{ - const struct nvkm_subdev *subdev = acr->base.subdev; - const struct acr_r352_ls_func *func = acr->func->ls_func[falcon_id]; - struct ls_ucode_img_r352 *img; - int ret; - - img = kzalloc(sizeof(*img), GFP_KERNEL); - if (!img) - return ERR_PTR(-ENOMEM); - - img->base.falcon_id = falcon_id; - - ret = func->load(sb, func->version_max, &img->base); - if (ret < 0) { - kfree(img->base.ucode_data); - kfree(img->base.sig); - kfree(img); - return ERR_PTR(ret); - } - - img->func = func->version[ret]; - - /* Check that the signature size matches our expectations... */ - if (img->base.sig_size != sizeof(img->lsb_header.signature)) { - nvkm_error(subdev, "invalid signature size for %s falcon!\n", - nvkm_secboot_falcon_name[falcon_id]); - return ERR_PTR(-EINVAL); - } - - /* Copy signature to the right place */ - memcpy(&img->lsb_header.signature, img->base.sig, img->base.sig_size); - - /* not needed? the signature should already have the right value */ - img->lsb_header.signature.falcon_id = falcon_id; - - return &img->base; -} - -#define LSF_LSB_HEADER_ALIGN 256 -#define LSF_BL_DATA_ALIGN 256 -#define LSF_BL_DATA_SIZE_ALIGN 256 -#define LSF_BL_CODE_SIZE_ALIGN 256 -#define LSF_UCODE_DATA_ALIGN 4096 - -/** - * acr_r352_ls_img_fill_headers - fill the WPR and LSB headers of an image - * @acr: ACR to use - * @img: image to generate for - * @offset: offset in the WPR region where this image starts - * - * Allocate space in the WPR area from offset and write the WPR and LSB headers - * accordingly. - * - * Return: offset at the end of this image. - */ -static u32 -acr_r352_ls_img_fill_headers(struct acr_r352 *acr, - struct ls_ucode_img_r352 *img, u32 offset) -{ - struct ls_ucode_img *_img = &img->base; - struct acr_r352_lsf_wpr_header *whdr = &img->wpr_header; - struct acr_r352_lsf_lsb_header *lhdr = &img->lsb_header; - struct ls_ucode_img_desc *desc = &_img->ucode_desc; - const struct acr_r352_lsf_func *func = img->func; - - /* Fill WPR header */ - whdr->falcon_id = _img->falcon_id; - whdr->bootstrap_owner = acr->base.boot_falcon; - whdr->status = LSF_IMAGE_STATUS_COPY; - - /* Skip bootstrapping falcons started by someone else than ACR */ - if (acr->lazy_bootstrap & BIT(_img->falcon_id)) - whdr->lazy_bootstrap = 1; - - /* Align, save off, and include an LSB header size */ - offset = ALIGN(offset, LSF_LSB_HEADER_ALIGN); - whdr->lsb_offset = offset; - offset += sizeof(*lhdr); - - /* - * Align, save off, and include the original (static) ucode - * image size - */ - offset = ALIGN(offset, LSF_UCODE_DATA_ALIGN); - _img->ucode_off = lhdr->ucode_off = offset; - offset += _img->ucode_size; - - /* - * For falcons that use a boot loader (BL), we append a loader - * desc structure on the end of the ucode image and consider - * this the boot loader data. The host will then copy the loader - * desc args to this space within the WPR region (before locking - * down) and the HS bin will then copy them to DMEM 0 for the - * loader. - */ - lhdr->bl_code_size = ALIGN(desc->bootloader_size, - LSF_BL_CODE_SIZE_ALIGN); - lhdr->ucode_size = ALIGN(desc->app_resident_data_offset, - LSF_BL_CODE_SIZE_ALIGN) + lhdr->bl_code_size; - lhdr->data_size = ALIGN(desc->app_size, LSF_BL_CODE_SIZE_ALIGN) + - lhdr->bl_code_size - lhdr->ucode_size; - /* - * Though the BL is located at 0th offset of the image, the VA - * is different to make sure that it doesn't collide the actual - * OS VA range - */ - lhdr->bl_imem_off = desc->bootloader_imem_offset; - lhdr->app_code_off = desc->app_start_offset + - desc->app_resident_code_offset; - lhdr->app_code_size = desc->app_resident_code_size; - lhdr->app_data_off = desc->app_start_offset + - desc->app_resident_data_offset; - lhdr->app_data_size = desc->app_resident_data_size; - - lhdr->flags = func->lhdr_flags; - if (_img->falcon_id == acr->base.boot_falcon) - lhdr->flags |= LSF_FLAG_DMACTL_REQ_CTX; - - /* Align and save off BL descriptor size */ - lhdr->bl_data_size = ALIGN(func->bl_desc_size, LSF_BL_DATA_SIZE_ALIGN); - - /* - * Align, save off, and include the additional BL data - */ - offset = ALIGN(offset, LSF_BL_DATA_ALIGN); - lhdr->bl_data_off = offset; - offset += lhdr->bl_data_size; - - return offset; -} - -/** - * acr_r352_ls_fill_headers - fill WPR and LSB headers of all managed images - */ -int -acr_r352_ls_fill_headers(struct acr_r352 *acr, struct list_head *imgs) -{ - struct ls_ucode_img_r352 *img; - struct list_head *l; - u32 count = 0; - u32 offset; - - /* Count the number of images to manage */ - list_for_each(l, imgs) - count++; - - /* - * Start with an array of WPR headers at the base of the WPR. - * The expectation here is that the secure falcon will do a single DMA - * read of this array and cache it internally so it's ok to pack these. - * Also, we add 1 to the falcon count to indicate the end of the array. - */ - offset = sizeof(img->wpr_header) * (count + 1); - - /* - * Walk the managed falcons, accounting for the LSB structs - * as well as the ucode images. - */ - list_for_each_entry(img, imgs, base.node) { - offset = acr_r352_ls_img_fill_headers(acr, img, offset); - } - - return offset; -} - -/** - * acr_r352_ls_write_wpr - write the WPR blob contents - */ -int -acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, - struct nvkm_gpuobj *wpr_blob, u64 wpr_addr) -{ - struct ls_ucode_img *_img; - u32 pos = 0; - u32 max_desc_size = 0; - u8 *gdesc; - - /* Figure out how large we need gdesc to be. */ - list_for_each_entry(_img, imgs, node) { - struct ls_ucode_img_r352 *img = ls_ucode_img_r352(_img); - const struct acr_r352_lsf_func *ls_func = img->func; - - max_desc_size = max(max_desc_size, ls_func->bl_desc_size); - } - - gdesc = kmalloc(max_desc_size, GFP_KERNEL); - if (!gdesc) - return -ENOMEM; - - nvkm_kmap(wpr_blob); - - list_for_each_entry(_img, imgs, node) { - struct ls_ucode_img_r352 *img = ls_ucode_img_r352(_img); - const struct acr_r352_lsf_func *ls_func = img->func; - - nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header, - sizeof(img->wpr_header)); - - nvkm_gpuobj_memcpy_to(wpr_blob, img->wpr_header.lsb_offset, - &img->lsb_header, sizeof(img->lsb_header)); - - /* Generate and write BL descriptor */ - memset(gdesc, 0, ls_func->bl_desc_size); - ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc); - - nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.bl_data_off, - gdesc, ls_func->bl_desc_size); - - /* Copy ucode */ - nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.ucode_off, - _img->ucode_data, _img->ucode_size); - - pos += sizeof(img->wpr_header); - } - - nvkm_wo32(wpr_blob, pos, NVKM_SECBOOT_FALCON_INVALID); - - nvkm_done(wpr_blob); - - kfree(gdesc); - - return 0; -} - -/* Both size and address of WPR need to be 256K-aligned */ -#define WPR_ALIGNMENT 0x40000 -/** - * acr_r352_prepare_ls_blob() - prepare the LS blob - * - * For each securely managed falcon, load the FW, signatures and bootloaders and - * prepare a ucode blob. Then, compute the offsets in the WPR region for each - * blob, and finally write the headers and ucode blobs into a GPU object that - * will be copied into the WPR region by the HS firmware. - */ -static int -acr_r352_prepare_ls_blob(struct acr_r352 *acr, struct nvkm_secboot *sb) -{ - const struct nvkm_subdev *subdev = acr->base.subdev; - struct list_head imgs; - struct ls_ucode_img *img, *t; - unsigned long managed_falcons = acr->base.managed_falcons; - u64 wpr_addr = sb->wpr_addr; - u32 wpr_size = sb->wpr_size; - int managed_count = 0; - u32 image_wpr_size, ls_blob_size; - int falcon_id; - int ret; - - INIT_LIST_HEAD(&imgs); - - /* Load all LS blobs */ - for_each_set_bit(falcon_id, &managed_falcons, NVKM_SECBOOT_FALCON_END) { - struct ls_ucode_img *img; - - img = acr->func->ls_ucode_img_load(acr, sb, falcon_id); - if (IS_ERR(img)) { - if (acr->base.optional_falcons & BIT(falcon_id)) { - managed_falcons &= ~BIT(falcon_id); - nvkm_info(subdev, "skipping %s falcon...\n", - nvkm_secboot_falcon_name[falcon_id]); - continue; - } - ret = PTR_ERR(img); - goto cleanup; - } - - list_add_tail(&img->node, &imgs); - managed_count++; - } - - /* Commit the actual list of falcons we will manage from now on */ - acr->base.managed_falcons = managed_falcons; - - /* - * If the boot falcon has a firmare, let it manage the bootstrap of other - * falcons. - */ - if (acr->func->ls_func[acr->base.boot_falcon] && - (managed_falcons & BIT(acr->base.boot_falcon))) { - for_each_set_bit(falcon_id, &managed_falcons, - NVKM_SECBOOT_FALCON_END) { - if (falcon_id == acr->base.boot_falcon) - continue; - - acr->lazy_bootstrap |= BIT(falcon_id); - } - } - - /* - * Fill the WPR and LSF headers with the right offsets and compute - * required WPR size - */ - image_wpr_size = acr->func->ls_fill_headers(acr, &imgs); - image_wpr_size = ALIGN(image_wpr_size, WPR_ALIGNMENT); - - ls_blob_size = image_wpr_size; - - /* - * If we need a shadow area, allocate twice the size and use the - * upper half as WPR - */ - if (wpr_size == 0 && acr->func->shadow_blob) - ls_blob_size *= 2; - - /* Allocate GPU object that will contain the WPR region */ - ret = nvkm_gpuobj_new(subdev->device, ls_blob_size, WPR_ALIGNMENT, - false, NULL, &acr->ls_blob); - if (ret) - goto cleanup; - - nvkm_debug(subdev, "%d managed LS falcons, WPR size is %d bytes\n", - managed_count, image_wpr_size); - - /* If WPR address and size are not fixed, set them to fit the LS blob */ - if (wpr_size == 0) { - wpr_addr = acr->ls_blob->addr; - if (acr->func->shadow_blob) - wpr_addr += acr->ls_blob->size / 2; - - wpr_size = image_wpr_size; - /* - * But if the WPR region is set by the bootloader, it is illegal for - * the HS blob to be larger than this region. - */ - } else if (image_wpr_size > wpr_size) { - nvkm_error(subdev, "WPR region too small for FW blob!\n"); - nvkm_error(subdev, "required: %dB\n", image_wpr_size); - nvkm_error(subdev, "available: %dB\n", wpr_size); - ret = -ENOSPC; - goto cleanup; - } - - /* Write LS blob */ - ret = acr->func->ls_write_wpr(acr, &imgs, acr->ls_blob, wpr_addr); - if (ret) - nvkm_gpuobj_del(&acr->ls_blob); - -cleanup: - list_for_each_entry_safe(img, t, &imgs, node) { - kfree(img->ucode_data); - kfree(img->sig); - kfree(img); - } - - return ret; -} - - - - -void -acr_r352_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb, - void *_desc) -{ - struct hsflcn_acr_desc *desc = _desc; - struct nvkm_gpuobj *ls_blob = acr->ls_blob; - - /* WPR region information if WPR is not fixed */ - if (sb->wpr_size == 0) { - u64 wpr_start = ls_blob->addr; - u64 wpr_end = wpr_start + ls_blob->size; - - desc->wpr_region_id = 1; - desc->regions.no_regions = 2; - desc->regions.region_props[0].start_addr = wpr_start >> 8; - desc->regions.region_props[0].end_addr = wpr_end >> 8; - desc->regions.region_props[0].region_id = 1; - desc->regions.region_props[0].read_mask = 0xf; - desc->regions.region_props[0].write_mask = 0xc; - desc->regions.region_props[0].client_mask = 0x2; - } else { - desc->ucode_blob_base = ls_blob->addr; - desc->ucode_blob_size = ls_blob->size; - } -} - -static void -acr_r352_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc, - u64 offset) -{ - struct acr_r352_flcn_bl_desc *bl_desc = _bl_desc; - u64 addr_code, addr_data; - - addr_code = offset >> 8; - addr_data = (offset + hdr->data_dma_base) >> 8; - - bl_desc->ctx_dma = FALCON_DMAIDX_VIRT; - bl_desc->code_dma_base = lower_32_bits(addr_code); - bl_desc->non_sec_code_off = hdr->non_sec_code_off; - bl_desc->non_sec_code_size = hdr->non_sec_code_size; - bl_desc->sec_code_off = hsf_load_header_app_off(hdr, 0); - bl_desc->sec_code_size = hsf_load_header_app_size(hdr, 0); - bl_desc->code_entry_point = 0; - bl_desc->data_dma_base = lower_32_bits(addr_data); - bl_desc->data_size = hdr->data_size; -} - -/** - * acr_r352_prepare_hs_blob - load and prepare a HS blob and BL descriptor - * - * @sb secure boot instance to prepare for - * @fw name of the HS firmware to load - * @blob pointer to gpuobj that will be allocated to receive the HS FW payload - * @bl_desc pointer to the BL descriptor to write for this firmware - * @patch whether we should patch the HS descriptor (only for HS loaders) - */ -static int -acr_r352_prepare_hs_blob(struct acr_r352 *acr, struct nvkm_secboot *sb, - const char *fw, struct nvkm_gpuobj **blob, - struct hsf_load_header *load_header, bool patch) -{ - struct nvkm_subdev *subdev = &sb->subdev; - void *acr_image; - struct fw_bin_header *hsbin_hdr; - struct hsf_fw_header *fw_hdr; - struct hsf_load_header *load_hdr; - void *acr_data; - int ret; - - acr_image = hs_ucode_load_blob(subdev, sb->boot_falcon, fw); - if (IS_ERR(acr_image)) - return PTR_ERR(acr_image); - - hsbin_hdr = acr_image; - fw_hdr = acr_image + hsbin_hdr->header_offset; - load_hdr = acr_image + fw_hdr->hdr_offset; - acr_data = acr_image + hsbin_hdr->data_offset; - - /* Patch descriptor with WPR information? */ - if (patch) { - struct hsflcn_acr_desc *desc; - - desc = acr_data + load_hdr->data_dma_base; - acr->func->fixup_hs_desc(acr, sb, desc); - } - - if (load_hdr->num_apps > ACR_R352_MAX_APPS) { - nvkm_error(subdev, "more apps (%d) than supported (%d)!", - load_hdr->num_apps, ACR_R352_MAX_APPS); - ret = -EINVAL; - goto cleanup; - } - memcpy(load_header, load_hdr, sizeof(*load_header) + - (sizeof(load_hdr->apps[0]) * 2 * load_hdr->num_apps)); - - /* Create ACR blob and copy HS data to it */ - ret = nvkm_gpuobj_new(subdev->device, ALIGN(hsbin_hdr->data_size, 256), - 0x1000, false, NULL, blob); - if (ret) - goto cleanup; - - nvkm_kmap(*blob); - nvkm_gpuobj_memcpy_to(*blob, 0, acr_data, hsbin_hdr->data_size); - nvkm_done(*blob); - -cleanup: - kfree(acr_image); - - return ret; -} - -/** - * acr_r352_load_blobs - load blobs common to all ACR V1 versions. - * - * This includes the LS blob, HS ucode loading blob, and HS bootloader. - * - * The HS ucode unload blob is only used on dGPU if the WPR region is variable. - */ -int -acr_r352_load_blobs(struct acr_r352 *acr, struct nvkm_secboot *sb) -{ - struct nvkm_subdev *subdev = &sb->subdev; - int ret; - - /* Firmware already loaded? */ - if (acr->firmware_ok) - return 0; - - /* Load and prepare the managed falcon's firmwares */ - ret = acr_r352_prepare_ls_blob(acr, sb); - if (ret) - return ret; - - /* Load the HS firmware that will load the LS firmwares */ - if (!acr->load_blob) { - ret = acr_r352_prepare_hs_blob(acr, sb, "acr/ucode_load", - &acr->load_blob, - &acr->load_bl_header, true); - if (ret) - return ret; - } - - /* If the ACR region is dynamically programmed, we need an unload FW */ - if (sb->wpr_size == 0) { - ret = acr_r352_prepare_hs_blob(acr, sb, "acr/ucode_unload", - &acr->unload_blob, - &acr->unload_bl_header, false); - if (ret) - return ret; - } - - /* Load the HS firmware bootloader */ - if (!acr->hsbl_blob) { - acr->hsbl_blob = nvkm_acr_load_firmware(subdev, "acr/bl", 0); - if (IS_ERR(acr->hsbl_blob)) { - ret = PTR_ERR(acr->hsbl_blob); - acr->hsbl_blob = NULL; - return ret; - } - - if (acr->base.boot_falcon != NVKM_SECBOOT_FALCON_PMU) { - acr->hsbl_unload_blob = nvkm_acr_load_firmware(subdev, - "acr/unload_bl", 0); - if (IS_ERR(acr->hsbl_unload_blob)) { - ret = PTR_ERR(acr->hsbl_unload_blob); - acr->hsbl_unload_blob = NULL; - return ret; - } - } else { - acr->hsbl_unload_blob = acr->hsbl_blob; - } - } - - acr->firmware_ok = true; - nvkm_debug(&sb->subdev, "LS blob successfully created\n"); - - return 0; -} - -/** - * acr_r352_load() - prepare HS falcon to run the specified blob, mapped. - * - * Returns the start address to use, or a negative error value. - */ -static int -acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon, - struct nvkm_gpuobj *blob, u64 offset) -{ - struct acr_r352 *acr = acr_r352(_acr); - const u32 bl_desc_size = acr->func->hs_bl_desc_size; - const struct hsf_load_header *load_hdr; - struct fw_bin_header *bl_hdr; - struct fw_bl_desc *hsbl_desc; - void *bl, *blob_data, *hsbl_code, *hsbl_data; - u32 code_size; - u8 *bl_desc; - - bl_desc = kzalloc(bl_desc_size, GFP_KERNEL); - if (!bl_desc) - return -ENOMEM; - - /* Find the bootloader descriptor for our blob and copy it */ - if (blob == acr->load_blob) { - load_hdr = &acr->load_bl_header; - bl = acr->hsbl_blob; - } else if (blob == acr->unload_blob) { - load_hdr = &acr->unload_bl_header; - bl = acr->hsbl_unload_blob; - } else { - nvkm_error(_acr->subdev, "invalid secure boot blob!\n"); - kfree(bl_desc); - return -EINVAL; - } - - bl_hdr = bl; - hsbl_desc = bl + bl_hdr->header_offset; - blob_data = bl + bl_hdr->data_offset; - hsbl_code = blob_data + hsbl_desc->code_off; - hsbl_data = blob_data + hsbl_desc->data_off; - code_size = ALIGN(hsbl_desc->code_size, 256); - - /* - * Copy HS bootloader data - */ - nvkm_falcon_load_dmem(falcon, hsbl_data, 0x0, hsbl_desc->data_size, 0); - - /* Copy HS bootloader code to end of IMEM */ - nvkm_falcon_load_imem(falcon, hsbl_code, falcon->code.limit - code_size, - code_size, hsbl_desc->start_tag, 0, false); - - /* Generate the BL header */ - acr->func->generate_hs_bl_desc(load_hdr, bl_desc, offset); - - /* - * Copy HS BL header where the HS descriptor expects it to be - */ - nvkm_falcon_load_dmem(falcon, bl_desc, hsbl_desc->dmem_load_off, - bl_desc_size, 0); - - kfree(bl_desc); - return hsbl_desc->start_tag << 8; -} - -static int -acr_r352_shutdown(struct acr_r352 *acr, struct nvkm_secboot *sb) -{ - struct nvkm_subdev *subdev = &sb->subdev; - int i; - - /* Run the unload blob to unprotect the WPR region */ - if (acr->unload_blob && sb->wpr_set) { - int ret; - - nvkm_debug(subdev, "running HS unload blob\n"); - ret = sb->func->run_blob(sb, acr->unload_blob, sb->halt_falcon); - if (ret < 0) - return ret; - /* - * Unload blob will return this error code - it is not an error - * and the expected behavior on RM as well - */ - if (ret && ret != 0x1d) { - nvkm_error(subdev, "HS unload failed, ret 0x%08x\n", ret); - return -EINVAL; - } - nvkm_debug(subdev, "HS unload blob completed\n"); - } - - for (i = 0; i < NVKM_SECBOOT_FALCON_END; i++) - acr->falcon_state[i] = NON_SECURE; - - sb->wpr_set = false; - - return 0; -} - -/** - * Check if the WPR region has been indeed set by the ACR firmware, and - * matches where it should be. - */ -static bool -acr_r352_wpr_is_set(const struct acr_r352 *acr, const struct nvkm_secboot *sb) -{ - const struct nvkm_subdev *subdev = &sb->subdev; - const struct nvkm_device *device = subdev->device; - u64 wpr_lo, wpr_hi; - u64 wpr_range_lo, wpr_range_hi; - - nvkm_wr32(device, 0x100cd4, 0x2); - wpr_lo = (nvkm_rd32(device, 0x100cd4) & ~0xff); - wpr_lo <<= 8; - nvkm_wr32(device, 0x100cd4, 0x3); - wpr_hi = (nvkm_rd32(device, 0x100cd4) & ~0xff); - wpr_hi <<= 8; - - if (sb->wpr_size != 0) { - wpr_range_lo = sb->wpr_addr; - wpr_range_hi = wpr_range_lo + sb->wpr_size; - } else { - wpr_range_lo = acr->ls_blob->addr; - wpr_range_hi = wpr_range_lo + acr->ls_blob->size; - } - - return (wpr_lo >= wpr_range_lo && wpr_lo < wpr_range_hi && - wpr_hi > wpr_range_lo && wpr_hi <= wpr_range_hi); -} - -static int -acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb) -{ - const struct nvkm_subdev *subdev = &sb->subdev; - unsigned long managed_falcons = acr->base.managed_falcons; - int falcon_id; - int ret; - - if (sb->wpr_set) - return 0; - - /* Make sure all blobs are ready */ - ret = acr_r352_load_blobs(acr, sb); - if (ret) - return ret; - - nvkm_debug(subdev, "running HS load blob\n"); - ret = sb->func->run_blob(sb, acr->load_blob, sb->boot_falcon); - /* clear halt interrupt */ - nvkm_falcon_clear_interrupt(sb->boot_falcon, 0x10); - sb->wpr_set = acr_r352_wpr_is_set(acr, sb); - if (ret < 0) { - return ret; - } else if (ret > 0) { - nvkm_error(subdev, "HS load failed, ret 0x%08x\n", ret); - return -EINVAL; - } - nvkm_debug(subdev, "HS load blob completed\n"); - /* WPR must be set at this point */ - if (!sb->wpr_set) { - nvkm_error(subdev, "ACR blob completed but WPR not set!\n"); - return -EINVAL; - } - - /* Run LS firmwares post_run hooks */ - for_each_set_bit(falcon_id, &managed_falcons, NVKM_SECBOOT_FALCON_END) { - const struct acr_r352_ls_func *func = - acr->func->ls_func[falcon_id]; - - if (func->post_run) { - ret = func->post_run(&acr->base, sb); - if (ret) - return ret; - } - } - - return 0; -} - -/** - * acr_r352_reset_nopmu - dummy reset method when no PMU firmware is loaded - * - * Reset is done by re-executing secure boot from scratch, with lazy bootstrap - * disabled. This has the effect of making all managed falcons ready-to-run. - */ -static int -acr_r352_reset_nopmu(struct acr_r352 *acr, struct nvkm_secboot *sb, - unsigned long falcon_mask) -{ - int falcon; - int ret; - - /* - * Perform secure boot each time we are called on FECS. Since only FECS - * and GPCCS are managed and started together, this ought to be safe. - */ - if (!(falcon_mask & BIT(NVKM_SECBOOT_FALCON_FECS))) - goto end; - - ret = acr_r352_shutdown(acr, sb); - if (ret) - return ret; - - ret = acr_r352_bootstrap(acr, sb); - if (ret) - return ret; - -end: - for_each_set_bit(falcon, &falcon_mask, NVKM_SECBOOT_FALCON_END) { - acr->falcon_state[falcon] = RESET; - } - return 0; -} - -/* - * acr_r352_reset() - execute secure boot from the prepared state - * - * Load the HS bootloader and ask the falcon to run it. This will in turn - * load the HS firmware and run it, so once the falcon stops all the managed - * falcons should have their LS firmware loaded and be ready to run. - */ -static int -acr_r352_reset(struct nvkm_acr *_acr, struct nvkm_secboot *sb, - unsigned long falcon_mask) -{ - struct acr_r352 *acr = acr_r352(_acr); - struct nvkm_msgqueue *queue; - int falcon; - bool wpr_already_set = sb->wpr_set; - int ret; - - /* Make sure secure boot is performed */ - ret = acr_r352_bootstrap(acr, sb); - if (ret) - return ret; - - /* No PMU interface? */ - if (!nvkm_secboot_is_managed(sb, _acr->boot_falcon)) { - /* Redo secure boot entirely if it was already done */ - if (wpr_already_set) - return acr_r352_reset_nopmu(acr, sb, falcon_mask); - /* Else return the result of the initial invokation */ - else - return ret; - } - - switch (_acr->boot_falcon) { - case NVKM_SECBOOT_FALCON_PMU: - queue = sb->subdev.device->pmu->queue; - break; - case NVKM_SECBOOT_FALCON_SEC2: - queue = sb->subdev.device->sec2->queue; - break; - default: - return -EINVAL; - } - - /* Otherwise just ask the LS firmware to reset the falcon */ - for_each_set_bit(falcon, &falcon_mask, NVKM_SECBOOT_FALCON_END) - nvkm_debug(&sb->subdev, "resetting %s falcon\n", - nvkm_secboot_falcon_name[falcon]); - ret = nvkm_msgqueue_acr_boot_falcons(queue, falcon_mask); - if (ret) { - nvkm_error(&sb->subdev, "error during falcon reset: %d\n", ret); - return ret; - } - nvkm_debug(&sb->subdev, "falcon reset done\n"); - - return 0; -} - -static int -acr_r352_fini(struct nvkm_acr *_acr, struct nvkm_secboot *sb, bool suspend) -{ - struct acr_r352 *acr = acr_r352(_acr); - - return acr_r352_shutdown(acr, sb); -} - -static void -acr_r352_dtor(struct nvkm_acr *_acr) -{ - struct acr_r352 *acr = acr_r352(_acr); - - nvkm_gpuobj_del(&acr->unload_blob); - - if (_acr->boot_falcon != NVKM_SECBOOT_FALCON_PMU) - kfree(acr->hsbl_unload_blob); - kfree(acr->hsbl_blob); - nvkm_gpuobj_del(&acr->load_blob); - nvkm_gpuobj_del(&acr->ls_blob); - - kfree(acr); -} - -static const struct acr_r352_lsf_func -acr_r352_ls_fecs_func_0 = { - .generate_bl_desc = acr_r352_generate_flcn_bl_desc, - .bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc), -}; - -const struct acr_r352_ls_func -acr_r352_ls_fecs_func = { - .load = acr_ls_ucode_load_fecs, - .version_max = 0, - .version = { - &acr_r352_ls_fecs_func_0, - } -}; - -static const struct acr_r352_lsf_func -acr_r352_ls_gpccs_func_0 = { - .generate_bl_desc = acr_r352_generate_flcn_bl_desc, - .bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc), - /* GPCCS will be loaded using PRI */ - .lhdr_flags = LSF_FLAG_FORCE_PRIV_LOAD, -}; - -const struct acr_r352_ls_func -acr_r352_ls_gpccs_func = { - .load = acr_ls_ucode_load_gpccs, - .version_max = 0, - .version = { - &acr_r352_ls_gpccs_func_0, - } -}; - - - -/** - * struct acr_r352_pmu_bl_desc - PMU DMEM bootloader descriptor - * @dma_idx: DMA context to be used by BL while loading code/data - * @code_dma_base: 256B-aligned Physical FB Address where code is located - * @total_code_size: total size of the code part in the ucode - * @code_size_to_load: size of the code part to load in PMU IMEM. - * @code_entry_point: entry point in the code. - * @data_dma_base: Physical FB address where data part of ucode is located - * @data_size: Total size of the data portion. - * @overlay_dma_base: Physical Fb address for resident code present in ucode - * @argc: Total number of args - * @argv: offset where args are copied into PMU's DMEM. - * - * Structure used by the PMU bootloader to load the rest of the code - */ -struct acr_r352_pmu_bl_desc { - u32 dma_idx; - u32 code_dma_base; - u32 code_size_total; - u32 code_size_to_load; - u32 code_entry_point; - u32 data_dma_base; - u32 data_size; - u32 overlay_dma_base; - u32 argc; - u32 argv; - u16 code_dma_base1; - u16 data_dma_base1; - u16 overlay_dma_base1; -}; - -/** - * acr_r352_generate_pmu_bl_desc() - populate a DMEM BL descriptor for PMU LS image - * - */ -static void -acr_r352_generate_pmu_bl_desc(const struct nvkm_acr *acr, - const struct ls_ucode_img *img, u64 wpr_addr, - void *_desc) -{ - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; - const struct nvkm_pmu *pmu = acr->subdev->device->pmu; - struct acr_r352_pmu_bl_desc *desc = _desc; - u64 base; - u64 addr_code; - u64 addr_data; - u32 addr_args; - - base = wpr_addr + img->ucode_off + pdesc->app_start_offset; - addr_code = (base + pdesc->app_resident_code_offset) >> 8; - addr_data = (base + pdesc->app_resident_data_offset) >> 8; - addr_args = pmu->falcon->data.limit; - addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE; - - desc->dma_idx = FALCON_DMAIDX_UCODE; - desc->code_dma_base = lower_32_bits(addr_code); - desc->code_dma_base1 = upper_32_bits(addr_code); - desc->code_size_total = pdesc->app_size; - desc->code_size_to_load = pdesc->app_resident_code_size; - desc->code_entry_point = pdesc->app_imem_entry; - desc->data_dma_base = lower_32_bits(addr_data); - desc->data_dma_base1 = upper_32_bits(addr_data); - desc->data_size = pdesc->app_resident_data_size; - desc->overlay_dma_base = lower_32_bits(addr_code); - desc->overlay_dma_base1 = upper_32_bits(addr_code); - desc->argc = 1; - desc->argv = addr_args; -} - -static const struct acr_r352_lsf_func -acr_r352_ls_pmu_func_0 = { - .generate_bl_desc = acr_r352_generate_pmu_bl_desc, - .bl_desc_size = sizeof(struct acr_r352_pmu_bl_desc), -}; - -static const struct acr_r352_ls_func -acr_r352_ls_pmu_func = { - .load = acr_ls_ucode_load_pmu, - .post_run = acr_ls_pmu_post_run, - .version_max = 0, - .version = { - &acr_r352_ls_pmu_func_0, - } -}; - -const struct acr_r352_func -acr_r352_func = { - .fixup_hs_desc = acr_r352_fixup_hs_desc, - .generate_hs_bl_desc = acr_r352_generate_hs_bl_desc, - .hs_bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc), - .ls_ucode_img_load = acr_r352_ls_ucode_img_load, - .ls_fill_headers = acr_r352_ls_fill_headers, - .ls_write_wpr = acr_r352_ls_write_wpr, - .ls_func = { - [NVKM_SECBOOT_FALCON_FECS] = &acr_r352_ls_fecs_func, - [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r352_ls_gpccs_func, - [NVKM_SECBOOT_FALCON_PMU] = &acr_r352_ls_pmu_func, - }, -}; - -static const struct nvkm_acr_func -acr_r352_base_func = { - .dtor = acr_r352_dtor, - .fini = acr_r352_fini, - .load = acr_r352_load, - .reset = acr_r352_reset, -}; - -struct nvkm_acr * -acr_r352_new_(const struct acr_r352_func *func, - enum nvkm_secboot_falcon boot_falcon, - unsigned long managed_falcons) -{ - struct acr_r352 *acr; - int i; - - /* Check that all requested falcons are supported */ - for_each_set_bit(i, &managed_falcons, NVKM_SECBOOT_FALCON_END) { - if (!func->ls_func[i]) - return ERR_PTR(-ENOTSUPP); - } - - acr = kzalloc(sizeof(*acr), GFP_KERNEL); - if (!acr) - return ERR_PTR(-ENOMEM); - - acr->base.boot_falcon = boot_falcon; - acr->base.managed_falcons = managed_falcons; - acr->base.func = &acr_r352_base_func; - acr->func = func; - - return &acr->base; -} - -struct nvkm_acr * -acr_r352_new(unsigned long managed_falcons) -{ - return acr_r352_new_(&acr_r352_func, NVKM_SECBOOT_FALCON_PMU, - managed_falcons); -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h deleted file mode 100644 index e516cab849dd..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef __NVKM_SECBOOT_ACR_R352_H__ -#define __NVKM_SECBOOT_ACR_R352_H__ - -#include "acr.h" -#include "ls_ucode.h" -#include "hs_ucode.h" - -struct ls_ucode_img; - -#define ACR_R352_MAX_APPS 8 - -#define LSF_FLAG_LOAD_CODE_AT_0 1 -#define LSF_FLAG_DMACTL_REQ_CTX 4 -#define LSF_FLAG_FORCE_PRIV_LOAD 8 - -static inline u32 -hsf_load_header_app_off(const struct hsf_load_header *hdr, u32 app) -{ - return hdr->apps[app]; -} - -static inline u32 -hsf_load_header_app_size(const struct hsf_load_header *hdr, u32 app) -{ - return hdr->apps[hdr->num_apps + app]; -} - -/** - * struct acr_r352_lsf_func - manages a specific LS firmware version - * - * @generate_bl_desc: function called on a block of bl_desc_size to generate the - * proper bootloader descriptor for this LS firmware - * @bl_desc_size: size of the bootloader descriptor - * @lhdr_flags: LS flags - */ -struct acr_r352_lsf_func { - void (*generate_bl_desc)(const struct nvkm_acr *, - const struct ls_ucode_img *, u64, void *); - u32 bl_desc_size; - u32 lhdr_flags; -}; - -/** - * struct acr_r352_ls_func - manages a single LS falcon - * - * @load: load the external firmware into a ls_ucode_img - * @post_run: hook called right after the ACR is executed - */ -struct acr_r352_ls_func { - int (*load)(const struct nvkm_secboot *, int maxver, - struct ls_ucode_img *); - int (*post_run)(const struct nvkm_acr *, const struct nvkm_secboot *); - int version_max; - const struct acr_r352_lsf_func *version[]; -}; - -struct acr_r352; - -/** - * struct acr_r352_func - manages nuances between ACR versions - * - * @generate_hs_bl_desc: function called on a block of bl_desc_size to generate - * the proper HS bootloader descriptor - * @hs_bl_desc_size: size of the HS bootloader descriptor - */ -struct acr_r352_func { - void (*generate_hs_bl_desc)(const struct hsf_load_header *, void *, - u64); - void (*fixup_hs_desc)(struct acr_r352 *, struct nvkm_secboot *, void *); - u32 hs_bl_desc_size; - bool shadow_blob; - - struct ls_ucode_img *(*ls_ucode_img_load)(const struct acr_r352 *, - const struct nvkm_secboot *, - enum nvkm_secboot_falcon); - int (*ls_fill_headers)(struct acr_r352 *, struct list_head *); - int (*ls_write_wpr)(struct acr_r352 *, struct list_head *, - struct nvkm_gpuobj *, u64); - - const struct acr_r352_ls_func *ls_func[NVKM_SECBOOT_FALCON_END]; -}; - -/** - * struct acr_r352 - ACR data for driver release 352 (and beyond) - */ -struct acr_r352 { - struct nvkm_acr base; - const struct acr_r352_func *func; - - /* - * HS FW - lock WPR region (dGPU only) and load LS FWs - * on Tegra the HS FW copies the LS blob into the fixed WPR instead - */ - struct nvkm_gpuobj *load_blob; - struct { - struct hsf_load_header load_bl_header; - u32 __load_apps[ACR_R352_MAX_APPS * 2]; - }; - - /* HS FW - unlock WPR region (dGPU only) */ - struct nvkm_gpuobj *unload_blob; - struct { - struct hsf_load_header unload_bl_header; - u32 __unload_apps[ACR_R352_MAX_APPS * 2]; - }; - - /* HS bootloader */ - void *hsbl_blob; - - /* HS bootloader for unload blob, if using a different falcon */ - void *hsbl_unload_blob; - - /* LS FWs, to be loaded by the HS ACR */ - struct nvkm_gpuobj *ls_blob; - - /* Firmware already loaded? */ - bool firmware_ok; - - /* Falcons to lazy-bootstrap */ - u32 lazy_bootstrap; - - /* To keep track of the state of all managed falcons */ - enum { - /* In non-secure state, no firmware loaded, no privileges*/ - NON_SECURE = 0, - /* In low-secure mode and ready to be started */ - RESET, - /* In low-secure mode and running */ - RUNNING, - } falcon_state[NVKM_SECBOOT_FALCON_END]; -}; -#define acr_r352(acr) container_of(acr, struct acr_r352, base) - -struct nvkm_acr *acr_r352_new_(const struct acr_r352_func *, - enum nvkm_secboot_falcon, unsigned long); - -struct ls_ucode_img *acr_r352_ls_ucode_img_load(const struct acr_r352 *, - const struct nvkm_secboot *, - enum nvkm_secboot_falcon); -int acr_r352_ls_fill_headers(struct acr_r352 *, struct list_head *); -int acr_r352_ls_write_wpr(struct acr_r352 *, struct list_head *, - struct nvkm_gpuobj *, u64); - -void acr_r352_fixup_hs_desc(struct acr_r352 *, struct nvkm_secboot *, void *); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c deleted file mode 100644 index f6b2d20d7fc3..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "acr_r361.h" - -#include <engine/falcon.h> -#include <core/msgqueue.h> -#include <subdev/pmu.h> -#include <engine/sec2.h> - -static void -acr_r361_generate_flcn_bl_desc(const struct nvkm_acr *acr, - const struct ls_ucode_img *img, u64 wpr_addr, - void *_desc) -{ - struct acr_r361_flcn_bl_desc *desc = _desc; - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; - u64 base, addr_code, addr_data; - - base = wpr_addr + img->ucode_off + pdesc->app_start_offset; - addr_code = base + pdesc->app_resident_code_offset; - addr_data = base + pdesc->app_resident_data_offset; - - desc->ctx_dma = FALCON_DMAIDX_UCODE; - desc->code_dma_base = u64_to_flcn64(addr_code); - desc->non_sec_code_off = pdesc->app_resident_code_offset; - desc->non_sec_code_size = pdesc->app_resident_code_size; - desc->code_entry_point = pdesc->app_imem_entry; - desc->data_dma_base = u64_to_flcn64(addr_data); - desc->data_size = pdesc->app_resident_data_size; -} - -void -acr_r361_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc, - u64 offset) -{ - struct acr_r361_flcn_bl_desc *bl_desc = _bl_desc; - - bl_desc->ctx_dma = FALCON_DMAIDX_VIRT; - bl_desc->code_dma_base = u64_to_flcn64(offset); - bl_desc->non_sec_code_off = hdr->non_sec_code_off; - bl_desc->non_sec_code_size = hdr->non_sec_code_size; - bl_desc->sec_code_off = hsf_load_header_app_off(hdr, 0); - bl_desc->sec_code_size = hsf_load_header_app_size(hdr, 0); - bl_desc->code_entry_point = 0; - bl_desc->data_dma_base = u64_to_flcn64(offset + hdr->data_dma_base); - bl_desc->data_size = hdr->data_size; -} - -static const struct acr_r352_lsf_func -acr_r361_ls_fecs_func_0 = { - .generate_bl_desc = acr_r361_generate_flcn_bl_desc, - .bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc), -}; - -const struct acr_r352_ls_func -acr_r361_ls_fecs_func = { - .load = acr_ls_ucode_load_fecs, - .version_max = 0, - .version = { - &acr_r361_ls_fecs_func_0, - } -}; - -static const struct acr_r352_lsf_func -acr_r361_ls_gpccs_func_0 = { - .generate_bl_desc = acr_r361_generate_flcn_bl_desc, - .bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc), - /* GPCCS will be loaded using PRI */ - .lhdr_flags = LSF_FLAG_FORCE_PRIV_LOAD, -}; - -const struct acr_r352_ls_func -acr_r361_ls_gpccs_func = { - .load = acr_ls_ucode_load_gpccs, - .version_max = 0, - .version = { - &acr_r361_ls_gpccs_func_0, - } -}; - -struct acr_r361_pmu_bl_desc { - u32 reserved; - u32 dma_idx; - struct flcn_u64 code_dma_base; - u32 total_code_size; - u32 code_size_to_load; - u32 code_entry_point; - struct flcn_u64 data_dma_base; - u32 data_size; - struct flcn_u64 overlay_dma_base; - u32 argc; - u32 argv; -}; - -static void -acr_r361_generate_pmu_bl_desc(const struct nvkm_acr *acr, - const struct ls_ucode_img *img, u64 wpr_addr, - void *_desc) -{ - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; - const struct nvkm_pmu *pmu = acr->subdev->device->pmu; - struct acr_r361_pmu_bl_desc *desc = _desc; - u64 base, addr_code, addr_data; - u32 addr_args; - - base = wpr_addr + img->ucode_off + pdesc->app_start_offset; - addr_code = base + pdesc->app_resident_code_offset; - addr_data = base + pdesc->app_resident_data_offset; - addr_args = pmu->falcon->data.limit; - addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE; - - desc->dma_idx = FALCON_DMAIDX_UCODE; - desc->code_dma_base = u64_to_flcn64(addr_code); - desc->total_code_size = pdesc->app_size; - desc->code_size_to_load = pdesc->app_resident_code_size; - desc->code_entry_point = pdesc->app_imem_entry; - desc->data_dma_base = u64_to_flcn64(addr_data); - desc->data_size = pdesc->app_resident_data_size; - desc->overlay_dma_base = u64_to_flcn64(addr_code); - desc->argc = 1; - desc->argv = addr_args; -} - -static const struct acr_r352_lsf_func -acr_r361_ls_pmu_func_0 = { - .generate_bl_desc = acr_r361_generate_pmu_bl_desc, - .bl_desc_size = sizeof(struct acr_r361_pmu_bl_desc), -}; - -const struct acr_r352_ls_func -acr_r361_ls_pmu_func = { - .load = acr_ls_ucode_load_pmu, - .post_run = acr_ls_pmu_post_run, - .version_max = 0, - .version = { - &acr_r361_ls_pmu_func_0, - } -}; - -static void -acr_r361_generate_sec2_bl_desc(const struct nvkm_acr *acr, - const struct ls_ucode_img *img, u64 wpr_addr, - void *_desc) -{ - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; - const struct nvkm_sec2 *sec = acr->subdev->device->sec2; - struct acr_r361_pmu_bl_desc *desc = _desc; - u64 base, addr_code, addr_data; - u32 addr_args; - - base = wpr_addr + img->ucode_off + pdesc->app_start_offset; - /* For some reason we should not add app_resident_code_offset here */ - addr_code = base; - addr_data = base + pdesc->app_resident_data_offset; - addr_args = sec->falcon->data.limit; - addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE; - - desc->dma_idx = FALCON_SEC2_DMAIDX_UCODE; - desc->code_dma_base = u64_to_flcn64(addr_code); - desc->total_code_size = pdesc->app_size; - desc->code_size_to_load = pdesc->app_resident_code_size; - desc->code_entry_point = pdesc->app_imem_entry; - desc->data_dma_base = u64_to_flcn64(addr_data); - desc->data_size = pdesc->app_resident_data_size; - desc->overlay_dma_base = u64_to_flcn64(addr_code); - desc->argc = 1; - /* args are stored at the beginning of EMEM */ - desc->argv = 0x01000000; -} - -const struct acr_r352_lsf_func -acr_r361_ls_sec2_func_0 = { - .generate_bl_desc = acr_r361_generate_sec2_bl_desc, - .bl_desc_size = sizeof(struct acr_r361_pmu_bl_desc), -}; - -static const struct acr_r352_ls_func -acr_r361_ls_sec2_func = { - .load = acr_ls_ucode_load_sec2, - .post_run = acr_ls_sec2_post_run, - .version_max = 0, - .version = { - &acr_r361_ls_sec2_func_0, - } -}; - - -const struct acr_r352_func -acr_r361_func = { - .fixup_hs_desc = acr_r352_fixup_hs_desc, - .generate_hs_bl_desc = acr_r361_generate_hs_bl_desc, - .hs_bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc), - .ls_ucode_img_load = acr_r352_ls_ucode_img_load, - .ls_fill_headers = acr_r352_ls_fill_headers, - .ls_write_wpr = acr_r352_ls_write_wpr, - .ls_func = { - [NVKM_SECBOOT_FALCON_FECS] = &acr_r361_ls_fecs_func, - [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r361_ls_gpccs_func, - [NVKM_SECBOOT_FALCON_PMU] = &acr_r361_ls_pmu_func, - [NVKM_SECBOOT_FALCON_SEC2] = &acr_r361_ls_sec2_func, - }, -}; - -struct nvkm_acr * -acr_r361_new(unsigned long managed_falcons) -{ - return acr_r352_new_(&acr_r361_func, NVKM_SECBOOT_FALCON_PMU, - managed_falcons); -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.h deleted file mode 100644 index 38dec93779c8..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVKM_SECBOOT_ACR_R361_H__ -#define __NVKM_SECBOOT_ACR_R361_H__ - -#include "acr_r352.h" - -/** - * struct acr_r361_flcn_bl_desc - DMEM bootloader descriptor - * @signature: 16B signature for secure code. 0s if no secure code - * @ctx_dma: DMA context to be used by BL while loading code/data - * @code_dma_base: 256B-aligned Physical FB Address where code is located - * (falcon's $xcbase register) - * @non_sec_code_off: offset from code_dma_base where the non-secure code is - * located. The offset must be multiple of 256 to help perf - * @non_sec_code_size: the size of the nonSecure code part. - * @sec_code_off: offset from code_dma_base where the secure code is - * located. The offset must be multiple of 256 to help perf - * @sec_code_size: offset from code_dma_base where the secure code is - * located. The offset must be multiple of 256 to help perf - * @code_entry_point: code entry point which will be invoked by BL after - * code is loaded. - * @data_dma_base: 256B aligned Physical FB Address where data is located. - * (falcon's $xdbase register) - * @data_size: size of data block. Should be multiple of 256B - * - * Structure used by the bootloader to load the rest of the code. This has - * to be filled by host and copied into DMEM at offset provided in the - * hsflcn_bl_desc.bl_desc_dmem_load_off. - */ -struct acr_r361_flcn_bl_desc { - u32 reserved[4]; - u32 signature[4]; - u32 ctx_dma; - struct flcn_u64 code_dma_base; - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - struct flcn_u64 data_dma_base; - u32 data_size; -}; - -void acr_r361_generate_hs_bl_desc(const struct hsf_load_header *, void *, u64); - -extern const struct acr_r352_ls_func acr_r361_ls_fecs_func; -extern const struct acr_r352_ls_func acr_r361_ls_gpccs_func; -extern const struct acr_r352_ls_func acr_r361_ls_pmu_func; -extern const struct acr_r352_lsf_func acr_r361_ls_sec2_func_0; -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r364.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r364.c deleted file mode 100644 index 30cf04109991..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r364.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "acr_r361.h" - -#include <core/gpuobj.h> - -/* - * r364 ACR: hsflcn_desc structure has changed to introduce the shadow_mem - * parameter. - */ - -struct acr_r364_hsflcn_desc { - union { - u8 reserved_dmem[0x200]; - u32 signatures[4]; - } ucode_reserved_space; - u32 wpr_region_id; - u32 wpr_offset; - u32 mmu_memory_range; - struct { - u32 no_regions; - struct { - u32 start_addr; - u32 end_addr; - u32 region_id; - u32 read_mask; - u32 write_mask; - u32 client_mask; - u32 shadow_mem_start_addr; - } region_props[2]; - } regions; - u32 ucode_blob_size; - u64 ucode_blob_base __aligned(8); - struct { - u32 vpr_enabled; - u32 vpr_start; - u32 vpr_end; - u32 hdcp_policies; - } vpr_desc; -}; - -static void -acr_r364_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb, - void *_desc) -{ - struct acr_r364_hsflcn_desc *desc = _desc; - struct nvkm_gpuobj *ls_blob = acr->ls_blob; - - /* WPR region information if WPR is not fixed */ - if (sb->wpr_size == 0) { - u64 wpr_start = ls_blob->addr; - u64 wpr_end = ls_blob->addr + ls_blob->size; - - if (acr->func->shadow_blob) - wpr_start += ls_blob->size / 2; - - desc->wpr_region_id = 1; - desc->regions.no_regions = 2; - desc->regions.region_props[0].start_addr = wpr_start >> 8; - desc->regions.region_props[0].end_addr = wpr_end >> 8; - desc->regions.region_props[0].region_id = 1; - desc->regions.region_props[0].read_mask = 0xf; - desc->regions.region_props[0].write_mask = 0xc; - desc->regions.region_props[0].client_mask = 0x2; - if (acr->func->shadow_blob) - desc->regions.region_props[0].shadow_mem_start_addr = - ls_blob->addr >> 8; - else - desc->regions.region_props[0].shadow_mem_start_addr = 0; - } else { - desc->ucode_blob_base = ls_blob->addr; - desc->ucode_blob_size = ls_blob->size; - } -} - -const struct acr_r352_func -acr_r364_func = { - .fixup_hs_desc = acr_r364_fixup_hs_desc, - .generate_hs_bl_desc = acr_r361_generate_hs_bl_desc, - .hs_bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc), - .ls_ucode_img_load = acr_r352_ls_ucode_img_load, - .ls_fill_headers = acr_r352_ls_fill_headers, - .ls_write_wpr = acr_r352_ls_write_wpr, - .ls_func = { - [NVKM_SECBOOT_FALCON_FECS] = &acr_r361_ls_fecs_func, - [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r361_ls_gpccs_func, - [NVKM_SECBOOT_FALCON_PMU] = &acr_r361_ls_pmu_func, - }, -}; - - -struct nvkm_acr * -acr_r364_new(unsigned long managed_falcons) -{ - return acr_r352_new_(&acr_r364_func, NVKM_SECBOOT_FALCON_PMU, - managed_falcons); -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c deleted file mode 100644 index 472ced29da7e..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c +++ /dev/null @@ -1,418 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "acr_r367.h" -#include "acr_r361.h" -#include "acr_r370.h" - -#include <core/gpuobj.h> - -/* - * r367 ACR: new LS signature format requires a rewrite of LS firmware and - * blob creation functions. Also the hsflcn_desc layout has changed slightly. - */ - -#define LSF_LSB_DEPMAP_SIZE 11 - -/** - * struct acr_r367_lsf_lsb_header - LS firmware header - * - * See also struct acr_r352_lsf_lsb_header for documentation. - */ -struct acr_r367_lsf_lsb_header { - /** - * LS falcon signatures - * @prd_keys: signature to use in production mode - * @dgb_keys: signature to use in debug mode - * @b_prd_present: whether the production key is present - * @b_dgb_present: whether the debug key is present - * @falcon_id: ID of the falcon the ucode applies to - */ - struct { - u8 prd_keys[2][16]; - u8 dbg_keys[2][16]; - u32 b_prd_present; - u32 b_dbg_present; - u32 falcon_id; - u32 supports_versioning; - u32 version; - u32 depmap_count; - u8 depmap[LSF_LSB_DEPMAP_SIZE * 2 * 4]; - u8 kdf[16]; - } signature; - u32 ucode_off; - u32 ucode_size; - u32 data_size; - u32 bl_code_size; - u32 bl_imem_off; - u32 bl_data_off; - u32 bl_data_size; - u32 app_code_off; - u32 app_code_size; - u32 app_data_off; - u32 app_data_size; - u32 flags; -}; - -/** - * struct acr_r367_lsf_wpr_header - LS blob WPR Header - * - * See also struct acr_r352_lsf_wpr_header for documentation. - */ -struct acr_r367_lsf_wpr_header { - u32 falcon_id; - u32 lsb_offset; - u32 bootstrap_owner; - u32 lazy_bootstrap; - u32 bin_version; - u32 status; -#define LSF_IMAGE_STATUS_NONE 0 -#define LSF_IMAGE_STATUS_COPY 1 -#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2 -#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3 -#define LSF_IMAGE_STATUS_VALIDATION_DONE 4 -#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5 -#define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6 -#define LSF_IMAGE_STATUS_REVOCATION_CHECK_FAILED 7 -}; - -/** - * struct ls_ucode_img_r367 - ucode image augmented with r367 headers - */ -struct ls_ucode_img_r367 { - struct ls_ucode_img base; - - const struct acr_r352_lsf_func *func; - - struct acr_r367_lsf_wpr_header wpr_header; - struct acr_r367_lsf_lsb_header lsb_header; -}; -#define ls_ucode_img_r367(i) container_of(i, struct ls_ucode_img_r367, base) - -struct ls_ucode_img * -acr_r367_ls_ucode_img_load(const struct acr_r352 *acr, - const struct nvkm_secboot *sb, - enum nvkm_secboot_falcon falcon_id) -{ - const struct nvkm_subdev *subdev = acr->base.subdev; - const struct acr_r352_ls_func *func = acr->func->ls_func[falcon_id]; - struct ls_ucode_img_r367 *img; - int ret; - - img = kzalloc(sizeof(*img), GFP_KERNEL); - if (!img) - return ERR_PTR(-ENOMEM); - - img->base.falcon_id = falcon_id; - - ret = func->load(sb, func->version_max, &img->base); - if (ret < 0) { - kfree(img->base.ucode_data); - kfree(img->base.sig); - kfree(img); - return ERR_PTR(ret); - } - - img->func = func->version[ret]; - - /* Check that the signature size matches our expectations... */ - if (img->base.sig_size != sizeof(img->lsb_header.signature)) { - nvkm_error(subdev, "invalid signature size for %s falcon!\n", - nvkm_secboot_falcon_name[falcon_id]); - return ERR_PTR(-EINVAL); - } - - /* Copy signature to the right place */ - memcpy(&img->lsb_header.signature, img->base.sig, img->base.sig_size); - - /* not needed? the signature should already have the right value */ - img->lsb_header.signature.falcon_id = falcon_id; - - return &img->base; -} - -#define LSF_LSB_HEADER_ALIGN 256 -#define LSF_BL_DATA_ALIGN 256 -#define LSF_BL_DATA_SIZE_ALIGN 256 -#define LSF_BL_CODE_SIZE_ALIGN 256 -#define LSF_UCODE_DATA_ALIGN 4096 - -static u32 -acr_r367_ls_img_fill_headers(struct acr_r352 *acr, - struct ls_ucode_img_r367 *img, u32 offset) -{ - struct ls_ucode_img *_img = &img->base; - struct acr_r367_lsf_wpr_header *whdr = &img->wpr_header; - struct acr_r367_lsf_lsb_header *lhdr = &img->lsb_header; - struct ls_ucode_img_desc *desc = &_img->ucode_desc; - const struct acr_r352_lsf_func *func = img->func; - - /* Fill WPR header */ - whdr->falcon_id = _img->falcon_id; - whdr->bootstrap_owner = acr->base.boot_falcon; - whdr->bin_version = lhdr->signature.version; - whdr->status = LSF_IMAGE_STATUS_COPY; - - /* Skip bootstrapping falcons started by someone else than ACR */ - if (acr->lazy_bootstrap & BIT(_img->falcon_id)) - whdr->lazy_bootstrap = 1; - - /* Align, save off, and include an LSB header size */ - offset = ALIGN(offset, LSF_LSB_HEADER_ALIGN); - whdr->lsb_offset = offset; - offset += sizeof(*lhdr); - - /* - * Align, save off, and include the original (static) ucode - * image size - */ - offset = ALIGN(offset, LSF_UCODE_DATA_ALIGN); - _img->ucode_off = lhdr->ucode_off = offset; - offset += _img->ucode_size; - - /* - * For falcons that use a boot loader (BL), we append a loader - * desc structure on the end of the ucode image and consider - * this the boot loader data. The host will then copy the loader - * desc args to this space within the WPR region (before locking - * down) and the HS bin will then copy them to DMEM 0 for the - * loader. - */ - lhdr->bl_code_size = ALIGN(desc->bootloader_size, - LSF_BL_CODE_SIZE_ALIGN); - lhdr->ucode_size = ALIGN(desc->app_resident_data_offset, - LSF_BL_CODE_SIZE_ALIGN) + lhdr->bl_code_size; - lhdr->data_size = ALIGN(desc->app_size, LSF_BL_CODE_SIZE_ALIGN) + - lhdr->bl_code_size - lhdr->ucode_size; - /* - * Though the BL is located at 0th offset of the image, the VA - * is different to make sure that it doesn't collide the actual - * OS VA range - */ - lhdr->bl_imem_off = desc->bootloader_imem_offset; - lhdr->app_code_off = desc->app_start_offset + - desc->app_resident_code_offset; - lhdr->app_code_size = desc->app_resident_code_size; - lhdr->app_data_off = desc->app_start_offset + - desc->app_resident_data_offset; - lhdr->app_data_size = desc->app_resident_data_size; - - lhdr->flags = func->lhdr_flags; - if (_img->falcon_id == acr->base.boot_falcon) - lhdr->flags |= LSF_FLAG_DMACTL_REQ_CTX; - - /* Align and save off BL descriptor size */ - lhdr->bl_data_size = ALIGN(func->bl_desc_size, LSF_BL_DATA_SIZE_ALIGN); - - /* - * Align, save off, and include the additional BL data - */ - offset = ALIGN(offset, LSF_BL_DATA_ALIGN); - lhdr->bl_data_off = offset; - offset += lhdr->bl_data_size; - - return offset; -} - -int -acr_r367_ls_fill_headers(struct acr_r352 *acr, struct list_head *imgs) -{ - struct ls_ucode_img_r367 *img; - struct list_head *l; - u32 count = 0; - u32 offset; - - /* Count the number of images to manage */ - list_for_each(l, imgs) - count++; - - /* - * Start with an array of WPR headers at the base of the WPR. - * The expectation here is that the secure falcon will do a single DMA - * read of this array and cache it internally so it's ok to pack these. - * Also, we add 1 to the falcon count to indicate the end of the array. - */ - offset = sizeof(img->wpr_header) * (count + 1); - - /* - * Walk the managed falcons, accounting for the LSB structs - * as well as the ucode images. - */ - list_for_each_entry(img, imgs, base.node) { - offset = acr_r367_ls_img_fill_headers(acr, img, offset); - } - - return offset; -} - -int -acr_r367_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, - struct nvkm_gpuobj *wpr_blob, u64 wpr_addr) -{ - struct ls_ucode_img *_img; - u32 pos = 0; - u32 max_desc_size = 0; - u8 *gdesc; - - list_for_each_entry(_img, imgs, node) { - struct ls_ucode_img_r367 *img = ls_ucode_img_r367(_img); - const struct acr_r352_lsf_func *ls_func = img->func; - - max_desc_size = max(max_desc_size, ls_func->bl_desc_size); - } - - gdesc = kmalloc(max_desc_size, GFP_KERNEL); - if (!gdesc) - return -ENOMEM; - - nvkm_kmap(wpr_blob); - - list_for_each_entry(_img, imgs, node) { - struct ls_ucode_img_r367 *img = ls_ucode_img_r367(_img); - const struct acr_r352_lsf_func *ls_func = img->func; - - nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header, - sizeof(img->wpr_header)); - - nvkm_gpuobj_memcpy_to(wpr_blob, img->wpr_header.lsb_offset, - &img->lsb_header, sizeof(img->lsb_header)); - - /* Generate and write BL descriptor */ - memset(gdesc, 0, ls_func->bl_desc_size); - ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc); - - nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.bl_data_off, - gdesc, ls_func->bl_desc_size); - - /* Copy ucode */ - nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.ucode_off, - _img->ucode_data, _img->ucode_size); - - pos += sizeof(img->wpr_header); - } - - nvkm_wo32(wpr_blob, pos, NVKM_SECBOOT_FALCON_INVALID); - - nvkm_done(wpr_blob); - - kfree(gdesc); - - return 0; -} - -struct acr_r367_hsflcn_desc { - u8 reserved_dmem[0x200]; - u32 signatures[4]; - u32 wpr_region_id; - u32 wpr_offset; - u32 mmu_memory_range; -#define FLCN_ACR_MAX_REGIONS 2 - struct { - u32 no_regions; - struct { - u32 start_addr; - u32 end_addr; - u32 region_id; - u32 read_mask; - u32 write_mask; - u32 client_mask; - u32 shadow_mem_start_addr; - } region_props[FLCN_ACR_MAX_REGIONS]; - } regions; - u32 ucode_blob_size; - u64 ucode_blob_base __aligned(8); - struct { - u32 vpr_enabled; - u32 vpr_start; - u32 vpr_end; - u32 hdcp_policies; - } vpr_desc; -}; - -void -acr_r367_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb, - void *_desc) -{ - struct acr_r367_hsflcn_desc *desc = _desc; - struct nvkm_gpuobj *ls_blob = acr->ls_blob; - - /* WPR region information if WPR is not fixed */ - if (sb->wpr_size == 0) { - u64 wpr_start = ls_blob->addr; - u64 wpr_end = ls_blob->addr + ls_blob->size; - - if (acr->func->shadow_blob) - wpr_start += ls_blob->size / 2; - - desc->wpr_region_id = 1; - desc->regions.no_regions = 2; - desc->regions.region_props[0].start_addr = wpr_start >> 8; - desc->regions.region_props[0].end_addr = wpr_end >> 8; - desc->regions.region_props[0].region_id = 1; - desc->regions.region_props[0].read_mask = 0xf; - desc->regions.region_props[0].write_mask = 0xc; - desc->regions.region_props[0].client_mask = 0x2; - if (acr->func->shadow_blob) - desc->regions.region_props[0].shadow_mem_start_addr = - ls_blob->addr >> 8; - else - desc->regions.region_props[0].shadow_mem_start_addr = 0; - } else { - desc->ucode_blob_base = ls_blob->addr; - desc->ucode_blob_size = ls_blob->size; - } -} - -static const struct acr_r352_ls_func -acr_r367_ls_sec2_func = { - .load = acr_ls_ucode_load_sec2, - .post_run = acr_ls_sec2_post_run, - .version_max = 1, - .version = { - &acr_r361_ls_sec2_func_0, - &acr_r370_ls_sec2_func_0, - } -}; - -const struct acr_r352_func -acr_r367_func = { - .fixup_hs_desc = acr_r367_fixup_hs_desc, - .generate_hs_bl_desc = acr_r361_generate_hs_bl_desc, - .hs_bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc), - .shadow_blob = true, - .ls_ucode_img_load = acr_r367_ls_ucode_img_load, - .ls_fill_headers = acr_r367_ls_fill_headers, - .ls_write_wpr = acr_r367_ls_write_wpr, - .ls_func = { - [NVKM_SECBOOT_FALCON_FECS] = &acr_r361_ls_fecs_func, - [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r361_ls_gpccs_func, - [NVKM_SECBOOT_FALCON_PMU] = &acr_r361_ls_pmu_func, - [NVKM_SECBOOT_FALCON_SEC2] = &acr_r367_ls_sec2_func, - }, -}; - -struct nvkm_acr * -acr_r367_new(enum nvkm_secboot_falcon boot_falcon, - unsigned long managed_falcons) -{ - return acr_r352_new_(&acr_r367_func, boot_falcon, managed_falcons); -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.h deleted file mode 100644 index 8bdfb3e5cd1c..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVKM_SECBOOT_ACR_R367_H__ -#define __NVKM_SECBOOT_ACR_R367_H__ - -#include "acr_r352.h" - -void acr_r367_fixup_hs_desc(struct acr_r352 *, struct nvkm_secboot *, void *); - -struct ls_ucode_img *acr_r367_ls_ucode_img_load(const struct acr_r352 *, - const struct nvkm_secboot *, - enum nvkm_secboot_falcon); -int acr_r367_ls_fill_headers(struct acr_r352 *, struct list_head *); -int acr_r367_ls_write_wpr(struct acr_r352 *, struct list_head *, - struct nvkm_gpuobj *, u64); -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c deleted file mode 100644 index e821d0fd6217..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "acr_r370.h" -#include "acr_r367.h" - -#include <core/msgqueue.h> -#include <engine/falcon.h> -#include <engine/sec2.h> - -static void -acr_r370_generate_flcn_bl_desc(const struct nvkm_acr *acr, - const struct ls_ucode_img *img, u64 wpr_addr, - void *_desc) -{ - struct acr_r370_flcn_bl_desc *desc = _desc; - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; - u64 base, addr_code, addr_data; - - base = wpr_addr + img->ucode_off + pdesc->app_start_offset; - addr_code = base + pdesc->app_resident_code_offset; - addr_data = base + pdesc->app_resident_data_offset; - - desc->ctx_dma = FALCON_DMAIDX_UCODE; - desc->code_dma_base = u64_to_flcn64(addr_code); - desc->non_sec_code_off = pdesc->app_resident_code_offset; - desc->non_sec_code_size = pdesc->app_resident_code_size; - desc->code_entry_point = pdesc->app_imem_entry; - desc->data_dma_base = u64_to_flcn64(addr_data); - desc->data_size = pdesc->app_resident_data_size; -} - -static const struct acr_r352_lsf_func -acr_r370_ls_fecs_func_0 = { - .generate_bl_desc = acr_r370_generate_flcn_bl_desc, - .bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc), -}; - -const struct acr_r352_ls_func -acr_r370_ls_fecs_func = { - .load = acr_ls_ucode_load_fecs, - .version_max = 0, - .version = { - &acr_r370_ls_fecs_func_0, - } -}; - -static const struct acr_r352_lsf_func -acr_r370_ls_gpccs_func_0 = { - .generate_bl_desc = acr_r370_generate_flcn_bl_desc, - .bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc), - /* GPCCS will be loaded using PRI */ - .lhdr_flags = LSF_FLAG_FORCE_PRIV_LOAD, -}; - -const struct acr_r352_ls_func -acr_r370_ls_gpccs_func = { - .load = acr_ls_ucode_load_gpccs, - .version_max = 0, - .version = { - &acr_r370_ls_gpccs_func_0, - } -}; - -static void -acr_r370_generate_sec2_bl_desc(const struct nvkm_acr *acr, - const struct ls_ucode_img *img, u64 wpr_addr, - void *_desc) -{ - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; - const struct nvkm_sec2 *sec = acr->subdev->device->sec2; - struct acr_r370_flcn_bl_desc *desc = _desc; - u64 base, addr_code, addr_data; - u32 addr_args; - - base = wpr_addr + img->ucode_off + pdesc->app_start_offset; - /* For some reason we should not add app_resident_code_offset here */ - addr_code = base; - addr_data = base + pdesc->app_resident_data_offset; - addr_args = sec->falcon->data.limit; - addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE; - - desc->ctx_dma = FALCON_SEC2_DMAIDX_UCODE; - desc->code_dma_base = u64_to_flcn64(addr_code); - desc->non_sec_code_off = pdesc->app_resident_code_offset; - desc->non_sec_code_size = pdesc->app_resident_code_size; - desc->code_entry_point = pdesc->app_imem_entry; - desc->data_dma_base = u64_to_flcn64(addr_data); - desc->data_size = pdesc->app_resident_data_size; - desc->argc = 1; - /* args are stored at the beginning of EMEM */ - desc->argv = 0x01000000; -} - -const struct acr_r352_lsf_func -acr_r370_ls_sec2_func_0 = { - .generate_bl_desc = acr_r370_generate_sec2_bl_desc, - .bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc), -}; - -const struct acr_r352_ls_func -acr_r370_ls_sec2_func = { - .load = acr_ls_ucode_load_sec2, - .post_run = acr_ls_sec2_post_run, - .version_max = 0, - .version = { - &acr_r370_ls_sec2_func_0, - } -}; - -void -acr_r370_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc, - u64 offset) -{ - struct acr_r370_flcn_bl_desc *bl_desc = _bl_desc; - - bl_desc->ctx_dma = FALCON_DMAIDX_VIRT; - bl_desc->non_sec_code_off = hdr->non_sec_code_off; - bl_desc->non_sec_code_size = hdr->non_sec_code_size; - bl_desc->sec_code_off = hsf_load_header_app_off(hdr, 0); - bl_desc->sec_code_size = hsf_load_header_app_size(hdr, 0); - bl_desc->code_entry_point = 0; - bl_desc->code_dma_base = u64_to_flcn64(offset); - bl_desc->data_dma_base = u64_to_flcn64(offset + hdr->data_dma_base); - bl_desc->data_size = hdr->data_size; -} - -const struct acr_r352_func -acr_r370_func = { - .fixup_hs_desc = acr_r367_fixup_hs_desc, - .generate_hs_bl_desc = acr_r370_generate_hs_bl_desc, - .hs_bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc), - .shadow_blob = true, - .ls_ucode_img_load = acr_r367_ls_ucode_img_load, - .ls_fill_headers = acr_r367_ls_fill_headers, - .ls_write_wpr = acr_r367_ls_write_wpr, - .ls_func = { - [NVKM_SECBOOT_FALCON_SEC2] = &acr_r370_ls_sec2_func, - [NVKM_SECBOOT_FALCON_FECS] = &acr_r370_ls_fecs_func, - [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r370_ls_gpccs_func, - }, -}; - -struct nvkm_acr * -acr_r370_new(enum nvkm_secboot_falcon boot_falcon, - unsigned long managed_falcons) -{ - return acr_r352_new_(&acr_r370_func, boot_falcon, managed_falcons); -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.h deleted file mode 100644 index 2efed6f995ad..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVKM_SECBOOT_ACR_R370_H__ -#define __NVKM_SECBOOT_ACR_R370_H__ - -#include "priv.h" -struct hsf_load_header; - -/* Same as acr_r361_flcn_bl_desc, plus argc/argv */ -struct acr_r370_flcn_bl_desc { - u32 reserved[4]; - u32 signature[4]; - u32 ctx_dma; - struct flcn_u64 code_dma_base; - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - struct flcn_u64 data_dma_base; - u32 data_size; - u32 argc; - u32 argv; -}; - -void acr_r370_generate_hs_bl_desc(const struct hsf_load_header *, void *, u64); -extern const struct acr_r352_ls_func acr_r370_ls_fecs_func; -extern const struct acr_r352_ls_func acr_r370_ls_gpccs_func; -extern const struct acr_r352_lsf_func acr_r370_ls_sec2_func_0; -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r375.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r375.c deleted file mode 100644 index 8f0647766038..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r375.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "acr_r370.h" -#include "acr_r367.h" - -#include <core/msgqueue.h> -#include <subdev/pmu.h> - -static void -acr_r375_generate_pmu_bl_desc(const struct nvkm_acr *acr, - const struct ls_ucode_img *img, u64 wpr_addr, - void *_desc) -{ - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; - const struct nvkm_pmu *pmu = acr->subdev->device->pmu; - struct acr_r370_flcn_bl_desc *desc = _desc; - u64 base, addr_code, addr_data; - u32 addr_args; - - base = wpr_addr + img->ucode_off + pdesc->app_start_offset; - addr_code = base + pdesc->app_resident_code_offset; - addr_data = base + pdesc->app_resident_data_offset; - addr_args = pmu->falcon->data.limit; - addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE; - - desc->ctx_dma = FALCON_DMAIDX_UCODE; - desc->code_dma_base = u64_to_flcn64(addr_code); - desc->non_sec_code_off = pdesc->app_resident_code_offset; - desc->non_sec_code_size = pdesc->app_resident_code_size; - desc->code_entry_point = pdesc->app_imem_entry; - desc->data_dma_base = u64_to_flcn64(addr_data); - desc->data_size = pdesc->app_resident_data_size; - desc->argc = 1; - desc->argv = addr_args; -} - -static const struct acr_r352_lsf_func -acr_r375_ls_pmu_func_0 = { - .generate_bl_desc = acr_r375_generate_pmu_bl_desc, - .bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc), -}; - -const struct acr_r352_ls_func -acr_r375_ls_pmu_func = { - .load = acr_ls_ucode_load_pmu, - .post_run = acr_ls_pmu_post_run, - .version_max = 0, - .version = { - &acr_r375_ls_pmu_func_0, - } -}; - -const struct acr_r352_func -acr_r375_func = { - .fixup_hs_desc = acr_r367_fixup_hs_desc, - .generate_hs_bl_desc = acr_r370_generate_hs_bl_desc, - .hs_bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc), - .shadow_blob = true, - .ls_ucode_img_load = acr_r367_ls_ucode_img_load, - .ls_fill_headers = acr_r367_ls_fill_headers, - .ls_write_wpr = acr_r367_ls_write_wpr, - .ls_func = { - [NVKM_SECBOOT_FALCON_FECS] = &acr_r370_ls_fecs_func, - [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r370_ls_gpccs_func, - [NVKM_SECBOOT_FALCON_PMU] = &acr_r375_ls_pmu_func, - }, -}; - -struct nvkm_acr * -acr_r375_new(enum nvkm_secboot_falcon boot_falcon, - unsigned long managed_falcons) -{ - return acr_r352_new_(&acr_r375_func, boot_falcon, managed_falcons); -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c deleted file mode 100644 index ee29c6c11afd..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/* - * Secure boot is the process by which NVIDIA-signed firmware is loaded into - * some of the falcons of a GPU. For production devices this is the only way - * for the firmware to access useful (but sensitive) registers. - * - * A Falcon microprocessor supporting advanced security modes can run in one of - * three modes: - * - * - Non-secure (NS). In this mode, functionality is similar to Falcon - * architectures before security modes were introduced (pre-Maxwell), but - * capability is restricted. In particular, certain registers may be - * inaccessible for reads and/or writes, and physical memory access may be - * disabled (on certain Falcon instances). This is the only possible mode that - * can be used if you don't have microcode cryptographically signed by NVIDIA. - * - * - Heavy Secure (HS). In this mode, the microprocessor is a black box - it's - * not possible to read or write any Falcon internal state or Falcon registers - * from outside the Falcon (for example, from the host system). The only way - * to enable this mode is by loading microcode that has been signed by NVIDIA. - * (The loading process involves tagging the IMEM block as secure, writing the - * signature into a Falcon register, and starting execution. The hardware will - * validate the signature, and if valid, grant HS privileges.) - * - * - Light Secure (LS). In this mode, the microprocessor has more privileges - * than NS but fewer than HS. Some of the microprocessor state is visible to - * host software to ease debugging. The only way to enable this mode is by HS - * microcode enabling LS mode. Some privileges available to HS mode are not - * available here. LS mode is introduced in GM20x. - * - * Secure boot consists in temporarily switching a HS-capable falcon (typically - * PMU) into HS mode in order to validate the LS firmwares of managed falcons, - * load them, and switch managed falcons into LS mode. Once secure boot - * completes, no falcon remains in HS mode. - * - * Secure boot requires a write-protected memory region (WPR) which can only be - * written by the secure falcon. On dGPU, the driver sets up the WPR region in - * video memory. On Tegra, it is set up by the bootloader and its location and - * size written into memory controller registers. - * - * The secure boot process takes place as follows: - * - * 1) A LS blob is constructed that contains all the LS firmwares we want to - * load, along with their signatures and bootloaders. - * - * 2) A HS blob (also called ACR) is created that contains the signed HS - * firmware in charge of loading the LS firmwares into their respective - * falcons. - * - * 3) The HS blob is loaded (via its own bootloader) and executed on the - * HS-capable falcon. It authenticates itself, switches the secure falcon to - * HS mode and setup the WPR region around the LS blob (dGPU) or copies the - * LS blob into the WPR region (Tegra). - * - * 4) The LS blob is now secure from all external tampering. The HS falcon - * checks the signatures of the LS firmwares and, if valid, switches the - * managed falcons to LS mode and makes them ready to run the LS firmware. - * - * 5) The managed falcons remain in LS mode and can be started. - * - */ - -#include "priv.h" -#include "acr.h" - -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <subdev/pmu.h> -#include <engine/sec2.h> - -const char * -nvkm_secboot_falcon_name[] = { - [NVKM_SECBOOT_FALCON_PMU] = "PMU", - [NVKM_SECBOOT_FALCON_RESERVED] = "<reserved>", - [NVKM_SECBOOT_FALCON_FECS] = "FECS", - [NVKM_SECBOOT_FALCON_GPCCS] = "GPCCS", - [NVKM_SECBOOT_FALCON_SEC2] = "SEC2", - [NVKM_SECBOOT_FALCON_END] = "<invalid>", -}; -/** - * nvkm_secboot_reset() - reset specified falcon - */ -int -nvkm_secboot_reset(struct nvkm_secboot *sb, unsigned long falcon_mask) -{ - /* Unmanaged falcon? */ - if ((falcon_mask | sb->acr->managed_falcons) != sb->acr->managed_falcons) { - nvkm_error(&sb->subdev, "cannot reset unmanaged falcon!\n"); - return -EINVAL; - } - - return sb->acr->func->reset(sb->acr, sb, falcon_mask); -} - -/** - * nvkm_secboot_is_managed() - check whether a given falcon is securely-managed - */ -bool -nvkm_secboot_is_managed(struct nvkm_secboot *sb, enum nvkm_secboot_falcon fid) -{ - if (!sb) - return false; - - return sb->acr->managed_falcons & BIT(fid); -} - -static int -nvkm_secboot_oneinit(struct nvkm_subdev *subdev) -{ - struct nvkm_secboot *sb = nvkm_secboot(subdev); - int ret = 0; - - switch (sb->acr->boot_falcon) { - case NVKM_SECBOOT_FALCON_PMU: - sb->halt_falcon = sb->boot_falcon = subdev->device->pmu->falcon; - break; - case NVKM_SECBOOT_FALCON_SEC2: - /* we must keep SEC2 alive forever since ACR will run on it */ - nvkm_engine_ref(&subdev->device->sec2->engine); - sb->boot_falcon = subdev->device->sec2->falcon; - sb->halt_falcon = subdev->device->pmu->falcon; - break; - default: - nvkm_error(subdev, "Unmanaged boot falcon %s!\n", - nvkm_secboot_falcon_name[sb->acr->boot_falcon]); - return -EINVAL; - } - nvkm_debug(subdev, "using %s falcon for ACR\n", sb->boot_falcon->name); - - /* Call chip-specific init function */ - if (sb->func->oneinit) - ret = sb->func->oneinit(sb); - if (ret) { - nvkm_error(subdev, "Secure Boot initialization failed: %d\n", - ret); - return ret; - } - - return 0; -} - -static int -nvkm_secboot_fini(struct nvkm_subdev *subdev, bool suspend) -{ - struct nvkm_secboot *sb = nvkm_secboot(subdev); - int ret = 0; - - if (sb->func->fini) - ret = sb->func->fini(sb, suspend); - - return ret; -} - -static void * -nvkm_secboot_dtor(struct nvkm_subdev *subdev) -{ - struct nvkm_secboot *sb = nvkm_secboot(subdev); - void *ret = NULL; - - if (sb->func->dtor) - ret = sb->func->dtor(sb); - - return ret; -} - -static const struct nvkm_subdev_func -nvkm_secboot = { - .oneinit = nvkm_secboot_oneinit, - .fini = nvkm_secboot_fini, - .dtor = nvkm_secboot_dtor, -}; - -int -nvkm_secboot_ctor(const struct nvkm_secboot_func *func, struct nvkm_acr *acr, - struct nvkm_device *device, int index, - struct nvkm_secboot *sb) -{ - unsigned long fid; - - nvkm_subdev_ctor(&nvkm_secboot, device, index, &sb->subdev); - sb->func = func; - sb->acr = acr; - acr->subdev = &sb->subdev; - - nvkm_debug(&sb->subdev, "securely managed falcons:\n"); - for_each_set_bit(fid, &sb->acr->managed_falcons, - NVKM_SECBOOT_FALCON_END) - nvkm_debug(&sb->subdev, "- %s\n", - nvkm_secboot_falcon_name[fid]); - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c deleted file mode 100644 index 5e91b3f90065..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - -#include "acr.h" -#include "gm200.h" - -#include <core/gpuobj.h> -#include <subdev/fb.h> -#include <engine/falcon.h> -#include <subdev/mc.h> - -/** - * gm200_secboot_run_blob() - run the given high-secure blob - * - */ -int -gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob, - struct nvkm_falcon *falcon) -{ - struct gm200_secboot *gsb = gm200_secboot(sb); - struct nvkm_subdev *subdev = &gsb->base.subdev; - struct nvkm_vma *vma = NULL; - u32 start_address; - int ret; - - ret = nvkm_falcon_get(falcon, subdev); - if (ret) - return ret; - - /* Map the HS firmware so the HS bootloader can see it */ - ret = nvkm_vmm_get(gsb->vmm, 12, blob->size, &vma); - if (ret) { - nvkm_falcon_put(falcon, subdev); - return ret; - } - - ret = nvkm_memory_map(blob, 0, gsb->vmm, vma, NULL, 0); - if (ret) - goto end; - - /* Reset and set the falcon up */ - ret = nvkm_falcon_reset(falcon); - if (ret) - goto end; - nvkm_falcon_bind_context(falcon, gsb->inst); - - /* Load the HS bootloader into the falcon's IMEM/DMEM */ - ret = sb->acr->func->load(sb->acr, falcon, blob, vma->addr); - if (ret < 0) - goto end; - - start_address = ret; - - /* Disable interrupts as we will poll for the HALT bit */ - nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, false); - - /* Set default error value in mailbox register */ - nvkm_falcon_wr32(falcon, 0x040, 0xdeada5a5); - - /* Start the HS bootloader */ - nvkm_falcon_set_start_addr(falcon, start_address); - nvkm_falcon_start(falcon); - ret = nvkm_falcon_wait_for_halt(falcon, 100); - if (ret) - goto end; - - /* - * The mailbox register contains the (positive) error code - return this - * to the caller - */ - ret = nvkm_falcon_rd32(falcon, 0x040); - -end: - /* Reenable interrupts */ - nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, true); - - /* We don't need the ACR firmware anymore */ - nvkm_vmm_put(gsb->vmm, &vma); - nvkm_falcon_put(falcon, subdev); - - return ret; -} - -int -gm200_secboot_oneinit(struct nvkm_secboot *sb) -{ - struct gm200_secboot *gsb = gm200_secboot(sb); - struct nvkm_device *device = sb->subdev.device; - int ret; - - /* Allocate instance block and VM */ - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0, true, - &gsb->inst); - if (ret) - return ret; - - ret = nvkm_vmm_new(device, 0, 600 * 1024, NULL, 0, NULL, "acr", - &gsb->vmm); - if (ret) - return ret; - - atomic_inc(&gsb->vmm->engref[NVKM_SUBDEV_PMU]); - gsb->vmm->debug = gsb->base.subdev.debug; - - ret = nvkm_vmm_join(gsb->vmm, gsb->inst); - if (ret) - return ret; - - if (sb->acr->func->oneinit) { - ret = sb->acr->func->oneinit(sb->acr, sb); - if (ret) - return ret; - } - - return 0; -} - -int -gm200_secboot_fini(struct nvkm_secboot *sb, bool suspend) -{ - int ret = 0; - - if (sb->acr->func->fini) - ret = sb->acr->func->fini(sb->acr, sb, suspend); - - return ret; -} - -void * -gm200_secboot_dtor(struct nvkm_secboot *sb) -{ - struct gm200_secboot *gsb = gm200_secboot(sb); - - sb->acr->func->dtor(sb->acr); - - nvkm_vmm_part(gsb->vmm, gsb->inst); - nvkm_vmm_unref(&gsb->vmm); - nvkm_memory_unref(&gsb->inst); - - return gsb; -} - - -static const struct nvkm_secboot_func -gm200_secboot = { - .dtor = gm200_secboot_dtor, - .oneinit = gm200_secboot_oneinit, - .fini = gm200_secboot_fini, - .run_blob = gm200_secboot_run_blob, -}; - -int -gm200_secboot_new(struct nvkm_device *device, int index, - struct nvkm_secboot **psb) -{ - int ret; - struct gm200_secboot *gsb; - struct nvkm_acr *acr; - - acr = acr_r361_new(BIT(NVKM_SECBOOT_FALCON_FECS) | - BIT(NVKM_SECBOOT_FALCON_GPCCS)); - if (IS_ERR(acr)) - return PTR_ERR(acr); - - gsb = kzalloc(sizeof(*gsb), GFP_KERNEL); - if (!gsb) { - psb = NULL; - return -ENOMEM; - } - *psb = &gsb->base; - - ret = nvkm_secboot_ctor(&gm200_secboot, acr, device, index, &gsb->base); - if (ret) - return ret; - - return 0; -} - - -MODULE_FIRMWARE("nvidia/gm200/acr/bl.bin"); -MODULE_FIRMWARE("nvidia/gm200/acr/ucode_load.bin"); -MODULE_FIRMWARE("nvidia/gm200/acr/ucode_unload.bin"); -MODULE_FIRMWARE("nvidia/gm200/gr/fecs_bl.bin"); -MODULE_FIRMWARE("nvidia/gm200/gr/fecs_inst.bin"); -MODULE_FIRMWARE("nvidia/gm200/gr/fecs_data.bin"); -MODULE_FIRMWARE("nvidia/gm200/gr/fecs_sig.bin"); -MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_bl.bin"); -MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_inst.bin"); -MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_data.bin"); -MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_sig.bin"); -MODULE_FIRMWARE("nvidia/gm200/gr/sw_ctx.bin"); -MODULE_FIRMWARE("nvidia/gm200/gr/sw_nonctx.bin"); -MODULE_FIRMWARE("nvidia/gm200/gr/sw_bundle_init.bin"); -MODULE_FIRMWARE("nvidia/gm200/gr/sw_method_init.bin"); - -MODULE_FIRMWARE("nvidia/gm204/acr/bl.bin"); -MODULE_FIRMWARE("nvidia/gm204/acr/ucode_load.bin"); -MODULE_FIRMWARE("nvidia/gm204/acr/ucode_unload.bin"); -MODULE_FIRMWARE("nvidia/gm204/gr/fecs_bl.bin"); -MODULE_FIRMWARE("nvidia/gm204/gr/fecs_inst.bin"); -MODULE_FIRMWARE("nvidia/gm204/gr/fecs_data.bin"); -MODULE_FIRMWARE("nvidia/gm204/gr/fecs_sig.bin"); -MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_bl.bin"); -MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_inst.bin"); -MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_data.bin"); -MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_sig.bin"); -MODULE_FIRMWARE("nvidia/gm204/gr/sw_ctx.bin"); -MODULE_FIRMWARE("nvidia/gm204/gr/sw_nonctx.bin"); -MODULE_FIRMWARE("nvidia/gm204/gr/sw_bundle_init.bin"); -MODULE_FIRMWARE("nvidia/gm204/gr/sw_method_init.bin"); - -MODULE_FIRMWARE("nvidia/gm206/acr/bl.bin"); -MODULE_FIRMWARE("nvidia/gm206/acr/ucode_load.bin"); -MODULE_FIRMWARE("nvidia/gm206/acr/ucode_unload.bin"); -MODULE_FIRMWARE("nvidia/gm206/gr/fecs_bl.bin"); -MODULE_FIRMWARE("nvidia/gm206/gr/fecs_inst.bin"); -MODULE_FIRMWARE("nvidia/gm206/gr/fecs_data.bin"); -MODULE_FIRMWARE("nvidia/gm206/gr/fecs_sig.bin"); -MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_bl.bin"); -MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_inst.bin"); -MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_data.bin"); -MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_sig.bin"); -MODULE_FIRMWARE("nvidia/gm206/gr/sw_ctx.bin"); -MODULE_FIRMWARE("nvidia/gm206/gr/sw_nonctx.bin"); -MODULE_FIRMWARE("nvidia/gm206/gr/sw_bundle_init.bin"); -MODULE_FIRMWARE("nvidia/gm206/gr/sw_method_init.bin"); - -MODULE_FIRMWARE("nvidia/gp100/acr/bl.bin"); -MODULE_FIRMWARE("nvidia/gp100/acr/ucode_load.bin"); -MODULE_FIRMWARE("nvidia/gp100/acr/ucode_unload.bin"); -MODULE_FIRMWARE("nvidia/gp100/gr/fecs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp100/gr/fecs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp100/gr/fecs_data.bin"); -MODULE_FIRMWARE("nvidia/gp100/gr/fecs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_data.bin"); -MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp100/gr/sw_ctx.bin"); -MODULE_FIRMWARE("nvidia/gp100/gr/sw_nonctx.bin"); -MODULE_FIRMWARE("nvidia/gp100/gr/sw_bundle_init.bin"); -MODULE_FIRMWARE("nvidia/gp100/gr/sw_method_init.bin"); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h deleted file mode 100644 index 62c5e162099a..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVKM_SECBOOT_GM200_H__ -#define __NVKM_SECBOOT_GM200_H__ - -#include "priv.h" - -struct gm200_secboot { - struct nvkm_secboot base; - - /* Instance block & address space used for HS FW execution */ - struct nvkm_memory *inst; - struct nvkm_vmm *vmm; -}; -#define gm200_secboot(sb) container_of(sb, struct gm200_secboot, base) - -int gm200_secboot_oneinit(struct nvkm_secboot *); -int gm200_secboot_fini(struct nvkm_secboot *, bool); -void *gm200_secboot_dtor(struct nvkm_secboot *); -int gm200_secboot_run_blob(struct nvkm_secboot *, struct nvkm_gpuobj *, - struct nvkm_falcon *); - -/* Tegra-only */ -int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *, u32); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c deleted file mode 100644 index df8b919dcf09..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "acr.h" -#include "gm200.h" - -#define TEGRA210_MC_BASE 0x70019000 - -#ifdef CONFIG_ARCH_TEGRA -#define MC_SECURITY_CARVEOUT2_CFG0 0xc58 -#define MC_SECURITY_CARVEOUT2_BOM_0 0xc5c -#define MC_SECURITY_CARVEOUT2_BOM_HI_0 0xc60 -#define MC_SECURITY_CARVEOUT2_SIZE_128K 0xc64 -#define TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED (1 << 1) -/** - * gm20b_secboot_tegra_read_wpr() - read the WPR registers on Tegra - * - * On dGPU, we can manage the WPR region ourselves, but on Tegra the WPR region - * is reserved from system memory by the bootloader and irreversibly locked. - * This function reads the address and size of the pre-configured WPR region. - */ -int -gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base) -{ - struct nvkm_secboot *sb = &gsb->base; - void __iomem *mc; - u32 cfg; - - mc = ioremap(mc_base, 0xd00); - if (!mc) { - nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n"); - return -ENOMEM; - } - sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) | - ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32); - sb->wpr_size = ioread32_native(mc + MC_SECURITY_CARVEOUT2_SIZE_128K) - << 17; - cfg = ioread32_native(mc + MC_SECURITY_CARVEOUT2_CFG0); - iounmap(mc); - - /* Check that WPR settings are valid */ - if (sb->wpr_size == 0) { - nvkm_error(&sb->subdev, "WPR region is empty\n"); - return -EINVAL; - } - - if (!(cfg & TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED)) { - nvkm_error(&sb->subdev, "WPR region not locked\n"); - return -EINVAL; - } - - return 0; -} -#else -int -gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base) -{ - nvkm_error(&gsb->base.subdev, "Tegra support not compiled in\n"); - return -EINVAL; -} -#endif - -static int -gm20b_secboot_oneinit(struct nvkm_secboot *sb) -{ - struct gm200_secboot *gsb = gm200_secboot(sb); - int ret; - - ret = gm20b_secboot_tegra_read_wpr(gsb, TEGRA210_MC_BASE); - if (ret) - return ret; - - return gm200_secboot_oneinit(sb); -} - -static const struct nvkm_secboot_func -gm20b_secboot = { - .dtor = gm200_secboot_dtor, - .oneinit = gm20b_secboot_oneinit, - .fini = gm200_secboot_fini, - .run_blob = gm200_secboot_run_blob, -}; - -int -gm20b_secboot_new(struct nvkm_device *device, int index, - struct nvkm_secboot **psb) -{ - int ret; - struct gm200_secboot *gsb; - struct nvkm_acr *acr; - - acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) | - BIT(NVKM_SECBOOT_FALCON_PMU)); - if (IS_ERR(acr)) - return PTR_ERR(acr); - /* Support the initial GM20B firmware release without PMU */ - acr->optional_falcons = BIT(NVKM_SECBOOT_FALCON_PMU); - - gsb = kzalloc(sizeof(*gsb), GFP_KERNEL); - if (!gsb) { - psb = NULL; - return -ENOMEM; - } - *psb = &gsb->base; - - ret = nvkm_secboot_ctor(&gm20b_secboot, acr, device, index, &gsb->base); - if (ret) - return ret; - - return 0; -} - -#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) -MODULE_FIRMWARE("nvidia/gm20b/acr/bl.bin"); -MODULE_FIRMWARE("nvidia/gm20b/acr/ucode_load.bin"); -MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_bl.bin"); -MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_inst.bin"); -MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_data.bin"); -MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_sig.bin"); -MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_inst.bin"); -MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_data.bin"); -MODULE_FIRMWARE("nvidia/gm20b/gr/sw_ctx.bin"); -MODULE_FIRMWARE("nvidia/gm20b/gr/sw_nonctx.bin"); -MODULE_FIRMWARE("nvidia/gm20b/gr/sw_bundle_init.bin"); -MODULE_FIRMWARE("nvidia/gm20b/gr/sw_method_init.bin"); -MODULE_FIRMWARE("nvidia/gm20b/pmu/desc.bin"); -MODULE_FIRMWARE("nvidia/gm20b/pmu/image.bin"); -MODULE_FIRMWARE("nvidia/gm20b/pmu/sig.bin"); -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c deleted file mode 100644 index 84a2f243ed9b..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "acr.h" -#include "gm200.h" - -#include "ls_ucode.h" -#include "hs_ucode.h" -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <engine/falcon.h> -#include <engine/nvdec.h> - -static bool -gp102_secboot_scrub_required(struct nvkm_secboot *sb) -{ - struct nvkm_subdev *subdev = &sb->subdev; - struct nvkm_device *device = subdev->device; - u32 reg; - - nvkm_wr32(device, 0x100cd0, 0x2); - reg = nvkm_rd32(device, 0x100cd0); - - return (reg & BIT(4)); -} - -static int -gp102_run_secure_scrub(struct nvkm_secboot *sb) -{ - struct nvkm_subdev *subdev = &sb->subdev; - struct nvkm_device *device = subdev->device; - struct nvkm_engine *engine; - struct nvkm_falcon *falcon; - void *scrub_image; - struct fw_bin_header *hsbin_hdr; - struct hsf_fw_header *fw_hdr; - struct hsf_load_header *lhdr; - void *scrub_data; - int ret; - - nvkm_debug(subdev, "running VPR scrubber binary on NVDEC...\n"); - - engine = nvkm_engine_ref(&device->nvdec[0]->engine); - if (IS_ERR(engine)) - return PTR_ERR(engine); - falcon = device->nvdec[0]->falcon; - - nvkm_falcon_get(falcon, &sb->subdev); - - scrub_image = hs_ucode_load_blob(subdev, falcon, "nvdec/scrubber"); - if (IS_ERR(scrub_image)) - return PTR_ERR(scrub_image); - - nvkm_falcon_reset(falcon); - nvkm_falcon_bind_context(falcon, NULL); - - hsbin_hdr = scrub_image; - fw_hdr = scrub_image + hsbin_hdr->header_offset; - lhdr = scrub_image + fw_hdr->hdr_offset; - scrub_data = scrub_image + hsbin_hdr->data_offset; - - nvkm_falcon_load_imem(falcon, scrub_data, lhdr->non_sec_code_off, - lhdr->non_sec_code_size, - lhdr->non_sec_code_off >> 8, 0, false); - nvkm_falcon_load_imem(falcon, scrub_data + lhdr->apps[0], - ALIGN(lhdr->apps[0], 0x100), - lhdr->apps[1], - lhdr->apps[0] >> 8, 0, true); - nvkm_falcon_load_dmem(falcon, scrub_data + lhdr->data_dma_base, 0, - lhdr->data_size, 0); - - kfree(scrub_image); - - nvkm_falcon_set_start_addr(falcon, 0x0); - nvkm_falcon_start(falcon); - - ret = nvkm_falcon_wait_for_halt(falcon, 500); - if (ret < 0) { - nvkm_error(subdev, "failed to run VPR scrubber binary!\n"); - ret = -ETIMEDOUT; - goto end; - } - - /* put nvdec in clean state - without reset it will remain in HS mode */ - nvkm_falcon_reset(falcon); - - if (gp102_secboot_scrub_required(sb)) { - nvkm_error(subdev, "VPR scrubber binary failed!\n"); - ret = -EINVAL; - goto end; - } - - nvkm_debug(subdev, "VPR scrub successfully completed\n"); - -end: - nvkm_falcon_put(falcon, &sb->subdev); - nvkm_engine_unref(&engine); - return ret; -} - -static int -gp102_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob, - struct nvkm_falcon *falcon) -{ - int ret; - - /* make sure the VPR region is unlocked */ - if (gp102_secboot_scrub_required(sb)) { - ret = gp102_run_secure_scrub(sb); - if (ret) - return ret; - } - - return gm200_secboot_run_blob(sb, blob, falcon); -} - -const struct nvkm_secboot_func -gp102_secboot = { - .dtor = gm200_secboot_dtor, - .oneinit = gm200_secboot_oneinit, - .fini = gm200_secboot_fini, - .run_blob = gp102_secboot_run_blob, -}; - -int -gp102_secboot_new(struct nvkm_device *device, int index, - struct nvkm_secboot **psb) -{ - int ret; - struct gm200_secboot *gsb; - struct nvkm_acr *acr; - - acr = acr_r367_new(NVKM_SECBOOT_FALCON_SEC2, - BIT(NVKM_SECBOOT_FALCON_FECS) | - BIT(NVKM_SECBOOT_FALCON_GPCCS) | - BIT(NVKM_SECBOOT_FALCON_SEC2)); - if (IS_ERR(acr)) - return PTR_ERR(acr); - - gsb = kzalloc(sizeof(*gsb), GFP_KERNEL); - if (!gsb) { - psb = NULL; - return -ENOMEM; - } - *psb = &gsb->base; - - ret = nvkm_secboot_ctor(&gp102_secboot, acr, device, index, &gsb->base); - if (ret) - return ret; - - return 0; -} - -MODULE_FIRMWARE("nvidia/gp102/acr/bl.bin"); -MODULE_FIRMWARE("nvidia/gp102/acr/unload_bl.bin"); -MODULE_FIRMWARE("nvidia/gp102/acr/ucode_load.bin"); -MODULE_FIRMWARE("nvidia/gp102/acr/ucode_unload.bin"); -MODULE_FIRMWARE("nvidia/gp102/gr/fecs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp102/gr/fecs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp102/gr/fecs_data.bin"); -MODULE_FIRMWARE("nvidia/gp102/gr/fecs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_data.bin"); -MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp102/gr/sw_ctx.bin"); -MODULE_FIRMWARE("nvidia/gp102/gr/sw_nonctx.bin"); -MODULE_FIRMWARE("nvidia/gp102/gr/sw_bundle_init.bin"); -MODULE_FIRMWARE("nvidia/gp102/gr/sw_method_init.bin"); -MODULE_FIRMWARE("nvidia/gp102/nvdec/scrubber.bin"); -MODULE_FIRMWARE("nvidia/gp102/sec2/desc.bin"); -MODULE_FIRMWARE("nvidia/gp102/sec2/image.bin"); -MODULE_FIRMWARE("nvidia/gp102/sec2/sig.bin"); -MODULE_FIRMWARE("nvidia/gp104/acr/bl.bin"); -MODULE_FIRMWARE("nvidia/gp104/acr/unload_bl.bin"); -MODULE_FIRMWARE("nvidia/gp104/acr/ucode_load.bin"); -MODULE_FIRMWARE("nvidia/gp104/acr/ucode_unload.bin"); -MODULE_FIRMWARE("nvidia/gp104/gr/fecs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp104/gr/fecs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp104/gr/fecs_data.bin"); -MODULE_FIRMWARE("nvidia/gp104/gr/fecs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_data.bin"); -MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp104/gr/sw_ctx.bin"); -MODULE_FIRMWARE("nvidia/gp104/gr/sw_nonctx.bin"); -MODULE_FIRMWARE("nvidia/gp104/gr/sw_bundle_init.bin"); -MODULE_FIRMWARE("nvidia/gp104/gr/sw_method_init.bin"); -MODULE_FIRMWARE("nvidia/gp104/nvdec/scrubber.bin"); -MODULE_FIRMWARE("nvidia/gp104/sec2/desc.bin"); -MODULE_FIRMWARE("nvidia/gp104/sec2/image.bin"); -MODULE_FIRMWARE("nvidia/gp104/sec2/sig.bin"); -MODULE_FIRMWARE("nvidia/gp106/acr/bl.bin"); -MODULE_FIRMWARE("nvidia/gp106/acr/unload_bl.bin"); -MODULE_FIRMWARE("nvidia/gp106/acr/ucode_load.bin"); -MODULE_FIRMWARE("nvidia/gp106/acr/ucode_unload.bin"); -MODULE_FIRMWARE("nvidia/gp106/gr/fecs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp106/gr/fecs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp106/gr/fecs_data.bin"); -MODULE_FIRMWARE("nvidia/gp106/gr/fecs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_data.bin"); -MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp106/gr/sw_ctx.bin"); -MODULE_FIRMWARE("nvidia/gp106/gr/sw_nonctx.bin"); -MODULE_FIRMWARE("nvidia/gp106/gr/sw_bundle_init.bin"); -MODULE_FIRMWARE("nvidia/gp106/gr/sw_method_init.bin"); -MODULE_FIRMWARE("nvidia/gp106/nvdec/scrubber.bin"); -MODULE_FIRMWARE("nvidia/gp106/sec2/desc.bin"); -MODULE_FIRMWARE("nvidia/gp106/sec2/image.bin"); -MODULE_FIRMWARE("nvidia/gp106/sec2/sig.bin"); -MODULE_FIRMWARE("nvidia/gp107/acr/bl.bin"); -MODULE_FIRMWARE("nvidia/gp107/acr/unload_bl.bin"); -MODULE_FIRMWARE("nvidia/gp107/acr/ucode_load.bin"); -MODULE_FIRMWARE("nvidia/gp107/acr/ucode_unload.bin"); -MODULE_FIRMWARE("nvidia/gp107/gr/fecs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp107/gr/fecs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp107/gr/fecs_data.bin"); -MODULE_FIRMWARE("nvidia/gp107/gr/fecs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_data.bin"); -MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp107/gr/sw_ctx.bin"); -MODULE_FIRMWARE("nvidia/gp107/gr/sw_nonctx.bin"); -MODULE_FIRMWARE("nvidia/gp107/gr/sw_bundle_init.bin"); -MODULE_FIRMWARE("nvidia/gp107/gr/sw_method_init.bin"); -MODULE_FIRMWARE("nvidia/gp107/nvdec/scrubber.bin"); -MODULE_FIRMWARE("nvidia/gp107/sec2/desc.bin"); -MODULE_FIRMWARE("nvidia/gp107/sec2/image.bin"); -MODULE_FIRMWARE("nvidia/gp107/sec2/sig.bin"); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c deleted file mode 100644 index 737a8d50a1f2..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright 2017 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "gm200.h" -#include "acr.h" - -int -gp108_secboot_new(struct nvkm_device *device, int index, - struct nvkm_secboot **psb) -{ - struct gm200_secboot *gsb; - struct nvkm_acr *acr; - - acr = acr_r370_new(NVKM_SECBOOT_FALCON_SEC2, - BIT(NVKM_SECBOOT_FALCON_FECS) | - BIT(NVKM_SECBOOT_FALCON_GPCCS) | - BIT(NVKM_SECBOOT_FALCON_SEC2)); - if (IS_ERR(acr)) - return PTR_ERR(acr); - - if (!(gsb = kzalloc(sizeof(*gsb), GFP_KERNEL))) { - acr->func->dtor(acr); - return -ENOMEM; - } - *psb = &gsb->base; - - return nvkm_secboot_ctor(&gp102_secboot, acr, device, index, &gsb->base); -} - -MODULE_FIRMWARE("nvidia/gp108/acr/bl.bin"); -MODULE_FIRMWARE("nvidia/gp108/acr/unload_bl.bin"); -MODULE_FIRMWARE("nvidia/gp108/acr/ucode_load.bin"); -MODULE_FIRMWARE("nvidia/gp108/acr/ucode_unload.bin"); -MODULE_FIRMWARE("nvidia/gp108/gr/fecs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp108/gr/fecs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp108/gr/fecs_data.bin"); -MODULE_FIRMWARE("nvidia/gp108/gr/fecs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_data.bin"); -MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp108/gr/sw_ctx.bin"); -MODULE_FIRMWARE("nvidia/gp108/gr/sw_nonctx.bin"); -MODULE_FIRMWARE("nvidia/gp108/gr/sw_bundle_init.bin"); -MODULE_FIRMWARE("nvidia/gp108/gr/sw_method_init.bin"); -MODULE_FIRMWARE("nvidia/gp108/nvdec/scrubber.bin"); -MODULE_FIRMWARE("nvidia/gp108/sec2/desc.bin"); -MODULE_FIRMWARE("nvidia/gp108/sec2/image.bin"); -MODULE_FIRMWARE("nvidia/gp108/sec2/sig.bin"); - -MODULE_FIRMWARE("nvidia/gv100/acr/bl.bin"); -MODULE_FIRMWARE("nvidia/gv100/acr/unload_bl.bin"); -MODULE_FIRMWARE("nvidia/gv100/acr/ucode_load.bin"); -MODULE_FIRMWARE("nvidia/gv100/acr/ucode_unload.bin"); -MODULE_FIRMWARE("nvidia/gv100/gr/fecs_bl.bin"); -MODULE_FIRMWARE("nvidia/gv100/gr/fecs_inst.bin"); -MODULE_FIRMWARE("nvidia/gv100/gr/fecs_data.bin"); -MODULE_FIRMWARE("nvidia/gv100/gr/fecs_sig.bin"); -MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_bl.bin"); -MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_inst.bin"); -MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_data.bin"); -MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_sig.bin"); -MODULE_FIRMWARE("nvidia/gv100/gr/sw_ctx.bin"); -MODULE_FIRMWARE("nvidia/gv100/gr/sw_nonctx.bin"); -MODULE_FIRMWARE("nvidia/gv100/gr/sw_bundle_init.bin"); -MODULE_FIRMWARE("nvidia/gv100/gr/sw_method_init.bin"); -MODULE_FIRMWARE("nvidia/gv100/nvdec/scrubber.bin"); -MODULE_FIRMWARE("nvidia/gv100/sec2/desc.bin"); -MODULE_FIRMWARE("nvidia/gv100/sec2/image.bin"); -MODULE_FIRMWARE("nvidia/gv100/sec2/sig.bin"); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c deleted file mode 100644 index 28ca29d0eeee..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "acr.h" -#include "gm200.h" - -#define TEGRA186_MC_BASE 0x02c10000 - -static int -gp10b_secboot_oneinit(struct nvkm_secboot *sb) -{ - struct gm200_secboot *gsb = gm200_secboot(sb); - int ret; - - ret = gm20b_secboot_tegra_read_wpr(gsb, TEGRA186_MC_BASE); - if (ret) - return ret; - - return gm200_secboot_oneinit(sb); -} - -static const struct nvkm_secboot_func -gp10b_secboot = { - .dtor = gm200_secboot_dtor, - .oneinit = gp10b_secboot_oneinit, - .fini = gm200_secboot_fini, - .run_blob = gm200_secboot_run_blob, -}; - -int -gp10b_secboot_new(struct nvkm_device *device, int index, - struct nvkm_secboot **psb) -{ - int ret; - struct gm200_secboot *gsb; - struct nvkm_acr *acr; - - acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) | - BIT(NVKM_SECBOOT_FALCON_GPCCS) | - BIT(NVKM_SECBOOT_FALCON_PMU)); - if (IS_ERR(acr)) - return PTR_ERR(acr); - - gsb = kzalloc(sizeof(*gsb), GFP_KERNEL); - if (!gsb) { - psb = NULL; - return -ENOMEM; - } - *psb = &gsb->base; - - ret = nvkm_secboot_ctor(&gp10b_secboot, acr, device, index, &gsb->base); - if (ret) - return ret; - - return 0; -} - -#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) -MODULE_FIRMWARE("nvidia/gp10b/acr/bl.bin"); -MODULE_FIRMWARE("nvidia/gp10b/acr/ucode_load.bin"); -MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_data.bin"); -MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_bl.bin"); -MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_inst.bin"); -MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_data.bin"); -MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_sig.bin"); -MODULE_FIRMWARE("nvidia/gp10b/gr/sw_ctx.bin"); -MODULE_FIRMWARE("nvidia/gp10b/gr/sw_nonctx.bin"); -MODULE_FIRMWARE("nvidia/gp10b/gr/sw_bundle_init.bin"); -MODULE_FIRMWARE("nvidia/gp10b/gr/sw_method_init.bin"); -MODULE_FIRMWARE("nvidia/gp10b/pmu/desc.bin"); -MODULE_FIRMWARE("nvidia/gp10b/pmu/image.bin"); -MODULE_FIRMWARE("nvidia/gp10b/pmu/sig.bin"); -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/hs_ucode.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/hs_ucode.c deleted file mode 100644 index 6b33182ddc2f..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/hs_ucode.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "hs_ucode.h" -#include "ls_ucode.h" -#include "acr.h" - -#include <engine/falcon.h> - -/** - * hs_ucode_patch_signature() - patch HS blob with correct signature for - * specified falcon. - */ -static void -hs_ucode_patch_signature(const struct nvkm_falcon *falcon, void *acr_image, - bool new_format) -{ - struct fw_bin_header *hsbin_hdr = acr_image; - struct hsf_fw_header *fw_hdr = acr_image + hsbin_hdr->header_offset; - void *hs_data = acr_image + hsbin_hdr->data_offset; - void *sig; - u32 sig_size; - u32 patch_loc, patch_sig; - - /* - * I had the brilliant idea to "improve" the binary format by - * removing this useless indirection. However to make NVIDIA files - * directly compatible, let's support both format. - */ - if (new_format) { - patch_loc = fw_hdr->patch_loc; - patch_sig = fw_hdr->patch_sig; - } else { - patch_loc = *(u32 *)(acr_image + fw_hdr->patch_loc); - patch_sig = *(u32 *)(acr_image + fw_hdr->patch_sig); - } - - /* Falcon in debug or production mode? */ - if (falcon->debug) { - sig = acr_image + fw_hdr->sig_dbg_offset; - sig_size = fw_hdr->sig_dbg_size; - } else { - sig = acr_image + fw_hdr->sig_prod_offset; - sig_size = fw_hdr->sig_prod_size; - } - - /* Patch signature */ - memcpy(hs_data + patch_loc, sig + patch_sig, sig_size); -} - -void * -hs_ucode_load_blob(struct nvkm_subdev *subdev, const struct nvkm_falcon *falcon, - const char *fw) -{ - void *acr_image; - bool new_format; - - acr_image = nvkm_acr_load_firmware(subdev, fw, 0); - if (IS_ERR(acr_image)) - return acr_image; - - /* detect the format to define how signature should be patched */ - switch (((u32 *)acr_image)[0]) { - case 0x3b1d14f0: - new_format = true; - break; - case 0x000010de: - new_format = false; - break; - default: - nvkm_error(subdev, "unknown header for HS blob %s\n", fw); - return ERR_PTR(-EINVAL); - } - - hs_ucode_patch_signature(falcon, acr_image, new_format); - - return acr_image; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/hs_ucode.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/hs_ucode.h deleted file mode 100644 index d8cfc6f7752a..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/hs_ucode.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVKM_SECBOOT_HS_UCODE_H__ -#define __NVKM_SECBOOT_HS_UCODE_H__ - -#include <core/os.h> -#include <core/subdev.h> - -struct nvkm_falcon; - -/** - * struct hsf_fw_header - HS firmware descriptor - * @sig_dbg_offset: offset of the debug signature - * @sig_dbg_size: size of the debug signature - * @sig_prod_offset: offset of the production signature - * @sig_prod_size: size of the production signature - * @patch_loc: offset of the offset (sic) of where the signature is - * @patch_sig: offset of the offset (sic) to add to sig_*_offset - * @hdr_offset: offset of the load header (see struct hs_load_header) - * @hdr_size: size of above header - * - * This structure is embedded in the HS firmware image at - * hs_bin_hdr.header_offset. - */ -struct hsf_fw_header { - u32 sig_dbg_offset; - u32 sig_dbg_size; - u32 sig_prod_offset; - u32 sig_prod_size; - u32 patch_loc; - u32 patch_sig; - u32 hdr_offset; - u32 hdr_size; -}; - -/** - * struct hsf_load_header - HS firmware load header - */ -struct hsf_load_header { - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 data_dma_base; - u32 data_size; - u32 num_apps; - /* - * Organized as follows: - * - app0_code_off - * - app1_code_off - * - ... - * - appn_code_off - * - app0_code_size - * - app1_code_size - * - ... - */ - u32 apps[0]; -}; - -void *hs_ucode_load_blob(struct nvkm_subdev *, const struct nvkm_falcon *, - const char *); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h deleted file mode 100644 index d43f906da3a7..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVKM_SECBOOT_LS_UCODE_H__ -#define __NVKM_SECBOOT_LS_UCODE_H__ - -#include <core/os.h> -#include <core/subdev.h> -#include <subdev/secboot.h> - -struct nvkm_acr; - -/** - * struct ls_ucode_img_desc - descriptor of firmware image - * @descriptor_size: size of this descriptor - * @image_size: size of the whole image - * @bootloader_start_offset: start offset of the bootloader in ucode image - * @bootloader_size: size of the bootloader - * @bootloader_imem_offset: start off set of the bootloader in IMEM - * @bootloader_entry_point: entry point of the bootloader in IMEM - * @app_start_offset: start offset of the LS firmware - * @app_size: size of the LS firmware's code and data - * @app_imem_offset: offset of the app in IMEM - * @app_imem_entry: entry point of the app in IMEM - * @app_dmem_offset: offset of the data in DMEM - * @app_resident_code_offset: offset of app code from app_start_offset - * @app_resident_code_size: size of the code - * @app_resident_data_offset: offset of data from app_start_offset - * @app_resident_data_size: size of data - * - * A firmware image contains the code, data, and bootloader of a given LS - * falcon in a single blob. This structure describes where everything is. - * - * This can be generated from a (bootloader, code, data) set if they have - * been loaded separately, or come directly from a file. - */ -struct ls_ucode_img_desc { - u32 descriptor_size; - u32 image_size; - u32 tools_version; - u32 app_version; - char date[64]; - u32 bootloader_start_offset; - u32 bootloader_size; - u32 bootloader_imem_offset; - u32 bootloader_entry_point; - u32 app_start_offset; - u32 app_size; - u32 app_imem_offset; - u32 app_imem_entry; - u32 app_dmem_offset; - u32 app_resident_code_offset; - u32 app_resident_code_size; - u32 app_resident_data_offset; - u32 app_resident_data_size; - u32 nb_overlays; - struct {u32 start; u32 size; } load_ovl[64]; - u32 compressed; -}; - -/** - * struct ls_ucode_img - temporary storage for loaded LS firmwares - * @node: to link within lsf_ucode_mgr - * @falcon_id: ID of the falcon this LS firmware is for - * @ucode_desc: loaded or generated map of ucode_data - * @ucode_data: firmware payload (code and data) - * @ucode_size: size in bytes of data in ucode_data - * @ucode_off: offset of the ucode in ucode_data - * @sig: signature for this firmware - * @sig:size: size of the signature in bytes - * - * Preparing the WPR LS blob requires information about all the LS firmwares - * (size, etc) to be known. This structure contains all the data of one LS - * firmware. - */ -struct ls_ucode_img { - struct list_head node; - enum nvkm_secboot_falcon falcon_id; - - struct ls_ucode_img_desc ucode_desc; - u8 *ucode_data; - u32 ucode_size; - u32 ucode_off; - - u8 *sig; - u32 sig_size; -}; - -/** - * struct fw_bin_header - header of firmware files - * @bin_magic: always 0x3b1d14f0 - * @bin_ver: version of the bin format - * @bin_size: entire image size including this header - * @header_offset: offset of the firmware/bootloader header in the file - * @data_offset: offset of the firmware/bootloader payload in the file - * @data_size: size of the payload - * - * This header is located at the beginning of the HS firmware and HS bootloader - * files, to describe where the headers and data can be found. - */ -struct fw_bin_header { - u32 bin_magic; - u32 bin_ver; - u32 bin_size; - u32 header_offset; - u32 data_offset; - u32 data_size; -}; - -/** - * struct fw_bl_desc - firmware bootloader descriptor - * @start_tag: starting tag of bootloader - * @desc_dmem_load_off: DMEM offset of flcn_bl_dmem_desc - * @code_off: offset of code section - * @code_size: size of code section - * @data_off: offset of data section - * @data_size: size of data section - * - * This structure is embedded in bootloader firmware files at to describe the - * IMEM and DMEM layout expected by the bootloader. - */ -struct fw_bl_desc { - u32 start_tag; - u32 dmem_load_off; - u32 code_off; - u32 code_size; - u32 data_off; - u32 data_size; -}; - -int acr_ls_ucode_load_fecs(const struct nvkm_secboot *, int, - struct ls_ucode_img *); -int acr_ls_ucode_load_gpccs(const struct nvkm_secboot *, int, - struct ls_ucode_img *); -int acr_ls_ucode_load_pmu(const struct nvkm_secboot *, int, - struct ls_ucode_img *); -int acr_ls_pmu_post_run(const struct nvkm_acr *, const struct nvkm_secboot *); -int acr_ls_ucode_load_sec2(const struct nvkm_secboot *, int, - struct ls_ucode_img *); -int acr_ls_sec2_post_run(const struct nvkm_acr *, const struct nvkm_secboot *); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c deleted file mode 100644 index 821d3b2bdb1f..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - -#include "ls_ucode.h" -#include "acr.h" - -#include <core/firmware.h> - -#define BL_DESC_BLK_SIZE 256 -/** - * Build a ucode image and descriptor from provided bootloader, code and data. - * - * @bl: bootloader image, including 16-bytes descriptor - * @code: LS firmware code segment - * @data: LS firmware data segment - * @desc: ucode descriptor to be written - * - * Return: allocated ucode image with corresponding descriptor information. desc - * is also updated to contain the right offsets within returned image. - */ -static void * -ls_ucode_img_build(const struct firmware *bl, const struct firmware *code, - const struct firmware *data, struct ls_ucode_img_desc *desc) -{ - struct fw_bin_header *bin_hdr = (void *)bl->data; - struct fw_bl_desc *bl_desc = (void *)bl->data + bin_hdr->header_offset; - void *bl_data = (void *)bl->data + bin_hdr->data_offset; - u32 pos = 0; - void *image; - - desc->bootloader_start_offset = pos; - desc->bootloader_size = ALIGN(bl_desc->code_size, sizeof(u32)); - desc->bootloader_imem_offset = bl_desc->start_tag * 256; - desc->bootloader_entry_point = bl_desc->start_tag * 256; - - pos = ALIGN(pos + desc->bootloader_size, BL_DESC_BLK_SIZE); - desc->app_start_offset = pos; - desc->app_size = ALIGN(code->size, BL_DESC_BLK_SIZE) + - ALIGN(data->size, BL_DESC_BLK_SIZE); - desc->app_imem_offset = 0; - desc->app_imem_entry = 0; - desc->app_dmem_offset = 0; - desc->app_resident_code_offset = 0; - desc->app_resident_code_size = ALIGN(code->size, BL_DESC_BLK_SIZE); - - pos = ALIGN(pos + desc->app_resident_code_size, BL_DESC_BLK_SIZE); - desc->app_resident_data_offset = pos - desc->app_start_offset; - desc->app_resident_data_size = ALIGN(data->size, BL_DESC_BLK_SIZE); - - desc->image_size = ALIGN(bl_desc->code_size, BL_DESC_BLK_SIZE) + - desc->app_size; - - image = kzalloc(desc->image_size, GFP_KERNEL); - if (!image) - return ERR_PTR(-ENOMEM); - - memcpy(image + desc->bootloader_start_offset, bl_data, - bl_desc->code_size); - memcpy(image + desc->app_start_offset, code->data, code->size); - memcpy(image + desc->app_start_offset + desc->app_resident_data_offset, - data->data, data->size); - - return image; -} - -/** - * ls_ucode_img_load_gr() - load and prepare a LS GR ucode image - * - * Load the LS microcode, bootloader and signature and pack them into a single - * blob. Also generate the corresponding ucode descriptor. - */ -static int -ls_ucode_img_load_gr(const struct nvkm_subdev *subdev, int maxver, - struct ls_ucode_img *img, const char *falcon_name) -{ - const struct firmware *bl, *code, *data, *sig; - char f[64]; - int ret; - - snprintf(f, sizeof(f), "gr/%s_bl", falcon_name); - ret = nvkm_firmware_get(subdev, f, &bl); - if (ret) - goto error; - - snprintf(f, sizeof(f), "gr/%s_inst", falcon_name); - ret = nvkm_firmware_get(subdev, f, &code); - if (ret) - goto free_bl; - - snprintf(f, sizeof(f), "gr/%s_data", falcon_name); - ret = nvkm_firmware_get(subdev, f, &data); - if (ret) - goto free_inst; - - snprintf(f, sizeof(f), "gr/%s_sig", falcon_name); - ret = nvkm_firmware_get(subdev, f, &sig); - if (ret) - goto free_data; - - img->sig = kmemdup(sig->data, sig->size, GFP_KERNEL); - if (!img->sig) { - ret = -ENOMEM; - goto free_sig; - } - img->sig_size = sig->size; - - img->ucode_data = ls_ucode_img_build(bl, code, data, - &img->ucode_desc); - if (IS_ERR(img->ucode_data)) { - kfree(img->sig); - ret = PTR_ERR(img->ucode_data); - goto free_sig; - } - img->ucode_size = img->ucode_desc.image_size; - -free_sig: - nvkm_firmware_put(sig); -free_data: - nvkm_firmware_put(data); -free_inst: - nvkm_firmware_put(code); -free_bl: - nvkm_firmware_put(bl); -error: - return ret; -} - -int -acr_ls_ucode_load_fecs(const struct nvkm_secboot *sb, int maxver, - struct ls_ucode_img *img) -{ - return ls_ucode_img_load_gr(&sb->subdev, maxver, img, "fecs"); -} - -int -acr_ls_ucode_load_gpccs(const struct nvkm_secboot *sb, int maxver, - struct ls_ucode_img *img) -{ - return ls_ucode_img_load_gr(&sb->subdev, maxver, img, "gpccs"); -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c deleted file mode 100644 index a84a999445bb..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - -#include "ls_ucode.h" -#include "acr.h" - -#include <core/firmware.h> -#include <core/msgqueue.h> -#include <subdev/pmu.h> -#include <engine/sec2.h> -#include <subdev/mc.h> -#include <subdev/timer.h> - -/** - * acr_ls_ucode_load_msgqueue - load and prepare a ucode img for a msgqueue fw - * - * Load the LS microcode, desc and signature and pack them into a single - * blob. - */ -static int -acr_ls_ucode_load_msgqueue(const struct nvkm_subdev *subdev, const char *name, - int maxver, struct ls_ucode_img *img) -{ - const struct firmware *image, *desc, *sig; - char f[64]; - int ver, ret; - - snprintf(f, sizeof(f), "%s/image", name); - ver = nvkm_firmware_get_version(subdev, f, 0, maxver, &image); - if (ver < 0) - return ver; - img->ucode_data = kmemdup(image->data, image->size, GFP_KERNEL); - nvkm_firmware_put(image); - if (!img->ucode_data) - return -ENOMEM; - - snprintf(f, sizeof(f), "%s/desc", name); - ret = nvkm_firmware_get_version(subdev, f, ver, ver, &desc); - if (ret < 0) - return ret; - memcpy(&img->ucode_desc, desc->data, sizeof(img->ucode_desc)); - img->ucode_size = ALIGN(img->ucode_desc.app_start_offset + img->ucode_desc.app_size, 256); - nvkm_firmware_put(desc); - - snprintf(f, sizeof(f), "%s/sig", name); - ret = nvkm_firmware_get_version(subdev, f, ver, ver, &sig); - if (ret < 0) - return ret; - img->sig_size = sig->size; - img->sig = kmemdup(sig->data, sig->size, GFP_KERNEL); - nvkm_firmware_put(sig); - if (!img->sig) - return -ENOMEM; - - return ver; -} - -static int -acr_ls_msgqueue_post_run(struct nvkm_msgqueue *queue, - struct nvkm_falcon *falcon, u32 addr_args) -{ - struct nvkm_device *device = falcon->owner->device; - u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE]; - - memset(buf, 0, sizeof(buf)); - nvkm_msgqueue_write_cmdline(queue, buf); - nvkm_falcon_load_dmem(falcon, buf, addr_args, sizeof(buf), 0); - /* rearm the queue so it will wait for the init message */ - nvkm_msgqueue_reinit(queue); - - /* Enable interrupts */ - nvkm_falcon_wr32(falcon, 0x10, 0xff); - nvkm_mc_intr_mask(device, falcon->owner->index, true); - - /* Start LS firmware on boot falcon */ - nvkm_falcon_start(falcon); - - return 0; -} - -int -acr_ls_ucode_load_pmu(const struct nvkm_secboot *sb, int maxver, - struct ls_ucode_img *img) -{ - struct nvkm_pmu *pmu = sb->subdev.device->pmu; - int ret; - - ret = acr_ls_ucode_load_msgqueue(&sb->subdev, "pmu", maxver, img); - if (ret) - return ret; - - /* Allocate the PMU queue corresponding to the FW version */ - ret = nvkm_msgqueue_new(img->ucode_desc.app_version, pmu->falcon, - sb, &pmu->queue); - if (ret) - return ret; - - return 0; -} - -int -acr_ls_pmu_post_run(const struct nvkm_acr *acr, const struct nvkm_secboot *sb) -{ - struct nvkm_device *device = sb->subdev.device; - struct nvkm_pmu *pmu = device->pmu; - u32 addr_args = pmu->falcon->data.limit - NVKM_MSGQUEUE_CMDLINE_SIZE; - int ret; - - ret = acr_ls_msgqueue_post_run(pmu->queue, pmu->falcon, addr_args); - if (ret) - return ret; - - nvkm_debug(&sb->subdev, "%s started\n", - nvkm_secboot_falcon_name[acr->boot_falcon]); - - return 0; -} - -int -acr_ls_ucode_load_sec2(const struct nvkm_secboot *sb, int maxver, - struct ls_ucode_img *img) -{ - struct nvkm_sec2 *sec = sb->subdev.device->sec2; - int ver, ret; - - ver = acr_ls_ucode_load_msgqueue(&sb->subdev, "sec2", maxver, img); - if (ver < 0) - return ver; - - /* Allocate the PMU queue corresponding to the FW version */ - ret = nvkm_msgqueue_new(img->ucode_desc.app_version, sec->falcon, - sb, &sec->queue); - if (ret) - return ret; - - return ver; -} - -int -acr_ls_sec2_post_run(const struct nvkm_acr *acr, const struct nvkm_secboot *sb) -{ - const struct nvkm_subdev *subdev = &sb->subdev; - struct nvkm_device *device = subdev->device; - struct nvkm_sec2 *sec = device->sec2; - /* on SEC arguments are always at the beginning of EMEM */ - const u32 addr_args = 0x01000000; - int ret; - - ret = acr_ls_msgqueue_post_run(sec->queue, sec->falcon, addr_args); - if (ret) - return ret; - - nvkm_debug(&sb->subdev, "%s started\n", - nvkm_secboot_falcon_name[acr->boot_falcon]); - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h deleted file mode 100644 index 959a7b2dbdc9..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVKM_SECBOOT_PRIV_H__ -#define __NVKM_SECBOOT_PRIV_H__ - -#include <subdev/secboot.h> -#include <subdev/mmu.h> -struct nvkm_gpuobj; - -struct nvkm_secboot_func { - int (*oneinit)(struct nvkm_secboot *); - int (*fini)(struct nvkm_secboot *, bool suspend); - void *(*dtor)(struct nvkm_secboot *); - int (*run_blob)(struct nvkm_secboot *, struct nvkm_gpuobj *, - struct nvkm_falcon *); -}; - -int nvkm_secboot_ctor(const struct nvkm_secboot_func *, struct nvkm_acr *, - struct nvkm_device *, int, struct nvkm_secboot *); -int nvkm_secboot_falcon_reset(struct nvkm_secboot *); -int nvkm_secboot_falcon_run(struct nvkm_secboot *); - -extern const struct nvkm_secboot_func gp102_secboot; - -struct flcn_u64 { - u32 lo; - u32 hi; -}; - -static inline u64 flcn64_to_u64(const struct flcn_u64 f) -{ - return ((u64)f.hi) << 32 | f.lo; -} - -static inline struct flcn_u64 u64_to_flcn64(u64 u) -{ - struct flcn_u64 ret; - - ret.hi = upper_32_bits(u); - ret.lo = lower_32_bits(u); - - return ret; -} - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c index 07914e36939e..fc5ee118e910 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c @@ -21,9 +21,11 @@ * * Authors: Martin Peres */ -#include <nvkm/core/option.h> #include "priv.h" +#include <core/option.h> +#include <subdev/pmu.h> + int nvkm_therm_temp_get(struct nvkm_therm *therm) { @@ -192,8 +194,7 @@ nvkm_therm_fan_mode(struct nvkm_therm *therm, int mode) /* The default PPWR ucode on fermi interferes with fan management */ if ((mode >= ARRAY_SIZE(name)) || - (mode != NVKM_THERM_CTRL_NONE && device->card_type >= NV_C0 && - !device->pmu)) + (mode != NVKM_THERM_CTRL_NONE && nvkm_pmu_fan_controlled(device))) return -EINVAL; /* do not allow automatic fan management if the thermal sensor is @@ -420,10 +421,10 @@ nvkm_therm = { }; void -nvkm_therm_ctor(struct nvkm_therm *therm, struct nvkm_device *device, - int index, const struct nvkm_therm_func *func) +nvkm_therm_ctor(struct nvkm_therm *therm, struct nvkm_device *device, enum nvkm_subdev_type type, + int inst, const struct nvkm_therm_func *func) { - nvkm_subdev_ctor(&nvkm_therm, device, index, &therm->subdev); + nvkm_subdev_ctor(&nvkm_therm, device, type, inst, &therm->subdev); therm->func = func; nvkm_alarm_init(&therm->alarm, nvkm_therm_alarm); @@ -442,13 +443,13 @@ nvkm_therm_ctor(struct nvkm_therm *therm, struct nvkm_device *device, int nvkm_therm_new_(const struct nvkm_therm_func *func, struct nvkm_device *device, - int index, struct nvkm_therm **ptherm) + enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { struct nvkm_therm *therm; if (!(therm = *ptherm = kzalloc(sizeof(*therm), GFP_KERNEL))) return -ENOMEM; - nvkm_therm_ctor(therm, device, index, func); + nvkm_therm_ctor(therm, device, type, inst, func); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c index 96f8da40ac82..4af86f2d3e7e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c @@ -223,12 +223,13 @@ g84_therm = { }; int -g84_therm_new(struct nvkm_device *device, int index, struct nvkm_therm **ptherm) +g84_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_therm **ptherm) { struct nvkm_therm *therm; int ret; - ret = nvkm_therm_new_(&g84_therm, device, index, &therm); + ret = nvkm_therm_new_(&g84_therm, device, type, inst, &therm); *ptherm = therm; if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c index 0981b02790e2..684aff7437ee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c @@ -41,6 +41,7 @@ pwm_info(struct nvkm_therm *therm, int line) default: break; } + break; default: break; } @@ -146,8 +147,8 @@ gf119_therm = { }; int -gf119_therm_new(struct nvkm_device *device, int index, - struct nvkm_therm **ptherm) +gf119_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_therm **ptherm) { - return nvkm_therm_new_(&gf119_therm, device, index, ptherm); + return nvkm_therm_new_(&gf119_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c index 4e03971d2e3d..45e295c271fb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c @@ -35,8 +35,8 @@ gk104_clkgate_enable(struct nvkm_therm *base) int i; /* Program ENG_MANT, ENG_FILTER */ - for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) { - if (!nvkm_device_subdev(dev, order[i].engine)) + for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) { + if (!nvkm_device_subdev(dev, order[i].type, order[i].inst)) continue; nvkm_mask(dev, 0x20200 + order[i].offset, 0xff00, 0x4500); @@ -47,8 +47,8 @@ gk104_clkgate_enable(struct nvkm_therm *base) nvkm_wr32(dev, 0x02028c, therm->idle_filter->hubmmu); /* Enable clockgating (ENG_CLK = RUN->AUTO) */ - for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) { - if (!nvkm_device_subdev(dev, order[i].engine)) + for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) { + if (!nvkm_device_subdev(dev, order[i].type, order[i].inst)) continue; nvkm_mask(dev, 0x20200 + order[i].offset, 0x00ff, 0x0045); @@ -64,8 +64,8 @@ gk104_clkgate_fini(struct nvkm_therm *base, bool suspend) int i; /* ENG_CLK = AUTO->RUN, ENG_PWR = RUN->AUTO */ - for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) { - if (!nvkm_device_subdev(dev, order[i].engine)) + for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) { + if (!nvkm_device_subdev(dev, order[i].type, order[i].inst)) continue; nvkm_mask(dev, 0x20200 + order[i].offset, 0xff, 0x54); @@ -73,15 +73,15 @@ gk104_clkgate_fini(struct nvkm_therm *base, bool suspend) } const struct gk104_clkgate_engine_info gk104_clkgate_engine_info[] = { - { NVKM_ENGINE_GR, 0x00 }, - { NVKM_ENGINE_MSPDEC, 0x04 }, - { NVKM_ENGINE_MSPPP, 0x08 }, - { NVKM_ENGINE_MSVLD, 0x0c }, - { NVKM_ENGINE_CE0, 0x10 }, - { NVKM_ENGINE_CE1, 0x14 }, - { NVKM_ENGINE_MSENC, 0x18 }, - { NVKM_ENGINE_CE2, 0x1c }, - { NVKM_SUBDEV_NR, 0 }, + { NVKM_ENGINE_GR, 0, 0x00 }, + { NVKM_ENGINE_MSPDEC, 0, 0x04 }, + { NVKM_ENGINE_MSPPP, 0, 0x08 }, + { NVKM_ENGINE_MSVLD, 0, 0x0c }, + { NVKM_ENGINE_CE, 0, 0x10 }, + { NVKM_ENGINE_CE, 1, 0x14 }, + { NVKM_ENGINE_MSENC, 0, 0x18 }, + { NVKM_ENGINE_CE, 2, 0x1c }, + { NVKM_SUBDEV_NR }, }; const struct gf100_idle_filter gk104_idle_filter = { @@ -106,9 +106,8 @@ gk104_therm_func = { }; static int -gk104_therm_new_(const struct nvkm_therm_func *func, - struct nvkm_device *device, - int index, +gk104_therm_new_(const struct nvkm_therm_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, const struct gk104_clkgate_engine_info *clkgate_order, const struct gf100_idle_filter *idle_filter, struct nvkm_therm **ptherm) @@ -118,19 +117,17 @@ gk104_therm_new_(const struct nvkm_therm_func *func, if (!therm) return -ENOMEM; - nvkm_therm_ctor(&therm->base, device, index, func); + nvkm_therm_ctor(&therm->base, device, type, inst, func); *ptherm = &therm->base; therm->clkgate_order = clkgate_order; therm->idle_filter = idle_filter; - return 0; } int -gk104_therm_new(struct nvkm_device *device, - int index, struct nvkm_therm **ptherm) +gk104_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { - return gk104_therm_new_(&gk104_therm_func, device, index, + return gk104_therm_new_(&gk104_therm_func, device, type, inst, gk104_clkgate_engine_info, &gk104_idle_filter, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h index 293e7743b19b..9a8641421038 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h @@ -31,7 +31,8 @@ #include "gf100.h" struct gk104_clkgate_engine_info { - enum nvkm_devidx engine; + enum nvkm_subdev_type type; + int inst; u8 offset; }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c index 86848ece4d89..c845fd392f58 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c @@ -68,8 +68,8 @@ gm107_therm = { }; int -gm107_therm_new(struct nvkm_device *device, int index, +gm107_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { - return nvkm_therm_new_(&gm107_therm, device, index, ptherm); + return nvkm_therm_new_(&gm107_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c index 73dc78093d5d..e0cdd12463ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c @@ -32,8 +32,8 @@ gm200_therm = { }; int -gm200_therm_new(struct nvkm_device *device, int index, +gm200_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { - return nvkm_therm_new_(&gm200_therm, device, index, ptherm); + return nvkm_therm_new_(&gm200_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.c index 9f0dea3f61dc..44f021392b95 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.c @@ -49,8 +49,8 @@ gp100_therm = { }; int -gp100_therm_new(struct nvkm_device *device, int index, +gp100_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { - return nvkm_therm_new_(&gp100_therm, device, index, ptherm); + return nvkm_therm_new_(&gp100_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c index 4caf401d001a..9e451bd9395c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c @@ -36,7 +36,7 @@ gt215_therm_fan_sense(struct nvkm_therm *therm) return -ENODEV; } -void +static void gt215_therm_init(struct nvkm_therm *therm) { struct nvkm_device *device = therm->subdev.device; @@ -68,8 +68,8 @@ gt215_therm = { }; int -gt215_therm_new(struct nvkm_device *device, int index, - struct nvkm_therm **ptherm) +gt215_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_therm **ptherm) { - return nvkm_therm_new_(>215_therm, device, index, ptherm); + return nvkm_therm_new_(>215_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c index 6e0ddc1bb583..abf3eda683f0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c @@ -36,8 +36,8 @@ probe_monitoring_device(struct nvkm_i2c_bus *bus, request_module("%s%s", I2C_MODULE_PREFIX, info->type); - client = i2c_new_device(&bus->i2c, info); - if (!client) + client = i2c_new_client_device(&bus->i2c, info); + if (IS_ERR(client)) return false; if (!client->dev.driver || @@ -116,6 +116,9 @@ nvkm_therm_ic_ctor(struct nvkm_therm *therm) return; } + if (nvbios_extdev_skip_probe(bios)) + return; + /* The vbios doesn't provide the address of an exisiting monitoring device. Let's try our static list. */ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c index 2c92ffb5f9d0..c13fee9734df 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c @@ -197,8 +197,8 @@ nv40_therm = { }; int -nv40_therm_new(struct nvkm_device *device, int index, +nv40_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { - return nvkm_therm_new_(&nv40_therm, device, index, ptherm); + return nvkm_therm_new_(&nv40_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c index 9b57b433d4cf..9cf16a75a3cd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c @@ -169,8 +169,8 @@ nv50_therm = { }; int -nv50_therm_new(struct nvkm_device *device, int index, +nv50_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { - return nvkm_therm_new_(&nv50_therm, device, index, ptherm); + return nvkm_therm_new_(&nv50_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h index 21659daf1864..54e960589411 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h @@ -30,10 +30,10 @@ #include <subdev/bios/gpio.h> #include <subdev/bios/perf.h> -int nvkm_therm_new_(const struct nvkm_therm_func *, struct nvkm_device *, - int index, struct nvkm_therm **); -void nvkm_therm_ctor(struct nvkm_therm *therm, struct nvkm_device *device, - int index, const struct nvkm_therm_func *func); +int nvkm_therm_new_(const struct nvkm_therm_func *, struct nvkm_device *, enum nvkm_subdev_type, + int, struct nvkm_therm **); +void nvkm_therm_ctor(struct nvkm_therm *, struct nvkm_device *, enum nvkm_subdev_type, int, + const struct nvkm_therm_func *); struct nvkm_fan { struct nvkm_therm *parent; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c index dd922033628c..8b0da0c06268 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c @@ -183,14 +183,14 @@ nvkm_timer = { int nvkm_timer_new_(const struct nvkm_timer_func *func, struct nvkm_device *device, - int index, struct nvkm_timer **ptmr) + enum nvkm_subdev_type type, int inst, struct nvkm_timer **ptmr) { struct nvkm_timer *tmr; if (!(tmr = *ptmr = kzalloc(sizeof(*tmr), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_timer, device, index, &tmr->subdev); + nvkm_subdev_ctor(&nvkm_timer, device, type, inst, &tmr->subdev); tmr->func = func; INIT_LIST_HEAD(&tmr->alarms); spin_lock_init(&tmr->lock); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c index 9ed5f64912d0..73c3776b6b83 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c @@ -33,7 +33,8 @@ gk20a_timer = { }; int -gk20a_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr) +gk20a_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_timer **ptmr) { - return nvkm_timer_new_(&gk20a_timer, device, index, ptmr); + return nvkm_timer_new_(&gk20a_timer, device, type, inst, ptmr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c index 7f48249f41de..0058e856b378 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c @@ -145,7 +145,8 @@ nv04_timer = { }; int -nv04_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr) +nv04_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_timer **ptmr) { - return nvkm_timer_new_(&nv04_timer, device, index, ptmr); + return nvkm_timer_new_(&nv04_timer, device, type, inst, ptmr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c index bb99a152f26e..7e1f8c22f2a8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c @@ -82,7 +82,8 @@ nv40_timer = { }; int -nv40_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr) +nv40_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_timer **ptmr) { - return nvkm_timer_new_(&nv40_timer, device, index, ptmr); + return nvkm_timer_new_(&nv40_timer, device, type, inst, ptmr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c index 3cf9ec1b1b57..c2b263721f10 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c @@ -79,7 +79,8 @@ nv41_timer = { }; int -nv41_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr) +nv41_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_timer **ptmr) { - return nvkm_timer_new_(&nv41_timer, device, index, ptmr); + return nvkm_timer_new_(&nv41_timer, device, type, inst, ptmr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h index 89e97294b182..e6debe7e2fa9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h @@ -4,8 +4,8 @@ #define nvkm_timer(p) container_of((p), struct nvkm_timer, subdev) #include <subdev/timer.h> -int nvkm_timer_new_(const struct nvkm_timer_func *, struct nvkm_device *, - int index, struct nvkm_timer **); +int nvkm_timer_new_(const struct nvkm_timer_func *, struct nvkm_device *, enum nvkm_subdev_type, + int, struct nvkm_timer **); struct nvkm_timer_func { void (*init)(struct nvkm_timer *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild index 438d9d78ab52..d5db845195dc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild @@ -1,3 +1,4 @@ # SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/top/base.o nvkm-y += nvkm/subdev/top/gk104.o +nvkm-y += nvkm/subdev/top/ga100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c index cce6e4e90ebf..28d0789f50fe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c @@ -28,7 +28,8 @@ nvkm_top_device_new(struct nvkm_top *top) { struct nvkm_top_device *info = kmalloc(sizeof(*info), GFP_KERNEL); if (info) { - info->index = NVKM_SUBDEV_NR; + info->type = NVKM_SUBDEV_NR; + info->inst = -1; info->addr = 0; info->fault = -1; info->engine = -1; @@ -41,14 +42,14 @@ nvkm_top_device_new(struct nvkm_top *top) } u32 -nvkm_top_addr(struct nvkm_device *device, enum nvkm_devidx index) +nvkm_top_addr(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { struct nvkm_top *top = device->top; struct nvkm_top_device *info; if (top) { list_for_each_entry(info, &top->device, head) { - if (info->index == index) + if (info->type == type && info->inst == inst) return info->addr; } } @@ -57,14 +58,14 @@ nvkm_top_addr(struct nvkm_device *device, enum nvkm_devidx index) } u32 -nvkm_top_reset(struct nvkm_device *device, enum nvkm_devidx index) +nvkm_top_reset(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { struct nvkm_top *top = device->top; struct nvkm_top_device *info; if (top) { list_for_each_entry(info, &top->device, head) { - if (info->index == index && info->reset >= 0) + if (info->type == type && info->inst == inst && info->reset >= 0) return BIT(info->reset); } } @@ -73,14 +74,14 @@ nvkm_top_reset(struct nvkm_device *device, enum nvkm_devidx index) } u32 -nvkm_top_intr_mask(struct nvkm_device *device, enum nvkm_devidx devidx) +nvkm_top_intr_mask(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { struct nvkm_top *top = device->top; struct nvkm_top_device *info; if (top) { list_for_each_entry(info, &top->device, head) { - if (info->index == devidx && info->intr >= 0) + if (info->type == type && info->inst == inst && info->intr >= 0) return BIT(info->intr); } } @@ -88,44 +89,21 @@ nvkm_top_intr_mask(struct nvkm_device *device, enum nvkm_devidx devidx) return 0; } -u32 -nvkm_top_intr(struct nvkm_device *device, u32 intr, u64 *psubdevs) -{ - struct nvkm_top *top = device->top; - struct nvkm_top_device *info; - u64 subdevs = 0; - u32 handled = 0; - - if (top) { - list_for_each_entry(info, &top->device, head) { - if (info->index != NVKM_SUBDEV_NR && info->intr >= 0) { - if (intr & BIT(info->intr)) { - subdevs |= BIT_ULL(info->index); - handled |= BIT(info->intr); - } - } - } - } - - *psubdevs = subdevs; - return intr & ~handled; -} - int -nvkm_top_fault_id(struct nvkm_device *device, enum nvkm_devidx devidx) +nvkm_top_fault_id(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { struct nvkm_top *top = device->top; struct nvkm_top_device *info; list_for_each_entry(info, &top->device, head) { - if (info->index == devidx && info->fault >= 0) + if (info->type == type && info->inst == inst && info->fault >= 0) return info->fault; } return -ENOENT; } -enum nvkm_devidx +struct nvkm_subdev * nvkm_top_fault(struct nvkm_device *device, int fault) { struct nvkm_top *top = device->top; @@ -133,28 +111,10 @@ nvkm_top_fault(struct nvkm_device *device, int fault) list_for_each_entry(info, &top->device, head) { if (info->fault == fault) - return info->index; - } - - return NVKM_SUBDEV_NR; -} - -enum nvkm_devidx -nvkm_top_engine(struct nvkm_device *device, int index, int *runl, int *engn) -{ - struct nvkm_top *top = device->top; - struct nvkm_top_device *info; - int n = 0; - - list_for_each_entry(info, &top->device, head) { - if (info->engine >= 0 && info->runlist >= 0 && n++ == index) { - *runl = info->runlist; - *engn = info->engine; - return info->index; - } + return nvkm_device_subdev(device, info->type, info->inst); } - return -ENODEV; + return NULL; } static int @@ -186,12 +146,12 @@ nvkm_top = { int nvkm_top_new_(const struct nvkm_top_func *func, struct nvkm_device *device, - int index, struct nvkm_top **ptop) + enum nvkm_subdev_type type, int inst, struct nvkm_top **ptop) { struct nvkm_top *top; if (!(top = *ptop = kzalloc(sizeof(*top), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_top, device, index, &top->subdev); + nvkm_subdev_ctor(&nvkm_top, device, type, inst, &top->subdev); top->func = func; INIT_LIST_HEAD(&top->device); return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c new file mode 100644 index 000000000000..c982d834c8d9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c @@ -0,0 +1,108 @@ +/* + * Copyright 2021 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +static int +ga100_top_oneinit(struct nvkm_top *top) +{ + struct nvkm_subdev *subdev = &top->subdev; + struct nvkm_device *device = subdev->device; + struct nvkm_top_device *info = NULL; + u32 data, type, inst; + int i, n, size = nvkm_rd32(device, 0x0224fc) >> 20; + + for (i = 0, n = 0; i < size; i++) { + if (!info) { + if (!(info = nvkm_top_device_new(top))) + return -ENOMEM; + type = ~0; + inst = 0; + } + + data = nvkm_rd32(device, 0x022800 + (i * 0x04)); + nvkm_trace(subdev, "%02x: %08x\n", i, data); + if (!data && n == 0) + continue; + + switch (n++) { + case 0: + type = (data & 0x3f000000) >> 24; + inst = (data & 0x000f0000) >> 16; + info->fault = (data & 0x0000007f); + break; + case 1: + info->addr = (data & 0x00fff000); + info->reset = (data & 0x0000001f); + break; + case 2: + info->runlist = (data & 0x00fffc00); + info->engine = (data & 0x00000003); + break; + default: + break; + } + + if (data & 0x80000000) + continue; + n = 0; + + /* Translate engine type to NVKM engine identifier. */ +#define I_(T,I) do { info->type = (T); info->inst = (I); } while(0) +#define O_(T,I) do { WARN_ON(inst); I_(T, I); } while (0) + switch (type) { + case 0x00000000: O_(NVKM_ENGINE_GR , 0); break; + case 0x0000000d: O_(NVKM_ENGINE_SEC2 , 0); break; + case 0x0000000e: I_(NVKM_ENGINE_NVENC , inst); break; + case 0x00000010: I_(NVKM_ENGINE_NVDEC , inst); break; + case 0x00000012: I_(NVKM_SUBDEV_IOCTRL, inst); break; + case 0x00000013: I_(NVKM_ENGINE_CE , inst); break; + case 0x00000014: O_(NVKM_SUBDEV_GSP , 0); break; + case 0x00000015: O_(NVKM_ENGINE_NVJPG , 0); break; + case 0x00000016: O_(NVKM_ENGINE_OFA , 0); break; + case 0x00000017: O_(NVKM_SUBDEV_FLA , 0); break; + break; + default: + break; + } + + nvkm_debug(subdev, "%02x.%d (%8s): addr %06x fault %2d " + "runlist %6x engine %2d reset %2d\n", type, inst, + info->type == NVKM_SUBDEV_NR ? "????????" : nvkm_subdev_type[info->type], + info->addr, info->fault, info->runlist < 0 ? 0 : info->runlist, + info->engine, info->reset); + info = NULL; + } + + return 0; +} + +static const struct nvkm_top_func +ga100_top = { + .oneinit = ga100_top_oneinit, +}; + +int +ga100_top_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_top **ptop) +{ + return nvkm_top_new_(&ga100_top, device, type, inst, ptop); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c index e01746ce9fc4..4dcad97bd505 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c @@ -70,27 +70,26 @@ gk104_top_oneinit(struct nvkm_top *top) continue; /* Translate engine type to NVKM engine identifier. */ -#define A_(A) if (inst == 0) info->index = NVKM_ENGINE_##A -#define B_(A) if (inst + NVKM_ENGINE_##A##0 < NVKM_ENGINE_##A##_LAST + 1) \ - info->index = NVKM_ENGINE_##A##0 + inst -#define C_(A) if (inst == 0) info->index = NVKM_SUBDEV_##A +#define I_(T,I) do { info->type = (T); info->inst = (I); } while(0) +#define O_(T,I) do { WARN_ON(inst); I_(T, I); } while (0) switch (type) { - case 0x00000000: A_(GR ); break; - case 0x00000001: A_(CE0 ); break; - case 0x00000002: A_(CE1 ); break; - case 0x00000003: A_(CE2 ); break; - case 0x00000008: A_(MSPDEC); break; - case 0x00000009: A_(MSPPP ); break; - case 0x0000000a: A_(MSVLD ); break; - case 0x0000000b: A_(MSENC ); break; - case 0x0000000c: A_(VIC ); break; - case 0x0000000d: A_(SEC2 ); break; - case 0x0000000e: B_(NVENC ); break; - case 0x0000000f: A_(NVENC1); break; - case 0x00000010: B_(NVDEC ); break; - case 0x00000013: B_(CE ); break; - case 0x00000014: C_(GSP ); break; - break; + case 0x00000000: O_(NVKM_ENGINE_GR , 0); break; + case 0x00000001: O_(NVKM_ENGINE_CE , 0); break; + case 0x00000002: O_(NVKM_ENGINE_CE , 1); break; + case 0x00000003: O_(NVKM_ENGINE_CE , 2); break; + case 0x00000008: O_(NVKM_ENGINE_MSPDEC, 0); break; + case 0x00000009: O_(NVKM_ENGINE_MSPPP , 0); break; + case 0x0000000a: O_(NVKM_ENGINE_MSVLD , 0); break; + case 0x0000000b: O_(NVKM_ENGINE_MSENC , 0); break; + case 0x0000000c: O_(NVKM_ENGINE_VIC , 0); break; + case 0x0000000d: O_(NVKM_ENGINE_SEC2 , 0); break; + case 0x0000000e: I_(NVKM_ENGINE_NVENC , inst); break; + case 0x0000000f: O_(NVKM_ENGINE_NVENC , 1); break; + case 0x00000010: I_(NVKM_ENGINE_NVDEC , inst); break; + case 0x00000012: I_(NVKM_SUBDEV_IOCTRL, inst); break; + case 0x00000013: I_(NVKM_ENGINE_CE , inst); break; + case 0x00000014: O_(NVKM_SUBDEV_GSP , 0); break; + case 0x00000015: O_(NVKM_ENGINE_NVJPG , 0); break; default: break; } @@ -98,8 +97,7 @@ gk104_top_oneinit(struct nvkm_top *top) nvkm_debug(subdev, "%02x.%d (%8s): addr %06x fault %2d " "engine %2d runlist %2d intr %2d " "reset %2d\n", type, inst, - info->index == NVKM_SUBDEV_NR ? NULL : - nvkm_subdev_name[info->index], + info->type == NVKM_SUBDEV_NR ? "????????" : nvkm_subdev_type[info->type], info->addr, info->fault, info->engine, info->runlist, info->intr, info->reset); info = NULL; @@ -114,7 +112,8 @@ gk104_top = { }; int -gk104_top_new(struct nvkm_device *device, int index, struct nvkm_top **ptop) +gk104_top_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_top **ptop) { - return nvkm_top_new_(&gk104_top, device, index, ptop); + return nvkm_top_new_(&gk104_top, device, type, inst, ptop); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h index a16baa2941cf..8e103a836705 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h @@ -8,19 +8,8 @@ struct nvkm_top_func { int (*oneinit)(struct nvkm_top *); }; -int nvkm_top_new_(const struct nvkm_top_func *, struct nvkm_device *, - int, struct nvkm_top **); - -struct nvkm_top_device { - enum nvkm_devidx index; - u32 addr; - int fault; - int engine; - int runlist; - int reset; - int intr; - struct list_head head; -}; +int nvkm_top_new_(const struct nvkm_top_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_top **); struct nvkm_top_device *nvkm_top_device_new(struct nvkm_top *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c index e344901cfdc7..a17a6dd8d3de 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c @@ -281,12 +281,12 @@ nvkm_volt = { void nvkm_volt_ctor(const struct nvkm_volt_func *func, struct nvkm_device *device, - int index, struct nvkm_volt *volt) + enum nvkm_subdev_type type, int inst, struct nvkm_volt *volt) { struct nvkm_bios *bios = device->bios; int i; - nvkm_subdev_ctor(&nvkm_volt, device, index, &volt->subdev); + nvkm_subdev_ctor(&nvkm_volt, device, type, inst, &volt->subdev); volt->func = func; /* Assuming the non-bios device should build the voltage table later */ @@ -319,10 +319,10 @@ nvkm_volt_ctor(const struct nvkm_volt_func *func, struct nvkm_device *device, int nvkm_volt_new_(const struct nvkm_volt_func *func, struct nvkm_device *device, - int index, struct nvkm_volt **pvolt) + enum nvkm_subdev_type type, int inst, struct nvkm_volt **pvolt) { if (!(*pvolt = kzalloc(sizeof(**pvolt), GFP_KERNEL))) return -ENOMEM; - nvkm_volt_ctor(func, device, index, *pvolt); + nvkm_volt_ctor(func, device, type, inst, *pvolt); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.c index d9ed6925ca64..b47a1c0817be 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.c @@ -56,12 +56,13 @@ gf100_volt = { }; int -gf100_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) +gf100_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_volt **pvolt) { struct nvkm_volt *volt; int ret; - ret = nvkm_volt_new_(&gf100_volt, device, index, &volt); + ret = nvkm_volt_new_(&gf100_volt, device, type, inst, &volt); *pvolt = volt; if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.c index 547a58f0aeac..03c8a2c2916c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.c @@ -46,12 +46,13 @@ gf117_volt = { }; int -gf117_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) +gf117_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_volt **pvolt) { struct nvkm_volt *volt; int ret; - ret = nvkm_volt_new_(&gf117_volt, device, index, &volt); + ret = nvkm_volt_new_(&gf117_volt, device, type, inst, &volt); *pvolt = volt; if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c index 1c744e029454..d1ce4309cfb8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c @@ -95,7 +95,8 @@ gk104_volt_pwm = { }; int -gk104_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) +gk104_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_volt **pvolt) { const struct nvkm_volt_func *volt_func = &gk104_volt_gpio; struct dcb_gpio_func gpio; @@ -114,7 +115,7 @@ gk104_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) if (!(volt = kzalloc(sizeof(*volt), GFP_KERNEL))) return -ENOMEM; - nvkm_volt_ctor(volt_func, device, index, &volt->base); + nvkm_volt_ctor(volt_func, device, type, inst, &volt->base); *pvolt = &volt->base; volt->bios = bios; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c index ce5d83cdc7cf..8c2faa964511 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c @@ -144,14 +144,14 @@ gk20a_volt = { }; int -gk20a_volt_ctor(struct nvkm_device *device, int index, +gk20a_volt_ctor(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, const struct cvb_coef *coefs, int nb_coefs, int vmin, struct gk20a_volt *volt) { struct nvkm_device_tegra *tdev = device->func->tegra(device); int i, uv; - nvkm_volt_ctor(&gk20a_volt, device, index, &volt->base); + nvkm_volt_ctor(&gk20a_volt, device, type, inst, &volt->base); uv = regulator_get_voltage(tdev->vdd); nvkm_debug(&volt->base.subdev, "the default voltage is %duV\n", uv); @@ -172,7 +172,7 @@ gk20a_volt_ctor(struct nvkm_device *device, int index, } int -gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) +gk20a_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_volt **pvolt) { struct gk20a_volt *volt; @@ -181,6 +181,6 @@ gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) return -ENOMEM; *pvolt = &volt->base; - return gk20a_volt_ctor(device, index, gk20a_cvb_coef, + return gk20a_volt_ctor(device, type, inst, gk20a_cvb_coef, ARRAY_SIZE(gk20a_cvb_coef), 0, volt); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.h b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.h index 6a6c97f9684e..01f8a5fcf496 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.h @@ -37,7 +37,7 @@ struct gk20a_volt { struct regulator *vdd; }; -int gk20a_volt_ctor(struct nvkm_device *device, int index, +int gk20a_volt_ctor(struct nvkm_device *device, enum nvkm_subdev_type, int, const struct cvb_coef *coefs, int nb_coefs, int vmin, struct gk20a_volt *volt); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c index 2925b9cae681..c2e9694d333f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c @@ -64,7 +64,8 @@ static const u32 speedo_to_vmin[] = { }; int -gm20b_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) +gm20b_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_volt **pvolt) { struct nvkm_device_tegra *tdev = device->func->tegra(device); struct gk20a_volt *volt; @@ -84,9 +85,9 @@ gm20b_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) vmin = speedo_to_vmin[tdev->gpu_speedo_id]; if (tdev->gpu_speedo_id >= 1) - return gk20a_volt_ctor(device, index, gm20b_na_cvb_coef, - ARRAY_SIZE(gm20b_na_cvb_coef), vmin, volt); + return gk20a_volt_ctor(device, type, inst, gm20b_na_cvb_coef, + ARRAY_SIZE(gm20b_na_cvb_coef), vmin, volt); else - return gk20a_volt_ctor(device, index, gm20b_cvb_coef, - ARRAY_SIZE(gm20b_cvb_coef), vmin, volt); + return gk20a_volt_ctor(device, type, inst, gm20b_cvb_coef, + ARRAY_SIZE(gm20b_cvb_coef), vmin, volt); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c index 23409387abb5..d6a587d6082d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c @@ -30,12 +30,13 @@ nv40_volt = { }; int -nv40_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) +nv40_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_volt **pvolt) { struct nvkm_volt *volt; int ret; - ret = nvkm_volt_new_(&nv40_volt, device, index, &volt); + ret = nvkm_volt_new_(&nv40_volt, device, type, inst, &volt); *pvolt = volt; if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h index 75f13a34671f..24e2d16d1913 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h @@ -4,10 +4,10 @@ #define nvkm_volt(p) container_of((p), struct nvkm_volt, subdev) #include <subdev/volt.h> -void nvkm_volt_ctor(const struct nvkm_volt_func *, struct nvkm_device *, - int index, struct nvkm_volt *); -int nvkm_volt_new_(const struct nvkm_volt_func *, struct nvkm_device *, - int index, struct nvkm_volt **); +void nvkm_volt_ctor(const struct nvkm_volt_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_volt *); +int nvkm_volt_new_(const struct nvkm_volt_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_volt **); struct nvkm_volt_func { int (*oneinit)(struct nvkm_volt *); |