diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-03-06 14:18:59 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-03-06 14:18:59 -0800 |
commit | 45763bf4bc1ebdf8eb95697607e1fd042a3e1221 (patch) | |
tree | c5b26c2d5d1190247b59d6d1fe68b8a247351362 /drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h | |
parent | da2577fe63f865cd9dc785a42c29c0071f567a35 (diff) | |
parent | 142a0f83b216a607aebed42e54a1be620765e28c (diff) |
Merge tag 'char-misc-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver updates from Greg KH:
"Here is the big char/misc driver patch pull request for 5.1-rc1.
The largest thing by far is the new habanalabs driver for their AI
accelerator chip. For now it is in the drivers/misc directory but will
probably move to a new directory soon along with other drivers of this
type.
Other than that, just the usual set of individual driver updates and
fixes. There's an "odd" merge in here from the DRM tree that they
asked me to do as the MEI driver is starting to interact with the i915
driver, and it needed some coordination. All of those patches have
been properly acked by the relevant subsystem maintainers.
All of these have been in linux-next with no reported issues, most for
quite some time"
* tag 'char-misc-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (219 commits)
habanalabs: adjust Kconfig to fix build errors
habanalabs: use %px instead of %p in error print
habanalabs: use do_div for 64-bit divisions
intel_th: gth: Fix an off-by-one in output unassigning
habanalabs: fix little-endian<->cpu conversion warnings
habanalabs: use NULL to initialize array of pointers
habanalabs: fix little-endian<->cpu conversion warnings
habanalabs: soft-reset device if context-switch fails
habanalabs: print pointer using %p
habanalabs: fix memory leak with CBs with unaligned size
habanalabs: return correct error code on MMU mapping failure
habanalabs: add comments in uapi/misc/habanalabs.h
habanalabs: extend QMAN0 job timeout
habanalabs: set DMA0 completion to SOB 1007
habanalabs: fix validation of WREG32 to DMA completion
habanalabs: fix mmu cache registers init
habanalabs: disable CPU access on timeouts
habanalabs: add MMU DRAM default page mapping
habanalabs: Dissociate RAZWI info from event types
misc/habanalabs: adjust Kconfig to fix build errors
...
Diffstat (limited to 'drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h')
-rw-r--r-- | drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h new file mode 100644 index 000000000000..920231d0afa5 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC_PLL_REGS_H_ +#define ASIC_REG_TPC_PLL_REGS_H_ + +/* + ***************************************** + * TPC_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmTPC_PLL_NR 0xE01100 + +#define mmTPC_PLL_NF 0xE01104 + +#define mmTPC_PLL_OD 0xE01108 + +#define mmTPC_PLL_NB 0xE0110C + +#define mmTPC_PLL_CFG 0xE01110 + +#define mmTPC_PLL_LOSE_MASK 0xE01120 + +#define mmTPC_PLL_LOCK_INTR 0xE01128 + +#define mmTPC_PLL_LOCK_BYPASS 0xE0112C + +#define mmTPC_PLL_DATA_CHNG 0xE01130 + +#define mmTPC_PLL_RST 0xE01134 + +#define mmTPC_PLL_SLIP_WD_CNTR 0xE01150 + +#define mmTPC_PLL_DIV_FACTOR_0 0xE01200 + +#define mmTPC_PLL_DIV_FACTOR_1 0xE01204 + +#define mmTPC_PLL_DIV_FACTOR_2 0xE01208 + +#define mmTPC_PLL_DIV_FACTOR_3 0xE0120C + +#define mmTPC_PLL_DIV_FACTOR_CMD_0 0xE01220 + +#define mmTPC_PLL_DIV_FACTOR_CMD_1 0xE01224 + +#define mmTPC_PLL_DIV_FACTOR_CMD_2 0xE01228 + +#define mmTPC_PLL_DIV_FACTOR_CMD_3 0xE0122C + +#define mmTPC_PLL_DIV_SEL_0 0xE01280 + +#define mmTPC_PLL_DIV_SEL_1 0xE01284 + +#define mmTPC_PLL_DIV_SEL_2 0xE01288 + +#define mmTPC_PLL_DIV_SEL_3 0xE0128C + +#define mmTPC_PLL_DIV_EN_0 0xE012A0 + +#define mmTPC_PLL_DIV_EN_1 0xE012A4 + +#define mmTPC_PLL_DIV_EN_2 0xE012A8 + +#define mmTPC_PLL_DIV_EN_3 0xE012AC + +#define mmTPC_PLL_DIV_FACTOR_BUSY_0 0xE012C0 + +#define mmTPC_PLL_DIV_FACTOR_BUSY_1 0xE012C4 + +#define mmTPC_PLL_DIV_FACTOR_BUSY_2 0xE012C8 + +#define mmTPC_PLL_DIV_FACTOR_BUSY_3 0xE012CC + +#define mmTPC_PLL_CLK_GATER 0xE01300 + +#define mmTPC_PLL_CLK_RLX_0 0xE01310 + +#define mmTPC_PLL_CLK_RLX_1 0xE01314 + +#define mmTPC_PLL_CLK_RLX_2 0xE01318 + +#define mmTPC_PLL_CLK_RLX_3 0xE0131C + +#define mmTPC_PLL_REF_CNTR_PERIOD 0xE01400 + +#define mmTPC_PLL_REF_LOW_THRESHOLD 0xE01410 + +#define mmTPC_PLL_REF_HIGH_THRESHOLD 0xE01420 + +#define mmTPC_PLL_PLL_NOT_STABLE 0xE01430 + +#define mmTPC_PLL_FREQ_CALC_EN 0xE01440 + +#endif /* ASIC_REG_TPC_PLL_REGS_H_ */ + |