diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2020-07-29 17:43:57 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2020-08-17 15:58:02 +0200 |
| commit | 7b70689b07c1d336a5ad6906927aa413619029bd (patch) | |
| tree | a5d91a61977290d5d6c78946c7d0b45a29b88994 /drivers/clk/meson/clk-phase.h | |
| parent | 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5 (diff) | |
clk: meson: add sclk-ws driver
This is yet another simple but odd driver for the audio block of the g12a
and sm1 SoC families.
For TDMOUT's sclk to be properly inverted, bit 29 of
AUDIO_CLK_TDMOUT_x_CTRL should be the inverse of bit 28.
IOW bit28 == !bit29 at all times
This setting is automatically applied on axg and the manual setting was
added on g12a.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200729154359.1983085-2-jbrunet@baylibre.com
Diffstat (limited to 'drivers/clk/meson/clk-phase.h')
| -rw-r--r-- | drivers/clk/meson/clk-phase.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/meson/clk-phase.h b/drivers/clk/meson/clk-phase.h index 5579f9ced142..b637b9b227bc 100644 --- a/drivers/clk/meson/clk-phase.h +++ b/drivers/clk/meson/clk-phase.h @@ -20,7 +20,13 @@ struct meson_clk_triphase_data { struct parm ph2; }; +struct meson_sclk_ws_inv_data { + struct parm ph; + struct parm ws; +}; + extern const struct clk_ops meson_clk_phase_ops; extern const struct clk_ops meson_clk_triphase_ops; +extern const struct clk_ops meson_sclk_ws_inv_ops; #endif /* __MESON_CLK_PHASE_H */ |