diff options
| author | Thomas Gleixner <tglx@linutronix.de> | 2019-05-27 08:55:01 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-05-30 11:26:32 -0700 |
| commit | 2874c5fd284268364ece81a7bd936f3c8168e567 (patch) | |
| tree | 81a787bcb5f3886d55dd56c4d583ff1e06041d77 /drivers/clk/at91/clk-audio-pll.c | |
| parent | a912e80bd0bbfec053ccfdca625c2c760a8b08e8 (diff) | |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 3029 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/clk/at91/clk-audio-pll.c')
| -rw-r--r-- | drivers/clk/at91/clk-audio-pll.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c index 3cc4a82f4e9f..a92da64c12e1 100644 --- a/drivers/clk/at91/clk-audio-pll.c +++ b/drivers/clk/at91/clk-audio-pll.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2016 Atmel Corporation, * Songjun Wu <songjun.wu@atmel.com>, @@ -5,11 +6,6 @@ * Copyright (C) 2017 Free Electrons, * Quentin Schulz <quentin.schulz@free-electrons.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * * The Sama5d2 SoC has two audio PLLs (PMC and PAD) that shares the same parent * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of * its own parent. PMC and PAD can then divide the FRAC rate to best match the @@ -32,7 +28,6 @@ * rate - rate is adjustable. * clk->rate = parent->rate / (qdaudio * div)) * parent - fixed parent. No clk_set_parent support - * */ #include <linux/clk.h> |