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authorRafael J. Wysocki <rafael.j.wysocki@intel.com>2021-04-26 17:04:41 +0200
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2021-04-26 17:04:41 +0200
commitb6237f61fc9ca79b8771a4fa412d2c630c9f8d2b (patch)
tree5a83f6f90292c16b3386f67d35d6948537d26dc8 /drivers/acpi/cppc_acpi.c
parentaad659e490eff3b8e11fca292e6ae4c75e86e871 (diff)
parent6ee4bdc27d1aee6fb4dde9b28c95fe87d87c1438 (diff)
Merge branch 'acpi-misc'
* acpi-misc: ACPI: dock: fix some coding style issues ACPI: sysfs: fix some coding style issues ACPI: PM: add a missed blank line after declarations ACPI: custom_method: fix a coding style issue ACPI: CPPC: fix some coding style issues ACPI: button: fix some coding style issues ACPI: battery: fix some coding style issues ACPI: acpi_pad: add a missed blank line after declarations ACPI: LPSS: add a missed blank line after declarations ACPI: ipmi: remove useless return statement for void function ACPI: processor: fix some coding style issues ACPI: APD: fix a block comment align issue ACPI: AC: fix some coding style issues ACPI: fix various typos in comments
Diffstat (limited to 'drivers/acpi/cppc_acpi.c')
-rw-r--r--drivers/acpi/cppc_acpi.c81
1 files changed, 41 insertions, 40 deletions
diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 2c2748041cef..a4d4eebba1da 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -100,14 +100,14 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
(cpc)->cpc_entry.reg.space_id == \
ACPI_ADR_SPACE_PLATFORM_COMM)
-/* Evalutes to True if reg is a NULL register descriptor */
+/* Evaluates to True if reg is a NULL register descriptor */
#define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
(reg)->address == 0 && \
(reg)->bit_width == 0 && \
(reg)->bit_offset == 0 && \
(reg)->access_width == 0)
-/* Evalutes to True if an optional cpc field is supported */
+/* Evaluates to True if an optional cpc field is supported */
#define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
!!(cpc)->cpc_entry.int_value : \
!IS_NULL_REG(&(cpc)->cpc_entry.reg))
@@ -318,6 +318,7 @@ end:
if (unlikely(ret)) {
for_each_possible_cpu(i) {
struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
+
if (!desc)
continue;
@@ -769,7 +770,7 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
} else {
- pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id);
+ pr_debug("Err in entry:%d in CPC table of CPU:%d\n", i, pr->id);
goto out_free;
}
}
@@ -859,7 +860,7 @@ void acpi_cppc_processor_exit(struct acpi_processor *pr)
void __iomem *addr;
int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
- if (pcc_ss_id >=0 && pcc_data[pcc_ss_id]) {
+ if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
pcc_data[pcc_ss_id]->refcount--;
if (!pcc_data[pcc_ss_id]->refcount) {
@@ -946,22 +947,22 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
val, reg->bit_width);
switch (reg->bit_width) {
- case 8:
- *val = readb_relaxed(vaddr);
- break;
- case 16:
- *val = readw_relaxed(vaddr);
- break;
- case 32:
- *val = readl_relaxed(vaddr);
- break;
- case 64:
- *val = readq_relaxed(vaddr);
- break;
- default:
- pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
- reg->bit_width, pcc_ss_id);
- ret_val = -EFAULT;
+ case 8:
+ *val = readb_relaxed(vaddr);
+ break;
+ case 16:
+ *val = readw_relaxed(vaddr);
+ break;
+ case 32:
+ *val = readl_relaxed(vaddr);
+ break;
+ case 64:
+ *val = readq_relaxed(vaddr);
+ break;
+ default:
+ pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
+ reg->bit_width, pcc_ss_id);
+ ret_val = -EFAULT;
}
return ret_val;
@@ -985,23 +986,23 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
val, reg->bit_width);
switch (reg->bit_width) {
- case 8:
- writeb_relaxed(val, vaddr);
- break;
- case 16:
- writew_relaxed(val, vaddr);
- break;
- case 32:
- writel_relaxed(val, vaddr);
- break;
- case 64:
- writeq_relaxed(val, vaddr);
- break;
- default:
- pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
- reg->bit_width, pcc_ss_id);
- ret_val = -EFAULT;
- break;
+ case 8:
+ writeb_relaxed(val, vaddr);
+ break;
+ case 16:
+ writew_relaxed(val, vaddr);
+ break;
+ case 32:
+ writel_relaxed(val, vaddr);
+ break;
+ case 64:
+ writeq_relaxed(val, vaddr);
+ break;
+ default:
+ pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
+ reg->bit_width, pcc_ss_id);
+ ret_val = -EFAULT;
+ break;
}
return ret_val;
@@ -1321,7 +1322,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
* is still with OSPM.
* pending_pcc_write_cmd can also be cleared by a different CPU, if
* there was a pcc CMD_READ waiting on down_write and it steals the lock
- * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this
+ * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
* case during a CMD_READ and if there are pending writes it delivers
* the write command before servicing the read command
*/
@@ -1346,8 +1347,8 @@ EXPORT_SYMBOL_GPL(cppc_set_perf);
/**
* cppc_get_transition_latency - returns frequency transition latency in ns
*
- * ACPI CPPC does not explicitly specifiy how a platform can specify the
- * transition latency for perfromance change requests. The closest we have
+ * ACPI CPPC does not explicitly specify how a platform can specify the
+ * transition latency for performance change requests. The closest we have
* is the timing information from the PCCT tables which provides the info
* on the number and frequency of PCC commands the platform can handle.
*/