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authorVincent Chen <vincent.chen@sifive.com>2020-02-21 10:47:55 +0800
committerPalmer Dabbelt <palmerdabbelt@google.com>2020-03-03 10:27:46 -0800
commitaad15bc85c189261b0554a7dc8e053641dd4025c (patch)
tree5514fdeb5db500ae542b733ae9aa11ec62fe15f4 /arch
parent0cff8bff7af886af0923d5c91776cd51603e531f (diff)
riscv: Change code model of module to medany to improve data accessing
All the loaded module locates in the region [&_end-2G,VMALLOC_END] at runtime, so the distance from the module start to the end of the kernel image does not exceed 2GB. Hence, the code model of the kernel module can be changed to medany to improve the performance data access. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/riscv/Makefile6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index b9009a2fbaf5..259cb53d7f20 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -13,8 +13,10 @@ LDFLAGS_vmlinux :=
ifeq ($(CONFIG_DYNAMIC_FTRACE),y)
LDFLAGS_vmlinux := --no-relax
endif
-KBUILD_AFLAGS_MODULE += -fPIC
-KBUILD_CFLAGS_MODULE += -fPIC
+
+ifeq ($(CONFIG_64BIT)$(CONFIG_CMODEL_MEDLOW),yy)
+KBUILD_CFLAGS_MODULE += -mcmodel=medany
+endif
export BITS
ifeq ($(CONFIG_ARCH_RV64I),y)