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authorMax Filippov <jcmvbkbc@gmail.com>2015-06-04 13:41:27 +0300
committerMax Filippov <jcmvbkbc@gmail.com>2015-08-17 07:32:51 +0300
commitdb8165f5d975533880f516fed142364ba3e6046e (patch)
treee737a4fa9c48d724cee5b25653b231281ff57f3c /arch/xtensa
parent5fdf377d802ddd439fe16dd2e9e38039af535af2 (diff)
xtensa: select PERF_USE_VMALLOC for cache-aliasing configurations
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa')
-rw-r--r--arch/xtensa/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 14a03fe628c7..66e4043659fe 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -22,6 +22,7 @@ config XTENSA
select HAVE_PERF_EVENTS
select IRQ_DOMAIN
select MODULES_USE_ELF_RELA
+ select PERF_USE_VMALLOC
select VIRT_TO_BUS
help
Xtensa processors are 32-bit RISC machines designed by Tensilica