diff options
| author | Damien Le Moal <damien.lemoal@wdc.com> | 2020-03-16 09:47:36 +0900 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-04-03 10:45:33 -0700 |
| commit | 956d705dd279f70d5a222375fa97b637d6e8c43d (patch) | |
| tree | e781737be5e254e288f757535a7d020d13286ec6 /arch/riscv/kernel/Makefile | |
| parent | f1e58583b9c7ceae7f11646e9edf2561d67f29c9 (diff) | |
riscv: Unaligned load/store handling for M_MODE
Add handlers for unaligned load and store traps that may be generated
by applications. Code heavily inspired from the OpenSBI project.
Handling of the unaligned access traps is suitable for applications
compiled with or without compressed instructions and is independent of
the kernel CONFIG_RISCV_ISA_C option value.
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/riscv/kernel/Makefile')
| -rw-r--r-- | arch/riscv/kernel/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index c121cc491eb8..1bad93f63dba 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -30,7 +30,7 @@ obj-y += cacheinfo.o obj-y += patch.o obj-$(CONFIG_MMU) += vdso.o vdso/ -obj-$(CONFIG_RISCV_M_MODE) += clint.o +obj-$(CONFIG_RISCV_M_MODE) += clint.o traps_misaligned.o obj-$(CONFIG_FPU) += fpu.o obj-$(CONFIG_SMP) += smpboot.o obj-$(CONFIG_SMP) += smp.o |