diff options
| author | Steven King <sfking@fdwdc.com> | 2012-06-06 14:28:31 -0700 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2012-07-16 09:59:21 +1000 |
| commit | bea8bcb12da09bd35cdada395d0d0db1aee2ba4c (patch) | |
| tree | 0a62830f7538f8ab83c75fa4c445643adc258350 /arch/m68k/include/asm/mcfgpio.h | |
| parent | bdee4e26ba6568118f2376ebcfdeef3b7f527bce (diff) | |
m68knommu: Add support for the Coldfire m5441x.
Add support for the Coldfire 5441x (54410/54415/54416/54417/54418). Currently
we only support noMMU mode. It requires the PIT patch posted previously as it
uses the PIT instead of the dma timer as a clock source so we can get all that
GENERIC_CLOCKEVENTS goodness. It also adds some simple clk definitions and
very simple minded power management. The gpio code is tweeked and some
additional devices are added to devices.c. The Makefile uses -mv4e as
apparently, the only difference a v4m (m5441x) and a v4e is the later has a
FPU, which I don't think should matter to us in the kernel.
Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/mcfgpio.h')
| -rw-r--r-- | arch/m68k/include/asm/mcfgpio.h | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h index b2471a5f02eb..fa1059f50dfc 100644 --- a/arch/m68k/include/asm/mcfgpio.h +++ b/arch/m68k/include/asm/mcfgpio.h @@ -104,7 +104,8 @@ static inline void gpio_free(unsigned gpio) #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M532x) || defined(CONFIG_M54xx) + defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \ + defined(CONFIG_M5441x) /* These parts have GPIO organized by 8 bit ports */ @@ -137,7 +138,8 @@ static inline void gpio_free(unsigned gpio) #define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE) #if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) + defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M532x) || defined(CONFIG_M5441x) /* * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses * read-modify-write to change an output and a GPIO module which has separate @@ -149,6 +151,9 @@ static inline void gpio_free(unsigned gpio) * read-modify-write as well as those controlled by the EPORT and GPIO modules. */ #define MCFGPIO_SCR_START 40 +#elif defined(CONFIGM5441x) +/* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */ +#define MCFGPIO_SCR_START 0 #else #define MCFGPIO_SCR_START 8 #endif @@ -189,7 +194,9 @@ static inline u32 __mcfgpio_ppdr(unsigned gpio) else return MCFSIM2_GPIO1READ; #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) + defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M532x) || defined(CONFIG_M5441x) +#if !defined(CONFIG_M5441x) if (gpio < 8) return MCFEPORT_EPPDR; #if defined(CONFIG_M528x) @@ -201,8 +208,9 @@ static inline u32 __mcfgpio_ppdr(unsigned gpio) return MCFQADC_PORTQA; else if (gpio < 40) return MCFQADC_PORTQB; -#endif +#endif /* defined(CONFIG_M528x) */ else +#endif /* !defined(CONFIG_M5441x) */ return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START); #else return 0; @@ -228,7 +236,9 @@ static inline u32 __mcfgpio_podr(unsigned gpio) else return MCFSIM2_GPIO1WRITE; #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) + defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M532x) || defined(CONFIG_M5441x) +#if !defined(CONFIG_M5441x) if (gpio < 8) return MCFEPORT_EPDR; #if defined(CONFIG_M528x) @@ -240,8 +250,9 @@ static inline u32 __mcfgpio_podr(unsigned gpio) return MCFQADC_PORTQA; else if (gpio < 40) return MCFQADC_PORTQB; -#endif +#endif /* defined(CONFIG_M528x) */ else +#endif /* !defined(CONFIG_M5441x) */ return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START); #else return 0; @@ -267,7 +278,9 @@ static inline u32 __mcfgpio_pddr(unsigned gpio) else return MCFSIM2_GPIO1ENABLE; #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) + defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M532x) || defined(CONFIG_M5441x) +#if !defined(CONFIG_M5441x) if (gpio < 8) return MCFEPORT_EPDDR; #if defined(CONFIG_M528x) @@ -279,8 +292,9 @@ static inline u32 __mcfgpio_pddr(unsigned gpio) return MCFQADC_DDRQA; else if (gpio < 40) return MCFQADC_DDRQB; -#endif +#endif /* defined(CONFIG_M528x) */ else +#endif /* !defined(CONFIG_M5441x) */ return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START); #else return 0; |