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authorNishanth Menon <nm@ti.com>2021-01-20 13:51:45 -0600
committerNishanth Menon <nm@ti.com>2021-01-28 08:51:18 -0600
commitae10ce938da59c19f303a91197ea7d664d1bc080 (patch)
treea175222ce9c8b210adb24f41c23953dbe6ef759e /arch/arm64/boot/dts/ti/k3-j721e.dtsi
parent0cf73209ce2c60c5b717a02d9de10a6d524e08a6 (diff)
arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific
We can use CPU specific pmu configuration to expose the appropriate CPU specific events rather than just the basic generic pmuv3 perf events. Reported-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Suman Anna <s-anna@ti.com> Reviewed-by: Tero Kristo <kristo@kernel.org> Link: https://lore.kernel.org/r/20210120195145.32259-1-nm@ti.com
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-j721e.dtsi')
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721e.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index cc483f7344af..f0587fde147e 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -115,7 +115,7 @@
};
pmu: pmu {
- compatible = "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a72-pmu";
/* Recommendation from GIC500 TRM Table A.3 */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};