diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2022-05-26 10:25:22 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-05-26 10:25:22 -0700 |
| commit | c011dd537ffe47462051930413fed07dbdc80313 (patch) | |
| tree | 3cf9bdf68a5e01bfe7e7e3cc49711e8f931c6381 | |
| parent | 3378323bbb9e77643a645f6b1ff10f7bdb9d61e4 (diff) | |
| parent | 426ecc5851021519374542b0a954b2a9a3942d04 (diff) | |
Merge tag 'arm-soc-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull 32-bit ARM SoC updates from Arnd Bergmann:
"These updates are for platform specific code in arch/arm/, mostly
fixing minor issues.
The at91 platform gains support for better power management on the
lan966 platform and new firmware on the sama5 platform. The mediatek
soc drivers in turn are enabled for the new mt8195 SoC"
* tag 'arm-soc-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (34 commits)
ARM: at91: debug: add lan966 support
ARM: at91: pm: add support for sama5d2 secure suspend
ARM: at91: add code to handle secure calls
ARM: at91: Kconfig: implement PIT64B selection
ARM: at91: pm: add quirks for pm
ARM: at91: pm: use kernel documentation style
ARM: at91: pm: introduce macros for pm mode replacement
ARM: at91: pm: keep documentation inline with structure members
orion5x: fix typos in comments
ARM: hisi: Add missing of_node_put after of_find_compatible_node
ARM: shmobile: rcar-gen2: Drop comma after OF match table sentinel
ARM: shmobile: Drop commas after dt_compat sentinels
soc: mediatek: mutex: remove mt8195 MOD0 and SOF0 definition
MAINTAINERS: Add Broadcom BCMBCA entry
arm: bcmbca: add arch bcmbca machine entry
MAINTAINERS: Broadcom internal lists aren't maintainers
dt-bindings: pwrap: mediatek: Update pwrap document for mt8195
soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
soc: mediatek: add mtk-mutex support for mt8195 vdosys0
soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
...
51 files changed, 1281 insertions, 187 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index b31d90dc9eb4..6ad023eec193 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -31,6 +31,7 @@ properties: - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys - mediatek,mt8192-mmsys + - mediatek,mt8195-mmsys - mediatek,mt8365-mmsys - const: syscon - items: @@ -41,6 +42,30 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier as defined by bindings + of the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + + mboxes: + description: + Using mailbox to communicate with GCE, it should have this + property and list of phandle, mailbox specifiers. See + Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details. + $ref: /schemas/types.yaml#/definitions/phandle-array + + mediatek,gce-client-reg: + description: + The register of client driver can be configured by gce with 4 arguments + defined in this property, such as phandle of gce, subsys id, + register offset and size. + Each subsys id is mapping to a base address of display function blocks + register which is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + "#clock-cells": const: 1 @@ -56,9 +81,16 @@ additionalProperties: false examples: - | + #include <dt-bindings/power/mt8173-power.h> + #include <dt-bindings/gce/mt8173-gce.h> + mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0x14000000 0x1000>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; #clock-cells = <1>; #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt index 214a34633824..0581dbda4828 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -31,20 +31,20 @@ Required properties in pwrap device node. "mediatek,mt8195-pwrap" for MT8195 SoCs "mediatek,mt8516-pwrap" for MT8516 SoCs - interrupts: IRQ for pwrap in SOC -- reg-names: Must include the following entries: +- reg-names: "pwrap" is required; "pwrap-bridge" is optional. "pwrap": Main registers base "pwrap-bridge": bridge base (IP Pairing) - reg: Must contain an entry for each entry in reg-names. -- reset-names: Must include the following entries: - "pwrap" - "pwrap-bridge" (IP Pairing) -- resets: Must contain an entry for each entry in reset-names. - clock-names: Must include the following entries: "spi": SPI bus clock "wrap": Main module clock - clocks: Must contain an entry for each entry in clock-names. Optional properities: +- reset-names: Some SoCs include the following entries: + "pwrap" + "pwrap-bridge" (IP Pairing) +- resets: Must contain an entry for each entry in reset-names. - pmic: Using either MediaTek PMIC MFD as the child device of pwrap See the following for child node definitions: Documentation/devicetree/bindings/mfd/mt6397.txt diff --git a/MAINTAINERS b/MAINTAINERS index 55114e73de26..6c0cb7e7c0da 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3753,9 +3753,23 @@ F: drivers/net/dsa/bcm_sf2* F: include/linux/dsa/brcm.h F: include/linux/platform_data/b53.h +BROADCOM BCMBCA ARM ARCHITECTURE +M: William Zhang <william.zhang@broadcom.com> +M: Anand Gore <anand.gore@broadcom.com> +M: Kursad Oney <kursad.oney@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +T: git git://github.com/broadcom/stblinux.git +F: Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml +F: arch/arm/boot/dts/bcm47622.dtsi +F: arch/arm/boot/dts/bcm947622.dts +N: bcmbca +N: bcm[9]?47622 + BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE M: Nicolas Saenz Julienne <nsaenz@kernel.org> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained @@ -3765,12 +3779,13 @@ F: drivers/pci/controller/pcie-brcmstb.c F: drivers/staging/vc04_services N: bcm2711 N: bcm283* +N: raspberrypi BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE M: Florian Fainelli <f.fainelli@gmail.com> M: Ray Jui <rjui@broadcom.com> M: Scott Branden <sbranden@broadcom.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> S: Maintained T: git git://github.com/broadcom/mach-bcm F: arch/arm/mach-bcm/ @@ -3790,7 +3805,7 @@ F: arch/mips/include/asm/mach-bcm47xx/* BROADCOM BCM4908 ETHERNET DRIVER M: Rafał Miłecki <rafal@milecki.pl> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: netdev@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml @@ -3799,7 +3814,7 @@ F: drivers/net/ethernet/broadcom/unimac.h BROADCOM BCM4908 PINMUX DRIVER M: Rafał Miłecki <rafal@milecki.pl> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-gpio@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml @@ -3809,7 +3824,7 @@ BROADCOM BCM5301X ARM ARCHITECTURE M: Florian Fainelli <f.fainelli@gmail.com> M: Hauke Mehrtens <hauke@hauke-m.de> M: Rafał Miłecki <zajec5@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/boot/dts/bcm470* @@ -3820,7 +3835,7 @@ F: arch/arm/mach-bcm/bcm_5301x.c BROADCOM BCM53573 ARM ARCHITECTURE M: Florian Fainelli <f.fainelli@gmail.com> M: Rafał Miłecki <rafal@milecki.pl> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/boot/dts/bcm47189* @@ -3828,7 +3843,7 @@ F: arch/arm/boot/dts/bcm53573* BROADCOM BCM63XX ARM ARCHITECTURE M: Florian Fainelli <f.fainelli@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://github.com/broadcom/stblinux.git @@ -3842,7 +3857,7 @@ F: drivers/usb/gadget/udc/bcm63xx_udc.* BROADCOM BCM7XXX ARM ARCHITECTURE M: Florian Fainelli <f.fainelli@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://github.com/broadcom/stblinux.git @@ -3860,21 +3875,21 @@ N: bcm7120 BROADCOM BDC DRIVER M: Al Cooper <alcooperx@gmail.com> L: linux-usb@vger.kernel.org -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> S: Maintained F: Documentation/devicetree/bindings/usb/brcm,bdc.yaml F: drivers/usb/gadget/udc/bdc/ BROADCOM BMIPS CPUFREQ DRIVER M: Markus Mayer <mmayer@broadcom.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-pm@vger.kernel.org S: Maintained F: drivers/cpufreq/bmips-cpufreq.c BROADCOM BMIPS MIPS ARCHITECTURE M: Florian Fainelli <f.fainelli@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-mips@vger.kernel.org S: Maintained T: git git://github.com/broadcom/stblinux.git @@ -3942,14 +3957,14 @@ F: drivers/net/wireless/broadcom/brcm80211/ BROADCOM BRCMSTB GPIO DRIVER M: Doug Berger <opendmb@gmail.com> M: Florian Fainelli <f.fainelli@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> S: Supported F: Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml F: drivers/gpio/gpio-brcmstb.c BROADCOM BRCMSTB I2C DRIVER M: Kamal Dasu <kdasu.kdev@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-i2c@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml @@ -3957,7 +3972,7 @@ F: drivers/i2c/busses/i2c-brcmstb.c BROADCOM BRCMSTB UART DRIVER M: Al Cooper <alcooperx@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-serial@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml @@ -3965,7 +3980,7 @@ F: drivers/tty/serial/8250/8250_bcm7271.c BROADCOM BRCMSTB USB EHCI DRIVER M: Al Cooper <alcooperx@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-usb@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/usb/brcm,bcm7445-ehci.yaml @@ -3973,7 +3988,7 @@ F: drivers/usb/host/ehci-brcm.* BROADCOM BRCMSTB USB PIN MAP DRIVER M: Al Cooper <alcooperx@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-usb@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/usb/brcm,usb-pinmap.yaml @@ -3981,14 +3996,14 @@ F: drivers/usb/misc/brcmstb-usb-pinmap.c BROADCOM BRCMSTB USB2 and USB3 PHY DRIVER M: Al Cooper <alcooperx@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-kernel@vger.kernel.org S: Maintained F: drivers/phy/broadcom/phy-brcm-usb* BROADCOM ETHERNET PHY DRIVERS M: Florian Fainelli <f.fainelli@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: netdev@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/net/broadcom-bcm87xx.txt @@ -3999,7 +4014,7 @@ F: include/linux/brcmphy.h BROADCOM GENET ETHERNET DRIVER M: Doug Berger <opendmb@gmail.com> M: Florian Fainelli <f.fainelli@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: netdev@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/net/brcm,bcmgenet.yaml @@ -4013,7 +4028,7 @@ F: include/linux/platform_data/mdio-bcm-unimac.h BROADCOM IPROC ARM ARCHITECTURE M: Ray Jui <rjui@broadcom.com> M: Scott Branden <sbranden@broadcom.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://github.com/broadcom/stblinux.git @@ -4041,7 +4056,7 @@ N: stingray BROADCOM IPROC GBIT ETHERNET DRIVER M: Rafał Miłecki <rafal@milecki.pl> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: netdev@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/net/brcm,amac.yaml @@ -4050,7 +4065,7 @@ F: drivers/net/ethernet/broadcom/unimac.h BROADCOM KONA GPIO DRIVER M: Ray Jui <rjui@broadcom.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> S: Supported F: Documentation/devicetree/bindings/gpio/brcm,kona-gpio.txt F: drivers/gpio/gpio-bcm-kona.c @@ -4083,7 +4098,7 @@ F: drivers/firmware/broadcom/* BROADCOM PMB (POWER MANAGEMENT BUS) DRIVER M: Rafał Miłecki <rafal@milecki.pl> M: Florian Fainelli <f.fainelli@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-pm@vger.kernel.org S: Maintained T: git git://github.com/broadcom/stblinux.git @@ -4099,7 +4114,7 @@ F: include/linux/bcma/ BROADCOM SPI DRIVER M: Kamal Dasu <kdasu.kdev@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> S: Maintained F: Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml F: drivers/spi/spi-bcm-qspi.* @@ -4108,7 +4123,7 @@ F: drivers/spi/spi-iproc-qspi.c BROADCOM STB AVS CPUFREQ DRIVER M: Markus Mayer <mmayer@broadcom.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-pm@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/cpufreq/brcm,stb-avs-cpu-freq.txt @@ -4116,7 +4131,7 @@ F: drivers/cpufreq/brcmstb* BROADCOM STB AVS TMON DRIVER M: Markus Mayer <mmayer@broadcom.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-pm@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml @@ -4124,7 +4139,7 @@ F: drivers/thermal/broadcom/brcmstb* BROADCOM STB DPFE DRIVER M: Markus Mayer <mmayer@broadcom.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.yaml @@ -4133,7 +4148,7 @@ F: drivers/memory/brcmstb_dpfe.c BROADCOM STB NAND FLASH DRIVER M: Brian Norris <computersforpeace@gmail.com> M: Kamal Dasu <kdasu.kdev@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-mtd@lists.infradead.org S: Maintained F: drivers/mtd/nand/raw/brcmnand/ @@ -4143,7 +4158,7 @@ BROADCOM STB PCIE DRIVER M: Jim Quinlan <jim2101024@gmail.com> M: Nicolas Saenz Julienne <nsaenz@kernel.org> M: Florian Fainelli <f.fainelli@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-pci@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -4151,7 +4166,7 @@ F: drivers/pci/controller/pcie-brcmstb.c BROADCOM SYSTEMPORT ETHERNET DRIVER M: Florian Fainelli <f.fainelli@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: netdev@vger.kernel.org S: Supported F: drivers/net/ethernet/broadcom/bcmsysport.* @@ -4168,7 +4183,7 @@ F: drivers/net/ethernet/broadcom/tg3.* BROADCOM VK DRIVER M: Scott Branden <scott.branden@broadcom.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> S: Supported F: drivers/misc/bcm-vk/ F: include/uapi/linux/misc/bcm_vk.h @@ -17775,7 +17790,7 @@ K: \bTIF_SECCOMP\b SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) Broadcom BRCMSTB DRIVER M: Al Cooper <alcooperx@gmail.com> -R: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> +R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> L: linux-mmc@vger.kernel.org S: Maintained F: drivers/mmc/host/sdhci-brcmstb* diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 0c9497d549e3..77b2db882e75 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -210,6 +210,26 @@ choice Say Y here if you want kernel low-level debugging support on the FLEXCOM3 port of SAMA7G5. + config DEBUG_AT91_LAN966_FLEXCOM + bool "Kernel low-level debugging on LAN966 FLEXCOM USART" + select DEBUG_AT91_UART + depends on SOC_LAN966 + help + Say Y here if you want kernel low-level debugging support + on the FLEXCOM port of LAN966. + + DEBUG_UART_PHYS | DEBUG_UART_VIRT + + 0xe0040200 | 0xfd040200 | FLEXCOM0 + 0xe0044200 | 0xfd044200 | FLEXCOM1 + 0xe0060200 | 0xfd060200 | FLEXCOM2 + 0xe0064200 | 0xfd064200 | FLEXCOM3 + 0xe0070200 | 0xfd070200 | FLEXCOM4 + + By default, enabling FLEXCOM3 port. Based on requirement, use + DEBUG_UART_PHYS and DEBUG_UART_VIRT configurations from above + table. + config DEBUG_BCM2835 bool "Kernel low-level debugging on BCM2835 PL011 UART" depends on ARCH_BCM2835 && ARCH_MULTI_V6 @@ -1685,6 +1705,7 @@ config DEBUG_UART_PHYS default 0xd4017000 if DEBUG_MMP_UART2 default 0xd4018000 if DEBUG_MMP_UART3 default 0xe0000000 if DEBUG_SPEAR13XX + default 0xe0064200 if DEBUG_AT91_LAN966_FLEXCOM default 0xe1824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3 default 0xe4007000 if DEBUG_HIP04_UART default 0xe6c40000 if DEBUG_RMOBILE_SCIFA0 @@ -1805,6 +1826,7 @@ config DEBUG_UART_VIRT default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT default 0xfcfe8600 if DEBUG_BCM63XX_UART default 0xfd000000 if DEBUG_SPEAR3XX || DEBUG_SPEAR13XX + default 0xfd064200 if DEBUG_AT91_LAN966_FLEXCOM default 0xfd531000 if DEBUG_STIH41X_SBC_ASC1 default 0xfd883000 if DEBUG_ALPINE_UART0 default 0xfdd32000 if DEBUG_STIH41X_ASC2 diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index 898490aaa39e..c7741289f213 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -6,7 +6,6 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_COMPAT_BRK is not set CONFIG_ARCH_S3C24XX=y CONFIG_S3C_ADC=y -CONFIG_S3C24XX_PWM=y # CONFIG_CPU_S3C2410 is not set CONFIG_CPU_S3C2440=y CONFIG_MACH_MINI2440=y @@ -228,6 +227,8 @@ CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_S3C=y CONFIG_DMADEVICES=y CONFIG_S3C24XX_DMAC=y +CONFIG_PWM=y +CONFIG_PWM_SAMSUNG=y CONFIG_EXT2_FS=m CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 153009130dab..0ec00aec2e8a 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -358,6 +358,8 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_S3C=y CONFIG_DMADEVICES=y CONFIG_S3C24XX_DMAC=y +CONFIG_PWM=y +CONFIG_PWM_SAMSUNG=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 279810381256..0edb60f7ccc6 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -165,6 +165,15 @@ config ATMEL_CLOCKSOURCE_TCB to make a single 32-bit timer. It can also be used as a clock event device supporting oneshot mode. +config MICROCHIP_CLOCKSOURCE_PIT64B + bool "64-bit Periodic Interval Timer (PIT64B) support" + default SOC_SAM9X60 || SOC_SAMA7 + select MICROCHIP_PIT64B + help + Select this to get a high resolution clockevent (SAM9X60) or + clocksource and clockevent (SAMA7G5) based on Microchip 64-bit + Periodic Interval Timer. + config HAVE_AT91_UTMI bool @@ -209,7 +218,16 @@ config SOC_SAMA5 select SRAM if PM config ATMEL_PM - bool + bool "Atmel PM support" + +config ATMEL_SECURE_PM + bool "Atmel Secure PM support" + depends on SOC_SAMA5D2 && ATMEL_PM + select ARM_PSCI + help + When running under a TEE, the suspend mode must be requested to be set + at TEE level. When enable, this option will use secure monitor calls + to set the suspend level. PSCI is then used to enter suspend. config SOC_SAMA7 bool diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 522b680b6446..0dcc37180588 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o -obj-$(CONFIG_SOC_SAMA5) += sama5.o +obj-$(CONFIG_SOC_SAMA5) += sama5.o sam_secure.o obj-$(CONFIG_SOC_SAMA7) += sama7.o obj-$(CONFIG_SOC_SAMV7) += samv7.o diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 0fd609e26615..b1a43d7bc56c 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -15,6 +15,7 @@ #include <linux/parser.h> #include <linux/suspend.h> +#include <linux/clk.h> #include <linux/clk/at91_pmc.h> #include <linux/platform_data/atmel.h> @@ -27,6 +28,7 @@ #include "generic.h" #include "pm.h" +#include "sam_secure.h" #define BACKUP_DDR_PHY_CALIBRATION (9) @@ -47,8 +49,8 @@ struct at91_pm_bu { unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION]; }; -/* - * struct at91_pm_sfrbu_offsets: registers mapping for SFRBU +/** + * struct at91_pm_sfrbu_regs - registers mapping for SFRBU * @pswbu: power switch BU control registers */ struct at91_pm_sfrbu_regs { @@ -61,13 +63,64 @@ struct at91_pm_sfrbu_regs { }; /** + * enum at91_pm_eth_clk - Ethernet clock indexes + * @AT91_PM_ETH_PCLK: pclk index + * @AT91_PM_ETH_HCLK: hclk index + * @AT91_PM_ETH_MAX_CLK: max index + */ +enum at91_pm_eth_clk { + AT91_PM_ETH_PCLK, + AT91_PM_ETH_HCLK, + AT91_PM_ETH_MAX_CLK, +}; + +/** + * enum at91_pm_eth - Ethernet controller indexes + * @AT91_PM_G_ETH: gigabit Ethernet controller index + * @AT91_PM_E_ETH: megabit Ethernet controller index + * @AT91_PM_MAX_ETH: max index + */ +enum at91_pm_eth { + AT91_PM_G_ETH, + AT91_PM_E_ETH, + AT91_PM_MAX_ETH, +}; + +/** + * struct at91_pm_quirk_eth - AT91 PM Ethernet quirks + * @dev: Ethernet device + * @np: Ethernet device node + * @clks: Ethernet clocks + * @modes: power management mode that this quirk applies to + * @dns_modes: do not suspend modes: stop suspending if Ethernet is configured + * as wakeup source but buggy and no other wakeup source is + * available + */ +struct at91_pm_quirk_eth { + struct device *dev; + struct device_node *np; + struct clk_bulk_data clks[AT91_PM_ETH_MAX_CLK]; + u32 modes; + u32 dns_modes; +}; + +/** + * struct at91_pm_quirks - AT91 PM quirks + * @eth: Ethernet quirks + */ +struct at91_pm_quirks { + struct at91_pm_quirk_eth eth[AT91_PM_MAX_ETH]; +}; + +/** * struct at91_soc_pm - AT91 SoC power management data structure * @config_shdwc_ws: wakeup sources configuration function for SHDWC * @config_pmc_ws: wakeup srouces configuration function for PMC * @ws_ids: wakup sources of_device_id array + * @bu: backup unit mapped data (for backup mode) + * @quirks: PM quirks * @data: PM data to be used on last phase of suspend * @sfrbu_regs: SFRBU registers mapping - * @bu: backup unit mapped data (for backup mode) * @memcs: memory chip select */ struct at91_soc_pm { @@ -75,19 +128,22 @@ struct at91_soc_pm { int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); const struct of_device_id *ws_ids; struct at91_pm_bu *bu; + struct at91_pm_quirks quirks; struct at91_pm_data data; struct at91_pm_sfrbu_regs sfrbu_regs; void *memcs; }; /** - * enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes + * enum at91_pm_iomaps - IOs that needs to be mapped for different PM modes * @AT91_PM_IOMAP_SHDWC: SHDWC controller * @AT91_PM_IOMAP_SFRBU: SFRBU controller + * @AT91_PM_IOMAP_ETHC: Ethernet controller */ enum at91_pm_iomaps { AT91_PM_IOMAP_SHDWC, AT91_PM_IOMAP_SFRBU, + AT91_PM_IOMAP_ETHC, }; #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name) @@ -263,6 +319,141 @@ static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) return 0; } +static bool at91_pm_eth_quirk_is_valid(struct at91_pm_quirk_eth *eth) +{ + struct platform_device *pdev; + + /* Interface NA in DT. */ + if (!eth->np) + return false; + + /* No quirks for this interface and current suspend mode. */ + if (!(eth->modes & BIT(soc_pm.data.mode))) + return false; + + if (!eth->dev) { + /* Driver not probed. */ + pdev = of_find_device_by_node(eth->np); + if (!pdev) + return false; + eth->dev = &pdev->dev; + } + + /* No quirks if device isn't a wakeup source. */ + if (!device_may_wakeup(eth->dev)) { + put_device(eth->dev); + return false; + } + + /* put_device(eth->dev) is called at the end of suspend. */ + return true; +} + +static int at91_pm_config_quirks(bool suspend) +{ + struct at91_pm_quirk_eth *eth; + int i, j, ret, tmp; + + /* + * Ethernet IPs who's device_node pointers are stored into + * soc_pm.quirks.eth[].np cannot handle WoL packets while in ULP0, ULP1 + * or both due to a hardware bug. If they receive WoL packets while in + * ULP0 or ULP1 IPs could stop working or the whole system could stop + * working. We cannot handle this scenario in the ethernet driver itself + * as the driver is common to multiple vendors and also we only know + * here, in this file, if we suspend to ULP0 or ULP1 mode. Thus handle + * these scenarios here, as quirks. + */ + for (i = 0; i < AT91_PM_MAX_ETH; i++) { + eth = &soc_pm.quirks.eth[i]; + + if (!at91_pm_eth_quirk_is_valid(eth)) + continue; + + /* + * For modes in dns_modes mask the system blocks if quirk is not + * applied but if applied the interface doesn't act at WoL + * events. Thus take care to avoid suspending if this interface + * is the only configured wakeup source. + */ + if (suspend && eth->dns_modes & BIT(soc_pm.data.mode)) { + int ws_count = 0; +#ifdef CONFIG_PM_SLEEP + struct wakeup_source *ws; + + for_each_wakeup_source(ws) { + if (ws->dev == eth->dev) + continue; + + ws_count++; + break; + } +#endif + + /* + * Checking !ws is good for all platforms with issues + * even when both G_ETH and E_ETH are available as dns_modes + * is populated only on G_ETH interface. + */ + if (!ws_count) { + pr_err("AT91: PM: Ethernet cannot resume from WoL!"); + ret = -EPERM; + put_device(eth->dev); + eth->dev = NULL; + /* No need to revert clock settings for this eth. */ + i--; + goto clk_unconfigure; + } + } + + if (suspend) { + clk_bulk_disable_unprepare(AT91_PM_ETH_MAX_CLK, eth->clks); + } else { + ret = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, + eth->clks); + if (ret) + goto clk_unconfigure; + /* + * Release the reference to eth->dev taken in + * at91_pm_eth_quirk_is_valid(). + */ + put_device(eth->dev); + eth->dev = NULL; + } + } + + return 0; + +clk_unconfigure: + /* + * In case of resume we reach this point if clk_prepare_enable() failed. + * we don't want to revert the previous clk_prepare_enable() for the + * other IP. + */ + for (j = i; j >= 0; j--) { + eth = &soc_pm.quirks.eth[j]; + if (suspend) { + if (!at91_pm_eth_quirk_is_valid(eth)) + continue; + + tmp = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, eth->clks); + if (tmp) { + pr_err("AT91: PM: failed to enable %s clocks\n", + j == AT91_PM_G_ETH ? "geth" : "eth"); + } + } else { + /* + * Release the reference to eth->dev taken in + * at91_pm_eth_quirk_is_valid(). + */ + put_device(eth->dev); + eth->dev = NULL; + } + } + + return ret; +} + /* * Called after processes are frozen, but before we shutdown devices. */ @@ -427,6 +618,12 @@ static void at91_pm_suspend(suspend_state_t state) */ static int at91_pm_enter(suspend_state_t state) { + int ret; + + ret = at91_pm_config_quirks(true); + if (ret) + return ret; + #ifdef CONFIG_PINCTRL_AT91 /* * FIXME: this is needed to communicate between the pinctrl driver and @@ -464,6 +661,7 @@ error: #ifdef CONFIG_PINCTRL_AT91 at91_pinctrl_gpio_resume(); #endif + at91_pm_config_quirks(false); return 0; } @@ -881,6 +1079,35 @@ securam_fail: return ret; } +static void at91_pm_secure_init(void) +{ + int suspend_mode; + struct arm_smccc_res res; + + suspend_mode = soc_pm.data.suspend_mode; + + res = sam_smccc_call(SAMA5_SMC_SIP_SET_SUSPEND_MODE, + suspend_mode, 0); + if (res.a0 == 0) { + pr_info("AT91: Secure PM: suspend mode set to %s\n", + pm_modes[suspend_mode].pattern); + return; + } + + pr_warn("AT91: Secure PM: %s mode not supported !\n", + pm_modes[suspend_mode].pattern); + + res = sam_smccc_call(SAMA5_SMC_SIP_GET_SUSPEND_MODE, 0, 0); + if (res.a0 == 0) { + pr_warn("AT91: Secure PM: failed to get default mode\n"); + return; + } + + pr_info("AT91: Secure PM: using default suspend mode %s\n", + pm_modes[suspend_mode].pattern); + + soc_pm.data.suspend_mode = res.a1; +} static const struct of_device_id atmel_shdwc_ids[] = { { .compatible = "atmel,sama5d2-shdwc" }, { .compatible = "microchip,sam9x60-shdwc" }, @@ -888,10 +1115,99 @@ static const struct of_device_id atmel_shdwc_ids[] = { { /* sentinel. */ } }; +static const struct of_device_id gmac_ids[] __initconst = { + { .compatible = "atmel,sama5d3-gem" }, + { .compatible = "atmel,sama5d2-gem" }, + { .compatible = "atmel,sama5d29-gem" }, + { .compatible = "microchip,sama7g5-gem" }, + { }, +}; + +static const struct of_device_id emac_ids[] __initconst = { + { .compatible = "atmel,sama5d3-macb" }, + { .compatible = "microchip,sama7g5-emac" }, + { }, +}; + +/* + * Replaces _mode_to_replace with a supported mode that doesn't depend + * on controller pointed by _map_bitmask + * @_maps: u32 array containing AT91_PM_IOMAP() flags and indexed by AT91 + * PM mode + * @_map_bitmask: AT91_PM_IOMAP() bitmask; if _mode_to_replace depends on + * controller represented by _map_bitmask, _mode_to_replace needs to be + * updated + * @_mode_to_replace: standby_mode or suspend_mode that need to be + * updated + * @_mode_to_check: standby_mode or suspend_mode; this is needed here + * to avoid having standby_mode and suspend_mode set with the same AT91 + * PM mode + */ +#define AT91_PM_REPLACE_MODE(_maps, _map_bitmask, _mode_to_replace, \ + _mode_to_check) \ + do { \ + if (((_maps)[(_mode_to_replace)]) & (_map_bitmask)) { \ + int _mode_to_use, _mode_complementary; \ + /* Use ULP0 if it doesn't need _map_bitmask. */ \ + if (!((_maps)[AT91_PM_ULP0] & (_map_bitmask))) {\ + _mode_to_use = AT91_PM_ULP0; \ + _mode_complementary = AT91_PM_STANDBY; \ + } else { \ + _mode_to_use = AT91_PM_STANDBY; \ + _mode_complementary = AT91_PM_STANDBY; \ + } \ + \ + if ((_mode_to_check) != _mode_to_use) \ + (_mode_to_replace) = _mode_to_use; \ + else \ + (_mode_to_replace) = _mode_complementary;\ + } \ + } while (0) + +/* + * Replaces standby and suspend modes with default supported modes: + * ULP0 and STANDBY. + * @_maps: u32 array indexed by AT91 PM mode containing AT91_PM_IOMAP() + * flags + * @_map: controller specific name; standby and suspend mode need to be + * replaced in order to not depend on this controller + */ +#define AT91_PM_REPLACE_MODES(_maps, _map) \ + do { \ + AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\ + (soc_pm.data.standby_mode), \ + (soc_pm.data.suspend_mode)); \ + AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\ + (soc_pm.data.suspend_mode), \ + (soc_pm.data.standby_mode)); \ + } while (0) + +static int __init at91_pm_get_eth_clks(struct device_node *np, + struct clk_bulk_data *clks) +{ + clks[AT91_PM_ETH_PCLK].clk = of_clk_get_by_name(np, "pclk"); + if (IS_ERR(clks[AT91_PM_ETH_PCLK].clk)) + return PTR_ERR(clks[AT91_PM_ETH_PCLK].clk); + + clks[AT91_PM_ETH_HCLK].clk = of_clk_get_by_name(np, "hclk"); + if (IS_ERR(clks[AT91_PM_ETH_HCLK].clk)) + return PTR_ERR(clks[AT91_PM_ETH_HCLK].clk); + + return 0; +} + +static int __init at91_pm_eth_clks_empty(struct clk_bulk_data *clks) +{ + return IS_ERR(clks[AT91_PM_ETH_PCLK].clk) || + IS_ERR(clks[AT91_PM_ETH_HCLK].clk); +} + static void __init at91_pm_modes_init(const u32 *maps, int len) { + struct at91_pm_quirk_eth *gmac = &soc_pm.quirks.eth[AT91_PM_G_ETH]; + struct at91_pm_quirk_eth *emac = &soc_pm.quirks.eth[AT91_PM_E_ETH]; struct device_node *np; - int ret, mode; + int ret; ret = at91_pm_backup_init(); if (ret) { @@ -906,17 +1222,7 @@ static void __init at91_pm_modes_init(const u32 *maps, int len) np = of_find_matching_node(NULL, atmel_shdwc_ids); if (!np) { pr_warn("%s: failed to find shdwc!\n", __func__); - - /* Use ULP0 if it doesn't needs SHDWC.*/ - if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC))) - mode = AT91_PM_ULP0; - else - mode = AT91_PM_STANDBY; - - if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC)) - soc_pm.data.standby_mode = mode; - if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) - soc_pm.data.suspend_mode = mode; + AT91_PM_REPLACE_MODES(maps, SHDWC); } else { soc_pm.data.shdwc = of_iomap(np, 0); of_node_put(np); @@ -928,27 +1234,48 @@ static void __init at91_pm_modes_init(const u32 *maps, int len) np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); if (!np) { pr_warn("%s: failed to find sfrbu!\n", __func__); - - /* - * Use ULP0 if it doesn't need SHDWC or if SHDWC - * was already located. - */ - if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) || - soc_pm.data.shdwc) - mode = AT91_PM_ULP0; - else - mode = AT91_PM_STANDBY; - - if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU)) - soc_pm.data.standby_mode = mode; - if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) - soc_pm.data.suspend_mode = mode; + AT91_PM_REPLACE_MODES(maps, SFRBU); } else { soc_pm.data.sfrbu = of_iomap(np, 0); of_node_put(np); } } + if ((at91_is_pm_mode_active(AT91_PM_ULP1) || + at91_is_pm_mode_active(AT91_PM_ULP0) || + at91_is_pm_mode_active(AT91_PM_ULP0_FAST)) && + (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(ETHC) || + maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(ETHC))) { + np = of_find_matching_node(NULL, gmac_ids); + if (!np) { + np = of_find_matching_node(NULL, emac_ids); + if (np) + goto get_emac_clks; + AT91_PM_REPLACE_MODES(maps, ETHC); + goto unmap_unused_nodes; + } else { + gmac->np = np; + at91_pm_get_eth_clks(np, gmac->clks); + } + + np = of_find_matching_node(NULL, emac_ids); + if (!np) { + if (at91_pm_eth_clks_empty(gmac->clks)) + AT91_PM_REPLACE_MODES(maps, ETHC); + } else { +get_emac_clks: + emac->np = np; + ret = at91_pm_get_eth_clks(np, emac->clks); + if (ret && at91_pm_eth_clks_empty(gmac->clks)) { + of_node_put(gmac->np); + of_node_put(emac->np); + gmac->np = NULL; + emac->np = NULL; + } + } + } + +unmap_unused_nodes: /* Unmap all unnecessary. */ if (soc_pm.data.shdwc && !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || @@ -1184,17 +1511,30 @@ void __init sama5_pm_init(void) static const int modes[] __initconst = { AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, }; + static const u32 iomaps[] __initconst = { + [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC), + [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC), + }; int ret; if (!IS_ENABLED(CONFIG_SOC_SAMA5)) return; at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); + at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); ret = at91_dt_ramc(false); if (ret) return; at91_pm_init(NULL); + + /* Quirks applies to ULP0, ULP0 fast and ULP1 modes. */ + soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) | + BIT(AT91_PM_ULP0_FAST) | + BIT(AT91_PM_ULP1); + /* Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup source. */ + soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) | + BIT(AT91_PM_ULP0_FAST); } void __init sama5d2_pm_init(void) @@ -1204,7 +1544,10 @@ void __init sama5d2_pm_init(void) AT91_PM_BACKUP, }; static const u32 iomaps[] __initconst = { - [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), + [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC), + [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC), + [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC) | + AT91_PM_IOMAP(ETHC), [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) | AT91_PM_IOMAP(SFRBU), }; @@ -1213,6 +1556,12 @@ void __init sama5d2_pm_init(void) if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) return; + if (IS_ENABLED(CONFIG_ATMEL_SECURE_PM)) { + pr_warn("AT91: Secure PM: ignoring standby mode\n"); + at91_pm_secure_init(); + return; + } + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); ret = at91_dt_ramc(false); @@ -1229,6 +1578,17 @@ void __init sama5d2_pm_init(void) soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); soc_pm.sfrbu_regs.pswbu.state = BIT(3); + + /* Quirk applies to ULP0, ULP0 fast and ULP1 modes. */ + soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) | + BIT(AT91_PM_ULP0_FAST) | + BIT(AT91_PM_ULP1); + /* + * Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup + * source. + */ + soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) | + BIT(AT91_PM_ULP0_FAST); } void __init sama7_pm_init(void) @@ -1239,7 +1599,8 @@ void __init sama7_pm_init(void) static const u32 iomaps[] __initconst = { [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU), [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) | - AT91_PM_IOMAP(SHDWC), + AT91_PM_IOMAP(SHDWC) | + AT91_PM_IOMAP(ETHC), [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) | AT91_PM_IOMAP(SHDWC), }; @@ -1264,6 +1625,10 @@ void __init sama7_pm_init(void) soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); soc_pm.sfrbu_regs.pswbu.state = BIT(2); + + /* Quirks applies to ULP1 for both Ethernet interfaces. */ + soc_pm.quirks.eth[AT91_PM_E_ETH].modes = BIT(AT91_PM_ULP1); + soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP1); } static int __init at91_pm_modes_select(char *str) diff --git a/arch/arm/mach-at91/sam_secure.c b/arch/arm/mach-at91/sam_secure.c new file mode 100644 index 000000000000..2a01f7a7d13f --- /dev/null +++ b/arch/arm/mach-at91/sam_secure.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2022, Microchip + */ + +#include <linux/arm-smccc.h> +#include <linux/of.h> + +#include "sam_secure.h" + +static bool optee_available; + +#define SAM_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +struct arm_smccc_res sam_smccc_call(u32 fn, u32 arg0, u32 arg1) +{ + struct arm_smccc_res res = {.a0 = -1}; + + if (WARN_ON(!optee_available)) + return res; + + arm_smccc_smc(SAM_SIP_SMC_STD_CALL_VAL(fn), arg0, arg1, 0, 0, 0, 0, 0, + &res); + + return res; +} + +void __init sam_secure_init(void) +{ + struct device_node *np; + + /* + * We only check that the OP-TEE node is present and available. The + * OP-TEE kernel driver is not needed for the type of interaction made + * with OP-TEE here so the driver's status is not checked. + */ + np = of_find_node_by_path("/firmware/optee"); + if (np && of_device_is_available(np)) + optee_available = true; + of_node_put(np); + + if (optee_available) + pr_info("Running under OP-TEE firmware\n"); +} diff --git a/arch/arm/mach-at91/sam_secure.h b/arch/arm/mach-at91/sam_secure.h new file mode 100644 index 000000000000..1e7d8b20ba1e --- /dev/null +++ b/arch/arm/mach-at91/sam_secure.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022, Microchip + */ + +#ifndef SAM_SECURE_H +#define SAM_SECURE_H + +#include <linux/arm-smccc.h> + +/* Secure Monitor mode APIs */ +#define SAMA5_SMC_SIP_SET_SUSPEND_MODE 0x400 +#define SAMA5_SMC_SIP_GET_SUSPEND_MODE 0x401 + +void __init sam_secure_init(void); +struct arm_smccc_res sam_smccc_call(u32 fn, u32 arg0, u32 arg1); + +#endif /* SAM_SECURE_H */ diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c index 89dab7cf01e8..de5dd28b392e 100644 --- a/arch/arm/mach-at91/sama5.c +++ b/arch/arm/mach-at91/sama5.c @@ -14,6 +14,7 @@ #include <asm/system_misc.h> #include "generic.h" +#include "sam_secure.h" static void __init sama5_dt_device_init(void) { @@ -47,6 +48,7 @@ MACHINE_END static void __init sama5d2_init(void) { of_platform_default_populate(NULL, NULL, NULL); + sam_secure_init(); sama5d2_pm_init(); } diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 8db655c3e321..f73a056bf560 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -218,4 +218,16 @@ config ARCH_BRCMSTB This enables support for Broadcom ARM-based set-top box chipsets, including the 7445 family of chips. +config ARCH_BCMBCA + bool "Broadcom Broadband SoC" + depends on ARCH_MULTI_V7 + select ARM_AMBA + select ARM_GIC + select HAVE_ARM_ARCH_TIMER + help + Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based + BCA chipset. + + This enables support for Broadcom BCA ARM-based broadband chipsets, + including the DSL, PON and Wireless family of chips. endif diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c index 4555f21e7077..9b457714a41c 100644 --- a/arch/arm/mach-bcm/platsmp-brcmstb.c +++ b/arch/arm/mach-bcm/platsmp-brcmstb.c @@ -59,7 +59,7 @@ static u32 hif_cont_reg; /* * We must quiesce a dying CPU before it can be killed by the boot CPU. Because * one or more cache may be disabled, we must flush to ensure coherency. We - * cannot use traditionl completion structures or spinlocks as they rely on + * cannot use traditional completion structures or spinlocks as they rely on * coherency. */ static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state); diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c index a56cc64deeb8..9ce93e0b6cdc 100644 --- a/arch/arm/mach-hisi/platsmp.c +++ b/arch/arm/mach-hisi/platsmp.c @@ -67,14 +67,17 @@ static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus) } ctrl_base = of_iomap(np, 0); if (!ctrl_base) { + of_node_put(np); pr_err("failed to map address\n"); return; } if (of_property_read_u32(np, "smp-offset", &offset) < 0) { + of_node_put(np); pr_err("failed to find smp-offset property\n"); return; } ctrl_base += offset; + of_node_put(np); } } @@ -160,6 +163,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle) if (WARN_ON(!node)) return -1; ctrl_base = of_iomap(node, 0); + of_node_put(node); /* set the secondary core boot from DDR */ remap_reg_value = readl_relaxed(ctrl_base + REG_SC_CTRL); diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c index e2d069fe67f1..87f2c2d2d754 100644 --- a/arch/arm/mach-omap2/cm_common.c +++ b/arch/arm/mach-omap2/cm_common.c @@ -320,8 +320,10 @@ int __init omap2_cm_base_init(void) data = (struct omap_prcm_init_data *)match->data; ret = of_address_to_resource(np, 0, &res); - if (ret) + if (ret) { + of_node_put(np); return ret; + } if (data->index == TI_CLKM_CM) mem = &cm_base; @@ -367,8 +369,10 @@ int __init omap_cm_init(void) continue; ret = omap2_clk_provider_init(np, data->index, NULL, data->mem); - if (ret) + if (ret) { + of_node_put(np); return ret; + } } return 0; diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 062d431fc33a..c514a9602269 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -769,8 +769,10 @@ int __init omap2_control_base_init(void) data = (struct control_init_data *)match->data; mem = of_iomap(np, 0); - if (!mem) + if (!mem) { + of_node_put(np); return -ENOMEM; + } if (data->index == TI_CLKM_CTRL) { omap2_ctrl_base = mem; @@ -810,22 +812,24 @@ int __init omap_control_init(void) if (scm_conf) { syscon = syscon_node_to_regmap(scm_conf); - if (IS_ERR(syscon)) - return PTR_ERR(syscon); + if (IS_ERR(syscon)) { + ret = PTR_ERR(syscon); + goto of_node_put; + } if (of_get_child_by_name(scm_conf, "clocks")) { ret = omap2_clk_provider_init(scm_conf, data->index, syscon, NULL); if (ret) - return ret; + goto of_node_put; } } else { /* No scm_conf found, direct access */ ret = omap2_clk_provider_init(np, data->index, NULL, data->mem); if (ret) - return ret; + goto of_node_put; } } @@ -836,6 +840,11 @@ int __init omap_control_init(void) } return 0; + +of_node_put: + of_node_put(np); + return ret; + } /** diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index 56d6814bec26..8b3701901991 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -96,9 +96,6 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, * omap_device, this function adds an entry in the clkdev table of the * form <dev-id=dev_name, con-id=role> if it does not exist already. * - * The function is called from inside omap_device_build_ss(), after - * omap_device_register. - * * This allows drivers to get a pointer to its optional clocks based on its role * by calling clk_get(<dev*>, <role>). * In the case of the main clock, a "fck" alias is used. @@ -473,23 +470,6 @@ struct dev_pm_domain omap_device_pm_domain = { } }; -/** - * omap_device_register - register an omap_device with one omap_hwmod - * @pdev: the platform device (omap_device) to register. - * - * Register the omap_device structure. This currently just calls - * platform_device_register() on the underlying platform_device. - * Returns the return value of platform_device_register(). - */ -int omap_device_register(struct platform_device *pdev) -{ - pr_debug("omap_device: %s: registering\n", pdev->name); - - dev_pm_domain_set(&pdev->dev, &omap_device_pm_domain); - return platform_device_add(pdev); -} - - /* Public functions for use by device drivers through struct platform_data */ /** diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h index f77e76a7841a..d607532cf5e0 100644 --- a/arch/arm/mach-omap2/omap_device.h +++ b/arch/arm/mach-omap2/omap_device.h @@ -71,7 +71,6 @@ int omap_device_idle(struct platform_device *pdev); struct omap_device *omap_device_alloc(struct platform_device *pdev, struct omap_hwmod **ohs, int oh_cnt); void omap_device_delete(struct omap_device *od); -int omap_device_register(struct platform_device *pdev); struct device *omap_device_get_by_hwmod_name(const char *oh_name); diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 65b2d82efa27..fb2d48cfe756 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -752,8 +752,10 @@ int __init omap2_prm_base_init(void) data = (struct omap_prcm_init_data *)match->data; ret = of_address_to_resource(np, 0, &res); - if (ret) + if (ret) { + of_node_put(np); return ret; + } data->mem = ioremap(res.start, resource_size(&res)); @@ -799,8 +801,10 @@ int __init omap_prcm_init(void) data = match->data; ret = omap2_clk_provider_init(np, data->index, NULL, data->mem); - if (ret) + if (ret) { + of_node_put(np); return ret; + } } omap_cm_init(); diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 87cb47220e82..d69259b6b60d 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -696,12 +696,12 @@ static void __init dns323_init(void) pr_err("DNS-323: failed to setup power-off GPIO\n"); pm_power_off = dns323c_power_off; - /* Now, -this- should theorically be done by the sata_mv driver + /* Now, -this- should theoretically be done by the sata_mv driver * once I figure out what's going on there. Maybe the behaviour * of the LEDs should be somewhat passed via the platform_data. * for now, just whack the register and make the LEDs happy * - * Note: AFAIK, rev B1 needs the same treatement but I'll let + * Note: AFAIK, rev B1 needs the same treatment but I'll let * somebody else test it. */ writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c); diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 5ec58d004b7d..36915a073c23 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -137,7 +137,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) /* * We communicate with the bootrom to active the cpus other * than cpu0, after a blob of initialize code, they will - * stay at wfe state, once they are actived, they will check + * stay at wfe state, once they are activated, they will check * the mailbox: * sram_base_addr + 4: 0xdeadbeaf * sram_base_addr + 8: start address for pc diff --git a/arch/arm/mach-s3c/Kconfig b/arch/arm/mach-s3c/Kconfig index 1899fc3f44fd..54548c051402 100644 --- a/arch/arm/mach-s3c/Kconfig +++ b/arch/arm/mach-s3c/Kconfig @@ -207,14 +207,6 @@ config SAMSUNG_DEV_PWM help Compile in platform device definition for PWM Timer -config S3C24XX_PWM - bool "PWM device support" - select PWM - select PWM_SAMSUNG - help - Support for exporting the PWM timer blocks via the pwm device - system - config GPIO_SAMSUNG def_bool y diff --git a/arch/arm/mach-s3c/Kconfig.s3c24xx b/arch/arm/mach-s3c/Kconfig.s3c24xx index 000e3e234f71..ee4b79ac3755 100644 --- a/arch/arm/mach-s3c/Kconfig.s3c24xx +++ b/arch/arm/mach-s3c/Kconfig.s3c24xx @@ -532,7 +532,6 @@ config MACH_NEO1973_GTA02 select MFD_PCF50633 select PCF50633_GPIO select POWER_SUPPLY - select S3C24XX_PWM select S3C_DEV_USB_HOST help Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone @@ -544,7 +543,6 @@ config MACH_RX1950 select S3C2410_COMMON_DCLK select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ select S3C2440_XTAL_16934400 - select S3C24XX_PWM select S3C_DEV_NAND help Say Y here if you're using HP iPAQ rx1950 diff --git a/arch/arm/mach-s3c/iotiming-s3c2410.c b/arch/arm/mach-s3c/iotiming-s3c2410.c index 28d9f473e24a..09f388d8f824 100644 --- a/arch/arm/mach-s3c/iotiming-s3c2410.c +++ b/arch/arm/mach-s3c/iotiming-s3c2410.c @@ -259,7 +259,7 @@ static const unsigned int tacc_tab[] = { /** * get_tacc - turn tACC value into cycle time * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds. - * @val: The bank timing register value, shifed down. + * @val: The bank timing register value, shifted down. */ static unsigned int get_tacc(unsigned long hclk_tns, unsigned long val) diff --git a/arch/arm/mach-s3c/pm-s3c64xx.c b/arch/arm/mach-s3c/pm-s3c64xx.c index 4f1778123dee..2529f21736ff 100644 --- a/arch/arm/mach-s3c/pm-s3c64xx.c +++ b/arch/arm/mach-s3c/pm-s3c64xx.c @@ -323,7 +323,7 @@ void s3c_pm_arch_update_uart(void __iomem *regs, struct pm_uart_save *save) /* S3C64XX UART blocks only support level interrupts, so ensure that * when we restore unused UART blocks we force the level interrupt - * settigs. */ + * settings. */ save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; /* We have a constraint on changing the clock type of the UART diff --git a/arch/arm/mach-s3c/s3c24xx.c b/arch/arm/mach-s3c/s3c24xx.c index ccfed48c98aa..37eaf9480da7 100644 --- a/arch/arm/mach-s3c/s3c24xx.c +++ b/arch/arm/mach-s3c/s3c24xx.c @@ -146,7 +146,7 @@ static struct map_desc s3c_iodesc[] __initdata __maybe_unused = { IODESC_ENT(UART) }; -/* read cpu identificaiton code */ +/* read cpu identification code */ static unsigned long s3c24xx_read_idcode_v5(void) { diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c index 09ef73b99dd8..abea41f7782e 100644 --- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c +++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c @@ -67,7 +67,7 @@ static const struct of_device_id rcar_gen2_quirk_match[] = { { .compatible = "dlg,da9063", .data = &da9063_msg }, { .compatible = "dlg,da9063l", .data = &da9063_msg }, { .compatible = "dlg,da9210", .data = &da9210_msg }, - {}, + { /* sentinel */ } }; static int regulator_quirk_notify(struct notifier_block *nb, diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index a328d2f52678..ed82d6429623 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c @@ -16,7 +16,7 @@ static const char *const emev2_boards_compat_dt[] __initconst = { "renesas,emev2", - NULL, + NULL }; DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c index 14867226f8f4..a70b99495e2e 100644 --- a/arch/arm/mach-shmobile/setup-r7s72100.c +++ b/arch/arm/mach-shmobile/setup-r7s72100.c @@ -14,7 +14,7 @@ static const char *const r7s72100_boards_compat_dt[] __initconst = { "renesas,r7s72100", - NULL, + NULL }; DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)") diff --git a/arch/arm/mach-shmobile/setup-r7s9210.c b/arch/arm/mach-shmobile/setup-r7s9210.c index 573fb9955e7e..90add728bc3d 100644 --- a/arch/arm/mach-shmobile/setup-r7s9210.c +++ b/arch/arm/mach-shmobile/setup-r7s9210.c @@ -15,7 +15,7 @@ static const char *const r7s9210_boards_compat_dt[] __initconst = { "renesas,r7s9210", - NULL, + NULL }; DT_MACHINE_START(R7S72100_DT, "Generic R7S9210 (Flattened Device Tree)") diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index 23a29a0ea9c9..9e3f4dc08372 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -14,7 +14,7 @@ static const char *const r8a73a4_boards_compat_dt[] __initconst = { "renesas,r8a73a4", - NULL, + NULL }; DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index f760c27c9907..9ac2b8a2aa6a 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -72,7 +72,7 @@ static void __init r8a7740_generic_init(void) static const char *const r8a7740_boards_compat_dt[] __initconst = { "renesas,r8a7740", - NULL, + NULL }; DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 02cda9cada4c..445017e8cfe8 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -43,7 +43,7 @@ static void __init r8a7778_init_irq_dt(void) static const char *const r8a7778_compat_dt[] __initconst = { "renesas,r8a7778", - NULL, + NULL }; DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index b6e282116d66..c3af2c8925ba 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -49,7 +49,7 @@ static void __init r8a7779_init_irq_dt(void) static const char *const r8a7779_compat_dt[] __initconst = { "renesas,r8a7779", - NULL, + NULL }; DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index d42d93443f2f..3edbf0719fb3 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -199,7 +199,7 @@ static const char * const rcar_gen2_boards_compat_dt[] __initconst = { "renesas,r8a7792", "renesas,r8a7793", "renesas,r8a7794", - NULL, + NULL }; DT_MACHINE_START(RCAR_GEN2_DT, "Generic R-Car Gen2 (Flattened Device Tree)") @@ -215,7 +215,7 @@ static const char * const rz_g1_boards_compat_dt[] __initconst = { "renesas,r8a7744", "renesas,r8a7745", "renesas,r8a77470", - NULL, + NULL }; DT_MACHINE_START(RZ_G1_DT, "Generic RZ/G1 (Flattened Device Tree)") diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 890bf537b7de..7fb27240e907 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -32,7 +32,7 @@ static void __init sh73a0_generic_init(void) static const char *const sh73a0_boards_compat_dt[] __initconst = { "renesas,sh73a0", - NULL, + NULL }; DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index e6911a14c096..1f57e7c0feae 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -83,7 +83,7 @@ static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle) * For warm boot CPU that was resumed from CPU hotplug, the * power will be resumed automatically after un-halting the * flow controller of the warm boot CPU. We need to wait for - * the confirmaiton that the CPU is powered then removing + * the confirmation that the CPU is powered then removing * the IO clamps. * For cold boot CPU, do not wait. After the cold boot CPU be * booted, it will run to tegra_secondary_init() and set diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c index bdc07030997b..9c1172f26885 100644 --- a/arch/arm/mm/cache-b15-rac.c +++ b/arch/arm/mm/cache-b15-rac.c @@ -74,7 +74,7 @@ static inline void __b15_rac_flush(void) __raw_writel(FLUSH_RAC, b15_rac_base + rac_flush_offset); do { /* This dmb() is required to force the Bus Interface Unit - * to clean oustanding writes, and forces an idle cycle + * to clean outstanding writes, and forces an idle cycle * to be inserted. */ dmb(); diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h index 2772ef5e3934..f7a35b3656bb 100644 --- a/drivers/soc/mediatek/mt8167-mmsys.h +++ b/drivers/soc/mediatek/mt8167-mmsys.h @@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0, }, { - DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0, + DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0, MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0 }, { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h index 0c021f4b76d2..ff6be1703469 100644 --- a/drivers/soc/mediatek/mt8183-mmsys.h +++ b/drivers/soc/mediatek/mt8183-mmsys.h @@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = { MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1, MT8183_OVL1_2L_MOUT_EN_RDMA1 }, { - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0, MT8183_DITHER0_MOUT_IN_DSI0 }, { diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h index c72ccf86ea28..eb1ad9c37a9c 100644 --- a/drivers/soc/mediatek/mt8186-mmsys.h +++ b/drivers/soc/mediatek/mt8186-mmsys.h @@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = { MT8186_RDMA0_SOUT_TO_COLOR0 }, { - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK, MT8186_DITHER0_MOUT_TO_DSI0, }, { - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK, MT8186_DSI0_FROM_DITHER0 }, diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h index 6aae0b12b6ff..a016d80b4bc1 100644 --- a/drivers/soc/mediatek/mt8192-mmsys.h +++ b/drivers/soc/mediatek/mt8192-mmsys.h @@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4, MT8192_OVL2_2L_MOUT_EN_RDMA4 }, { - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0, MT8192_DITHER0_MOUT_IN_DSI0 }, { @@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0, MT8192_AAL0_SEL_IN_CCORR0 }, { - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0, MT8192_DSI0_SEL_IN_DITHER0 }, { diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h new file mode 100644 index 000000000000..abfe94a30248 --- /dev/null +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -0,0 +1,370 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H +#define __SOC_MEDIATEK_MT8195_MMSYS_H + +#define MT8195_VDO0_OVL_MOUT_EN 0xf14 +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) + +#define MT8195_VDO0_SEL_IN 0xf34 +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9) +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12) +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0) +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) +#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16) +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) +#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17) +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20) +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21) +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22) +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22) + +#define MT8195_VDO0_SEL_OUT 0xf38 +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0) +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1) +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) +#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11) +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) + +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0, + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0, + MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1, + MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 + }, { + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1, + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 + }, { + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1, + MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 + }, { + DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0, + MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, + MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, + MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, + MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, + MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, + MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, + MT8195_SEL_IN_DSI1_FROM_VPP_MERGE + }, { + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, + MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, + MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK, + MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, + MT8195_SOUT_DISP_DITHER0_TO_DSI0 + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, + MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, + MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_DSI1 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK, + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE + } +}; + +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h index 690e3fe2dee0..24129a6c25f8 100644 --- a/drivers/soc/mediatek/mt8365-mmsys.h +++ b/drivers/soc/mediatek/mt8365-mmsys.h @@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = { MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0 }, { - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN, MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0 }, { - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER }, diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 3c8e4212d941..c1837a468267 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -425,34 +425,11 @@ int cmdq_pkt_finalize(struct cmdq_pkt *pkt) } EXPORT_SYMBOL(cmdq_pkt_finalize); -static void cmdq_pkt_flush_async_cb(struct cmdq_cb_data data) -{ - struct cmdq_pkt *pkt = (struct cmdq_pkt *)data.data; - struct cmdq_task_cb *cb = &pkt->cb; - struct cmdq_client *client = (struct cmdq_client *)pkt->cl; - - dma_sync_single_for_cpu(client->chan->mbox->dev, pkt->pa_base, - pkt->cmd_buf_size, DMA_TO_DEVICE); - if (cb->cb) { - data.data = cb->data; - cb->cb(data); - } -} - -int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb, - void *data) +int cmdq_pkt_flush_async(struct cmdq_pkt *pkt) { int err; struct cmdq_client *client = (struct cmdq_client *)pkt->cl; - pkt->cb.cb = cb; - pkt->cb.data = data; - pkt->async_cb.cb = cmdq_pkt_flush_async_cb; - pkt->async_cb.data = pkt; - - dma_sync_single_for_device(client->chan->mbox->dev, pkt->pa_base, - pkt->cmd_buf_size, DMA_TO_DEVICE); - err = mbox_send_message(client->chan, pkt); if (err < 0) return err; diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 4fc4c2c9ea20..06d8e83a2cb5 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -17,6 +17,7 @@ #include "mt8183-mmsys.h" #include "mt8186-mmsys.h" #include "mt8192-mmsys.h" +#include "mt8195-mmsys.h" #include "mt8365-mmsys.h" static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { @@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .num_routes = ARRAY_SIZE(mmsys_default_routing_table), }; +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = { + .num_drv_data = 1, + .drv_data = { + &mt2701_mmsys_driver_data, + }, +}; + static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .clk_driver = "clk-mt2712-mm", .routes = mmsys_default_routing_table, .num_routes = ARRAY_SIZE(mmsys_default_routing_table), }; +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = { + .num_drv_data = 1, + .drv_data = { + &mt2712_mmsys_driver_data, + }, +}; + static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", }; +static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = { + .num_drv_data = 1, + .drv_data = { + &mt6779_mmsys_driver_data, + }, +}; + static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", }; +static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = { + .num_drv_data = 1, + .drv_data = { + &mt6797_mmsys_driver_data, + }, +}; + static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { .clk_driver = "clk-mt8167-mm", .routes = mt8167_mmsys_routing_table, .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), }; +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = { + .num_drv_data = 1, + .drv_data = { + &mt8167_mmsys_driver_data, + }, +}; + static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", .routes = mmsys_default_routing_table, @@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, }; +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = { + .num_drv_data = 1, + .drv_data = { + &mt8173_mmsys_driver_data, + }, +}; + static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", .routes = mmsys_mt8183_routing_table, @@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, }; +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = { + .num_drv_data = 1, + .drv_data = { + &mt8183_mmsys_driver_data, + }, +}; + static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .clk_driver = "clk-mt8186-mm", .routes = mmsys_mt8186_routing_table, @@ -66,10 +116,45 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, }; +static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = { + .num_drv_data = 1, + .drv_data = { + &mt8186_mmsys_driver_data, + }, +}; + static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .clk_driver = "clk-mt8192-mm", .routes = mmsys_mt8192_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), + .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, +}; + +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = { + .num_drv_data = 1, + .drv_data = { + &mt8192_mmsys_driver_data, + }, +}; + +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { + .io_start = 0x1c01a000, + .clk_driver = "clk-mt8195-vdo0", + .routes = mmsys_mt8195_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), +}; + +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { + .io_start = 0x1c100000, + .clk_driver = "clk-mt8195-vdo1", +}; + +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = { + .num_drv_data = 2, + .drv_data = { + &mt8195_vdosys0_driver_data, + &mt8195_vdosys1_driver_data, + }, }; static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { @@ -78,13 +163,33 @@ static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table), }; +static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = { + .num_drv_data = 1, + .drv_data = { + &mt8365_mmsys_driver_data, + }, +}; + struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; spinlock_t lock; /* protects mmsys_sw_rst_b reg */ struct reset_controller_dev rcdev; + phys_addr_t io_start; }; +static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys, + const struct mtk_mmsys_match_data *match) +{ + int i; + + for (i = 0; i < match->num_drv_data; i++) + if (mmsys->io_start == match->drv_data[i]->io_start) + return i; + + return -EINVAL; +} + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) @@ -179,7 +284,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct platform_device *clks; struct platform_device *drm; + const struct mtk_mmsys_match_data *match_data; struct mtk_mmsys *mmsys; + struct resource *res; int ret; mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); @@ -205,7 +312,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return ret; } - mmsys->data = of_device_get_match_data(&pdev->dev); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "Couldn't get mmsys resource\n"); + return -EINVAL; + } + mmsys->io_start = res->start; + + match_data = of_device_get_match_data(dev); + if (match_data->num_drv_data > 1) { + /* This SoC has multiple mmsys channels */ + ret = mtk_mmsys_find_match_drvdata(mmsys, match_data); + if (ret < 0) { + dev_err(dev, "Couldn't get match driver data\n"); + return ret; + } + mmsys->data = match_data->drv_data[ret]; + } else { + dev_dbg(dev, "Using single mmsys channel\n"); + mmsys->data = match_data->drv_data[0]; + } + platform_set_drvdata(pdev, mmsys); clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, @@ -226,43 +353,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev) static const struct of_device_id of_match_mtk_mmsys[] = { { .compatible = "mediatek,mt2701-mmsys", - .data = &mt2701_mmsys_driver_data, + .data = &mt2701_mmsys_match_data, }, { .compatible = "mediatek,mt2712-mmsys", - .data = &mt2712_mmsys_driver_data, + .data = &mt2712_mmsys_match_data, }, { .compatible = "mediatek,mt6779-mmsys", - .data = &mt6779_mmsys_driver_data, + .data = &mt6779_mmsys_match_data, }, { .compatible = "mediatek,mt6797-mmsys", - .data = &mt6797_mmsys_driver_data, + .data = &mt6797_mmsys_match_data, }, { .compatible = "mediatek,mt8167-mmsys", - .data = &mt8167_mmsys_driver_data, + .data = &mt8167_mmsys_match_data, }, { .compatible = "mediatek,mt8173-mmsys", - .data = &mt8173_mmsys_driver_data, + .data = &mt8173_mmsys_match_data, }, { .compatible = "mediatek,mt8183-mmsys", - .data = &mt8183_mmsys_driver_data, + .data = &mt8183_mmsys_match_data, }, { .compatible = "mediatek,mt8186-mmsys", - .data = &mt8186_mmsys_driver_data, + .data = &mt8186_mmsys_match_data, }, { .compatible = "mediatek,mt8192-mmsys", - .data = &mt8192_mmsys_driver_data, + .data = &mt8192_mmsys_match_data, + }, + { + .compatible = "mediatek,mt8195-mmsys", + .data = &mt8195_mmsys_match_data, }, { .compatible = "mediatek,mt8365-mmsys", - .data = &mt8365_mmsys_driver_data, + .data = &mt8365_mmsys_match_data, }, { } }; diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 77f37f8c715b..f01ba206481d 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -87,12 +87,18 @@ struct mtk_mmsys_routes { }; struct mtk_mmsys_driver_data { + const resource_size_t io_start; const char *clk_driver; const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; }; +struct mtk_mmsys_match_data { + unsigned short num_drv_data; + const struct mtk_mmsys_driver_data *drv_data[]; +}; + /* * Routes in mt8173, mt2701, mt2712 are different. That means * in the same register address, it controls different input/output diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index aaf8fc1abb43..981d56967e7a 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -96,6 +96,20 @@ #define MT8173_MUTEX_MOD_DISP_PWM1 24 #define MT8173_MUTEX_MOD_DISP_OD 25 +#define MT8195_MUTEX_MOD_DISP_OVL0 0 +#define MT8195_MUTEX_MOD_DISP_WDMA0 1 +#define MT8195_MUTEX_MOD_DISP_RDMA0 2 +#define MT8195_MUTEX_MOD_DISP_COLOR0 3 +#define MT8195_MUTEX_MOD_DISP_CCORR0 4 +#define MT8195_MUTEX_MOD_DISP_AAL0 5 +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6 +#define MT8195_MUTEX_MOD_DISP_DITHER0 7 +#define MT8195_MUTEX_MOD_DISP_DSI0 8 +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 +#define MT8195_MUTEX_MOD_DISP_PWM0 27 + #define MT2712_MUTEX_MOD_DISP_PWM2 10 #define MT2712_MUTEX_MOD_DISP_OVL0 11 #define MT2712_MUTEX_MOD_DISP_OVL1 12 @@ -132,9 +146,21 @@ #define MT8167_MUTEX_SOF_DPI1 3 #define MT8183_MUTEX_SOF_DSI0 1 #define MT8183_MUTEX_SOF_DPI0 2 +#define MT8195_MUTEX_SOF_DSI0 1 +#define MT8195_MUTEX_SOF_DSI1 2 +#define MT8195_MUTEX_SOF_DP_INTF0 3 +#define MT8195_MUTEX_SOF_DP_INTF1 4 +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */ +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */ #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) +#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) +#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) +#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) +#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7) +#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7) +#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7) struct mtk_mutex { int id; @@ -149,6 +175,9 @@ enum mtk_mutex_sof_id { MUTEX_SOF_DPI1, MUTEX_SOF_DSI2, MUTEX_SOF_DSI3, + MUTEX_SOF_DP_INTF0, + MUTEX_SOF_DP_INTF1, + DDP_MUTEX_SOF_MAX, }; struct mtk_mutex_data { @@ -200,7 +229,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, - [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER, + [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER, [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA, [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1, @@ -233,7 +262,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, - [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0, [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, @@ -247,7 +276,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0, [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0, - [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0, [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0, [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L, @@ -260,7 +289,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0, - [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0, [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0, [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0, [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0, @@ -270,7 +299,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, }; -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE, + [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, + [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, +}; + +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, @@ -280,7 +325,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, }; -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, @@ -288,7 +333,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { }; /* Add EOF setting so overlay hardware can receive frame done irq */ -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, @@ -300,6 +345,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0, }; +/* + * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should + * select the EOF source and configure the EOF plus timing from the + * module that provides the timing signal. + * So that MUTEX can not only send a STREAM_DONE event to GCE + * but also detect the error at end of frame(EAEOF) when EOF signal + * arrives. + */ +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0, + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1, + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0, + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1, + [MUTEX_SOF_DP_INTF0] = + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0, + [MUTEX_SOF_DP_INTF1] = + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1, +}; + static const struct mtk_mutex_data mt2701_mutex_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -351,6 +416,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = { .mutex_sof_reg = MT8183_MUTEX0_SOF0, }; +static const struct mtk_mutex_data mt8195_mutex_driver_data = { + .mutex_mod = mt8195_mutex_mod, + .mutex_sof = mt8195_mutex_sof, + .mutex_mod_reg = MT8183_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_MUTEX0_SOF0, +}; + struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -423,6 +495,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DPI1: sof_id = MUTEX_SOF_DPI1; break; + case DDP_COMPONENT_DP_INTF0: + sof_id = MUTEX_SOF_DP_INTF0; + break; default: if (mtx->data->mutex_mod[id] < 32) { offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, @@ -462,6 +537,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DSI3: case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI1: + case DDP_COMPONENT_DP_INTF0: writel_relaxed(MUTEX_SOF_SINGLE_MODE, mtx->regs + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, @@ -587,6 +663,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8186_mutex_driver_data}, { .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data}, + { .compatible = "mediatek,mt8195-disp-mutex", + .data = &mt8195_mutex_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index ac6b5f3cba95..2b498f4f3946 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -268,8 +268,6 @@ int cmdq_pkt_finalize(struct cmdq_pkt *pkt); * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ * packet and call back at the end of done packet * @pkt: the CMDQ packet - * @cb: called at the end of done packet - * @data: this data will pass back to cb * * Return: 0 for success; else the error code is returned * @@ -277,7 +275,6 @@ int cmdq_pkt_finalize(struct cmdq_pkt *pkt); * at the end of done packet. Note that this is an ASYNC function. When the * function returned, it may or may not be finished. */ -int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb, - void *data); +int cmdq_pkt_flush_async(struct cmdq_pkt *pkt); #endif /* __MTK_CMDQ_H__ */ diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 4bba275e235a..59117d970daf 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -17,13 +17,25 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, DDP_COMPONENT_DITHER, + DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER, + DDP_COMPONENT_DITHER1, + DDP_COMPONENT_DP_INTF0, + DDP_COMPONENT_DP_INTF1, DDP_COMPONENT_DPI0, DDP_COMPONENT_DPI1, + DDP_COMPONENT_DSC0, + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_DSI2, DDP_COMPONENT_DSI3, DDP_COMPONENT_GAMMA, + DDP_COMPONENT_MERGE0, + DDP_COMPONENT_MERGE1, + DDP_COMPONENT_MERGE2, + DDP_COMPONENT_MERGE3, + DDP_COMPONENT_MERGE4, + DDP_COMPONENT_MERGE5, DDP_COMPONENT_OD0, DDP_COMPONENT_OD1, DDP_COMPONENT_OVL0, |