diff options
Diffstat (limited to 'arch/arm64/mm')
| -rw-r--r-- | arch/arm64/mm/context.c | 6 | ||||
| -rw-r--r-- | arch/arm64/mm/fault.c | 16 | ||||
| -rw-r--r-- | arch/arm64/mm/proc.S | 8 |
3 files changed, 3 insertions, 27 deletions
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index a5b64c1ff72d..baa758d37021 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -157,9 +157,3 @@ void __new_context(struct mm_struct *mm) set_mm_context(mm, asid); raw_spin_unlock(&cpu_asid_lock); } - -/* Errata workaround post TTBRx_EL1 update. */ -asmlinkage void post_ttbr_update_workaround(void) -{ - arm64_apply_bp_hardening(); -} diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 07b352893cd4..3d1c63edf537 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -476,22 +476,6 @@ asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, arm64_notify_die("", regs, &info, esr); } -asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, - unsigned int esr, - struct pt_regs *regs) -{ - /* - * We've taken an instruction abort from userspace and not yet - * re-enabled IRQs. If the address is a kernel address, apply - * BP hardening prior to enabling IRQs and pre-emption. - */ - if (addr > TASK_SIZE) - arm64_apply_bp_hardening(); - - local_irq_enable(); - do_mem_abort(addr, esr, regs); -} - /* * Handle stack alignment exceptions. */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 8820b86bb68f..f66334910acc 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -105,13 +105,12 @@ ENTRY(cpu_do_suspend) mrs x10, mdscr_el1 mrs x11, oslsr_el1 mrs x12, sctlr_el1 - mrs x13, tpidr_el1 stp x2, x3, [x0] stp x4, x5, [x0, #16] stp x6, x7, [x0, #32] stp x8, x9, [x0, #48] stp x10, x11, [x0, #64] - stp x12, x13, [x0, #80] + str x12, [x0, #80] ret ENDPROC(cpu_do_suspend) @@ -134,7 +133,7 @@ ENTRY(cpu_do_resume) ldp x6, x7, [x0, #32] ldp x8, x9, [x0, #48] ldp x10, x11, [x0, #64] - ldp x12, x13, [x0, #80] + ldr x12, [x0, #80] msr tpidr_el0, x2 msr tpidrro_el0, x3 msr contextidr_el1, x4 @@ -145,7 +144,6 @@ ENTRY(cpu_do_resume) msr tcr_el1, x8 msr vbar_el1, x9 msr mdscr_el1, x10 - msr tpidr_el1, x13 /* * Restore oslsr_el1 by writing oslar_el1 */ @@ -170,7 +168,7 @@ ENTRY(cpu_do_switch_mm) bfi x0, x1, #48, #16 // set the ASID msr ttbr0_el1, x0 // set TTBR0 isb - b post_ttbr_update_workaround // Back to C code... + ret ENDPROC(cpu_do_switch_mm) .section ".text.init", #alloc, #execinstr |