diff options
| author | Tom Rini <trini@konsulko.com> | 2018-12-10 07:15:55 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-12-10 07:15:55 -0500 |
| commit | 7504e9e75f76a5101b47cd32851ad7bd4ea8ff70 (patch) | |
| tree | b62e8af678b5b5512f5f5f00c927aafe9da5fce1 | |
| parent | e7463b37a1a437c46fb0d15433d4a3d6362e9a22 (diff) | |
| parent | 5055a4e9008dcb8db78b98ad6a700605cd3ae0e9 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-sh
| -rw-r--r-- | arch/arm/mach-rmobile/cpu_info.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-rmobile/memmap-gen3.c | 24 |
2 files changed, 22 insertions, 6 deletions
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 65a9ca8c01..aa5be52dfd 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -7,8 +7,6 @@ #include <asm/io.h> #include <linux/ctype.h> -/* R-Car Gen3 caches are enabled in memmap-gen3.c */ -#ifndef CONFIG_RCAR_GEN3 #ifdef CONFIG_ARCH_CPU_INIT int arch_cpu_init(void) { @@ -17,6 +15,8 @@ int arch_cpu_init(void) } #endif +/* R-Car Gen3 D-cache is enabled in memmap-gen3.c */ +#ifndef CONFIG_RCAR_GEN3 #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c index 7e29ccc351..1a9eb72bb9 100644 --- a/arch/arm/mach-rmobile/memmap-gen3.c +++ b/arch/arm/mach-rmobile/memmap-gen3.c @@ -21,7 +21,13 @@ static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = { }, { .virt = 0x40000000UL, .phys = 0x40000000UL, - .size = 0x80000000UL, + .size = 0x03F00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x47E00000UL, + .phys = 0x47E00000UL, + .size = 0x78200000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -76,8 +82,16 @@ void enable_caches(void) /* Mark memory reserved by ATF as cacheable too. */ if (start == 0x48000000) { - start = 0x40000000ULL; - size += 0x08000000ULL; + /* Unmark protection area (0x43F00000 to 0x47DFFFFF) */ + gen3_mem_map[i].virt = 0x40000000ULL; + gen3_mem_map[i].phys = 0x40000000ULL; + gen3_mem_map[i].size = 0x03F00000ULL; + gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + i++; + + start = 0x47E00000ULL; + size += 0x00200000ULL; } gen3_mem_map[i].virt = start; @@ -126,6 +140,8 @@ void enable_caches(void) gen3_mem_map[i].attrs = 0; } - icache_enable(); + if (!icache_status()) + icache_enable(); + dcache_enable(); } |