diff options
| author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2013-04-04 00:10:08 +0800 |
|---|---|---|
| committer | Haojian Zhuang <haojian.zhuang@linaro.org> | 2013-04-04 00:10:08 +0800 |
| commit | 3c5835bc28f5e1bd3e80da0daf7c55ca8d8e859e (patch) | |
| tree | fd22a3c85147f7f67575ac9d3bc3e10b6011cc9f | |
| parent | 2c037e1c7da4c473c39b02e61a4b1f114f4d20bf (diff) | |
clk: hi3xxx: not disable clock for clkgate preparetopic/clock-m2
If hi3xxx clock gate is disabled in prepare stage, the uart console
can't output anything until it's enabled. It makes debugging kernel
harder in kernel boot stage.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| -rw-r--r-- | drivers/clk/hisilicon/clk-hi3xxx.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/clk/hisilicon/clk-hi3xxx.c b/drivers/clk/hisilicon/clk-hi3xxx.c index c61041a3b49c..9682517edfd4 100644 --- a/drivers/clk/hisilicon/clk-hi3xxx.c +++ b/drivers/clk/hisilicon/clk-hi3xxx.c @@ -100,7 +100,6 @@ static int hi3620_clkgate_prepare(struct clk_hw *hw) if (pclk->lock) spin_lock_irqsave(pclk->lock, flags); - writel_relaxed(pclk->ebits, pclk->enable + HI3620_DISABLE_OFF); if (pclk->reset) { writel_relaxed(pclk->rbits, pclk->reset + HI3620_DISABLE_OFF); readl_relaxed(pclk->reset + HI3620_STATUS_OFF); |