diff options
| author | Guodong Xu <guodong.xu@linaro.org> | 2013-03-25 09:09:58 +0800 |
|---|---|---|
| committer | Guodong Xu <guodong.xu@linaro.org> | 2013-03-25 09:09:58 +0800 |
| commit | 576833ba984d76a6da4ef9d662f7fdd64e196e6b (patch) | |
| tree | 940e511687085a6a2b9135a0ead6eb07e39dce8a | |
| parent | 16a1f3c2e0ef7036ac1755ce22871e3f6d37d957 (diff) | |
PM: workaround translation table base p2v +=0xC0000000topic-suspend-resume
| -rw-r--r-- | arch/arm/mach-hs/hilpm-cpugodp.S | 33 |
1 files changed, 20 insertions, 13 deletions
diff --git a/arch/arm/mach-hs/hilpm-cpugodp.S b/arch/arm/mach-hs/hilpm-cpugodp.S index 2640225943bf..37fb7bb4c533 100644 --- a/arch/arm/mach-hs/hilpm-cpugodp.S +++ b/arch/arm/mach-hs/hilpm-cpugodp.S @@ -399,25 +399,33 @@ ttbr_error: create_idmap: /**read TTBR0 registers**/ - mrc p15, 0, r2, c2, c0, 0 - ldr r5, =TTBRBIT_MASK - and r2, r5 - ldr r4, =(hisi_v2p(disable_mmu)) - ldr r5, =TABLE_INDEX_MASK - and r4, r5 - ldr r1, =TABLE_ENTRY - add r1, r1, r4 - lsr r4, #18 - add r2, r4 + mrc p15, 0, r2, c2, c0, 0 @ r2: translation table base register 0 + ldr r5, =TTBRBIT_MASK @ 0xFFFFC000, high 18 bits + and r2, r5 @ r2 = TTBR0's high 18 bits + ldr r4, =(hisi_v2p(disable_mmu)) @ r4, pa(disable_mmu) + ldr r5, =TABLE_INDEX_MASK @ 0xFFF00000, top 12 bits. + and r4, r5 @ r4 = keeps the top 12 bits + ldr r1, =TABLE_ENTRY @ r1 = 0x00000C02 // why 0x0C02? these are ttb property bits. any change in v3.8? + add r1, r1, r4 @ r1 = top 12 bits of pa(disable_mmu) | 0x0C02 + lsr r4, #18 @ r4 = r4 >> 18 + add r2, r4 @r2 = r2 + r4, TTBR0's high 18 bits + r4's top 14 bits (shifted to low 14 bits) /**r2 virtual addr for TLB**/ p2v r2, r4, PLAT_PHYS_OFFSET, PAGE_OFFSET + @ it assumes that r2/TTBR0 is physical address. + @ is that a correct assumption? + /* TODO: debug */ + ldr r4, =0xC0000000 + add r2, r2, r4 @ workaround. reason unknown + + @ now, r2 is the virtual address of disable_mmu() code part. + @ what if disable_mmu() code part cross two or more translation table section? /**read the TLB**/ LDR r7, [r2] /**config the identy mapping**/ - STR r1, [r2] + STR r1, [r2] @ change the TLB its to it's physical address. /**r9 virtual addr for tlb**/ mov r9, r2 @@ -425,8 +433,7 @@ create_idmap: /**r11 virtual addr of the enable_mmu**/ ADR r11, mmu_enalbed /* debug TODO: add 'nop' to fix mmu_enalbed. <imm8m> address-able */ - nop - + nop LDR r6, =(hisi_v2p(ready_to_store)) LDR pc, =(hisi_v2p(disable_mmu)) |