aboutsummaryrefslogtreecommitdiff
path: root/arch/blackfin/mach-bf561/include/mach/mem_map.h
blob: a63e15c86d90438dec954ce6b6d883682e13374a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
/*
 * BF561 memory map
 *
 * Copyright 2004-2009 Analog Devices Inc.
 * Licensed under the GPL-2 or later.
 */

#ifndef __BFIN_MACH_MEM_MAP_H__
#define __BFIN_MACH_MEM_MAP_H__

#ifndef __BFIN_MEM_MAP_H__
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
#endif

/* Async Memory Banks */
#define ASYNC_BANK3_BASE	0x2C000000	 /* Async Bank 3 */
#define ASYNC_BANK3_SIZE	0x04000000	/* 64M */
#define ASYNC_BANK2_BASE	0x28000000	 /* Async Bank 2 */
#define ASYNC_BANK2_SIZE	0x04000000	/* 64M */
#define ASYNC_BANK1_BASE	0x24000000	 /* Async Bank 1 */
#define ASYNC_BANK1_SIZE	0x04000000	/* 64M */
#define ASYNC_BANK0_BASE	0x20000000	 /* Async Bank 0 */
#define ASYNC_BANK0_SIZE	0x04000000	/* 64M */

/* Boot ROM Memory */

#define BOOT_ROM_START		0xEF000000
#define BOOT_ROM_LENGTH		0x800

/* Level 1 Memory */

#ifdef CONFIG_BFIN_ICACHE
#define BFIN_ICACHESIZE	(16*1024)
#else
#define BFIN_ICACHESIZE	(0*1024)
#endif

/* Memory Map for ADSP-BF561 processors */

#ifdef CONFIG_BF561
#define COREA_L1_CODE_START       0xFFA00000
#define COREA_L1_DATA_A_START     0xFF800000
#define COREA_L1_DATA_B_START     0xFF900000
#define COREB_L1_CODE_START       0xFF600000
#define COREB_L1_DATA_A_START     0xFF400000
#define COREB_L1_DATA_B_START     0xFF500000

#define L1_CODE_START       COREA_L1_CODE_START
#define L1_DATA_A_START     COREA_L1_DATA_A_START
#define L1_DATA_B_START     COREA_L1_DATA_B_START

#define L1_CODE_LENGTH      0x4000

#ifdef CONFIG_BFIN_DCACHE

#ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH      0x8000
#define BFIN_DCACHESIZE	(16*1024)
#define BFIN_DSUPBANKS	1
#else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
#define BFIN_DCACHESIZE	(32*1024)
#define BFIN_DSUPBANKS	2
#endif

#else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH      0x8000
#define L1_DATA_B_LENGTH      0x8000
#define BFIN_DCACHESIZE	(0*1024)
#define BFIN_DSUPBANKS	0
#endif /*CONFIG_BFIN_DCACHE*/
#endif

/* Level 2 Memory */
#define L2_START		0xFEB00000
#define L2_LENGTH		0x20000

/* Scratch Pad Memory */

#define COREA_L1_SCRATCH_START	0xFFB00000
#define COREB_L1_SCRATCH_START	0xFF700000

#ifdef __ASSEMBLY__

/*
 * The following macros both return the address of the PDA for the
 * current core.
 *
 * In its first safe (and hairy) form, the macro neither clobbers any
 * register aside of the output Preg, nor uses the stack, since it
 * could be called with an invalid stack pointer, or the current stack
 * space being uncovered by any CPLB (e.g. early exception handling).
 *
 * The constraints on the second form are a bit relaxed, and the code
 * is allowed to use the specified Dreg for determining the PDA
 * address to be returned into Preg.
 */
#ifdef CONFIG_SMP
#define GET_PDA_SAFE(preg)		\
	preg.l = lo(DSPID);		\
	preg.h = hi(DSPID);		\
	preg = [preg];			\
	preg = preg << 2;		\
	preg = preg << 2;		\
	preg = preg << 2;		\
	preg = preg << 2;		\
	preg = preg << 2;		\
	preg = preg << 2;		\
	preg = preg << 2;		\
	preg = preg << 2;		\
	preg = preg << 2;		\
	preg = preg << 2;		\
	preg = preg << 2;		\
	preg = preg << 2;		\
	if cc jump 2f;			\
	cc = preg == 0x0;		\
	preg.l = _cpu_pda;		\
	preg.h = _cpu_pda;		\
	if !cc jump 3f;			\
1:					\
	/* preg = 0x0; */		\
	cc = !cc; /* restore cc to 0 */	\
	jump 4f;			\
2:					\
	cc = preg == 0x0;		\
	preg.l = _cpu_pda;		\
	preg.h = _cpu_pda;		\
	if cc jump 4f;			\
	/* preg = 0x1000000; */		\
	cc = !cc; /* restore cc to 1 */	\
3:					\
	preg = [preg];			\
4:

#define GET_PDA(preg, dreg)		\
	preg.l = lo(DSPID);		\
	preg.h = hi(DSPID);		\
	dreg = [preg];			\
	preg.l = _cpu_pda;		\
	preg.h = _cpu_pda;		\
	cc = bittst(dreg, 0);		\
	if !cc jump 1f;			\
	preg = [preg];			\
1:					\

#define GET_CPUID(preg, dreg)		\
	preg.l = lo(DSPID);		\
	preg.h = hi(DSPID);		\
	dreg = [preg];			\
	dreg = ROT dreg BY -1;		\
	dreg = CC;

static inline unsigned long get_l1_scratch_start_cpu(int cpu)
{
	return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
}
static inline unsigned long get_l1_code_start_cpu(int cpu)
{
	return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START;
}
static inline unsigned long get_l1_data_a_start_cpu(int cpu)
{
	return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
}
static inline unsigned long get_l1_data_b_start_cpu(int cpu)
{
	return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
}

static inline unsigned long get_l1_scratch_start(void)
{
	return get_l1_scratch_start_cpu(blackfin_core_id());
}
static inline unsigned long get_l1_code_start(void)
{
	return get_l1_code_start_cpu(blackfin_core_id());
}
static inline unsigned long get_l1_data_a_start(void)
{
	return get_l1_data_a_start_cpu(blackfin_core_id());
}
static inline unsigned long get_l1_data_b_start(void)
{
	return get_l1_data_b_start_cpu(blackfin_core_id());
}

#endif /* CONFIG_SMP */

#endif /* __ASSEMBLY__ */

#endif