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path: root/drivers/gpu/drm/i915/intel_ddi.c
AgeCommit message (Expand)Author
2015-09-01drm/i915: Don't use link_bw for PLL setupVille Syrjälä
2015-08-26drm/i915/skl: Update DDI buffer translation programming.Rodrigo Vivi
2015-08-14drm/i915: Per-DDI I_boost overrideAntti Koskipaa
2015-08-14drm/i915: Set alternate aux for DDI-ERodrigo Vivi
2015-07-06drm/i915: set FDI translations to NULL on SKLPaulo Zanoni
2015-07-06drm/i915/bxt: BUNs related to port PLLVandana Kannan
2015-07-06drm/i915: Fix HDMI 12bpc and pixel repeat clock readout for DDI platformsVille Syrjälä
2015-07-03drm/i915/bxt: mask off the DPLL state checker bits we don't programImre Deak
2015-06-30drm/i915/bxt: add DDI port HW readout supportImre Deak
2015-06-30drm/i915/bxt: add missing DDI PLL registers to the state checkingImre Deak
2015-06-30drm/i915/skl: Buffer translation improvementsDavid Weinehall
2015-06-26drm/i915/skl: Skip remaining dividers when deviation is 0Damien Lespiau
2015-06-26drm/i915/skl: Prefer even dividers for SKL DPLLsDamien Lespiau
2015-06-26drm/i915/skl: Replace the HDMI DPLL divider computation algorithmDamien Lespiau
2015-06-12drm/i915/bxt: fix DDI PHY vswing scale value settingImre Deak
2015-06-12drm/i915: Don't display the boot CDCLK twiceDamien Lespiau
2015-06-03drm/i915/bxt: edp1.4 Intermediate Freq supportSonika Jindal
2015-05-29drm/i915/skl: Don't try to store the wrong central frequencyDamien Lespiau
2015-05-29drm/i915: Correctly prefix HSW/BDW HDMI clock functionsDamien Lespiau
2015-05-29drm/i915/skl: Remove unnecessary () used with abs_diff()Damien Lespiau
2015-05-29drm/i915/skl: Remove unnecessary () used with div_u64()Damien Lespiau
2015-05-29drm/i915/skl: Factor out computing the DPLL paramaters from the dividersDamien Lespiau
2015-05-29drm/i915/skl: Use a more idomatic early returnDamien Lespiau
2015-05-29drm/i915/skl: Propagate the error if we fail to find a suitable DPLL dividerDamien Lespiau
2015-05-29drm/i915/skl: Display the WRPLL frequency we couldn't accomodate when failingDamien Lespiau
2015-05-29drm/i915/skl: Make sure to break when not finding suitable PLL dividersDamien Lespiau
2015-05-29drm/i915: remove useless DP and DDI encoder ->hot_plug hooksJani Nikula
2015-05-29drm/i915: group all hotplug related fields into a new struct in dev_privJani Nikula
2015-05-21drm/i915/skl: Deinit/init the display at suspend/resumeDamien Lespiau
2015-05-20drm/i915/bxt: Move around lane stagger calculationVandana Kannan
2015-05-20drm/i915/bxt: Port PLL programming BUNVandana Kannan
2015-05-20drm/i915: Don't overwrite (e)DP PLL selection on SKLAnder Conselvan de Oliveira
2015-05-08drm/i915/skl: Re-indent part of skl_ddi_calculate_wrpll()Damien Lespiau
2015-05-08drm/i915: Use for_each_connector_in_state helper macroAnder Conselvan de Oliveira
2015-05-08drm/i915/skl: Add module parameter to select edp vswing tableSonika Jindal
2015-05-08drm/i915/skl: Fix the CTRL typo in the DPLL_CRTL1 definesDamien Lespiau
2015-04-30drm/i915: fix intel_prepare_ddiImre Deak
2015-04-30drm/i915: factor out ddi_get_encoder_portImre Deak
2015-04-16drm/i915/bxt: VSwing programming sequenceVandana Kannan
2015-04-16drm/i915: Don't write the HDMI buffer translation entry when not neededDamien Lespiau
2015-04-16drm/i915: Iterate through the initialized DDIs to prepare their buffersDamien Lespiau
2015-04-16drm/i915/bxt: Determine programmed frequencySatheeshakrishna M
2015-04-16drm/i915/bxt: Assign PLL for pipeSatheeshakrishna M
2015-04-16drm/i915/bxt: BXT clock divider calculationSatheeshakrishna M
2015-04-16drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequenceSatheeshakrishna M
2015-04-16drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9Satheeshakrishna M
2015-04-16drm/i915/skl: Add back HDMI translation tableSonika Jindal
2015-04-16drm/i915/bxt: add display initialize/uninitialize sequence (PHY)Vandana Kannan
2015-04-16drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)Vandana Kannan
2015-04-14Merge branch 'topic/bxt-stage1' into drm-intel-next-queuedDaniel Vetter
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