[MIPS] Remove Momenco Jaguar ATX support

It has some hackish code and it odd DMA results in the need to support
old features in kernel code.

Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

10 files changed, 0 insertions, 1341 deletions

diff --git a/arch/mips/momentum/Kconfig b/arch/mips/momentum/Kconfig
deleted file mode 100644
index 70a61cf7174d..000000000000
--- a/arch/mips/momentum/Kconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-config JAGUAR_DMALOW
-	bool "Low DMA Mode"
-	depends on MOMENCO_JAGUAR_ATX
-	help
-	  Select to Y if jump JP5 is set on your board, N otherwise.  Normally
-	  the jumper is set, so if you feel unsafe, just say Y.
diff --git a/arch/mips/momentum/jaguar_atx/Makefile b/arch/mips/momentum/jaguar_atx/Makefile
deleted file mode 100644
index 2e8cebd49bc0..000000000000
--- a/arch/mips/momentum/jaguar_atx/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Makefile for Momentum Computer's Jaguar-ATX board.
-#
-# Note! Dependencies are done automagically by 'make dep', which also
-# removes any old dependencies. DON'T put your own dependencies here
-# unless it's something special (ie not a .c file).
-#
-
-obj-y += irq.o platform.o prom.o reset.o setup.o
-
-obj-$(CONFIG_SERIAL_8250_CONSOLE) += ja-console.o
-obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
diff --git a/arch/mips/momentum/jaguar_atx/dbg_io.c b/arch/mips/momentum/jaguar_atx/dbg_io.c
deleted file mode 100644
index b85a6521f72d..000000000000
--- a/arch/mips/momentum/jaguar_atx/dbg_io.c
+++ /dev/null
@@ -1,125 +0,0 @@
-
-#if defined(CONFIG_REMOTE_DEBUG)
-
-#include <asm/serial.h> /* For the serial port location and base baud */
-
-/* --- CONFIG --- */
-
-typedef unsigned char uint8;
-typedef unsigned int uint32;
-
-/* --- END OF CONFIG --- */
-
-#define         UART16550_BAUD_2400             2400
-#define         UART16550_BAUD_4800             4800
-#define         UART16550_BAUD_9600             9600
-#define         UART16550_BAUD_19200            19200
-#define         UART16550_BAUD_38400            38400
-#define         UART16550_BAUD_57600            57600
-#define         UART16550_BAUD_115200           115200
-
-#define         UART16550_PARITY_NONE           0
-#define         UART16550_PARITY_ODD            0x08
-#define         UART16550_PARITY_EVEN           0x18
-#define         UART16550_PARITY_MARK           0x28
-#define         UART16550_PARITY_SPACE          0x38
-
-#define         UART16550_DATA_5BIT             0x0
-#define         UART16550_DATA_6BIT             0x1
-#define         UART16550_DATA_7BIT             0x2
-#define         UART16550_DATA_8BIT             0x3
-
-#define         UART16550_STOP_1BIT             0x0
-#define         UART16550_STOP_2BIT             0x4
-
-/* ----------------------------------------------------- */
-
-/* === CONFIG === */
-
-/* [jsun] we use the second serial port for kdb */
-#define         BASE                    OCELOT_SERIAL1_BASE
-#define         MAX_BAUD                OCELOT_BASE_BAUD
-
-/* === END OF CONFIG === */
-
-#define         REG_OFFSET              4
-
-/* register offset */
-#define         OFS_RCV_BUFFER          0
-#define         OFS_TRANS_HOLD          0
-#define         OFS_SEND_BUFFER         0
-#define         OFS_INTR_ENABLE         (1*REG_OFFSET)
-#define         OFS_INTR_ID             (2*REG_OFFSET)
-#define         OFS_DATA_FORMAT         (3*REG_OFFSET)
-#define         OFS_LINE_CONTROL        (3*REG_OFFSET)
-#define         OFS_MODEM_CONTROL       (4*REG_OFFSET)
-#define         OFS_RS232_OUTPUT        (4*REG_OFFSET)
-#define         OFS_LINE_STATUS         (5*REG_OFFSET)
-#define         OFS_MODEM_STATUS        (6*REG_OFFSET)
-#define         OFS_RS232_INPUT         (6*REG_OFFSET)
-#define         OFS_SCRATCH_PAD         (7*REG_OFFSET)
-
-#define         OFS_DIVISOR_LSB         (0*REG_OFFSET)
-#define         OFS_DIVISOR_MSB         (1*REG_OFFSET)
-
-
-/* memory-mapped read/write of the port */
-#define         UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
-#define         UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)
-
-void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
-{
-	/* disable interrupts */
-	UART16550_WRITE(OFS_INTR_ENABLE, 0);
-
-	/* set up baud rate */
-	{
-		uint32 divisor;
-
-		/* set DIAB bit */
-		UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
-
-		/* set divisor */
-		divisor = MAX_BAUD / baud;
-		UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
-		UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
-
-		/* clear DIAB bit */
-		UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
-	}
-
-	/* set data format */
-	UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
-}
-
-static int remoteDebugInitialized = 0;
-
-uint8 getDebugChar(void)
-{
-	if (!remoteDebugInitialized) {
-		remoteDebugInitialized = 1;
-		debugInit(UART16550_BAUD_38400,
-			  UART16550_DATA_8BIT,
-			  UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-	}
-
-	while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
-	return UART16550_READ(OFS_RCV_BUFFER);
-}
-
-
-int putDebugChar(uint8 byte)
-{
-	if (!remoteDebugInitialized) {
-		remoteDebugInitialized = 1;
-		debugInit(UART16550_BAUD_38400,
-			  UART16550_DATA_8BIT,
-			  UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-	}
-
-	while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
-	UART16550_WRITE(OFS_SEND_BUFFER, byte);
-	return 1;
-}
-
-#endif
diff --git a/arch/mips/momentum/jaguar_atx/irq.c b/arch/mips/momentum/jaguar_atx/irq.c
deleted file mode 100644
index f2b432585df2..000000000000
--- a/arch/mips/momentum/jaguar_atx/irq.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright (C) 2002 Momentum Computer, Inc.
- * Author: Matthew Dharm, mdharm@momenco.com
- *
- * Based on work by:
- *   Copyright (C) 2000 RidgeRun, Inc.
- *   Author: RidgeRun, Inc.
- *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
- *
- *   Copyright 2001 MontaVista Software Inc.
- *   Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- *   Copyright (C) 2000, 01, 06 Ralf Baechle (ralf@linux-mips.org)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/signal.h>
-#include <linux/types.h>
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-#include <asm/time.h>
-
-asmlinkage void plat_irq_dispatch(void)
-{
-	unsigned int pending = read_c0_cause() & read_c0_status();
-
-	if (pending & STATUSF_IP0)
-		do_IRQ(0);
-	else if (pending & STATUSF_IP1)
-		do_IRQ(1);
-	else if (pending & STATUSF_IP2)
-		do_IRQ(2);
-	else if (pending & STATUSF_IP3)
-		do_IRQ(3);
-	else if (pending & STATUSF_IP4)
-		do_IRQ(4);
-	else if (pending & STATUSF_IP5)
-		do_IRQ(5);
-	else if (pending & STATUSF_IP6)
-		do_IRQ(6);
-	else if (pending & STATUSF_IP7)
-		ll_timer_interrupt(7);
-	else {
-		/*
-		 * Now look at the extended interrupts
-		 */
-		pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
-		if (pending & STATUSF_IP8)
-			ll_mv64340_irq();
-	}
-}
-
-static struct irqaction cascade_mv64340 = {
-	no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
-};
-
-void __init arch_init_irq(void)
-{
-	/*
-	 * Clear all of the interrupts while we change the able around a bit.
-	 * int-handler is not on bootstrap
-	 */
-	clear_c0_status(ST0_IM);
-
-	mips_cpu_irq_init();
-	rm7k_cpu_irq_init();
-
-	/* set up the cascading interrupts */
-	setup_irq(8, &cascade_mv64340);
-
-	mv64340_irq_init(16);
-
-	set_c0_status(ST0_IM);
-}
diff --git a/arch/mips/momentum/jaguar_atx/ja-console.c b/arch/mips/momentum/jaguar_atx/ja-console.c
deleted file mode 100644
index 2c30b4f56245..000000000000
--- a/arch/mips/momentum/jaguar_atx/ja-console.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001, 2002, 2004 Ralf Baechle
- */
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/kdev_t.h>
-#include <linux/major.h>
-#include <linux/termios.h>
-#include <linux/sched.h>
-#include <linux/tty.h>
-
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <asm/serial.h>
-
-/* SUPERIO uart register map */
-struct ja_uartregs {
-	union {
-		volatile u8	pad0[3];
-		volatile u8	rbr;	/* read only, DLAB == 0 */
-		volatile u8	pad1[3];
-		volatile u8	thr;	/* write only, DLAB == 0 */
-		volatile u8	pad2[3];
-		volatile u8	dll;	/* DLAB == 1 */
-	} u1;
-	union {
-		volatile u8	pad0[3];
-		volatile u8	ier;	/* DLAB == 0 */
-		volatile u8	pad1[3];
-		volatile u8	dlm;	/* DLAB == 1 */
-	} u2;
-	union {
-		volatile u8	pad0[3];
-		volatile u8	iir;	/* read only */
-		volatile u8	pad1[3];
-		volatile u8	fcr;	/* write only */
-	} u3;
-	volatile u8	pad0[3];
-	volatile u8	iu_lcr;
-	volatile u8	pad1[3];
-	volatile u8	iu_mcr;
-	volatile u8	pad2[3];
-	volatile u8	iu_lsr;
-	volatile u8	pad3[3];
-	volatile u8	iu_msr;
-	volatile u8	pad4[3];
-	volatile u8	iu_scr;
-} ja_uregs_t;
-
-#define iu_rbr u1.rbr
-#define iu_thr u1.thr
-#define iu_dll u1.dll
-#define iu_ier u2.ier
-#define iu_dlm u2.dlm
-#define iu_iir u3.iir
-#define iu_fcr u3.fcr
-
-extern unsigned long uart_base;
-
-static inline struct ja_uartregs *console_uart(void)
-{
-	return (struct ja_uartregs *) (uart_base + 0x23UL);
-}
-
-void prom_putchar(char c)
-{
-	struct ja_uartregs *uart = console_uart();
-
-	while ((uart->iu_lsr & 0x20) == 0);
-	uart->iu_thr = c;
-}
-
-static void inline ja_console_probe(void)
-{
-	struct uart_port up;
-
-	/*
-	 * Register to interrupt zero because we share the interrupt with
-	 * the serial driver which we don't properly support yet.
-	 */
-	memset(&up, 0, sizeof(up));
-	up.membase	= (unsigned char *) uart_base + 0x23UL;
-	up.irq		= JAGUAR_ATX_SERIAL1_IRQ;
-	up.uartclk	= JAGUAR_ATX_UART_CLK;
-	up.regshift	= 2;
-	up.iotype	= UPIO_MEM;
-	up.flags	= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-	up.line		= 0;
-
-	if (early_serial_setup(&up))
-		printk(KERN_ERR "Early serial init of port 0 failed\n");
-}
-
-__init void ja_setup_console(void)
-{
-	ja_console_probe();
-}
diff --git a/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h b/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h
deleted file mode 100644
index 022f6974b76e..000000000000
--- a/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Jaguar-ATX Board Register Definitions
- *
- * (C) 2002 Momentum Computer Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __JAGUAR_ATX_FPGA_H__
-#define __JAGUAR_ATX_FPGA_H__
-
-#define JAGUAR_ATX_REG_BOARDREV		0x0
-#define JAGUAR_ATX_REG_FPGA_REV		0x1
-#define JAGUAR_ATX_REG_FPGA_TYPE	0x2
-#define JAGUAR_ATX_REG_RESET_STATUS	0x3
-#define JAGUAR_ATX_REG_BOARD_STATUS	0x4
-#define JAGUAR_ATX_REG_RESERVED1	0x5
-#define JAGUAR_ATX_REG_SET		0x6
-#define JAGUAR_ATX_REG_CLR		0x7
-#define JAGUAR_ATX_REG_EEPROM_MODE	0x9
-#define JAGUAR_ATX_REG_RESERVED2	0xa
-#define JAGUAR_ATX_REG_RESERVED3	0xb
-#define JAGUAR_ATX_REG_RESERVED4	0xc
-#define JAGUAR_ATX_REG_PHY_INTSTAT	0xd
-#define JAGUAR_ATX_REG_RESERVED5	0xe
-#define JAGUAR_ATX_REG_RESERVED6	0xf
-
-#define JAGUAR_ATX_CS0_ADDR		0xfc000000L
-
-extern unsigned long ja_fpga_base;
-
-#define __FPGA_REG_TO_ADDR(reg)						\
-	((void *) ja_fpga_base + JAGUAR_ATX_REG_##reg)
-#define JAGUAR_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
-#define JAGUAR_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
-
-#endif
diff --git a/arch/mips/momentum/jaguar_atx/platform.c b/arch/mips/momentum/jaguar_atx/platform.c
deleted file mode 100644
index 561844878a90..000000000000
--- a/arch/mips/momentum/jaguar_atx/platform.c
+++ /dev/null
@@ -1,208 +0,0 @@
-#include <linux/delay.h>
-#include <linux/if_ether.h>
-#include <linux/ioport.h>
-#include <linux/mv643xx.h>
-#include <linux/platform_device.h>
-
-#include "jaguar_atx_fpga.h"
-
-#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
-
-static struct resource mv643xx_eth_shared_resources[] = {
-	[0] = {
-		.name   = "ethernet shared base",
-		.start  = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
-		.end    = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
-		                       MV643XX_ETH_SHARED_REGS_SIZE - 1,
-		.flags  = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device mv643xx_eth_shared_device = {
-	.name		= MV643XX_ETH_SHARED_NAME,
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(mv643xx_eth_shared_resources),
-	.resource	= mv643xx_eth_shared_resources,
-};
-
-#define MV_SRAM_BASE			0xfe000000UL
-#define MV_SRAM_SIZE			(256 * 1024)
-
-#define MV_SRAM_RXRING_SIZE		(MV_SRAM_SIZE / 4)
-#define MV_SRAM_TXRING_SIZE		(MV_SRAM_SIZE / 4)
-
-#define MV_SRAM_BASE_ETH0		MV_SRAM_BASE
-#define MV_SRAM_BASE_ETH1		(MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
-
-#define MV64x60_IRQ_ETH_0 48
-#define MV64x60_IRQ_ETH_1 49
-#define MV64x60_IRQ_ETH_2 50
-
-static struct resource mv64x60_eth0_resources[] = {
-	[0] = {
-		.name	= "eth0 irq",
-		.start	= MV64x60_IRQ_ETH_0,
-		.end	= MV64x60_IRQ_ETH_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct mv643xx_eth_platform_data eth0_pd = {
-	.port_number	= 0,
-
-	.tx_sram_addr	= MV_SRAM_BASE_ETH0,
-	.tx_sram_size	= MV_SRAM_TXRING_SIZE,
-	.tx_queue_size	= MV_SRAM_TXRING_SIZE / 16,
-
-	.rx_sram_addr	= MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
-	.rx_sram_size	= MV_SRAM_RXRING_SIZE,
-	.rx_queue_size	= MV_SRAM_RXRING_SIZE / 16,
-};
-
-static struct platform_device eth0_device = {
-	.name		= MV643XX_ETH_NAME,
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(mv64x60_eth0_resources),
-	.resource	= mv64x60_eth0_resources,
-	.dev = {
-		.platform_data = &eth0_pd,
-	},
-};
-
-static struct resource mv64x60_eth1_resources[] = {
-	[0] = {
-		.name	= "eth1 irq",
-		.start	= MV64x60_IRQ_ETH_1,
-		.end	= MV64x60_IRQ_ETH_1,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct mv643xx_eth_platform_data eth1_pd = {
-	.port_number	= 1,
-
-	.tx_sram_addr	= MV_SRAM_BASE_ETH1,
-	.tx_sram_size	= MV_SRAM_TXRING_SIZE,
-	.tx_queue_size	= MV_SRAM_TXRING_SIZE / 16,
-
-	.rx_sram_addr	= MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
-	.rx_sram_size	= MV_SRAM_RXRING_SIZE,
-	.rx_queue_size	= MV_SRAM_RXRING_SIZE / 16,
-};
-
-static struct platform_device eth1_device = {
-	.name		= MV643XX_ETH_NAME,
-	.id		= 1,
-	.num_resources	= ARRAY_SIZE(mv64x60_eth1_resources),
-	.resource	= mv64x60_eth1_resources,
-	.dev = {
-		.platform_data = &eth1_pd,
-	},
-};
-
-static struct resource mv64x60_eth2_resources[] = {
-	[0] = {
-		.name	= "eth2 irq",
-		.start	= MV64x60_IRQ_ETH_2,
-		.end	= MV64x60_IRQ_ETH_2,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct mv643xx_eth_platform_data eth2_pd = {
-	.port_number	= 2,
-};
-
-static struct platform_device eth2_device = {
-	.name		= MV643XX_ETH_NAME,
-	.id		= 2,
-	.num_resources	= ARRAY_SIZE(mv64x60_eth2_resources),
-	.resource	= mv64x60_eth2_resources,
-	.dev = {
-		.platform_data = &eth2_pd,
-	},
-};
-
-static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
-	&mv643xx_eth_shared_device,
-	&eth0_device,
-	&eth1_device,
-	&eth2_device,
-};
-
-static u8 __init exchange_bit(u8 val, u8 cs)
-{
-	/* place the data */
-	JAGUAR_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
-	udelay(1);
-
-	/* turn the clock on */
-	JAGUAR_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
-	udelay(1);
-
-	/* turn the clock off and read-strobe */
-	JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
-
-	/* return the data */
-	return (JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
-}
-
-static void __init get_mac(char dest[6])
-{
-	u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-	int i,j;
-
-	for (i = 0; i < 12; i++)
-		exchange_bit(read_opcode[i], 1);
-
-	for (j = 0; j < 6; j++) {
-		dest[j] = 0;
-		for (i = 0; i < 8; i++) {
-			dest[j] <<= 1;
-			dest[j] |= exchange_bit(0, 1);
-		}
-	}
-
-	/* turn off CS */
-	exchange_bit(0,0);
-}
-
-/*
- * Copy and increment ethernet MAC address by a small value.
- *
- * This is useful for systems where the only one MAC address is stored in
- * non-volatile memory for multiple ports.
- */
-static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
-	unsigned int add)
-{
-	int i;
-
-	BUG_ON(add >= 256);
-
-	for (i = ETH_ALEN; i >= 0; i--) {
-		dst[i] = src[i] + add;
-		add = dst[i] < src[i];		/* compute carry */
-	}
-
-	WARN_ON(add);
-}
-
-static int __init mv643xx_eth_add_pds(void)
-{
-	unsigned char mac[ETH_ALEN];
-	int ret;
-
-	get_mac(mac);
-	eth_mac_add(eth0_pd.mac_addr, mac, 0);
-	eth_mac_add(eth1_pd.mac_addr, mac, 1);
-	eth_mac_add(eth2_pd.mac_addr, mac, 2);
-	ret = platform_add_devices(mv643xx_eth_pd_devs,
-			ARRAY_SIZE(mv643xx_eth_pd_devs));
-
-	return ret;
-}
-
-device_initcall(mv643xx_eth_add_pds);
-
-#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c
deleted file mode 100644
index 5dd154ee58f6..000000000000
--- a/arch/mips/momentum/jaguar_atx/prom.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * Copyright 2002 Momentum Computer Inc.
- * Author: Matthew Dharm <mdharm@momenco.com>
- *
- * Louis Hamilton, Red Hat, Inc.
- * hamilton@redhat.com  [MIPS64 modifications]
- *
- * Based on Ocelot Linux port, which is
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * Added changes for SMP - Manish Lachwani (lachwani@pmc-sierra.com)
- */
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/bootmem.h>
-#include <linux/mv643xx.h>
-
-#include <asm/addrspace.h>
-#include <asm/bootinfo.h>
-#include <asm/pmon.h>
-
-#include "jaguar_atx_fpga.h"
-
-extern void ja_setup_console(void);
-
-struct callvectors *debug_vectors;
-
-extern unsigned long cpu_clock;
-
-const char *get_system_type(void)
-{
-	return "Momentum Jaguar-ATX";
-}
-
-#ifdef CONFIG_64BIT
-
-unsigned long signext(unsigned long addr)
-{
-	addr &= 0xffffffff;
-	return (unsigned long)((int)addr);
-}
-
-void *get_arg(unsigned long args, int arc)
-{
-	unsigned long ul;
-	unsigned char *puc, uc;
-
-	args += (arc * 4);
-	ul = (unsigned long)signext(args);
-	puc = (unsigned char *)ul;
-	if (puc == 0)
-		return (void *)0;
-
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-	uc = *puc++;
-	l = (unsigned long)uc;
-	uc = *puc++;
-	ul |= (((unsigned long)uc) << 8);
-	uc = *puc++;
-	ul |= (((unsigned long)uc) << 16);
-	uc = *puc++;
-	ul |= (((unsigned long)uc) << 24);
-#else
-	uc = *puc++;
-	ul = ((unsigned long)uc) << 24;
-	uc = *puc++;
-	ul |= (((unsigned long)uc) << 16);
-	uc = *puc++;
-	ul |= (((unsigned long)uc) << 8);
-	uc = *puc++;
-	ul |= ((unsigned long)uc);
-#endif
-	ul = signext(ul);
-
-	return (void *)ul;
-}
-
-char *arg64(unsigned long addrin, int arg_index)
-{
-	unsigned long args;
-	char *p;
-
-	args = signext(addrin);
-	p = (char *)get_arg(args, arg_index);
-
-	return p;
-}
-#endif  /* CONFIG_64BIT */
-
-/* PMON passes arguments in C main() style */
-void __init prom_init(void)
-{
-	int argc = fw_arg0;
-	char **arg = (char **) fw_arg1;
-	char **env = (char **) fw_arg2;
-	struct callvectors *cv = (struct callvectors *) fw_arg3;
-	int i;
-
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-//	ja_setup_console();	/* The very first thing.  */
-#endif
-
-#ifdef CONFIG_64BIT
-	char *ptr;
-
-	printk("Mips64 Jaguar-ATX\n");
-	/* save the PROM vectors for debugging use */
-	debug_vectors = (struct callvectors *)signext((unsigned long)cv);
-
-	/* arg[0] is "g", the rest is boot parameters */
-	arcs_cmdline[0] = '\0';
-
-	for (i = 1; i < argc; i++) {
-		ptr = (char *)arg64((unsigned long)arg, i);
-		if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
-		    sizeof(arcs_cmdline))
-			break;
-		strcat(arcs_cmdline, ptr);
-		strcat(arcs_cmdline, " ");
-	}
-
-	i = 0;
-	while (1) {
-		ptr = (char *)arg64((unsigned long)env, i);
-		if (! ptr)
-			break;
-
-		if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
-			marvell_base = simple_strtol(ptr + strlen("gtbase="),
-							NULL, 16);
-
-			if ((marvell_base & 0xffffffff00000000) == 0)
-				marvell_base |= 0xffffffff00000000;
-
-			printk("marvell_base set to 0x%016lx\n", marvell_base);
-		}
-		if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
-			cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
-							NULL, 10);
-			printk("cpu_clock set to %d\n", cpu_clock);
-		}
-		i++;
-	}
-	printk("arcs_cmdline: %s\n", arcs_cmdline);
-
-#else   /* CONFIG_64BIT */
-	/* save the PROM vectors for debugging use */
-	debug_vectors = cv;
-
-	/* arg[0] is "g", the rest is boot parameters */
-	arcs_cmdline[0] = '\0';
-	for (i = 1; i < argc; i++) {
-		if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
-		    >= sizeof(arcs_cmdline))
-			break;
-		strcat(arcs_cmdline, arg[i]);
-		strcat(arcs_cmdline, " ");
-	}
-
-	while (*env) {
-		if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
-			marvell_base = simple_strtol(*env + strlen("gtbase="),
-							NULL, 16);
-		}
-		if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
-			cpu_clock = simple_strtol(*env + strlen("cpuclock="),
-							NULL, 10);
-		}
-		env++;
-	}
-#endif /* CONFIG_64BIT */
-	mips_machgroup = MACH_GROUP_MOMENCO;
-	mips_machtype = MACH_MOMENCO_JAGUAR_ATX;
-}
-
-void __init prom_free_prom_memory(void)
-{
-}
-
-void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
-{
-}
-
-int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp)
-{
-	/* Clear the semaphore */
-	*(volatile uint32_t *)(0xbb000a68) = 0x80000000;
-
-	return 1;
-}
-
-void prom_init_secondary(void)
-{
-        clear_c0_config(CONF_CM_CMASK);
-        set_c0_config(0x2);
-
-	clear_c0_status(ST0_IM);
-	set_c0_status(0x1ffff);
-}
-
-void prom_smp_finish(void)
-{
-}
diff --git a/arch/mips/momentum/jaguar_atx/reset.c b/arch/mips/momentum/jaguar_atx/reset.c
deleted file mode 100644
index c73b0897dc52..000000000000
--- a/arch/mips/momentum/jaguar_atx/reset.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * Copyright (C) 1997, 2001 Ralf Baechle
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * Copyright (C) 2002 Momentum Computer Inc.
- * Author: Matthew Dharm <mdharm@momenco.com>
- *
- * Louis Hamilton, Red Hat, Inc.
- * hamilton@redhat.com  [MIPS64 modifications]
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/system.h>
-#include <linux/delay.h>
-
-void momenco_jaguar_restart(char *command)
-{
-	/* base address of timekeeper portion of part */
-#ifdef CONFIG_64BIT
-	void *nvram = (void*) 0xfffffffffc807000;
-#else
-	void *nvram = (void*) 0xfc807000;
-#endif
-	/* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
-	writeb(0x84, nvram + 0xff7);
-
-	/* wait for the watchdog to go off */
-	mdelay(100+(1000/16));
-
-	/* if the watchdog fails for some reason, let people know */
-	printk(KERN_NOTICE "Watchdog reset failed\n");
-}
-
-void momenco_jaguar_halt(void)
-{
-	printk(KERN_NOTICE "\n** You can safely turn off the power\n");
-	while (1)
-		__asm__(".set\tmips3\n\t"
-	                "wait\n\t"
-			".set\tmips0");
-}
-
-void momenco_jaguar_power_off(void)
-{
-	momenco_jaguar_halt();
-}
diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c
deleted file mode 100644
index 5a510142b978..000000000000
--- a/arch/mips/momentum/jaguar_atx/setup.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- * Momentum Computer Jaguar-ATX board dependent boot routines
- *
- * Copyright (C) 1996, 1997, 2001, 04, 06  Ralf Baechle (ralf@linux-mips.org)
- * Copyright (C) 2000 RidgeRun, Inc.
- * Copyright (C) 2001 Red Hat, Inc.
- * Copyright (C) 2002 Momentum Computer
- *
- * Author: Matthew Dharm, Momentum Computer
- *   mdharm@momenco.com
- *
- * Louis Hamilton, Red Hat, Inc.
- *   hamilton@redhat.com  [MIPS64 modifications]
- *
- * Author: RidgeRun, Inc.
- *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/bcd.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/swap.h>
-#include <linux/ioport.h>
-#include <linux/pm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/timex.h>
-#include <linux/vmalloc.h>
-#include <linux/mv643xx.h>
-
-#include <asm/time.h>
-#include <asm/bootinfo.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/tlbflush.h>
-
-#include "jaguar_atx_fpga.h"
-
-extern unsigned long mv64340_sram_base;
-unsigned long cpu_clock;
-
-/* These functions are used for rebooting or halting the machine*/
-extern void momenco_jaguar_restart(char *command);
-extern void momenco_jaguar_halt(void);
-extern void momenco_jaguar_power_off(void);
-
-void momenco_time_init(void);
-
-static char reset_reason;
-
-static inline unsigned long ENTRYLO(unsigned long paddr)
-{
-	return ((paddr & PAGE_MASK) |
-	       (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
-		_CACHE_UNCACHED)) >> 6;
-}
-
-void __init bus_error_init(void) { /* nothing */ }
-
-/*
- * Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going
- * to be hit on every IRQ anyway - there's absolutely no point in letting it be
- * a random TLB entry, as it'll just cause needless churning of the TLB. And we
- * use the other half for the serial port, which is just a PITA otherwise :)
- *
- *	Device			Physical	Virtual
- *	MV64340 Internal Regs	0xf4000000	0xf4000000
- *	Ocelot-C[S] PLD (CS0)	0xfc000000	0xfc000000
- *	NVRAM (CS1)		0xfc800000	0xfc800000
- *	UARTs (CS2)		0xfd000000	0xfd000000
- *	Internal SRAM		0xfe000000	0xfe000000
- *	M-Systems DOC (CS3)	0xff000000	0xff000000
- */
-
-static __init void wire_stupidity_into_tlb(void)
-{
-#ifdef CONFIG_32BIT
-	write_c0_wired(0);
-	local_flush_tlb_all();
-
-	/* marvell and extra space */
-	add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
-	                0xf4000000UL, PM_64K);
-	/* fpga, rtc, and uart */
-	add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000),
-	                0xfc000000UL, PM_16M);
-//	/* m-sys and internal SRAM */
-//	add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
-//	                0xfe000000UL, PM_16M);
-
-	marvell_base = 0xf4000000;
-	//mv64340_sram_base = 0xfe000000;	/* Currently unused */
-#endif
-}
-
-unsigned long marvell_base	= 0xf4000000L;
-unsigned long ja_fpga_base	= JAGUAR_ATX_CS0_ADDR;
-unsigned long uart_base		= 0xfd000000L;
-static unsigned char *rtc_base	= (unsigned char*) 0xfc800000L;
-
-EXPORT_SYMBOL(marvell_base);
-
-static __init int per_cpu_mappings(void)
-{
-	marvell_base	= (unsigned long) ioremap(0xf4000000, 0x10000);
-	ja_fpga_base	= (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR,  0x1000);
-	uart_base	= (unsigned long) ioremap(0xfd000000UL, 0x1000);
-	rtc_base	= ioremap(0xfc000000UL, 0x8000);
-	// ioremap(0xfe000000,  32 << 20);
-	write_c0_wired(0);
-	local_flush_tlb_all();
-	ja_setup_console();
-
-	return 0;
-}
-arch_initcall(per_cpu_mappings);
-
-unsigned long m48t37y_get_time(void)
-{
-	unsigned int year, month, day, hour, min, sec;
-	unsigned long flags;
-
-	spin_lock_irqsave(&rtc_lock, flags);
-	/* stop the update */
-	rtc_base[0x7ff8] = 0x40;
-
-	year = BCD2BIN(rtc_base[0x7fff]);
-	year += BCD2BIN(rtc_base[0x7ff1]) * 100;
-
-	month = BCD2BIN(rtc_base[0x7ffe]);
-
-	day = BCD2BIN(rtc_base[0x7ffd]);
-
-	hour = BCD2BIN(rtc_base[0x7ffb]);
-	min = BCD2BIN(rtc_base[0x7ffa]);
-	sec = BCD2BIN(rtc_base[0x7ff9]);
-
-	/* start the update */
-	rtc_base[0x7ff8] = 0x00;
-	spin_unlock_irqrestore(&rtc_lock, flags);
-
-	return mktime(year, month, day, hour, min, sec);
-}
-
-int m48t37y_set_time(unsigned long sec)
-{
-	struct rtc_time tm;
-	unsigned long flags;
-
-	/* convert to a more useful format -- note months count from 0 */
-	to_tm(sec, &tm);
-	tm.tm_mon += 1;
-
-	spin_lock_irqsave(&rtc_lock, flags);
-	/* enable writing */
-	rtc_base[0x7ff8] = 0x80;
-
-	/* year */
-	rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
-	rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
-
-	/* month */
-	rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
-
-	/* day */
-	rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
-
-	/* hour/min/sec */
-	rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
-	rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
-	rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
-
-	/* day of week -- not really used, but let's keep it up-to-date */
-	rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
-
-	/* disable writing */
-	rtc_base[0x7ff8] = 0x00;
-	spin_unlock_irqrestore(&rtc_lock, flags);
-
-	return 0;
-}
-
-void __init plat_timer_setup(struct irqaction *irq)
-{
-	setup_irq(8, irq);
-}
-
-/*
- * Ugly but the least of all evils.  TLB initialization did flush the TLB so
- * We need to setup mappings again before we can touch the RTC.
- */
-void momenco_time_init(void)
-{
-	wire_stupidity_into_tlb();
-
-	mips_hpt_frequency = cpu_clock / 2;
-
-	rtc_mips_get_time = m48t37y_get_time;
-	rtc_mips_set_time = m48t37y_set_time;
-}
-
-static struct resource mv_pci_io_mem0_resource = {
-	.name	= "MV64340 PCI0 IO MEM",
-	.flags	= IORESOURCE_IO
-};
-
-static struct resource mv_pci_mem0_resource = {
-	.name	= "MV64340 PCI0 MEM",
-	.flags	= IORESOURCE_MEM
-};
-
-static struct mv_pci_controller mv_bus0_controller = {
-	.pcic = {
-		.pci_ops	= &mv_pci_ops,
-		.mem_resource	= &mv_pci_mem0_resource,
-		.io_resource	= &mv_pci_io_mem0_resource,
-	},
-	.config_addr	= MV64340_PCI_0_CONFIG_ADDR,
-	.config_vreg	= MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
-};
-
-static uint32_t mv_io_base, mv_io_size;
-
-static void ja_pci0_init(void)
-{
-	uint32_t mem0_base, mem0_size;
-	uint32_t io_base, io_size;
-
-	io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
-	io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
-	mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
-	mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
-
-	mv_pci_io_mem0_resource.start		= 0;
-	mv_pci_io_mem0_resource.end		= io_size - 1;
-	mv_pci_mem0_resource.start		= mem0_base;
-	mv_pci_mem0_resource.end		= mem0_base + mem0_size - 1;
-	mv_bus0_controller.pcic.mem_offset	= mem0_base;
-	mv_bus0_controller.pcic.io_offset	= 0;
-
-	ioport_resource.end		= io_size - 1;
-
-	register_pci_controller(&mv_bus0_controller.pcic);
-
-	mv_io_base = io_base;
-	mv_io_size = io_size;
-}
-
-static struct resource mv_pci_io_mem1_resource = {
-	.name	= "MV64340 PCI1 IO MEM",
-	.flags	= IORESOURCE_IO
-};
-
-static struct resource mv_pci_mem1_resource = {
-	.name	= "MV64340 PCI1 MEM",
-	.flags	= IORESOURCE_MEM
-};
-
-static struct mv_pci_controller mv_bus1_controller = {
-	.pcic = {
-		.pci_ops	= &mv_pci_ops,
-		.mem_resource	= &mv_pci_mem1_resource,
-		.io_resource	= &mv_pci_io_mem1_resource,
-	},
-	.config_addr	= MV64340_PCI_1_CONFIG_ADDR,
-	.config_vreg	= MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
-};
-
-static __init void ja_pci1_init(void)
-{
-	uint32_t mem0_base, mem0_size;
-	uint32_t io_base, io_size;
-
-	io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
-	io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
-	mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
-	mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
-
-	/*
-	 * Here we assume the I/O window of second bus to be contiguous with
-	 * the first.  A gap is no problem but would waste address space for
-	 * remapping the port space.
-	 */
-	mv_pci_io_mem1_resource.start		= mv_io_size;
-	mv_pci_io_mem1_resource.end		= mv_io_size + io_size - 1;
-	mv_pci_mem1_resource.start		= mem0_base;
-	mv_pci_mem1_resource.end		= mem0_base + mem0_size - 1;
-	mv_bus1_controller.pcic.mem_offset	= mem0_base;
-	mv_bus1_controller.pcic.io_offset	= 0;
-
-	ioport_resource.end		= io_base + io_size -mv_io_base - 1;
-
-	register_pci_controller(&mv_bus1_controller.pcic);
-
-	mv_io_size = io_base + io_size - mv_io_base;
-}
-
-static __init int __init ja_pci_init(void)
-{
-	unsigned long io_v_base;
-	uint32_t enable;
-
-	enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
-
-	/*
-	 * We require at least one enabled I/O or PCI memory window or we
-	 * will ignore this PCI bus.  We ignore PCI windows 1, 2 and 3.
-	 */
-	if (enable & (0x01 <<  9) || enable & (0x01 << 10))
-		ja_pci0_init();
-
-	if (enable & (0x01 << 14) || enable & (0x01 << 15))
-		ja_pci1_init();
-
-	if (mv_io_size) {
-		io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
-		if (!io_v_base)
-			panic("Could not ioremap I/O port range");
-
-		set_io_port_base(io_v_base);
-	}
-
-	return 0;
-}
-
-arch_initcall(ja_pci_init);
-
-void __init plat_mem_setup(void)
-{
-	unsigned int tmpword;
-
-	board_time_init = momenco_time_init;
-
-	_machine_restart = momenco_jaguar_restart;
-	_machine_halt = momenco_jaguar_halt;
-	pm_power_off = momenco_jaguar_power_off;
-
-	/*
-	 * initrd_start = (unsigned long)jaguar_initrd_start;
-	 * initrd_end = (unsigned long)jaguar_initrd_start + (ulong)jaguar_initrd_size;
-	 * initrd_below_start_ok = 1;
-	 */
-
-	wire_stupidity_into_tlb();
-
-	/*
-	 * shut down ethernet ports, just to be sure our memory doesn't get
-	 * corrupted by random ethernet traffic.
-	 */
-	MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
-	MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
-	MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
-	MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
-	MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
-	MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
-	while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
-	while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
-	while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
-	while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
-	while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
-	while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
-	MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
-	         MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
-	MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
-	         MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
-	MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2),
-	         MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
-
-	/* Turn off the Bit-Error LED */
-	JAGUAR_FPGA_WRITE(0x80, CLR);
-
-	tmpword = JAGUAR_FPGA_READ(BOARDREV);
-	if (tmpword < 26)
-		printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
-			'A'+tmpword);
-	else
-		printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
-			tmpword);
-
-	tmpword = JAGUAR_FPGA_READ(FPGA_REV);
-	printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
-	tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
-	printk("Reset reason: 0x%x\n", tmpword);
-	switch (tmpword) {
-	case 0x1:
-		printk("  - Power-up reset\n");
-		break;
-	case 0x2:
-		printk("  - Push-button reset\n");
-		break;
-	case 0x8:
-		printk("  - Watchdog reset\n");
-		break;
-	case 0x10:
-		printk("  - JTAG reset\n");
-		break;
-	default:
-		printk("  - Unknown reset cause\n");
-	}
-	reset_reason = tmpword;
-	JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
-
-	tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
-	printk("Board Status register: 0x%02x\n", tmpword);
-	printk("  - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
-	printk("  - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
-
-	/* 256MiB of RM9000x2 DDR */
-//	add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
-
-	/* 128MiB of MV-64340 DDR */
-//	add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
-
-	/* XXX Memory configuration should be picked up from PMON2k */
-#ifdef CONFIG_JAGUAR_DMALOW
-	printk("Jaguar ATX DMA-low mode set\n");
-	add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
-	add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
-#else
-	/* 128MiB of MV-64340 DDR RAM */
-	printk("Jaguar ATX DMA-low mode is not set\n");
-	add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
-#endif
-
-#ifdef GEMDEBUG_TRACEBUFFER
-	{
-	  unsigned int tbControl;
-	  tbControl =
-	    0 << 26 |  /* post trigger delay 0 */
-		    0x2 << 16 |		/* sequential trace mode */
-	    //	    0x0 << 16 |		/* non-sequential trace mode */
-	    //	    0xf << 4 |		/* watchpoints disabled */
-	    2 << 2 |		/* armed */
-	    2 ;			/* interrupt disabled  */
-	  printk ("setting     tbControl = %08lx\n", tbControl);
-	  write_32bit_cp0_set1_register($22, tbControl);
-	  __asm__ __volatile__(".set noreorder\n\t" \
-			       "nop; nop; nop; nop; nop; nop;\n\t" \
-			       "nop; nop; nop; nop; nop; nop;\n\t" \
-			       ".set reorder\n\t");
-
-	}
-#endif
-}