diff options
| author | Jon Medhurst <tixy@linaro.org> | 2013-07-17 12:01:50 +0100 |
|---|---|---|
| committer | Jon Medhurst <tixy@linaro.org> | 2013-07-17 12:01:50 +0100 |
| commit | 95106c3b6742a45828bd675ca55e3e378d6d3071 (patch) | |
| tree | b61b339f9a407443bce35d3685320c812ba6c239 /arch/arm | |
| parent | fcd1e5ad6653a951c1b0e945197bcf79a51e1e65 (diff) | |
| parent | 4311d5a4b599317bc321b1d8b9c0d1f4e49e7df5 (diff) | |
Merge branch 'tracking-armlt-cci' into lsk-3.10-vexpress
Conflicts:
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 36 |
1 files changed, 35 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index f51f21a66352..eea14dad3816 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -84,6 +84,7 @@ cluster = <&cluster1>; core = <&core2>; clock-frequency = <800000000>; + cci-control-port = <&cci_control2>; }; cpu3: cpu@3 { @@ -93,6 +94,7 @@ cluster = <&cluster1>; core = <&core3>; clock-frequency = <800000000>; + cci-control-port = <&cci_control2>; }; cpu4: cpu@4 { @@ -102,6 +104,7 @@ cluster = <&cluster1>; core = <&core4>; clock-frequency = <800000000>; + cci-control-port = <&cci_control2>; }; cpu0: cpu@0 { @@ -111,6 +114,7 @@ cluster = <&cluster0>; core = <&core0>; clock-frequency = <1000000000>; + cci-control-port = <&cci_control1>; }; cpu1: cpu@1 { @@ -120,8 +124,8 @@ cluster = <&cluster0>; core = <&core1>; clock-frequency = <1000000000>; + cci-control-port = <&cci_control1>; }; - }; memory@80000000 { @@ -194,6 +198,36 @@ }; }; + cci@2c090000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x2c090000 0 0x1000>; + ranges = <0x0 0x0 0x2c090000 0x10000>; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + }; + + cci-pmu@2c099000 { + compatible = "arm,cci-400-pmu"; + reg = <0 0x2c099000 0 0x6000>; + interrupts = <0 101 4>, + <0 102 4>, + <0 103 4>, + <0 104 4>, + <0 105 4>; + }; + memory-controller@7ffd0000 { compatible = "arm,pl354", "arm,primecell"; reg = <0 0x7ffd0000 0 0x1000>; |