Merge tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull late ARM soc platform updates from Olof Johansson:
 "This branch contains updates to OMAP and Marvell platforms (kirkwood,
  dove, mvebu) that came in after we had done the big multiplatform
  merges, so they were kept separate from the rest, and not separated
  into the traditional topics of cleanup/driver/platform features.

  For OMAP, the updates are:
   - Runtime PM conversions for the GPMC and RNG IP blocks
   - Preparation patches for the OMAP common clock framework conversion
   - clkdev alias additions required by other drivers
   - Performance Monitoring Unit (PMU) support for OMAP2, 3, and
     non-4430 OMAP4
   - OMAP hwmod code and data improvements
   - Preparation patches for the IOMMU runtime PM conversion
   - Preparation patches for OMAP4 full-chip retention support

  For Kirkwood/Dove/mvebu:
   - New driver for "address decoder controller" for mvebu, which is a
     piece of hardware that configures addressable devices and
     peripherals.  First user is the boot rom aperture on armada XP
     since it is needed for SMP support.
   - New device tree bindings for peripherals such as gpio-fan, iconnect
     nand, mv_cesa and the above address decoder controller.
   - Some defconfig updates, mostly to enable new DT boards and a few
     drivers.
   - New drivers using the pincontrol subsystem for dove, kirkwood and
     mvebu
   - New clean gpio driver for mvebu"

* tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (98 commits)
  ARM: mvebu: fix build breaks from multi-platform conversion
  ARM: OMAP4460/4470: PMU: Enable PMU for OMAP4460/70
  ARM: OMAP2+: PMU: Add runtime PM support
  ARM: OMAP4430: PMU: prepare to create PMU device via HWMOD
  ARM: OMAP2+: PMU: Convert OMAP2/3 devices to use HWMOD
  ARM: OMAP3: hwmod data: Add debugss HWMOD data
  ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU clockdomain idle problems
  ARM: OMAP: Add a timer attribute for timers that can interrupt the DSP
  hwrng: OMAP: remove SoC restrictions from driver registration
  ARM: OMAP: split OMAP1, OMAP2+ RNG device registration
  hwrng: OMAP: convert to use runtime PM
  hwrng: OMAP: store per-device data in per-device variables, not file statics
  ARM: OMAP2xxx: hwmod/CM: add RNG integration data
  ARM: OMAP2+: gpmc: minimal driver support
  ARM: OMAP2+: gpmc: Adapt to HWMOD
  ARM: OMAP2/3: hwmod data: add gpmc
  ARM: OMAP4: hwmod data: add mmu hwmod for ipu and dsp
  ARM: OMAP3: hwmod data: add mmu data for iva and isp
  ARM: OMAP: iommu: fix including iommu.h without IOMMU_API selected
  ARM: OMAP4: hwmod data: add missing HWMOD_NO_IDLEST flags to some PRCM IP blocks
  ...

9 files changed, 31 insertions, 34 deletions

diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index c20ce0f5ce33..a82cecb84948 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -1,10 +1,10 @@
 #
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 
-obj-y	:= irq.o pcie.o time.o common.o mpp.o addr-map.o
-obj-m	:=
-obj-n	:=
-obj-	:=
+obj-y                             += addr-map.o
 
-obj-$(CONFIG_GENERIC_GPIO) += gpio.o
+orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += $(orion-gpio-y)
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
index 367ca89ac403..a7b8060c293a 100644
--- a/arch/arm/plat-orion/addr-map.c
+++ b/arch/arm/plat-orion/addr-map.c
@@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
 static void __init __iomem *
 orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
 {
-	return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
+	return cfg->bridge_virt_base + (win << 4);
 }
 
 /*
@@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
  * Setup MBUS dram target info.
  */
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-					const u32 ddr_window_cpu_base)
+					const void __iomem *ddr_window_cpu_base)
 {
-	void __iomem *addr;
 	int i;
 	int cs;
 
 	orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 
-	addr = (void __iomem *)ddr_window_cpu_base;
-
 	for (i = 0, cs = 0; i < 4; i++) {
-		u32 base = readl(addr + DDR_BASE_CS_OFF(i));
-		u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
+		u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
+		u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
 
 		/*
 		 * Chip select enabled?
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 87f53caef655..b8a688cad4c2 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -86,13 +86,13 @@ static void __init uart_complete(
 	struct platform_device *orion_uart,
 	struct plat_serial8250_port *data,
 	struct resource *resources,
-	unsigned int membase,
+	void __iomem *membase,
 	resource_size_t mapbase,
 	unsigned int irq,
 	struct clk *clk)
 {
 	data->mapbase = mapbase;
-	data->membase = (void __iomem *)membase;
+	data->membase = membase;
 	data->irq = irq;
 	data->uartclk = uart_get_clk_rate(clk);
 	orion_uart->dev.platform_data = data;
@@ -120,7 +120,7 @@ static struct platform_device orion_uart0 = {
 	.id			= PLAT8250_DEV_PLATFORM,
 };
 
-void __init orion_uart0_init(unsigned int membase,
+void __init orion_uart0_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk)
@@ -148,7 +148,7 @@ static struct platform_device orion_uart1 = {
 	.id			= PLAT8250_DEV_PLATFORM1,
 };
 
-void __init orion_uart1_init(unsigned int membase,
+void __init orion_uart1_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk)
@@ -176,7 +176,7 @@ static struct platform_device orion_uart2 = {
 	.id			= PLAT8250_DEV_PLATFORM2,
 };
 
-void __init orion_uart2_init(unsigned int membase,
+void __init orion_uart2_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk)
@@ -204,7 +204,7 @@ static struct platform_device orion_uart3 = {
 	.id			= 3,
 };
 
-void __init orion_uart3_init(unsigned int membase,
+void __init orion_uart3_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk)
diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
index fd556f77562c..ec63e4a627d0 100644
--- a/arch/arm/plat-orion/include/plat/addr-map.h
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
 struct orion_addr_map_cfg {
 	const int num_wins;	/* Total number of windows */
 	const int remappable_wins;
-	const u32 bridge_virt_base;
+	void __iomem *bridge_virt_base;
 
 	/* If NULL, the default cpu_win_can_remap will be used, using
 	   the value in remappable_wins */
@@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
 				const u8 attr, const int remap);
 
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-					const u32 ddr_window_cpu_base);
+					const void __iomem *ddr_window_cpu_base);
 #endif
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index ae2377ef63e5..6bbc3fe5f58e 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -13,22 +13,22 @@
 
 struct dsa_platform_data;
 
-void __init orion_uart0_init(unsigned int membase,
+void __init orion_uart0_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk);
 
-void __init orion_uart1_init(unsigned int membase,
+void __init orion_uart1_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk);
 
-void __init orion_uart2_init(unsigned int membase,
+void __init orion_uart2_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk);
 
-void __init orion_uart3_init(unsigned int membase,
+void __init orion_uart3_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk);
diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h
index 723adce99f41..254552fee889 100644
--- a/arch/arm/plat-orion/include/plat/mpp.h
+++ b/arch/arm/plat-orion/include/plat/mpp.h
@@ -29,6 +29,6 @@
 #define MPP_OUTPUT_MASK		GENERIC_MPP(0, 0x0, 0, 1)
 
 void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
-			   unsigned int mpp_max, unsigned int dev_bus);
+			   unsigned int mpp_max, void __iomem *dev_bus);
 
 #endif
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
index 4d5f1f6e18df..07527e417c62 100644
--- a/arch/arm/plat-orion/include/plat/time.h
+++ b/arch/arm/plat-orion/include/plat/time.h
@@ -11,9 +11,9 @@
 #ifndef __PLAT_TIME_H
 #define __PLAT_TIME_H
 
-void orion_time_set_base(u32 timer_base);
+void orion_time_set_base(void __iomem *timer_base);
 
-void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
+void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,
 		     unsigned int irq, unsigned int tclk);
 
 
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
index 7740bb31d662..e686fe76a96b 100644
--- a/arch/arm/plat-orion/mpp.c
+++ b/arch/arm/plat-orion/mpp.c
@@ -18,15 +18,15 @@
 #include <plat/mpp.h>
 
 /* Address of the ith MPP control register */
-static __init unsigned long mpp_ctrl_addr(unsigned int i,
-					  unsigned long dev_bus)
+static __init void __iomem *mpp_ctrl_addr(unsigned int i,
+					  void __iomem *dev_bus)
 {
 	return dev_bus + (i) * 4;
 }
 
 
 void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
-			   unsigned int mpp_max, unsigned int dev_bus)
+			   unsigned int mpp_max, void __iomem *dev_bus)
 {
 	unsigned int mpp_nr_regs = (1 + mpp_max/8);
 	u32 mpp_ctrl[mpp_nr_regs];
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 1ed8d1397fcf..0f4fa863dd55 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -180,13 +180,13 @@ static struct irqaction orion_timer_irq = {
 };
 
 void __init
-orion_time_set_base(u32 _timer_base)
+orion_time_set_base(void __iomem *_timer_base)
 {
-	timer_base = (void __iomem *)_timer_base;
+	timer_base = _timer_base;
 }
 
 void __init
-orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
+orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
 		unsigned int irq, unsigned int tclk)
 {
 	u32 u;
@@ -194,7 +194,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
 	/*
 	 * Set SoC-specific data.
 	 */
-	bridge_base = (void __iomem *)_bridge_base;
+	bridge_base = _bridge_base;
 	bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
 
 	ticks_per_jiffy = (tclk + HZ/2) / HZ;