diff options
| author | Jon Medhurst <tixy@linaro.org> | 2013-05-14 15:22:02 +0100 |
|---|---|---|
| committer | Jon Medhurst <tixy@linaro.org> | 2013-07-01 11:04:15 +0100 |
| commit | d2cab175b788011e535f4d5184560b61012e51e1 (patch) | |
| tree | 4f9e6c6c41207f66a76f3c3c31995f7c3f9477f5 /arch/arm/boot/dts | |
| parent | e63a47a858f5404b5d7f1dc73dab8c78115e9c04 (diff) | |
rtsm: fixup for new CCI driver
We include the compatible string "arm,cci" because the semihosting
bootwrapper searches for this to initialise the CCI before boot.
The boot-wrapper will need updating for the new CCI device-tree
bindings when they are stable, then we can remove this old compatible
string from the RTSM device-trees.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts | 21 | ||||
| -rw-r--r-- | arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts | 27 |
2 files changed, 44 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts b/arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts index 55d4f5ce019e..fe8cf5dc8570 100644 --- a/arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts +++ b/arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts @@ -72,6 +72,7 @@ cluster = <&cluster0>; core = <&core0>; // clock-frequency = <1000000000>; + cci-control-port = <&cci_control1>; }; cpu1: cpu@1 { @@ -81,6 +82,7 @@ cluster = <&cluster1>; core = <&core1>; // clock-frequency = <800000000>; + cci-control-port = <&cci_control2>; }; }; @@ -90,8 +92,23 @@ }; cci@2c090000 { - compatible = "arm,cci"; - reg = <0 0x2c090000 0 0x8000>; + compatible = "arm,cci-400", "arm,cci"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x2c090000 0 0x1000>; + ranges = <0x0 0x0 0x2c090000 0x10000>; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; }; dcscb@60000000 { diff --git a/arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts b/arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts index a2d4441568a0..f715285131d8 100644 --- a/arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts +++ b/arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts @@ -96,6 +96,7 @@ cluster = <&cluster0>; core = <&core0>; // clock-frequency = <1000000000>; + cci-control-port = <&cci_control1>; }; cpu1: cpu@1 { @@ -105,6 +106,7 @@ cluster = <&cluster0>; core = <&core1>; // clock-frequency = <1000000000>; + cci-control-port = <&cci_control1>; }; cpu2: cpu@2 { @@ -114,6 +116,7 @@ cluster = <&cluster0>; core = <&core2>; // clock-frequency = <1000000000>; + cci-control-port = <&cci_control1>; }; cpu3: cpu@3 { @@ -123,6 +126,7 @@ cluster = <&cluster0>; core = <&core3>; // clock-frequency = <1000000000>; + cci-control-port = <&cci_control1>; }; cpu4: cpu@4 { @@ -132,6 +136,7 @@ cluster = <&cluster1>; core = <&core4>; // clock-frequency = <800000000>; + cci-control-port = <&cci_control2>; }; cpu5: cpu@5 { @@ -141,6 +146,7 @@ cluster = <&cluster1>; core = <&core5>; // clock-frequency = <800000000>; + cci-control-port = <&cci_control2>; }; cpu6: cpu@6 { @@ -150,6 +156,7 @@ cluster = <&cluster1>; core = <&core6>; // clock-frequency = <800000000>; + cci-control-port = <&cci_control2>; }; cpu7: cpu@7 { @@ -159,6 +166,7 @@ cluster = <&cluster1>; core = <&core7>; // clock-frequency = <800000000>; + cci-control-port = <&cci_control2>; }; }; @@ -168,8 +176,23 @@ }; cci@2c090000 { - compatible = "arm,cci"; - reg = <0 0x2c090000 0 0x8000>; + compatible = "arm,cci-400", "arm,cci"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x2c090000 0 0x1000>; + ranges = <0x0 0x0 0x2c090000 0x10000>; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; }; dcscb@60000000 { |