diff options
| author | Mingkai Hu <Mingkai.hu@freescale.com> | 2010-10-12 18:18:33 +0800 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2010-10-12 21:38:12 -0600 |
| commit | f3016fa591c788d6d545ef7907e24c8b5d788759 (patch) | |
| tree | 75b05dbe3a010fb026143c36a0d85f2fb5864e83 /Documentation/powerpc | |
| parent | 8b60d6c25b2a2d3525d5322de856c3ca408e5783 (diff) | |
powerpc/of: add eSPI controller dts bindings and DTS modification
Also modifiy the document of cell-index in SPI controller. Add the
SPI flash(s25fl128p01) support on p4080ds and mpc8536ds board.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'Documentation/powerpc')
| -rw-r--r-- | Documentation/powerpc/dts-bindings/fsl/spi.txt | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt b/Documentation/powerpc/dts-bindings/fsl/spi.txt index 80510c018eea..777abd7399d5 100644 --- a/Documentation/powerpc/dts-bindings/fsl/spi.txt +++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt @@ -1,7 +1,9 @@ * SPI (Serial Peripheral Interface) Required properties: -- cell-index : SPI controller index. +- cell-index : QE SPI subblock index. + 0: QE subblock SPI1 + 1: QE subblock SPI2 - compatible : should be "fsl,spi". - mode : the SPI operation mode, it can be "cpu" or "cpu-qe". - reg : Offset and length of the register set for the device @@ -29,3 +31,23 @@ Example: gpios = <&gpio 18 1 // device reg=<0> &gpio 19 1>; // device reg=<1> }; + + +* eSPI (Enhanced Serial Peripheral Interface) + +Required properties: +- compatible : should be "fsl,mpc8536-espi". +- reg : Offset and length of the register set for the device. +- interrupts : should contain eSPI interrupt, the device has one interrupt. +- fsl,espi-num-chipselects : the number of the chipselect signals. + +Example: + spi@110000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc8536-espi"; + reg = <0x110000 0x1000>; + interrupts = <53 0x2>; + interrupt-parent = <&mpic>; + fsl,espi-num-chipselects = <4>; + }; |