diff options
authorSteve Capper <steve.capper@linaro.org>2014-07-02 11:46:23 +0100
committerMark Brown <broonie@linaro.org>2014-07-23 00:26:57 +0100
commit81151e675fb49cc89af86b6e8dd1aaa12ccf9415 (patch)
parentab1b3244377165e41b85c0953c075a75bd302ad2 (diff)
arm64: mm: Make icache synchronisation logic huge page awarev3.10/topic/arm64-hugepages
The __sync_icache_dcache routine will only flush the dcache for the first page of a compound page, potentially leading to stale icache data residing further on in a hugetlb page. This patch addresses this issue by taking into consideration the order of the page when flushing the dcache. Reported-by: Mark Brown <broonie@linaro.org> Tested-by: Mark Brown <broonie@linaro.org> Signed-off-by: Steve Capper <steve.capper@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@vger.kernel.org> # v3.11+ (cherry picked from commit 923b8f5044da753e4985ab15c1374ced2cdf616c) Signed-off-by: Mark Brown <broonie@linaro.org> Conflicts: arch/arm64/mm/flush.c
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
index 88611c3a421a..805fcce14da6 100644
--- a/arch/arm64/mm/flush.c
+++ b/arch/arm64/mm/flush.c
@@ -86,7 +86,8 @@ void __sync_icache_dcache(pte_t pte, unsigned long addr)
page = pfn_to_page(pfn);
if (!test_and_set_bit(PG_dcache_clean, &page->flags)) {
- __flush_dcache_page(page);
+ __flush_dcache_area(page_address(page),
+ PAGE_SIZE << compound_order(page));
} else if (icache_is_aivivt()) {