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authorRussell King <rmk+kernel@armlinux.org.uk>2017-11-27 11:22:42 +0000
committerAlex Shi <alex.shi@linaro.org>2017-12-07 09:26:56 +0800
commitb1cd381416ccee0e461b61837b31e17d2efdaa93 (patch)
tree115503cd55e429c6e2dce1a872066e4ed856d1ec
parentafd9e2868d7b987d694a911bc85d3313d4ce892d (diff)
downloadlinux-linaro-stable-linux-linaro-lsk-v4.4-test.tar.gz
ARM: avoid faulting on qemulinux-linaro-lsk-v4.4-test
When qemu starts a kernel in a bare environment, the default SCR has the AW and FW bits clear, which means that the kernel can't modify the PSR A or PSR F bits, and means that FIQs and imprecise aborts are always masked. When running uboot under qemu, the AW and FW SCR bits are set, and the kernel functions normally - and this is how real hardware behaves. Fix this for qemu by ignoring the FIQ bit. Fixes: 8bafae202c82 ("ARM: BUG if jumping to usermode address in kernel mode") Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> (cherry picked from commit 3aaf33bebda8d4ffcc0fc8ef39e6c1ac68823b11) Signed-off-by: Alex Shi <alex.shi@linaro.org>
-rw-r--r--arch/arm/kernel/entry-header.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 3fd24e2..6d243e83 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -295,7 +295,7 @@
mov r2, sp
ldr r1, [r2, #\offset + S_PSR] @ get calling cpsr
ldr lr, [r2, #\offset + S_PC]! @ get pc
- tst r1, #0xcf
+ tst r1, #PSR_I_BIT | 0x0f
bne 1f
msr spsr_cxsf, r1 @ save in spsr_svc
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
@@ -327,7 +327,7 @@
ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
ldr lr, [sp, #\offset + S_PC] @ get pc
add sp, sp, #\offset + S_SP
- tst r1, #0xcf
+ tst r1, #PSR_I_BIT | 0x0f
bne 1f
msr spsr_cxsf, r1 @ save in spsr_svc