diff options
Diffstat (limited to 'arch/m68k/include/asm/m5272sim.h')
| -rw-r--r-- | arch/m68k/include/asm/m5272sim.h | 99 |
1 files changed, 50 insertions, 49 deletions
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index a58f1760d85..1fb01bb05d6 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -21,52 +21,52 @@ /* * Define the 5272 SIM register set addresses. */ -#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ -#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ -#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ -#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ -#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ - -#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ -#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ -#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ -#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ - -#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ -#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ -#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ -#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ - -#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ -#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ -#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ -#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ - -#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ -#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ -#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ -#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ -#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ -#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ -#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ -#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ -#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ -#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ -#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ -#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ -#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ -#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ -#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ -#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ - -#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ -#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ -#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ -#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ -#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ -#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ -#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ +#define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */ +#define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */ +#define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */ +#define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */ +#define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */ + +#define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */ +#define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */ +#define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */ +#define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */ + +#define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */ +#define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */ +#define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */ +#define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */ + +#define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */ +#define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */ +#define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */ +#define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */ + +#define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */ +#define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */ +#define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */ +#define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */ +#define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */ +#define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */ +#define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */ +#define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */ +#define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */ +#define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */ +#define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */ +#define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */ +#define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */ +#define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */ +#define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */ +#define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */ + +#define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */ +#define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */ +#define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */ +#define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */ +#define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */ +#define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */ +#define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */ +#define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */ #define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */ #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ @@ -132,8 +132,9 @@ /* * Generic GPIO support */ -#define MCFGPIO_PIN_MAX 48 -#define MCFGPIO_IRQ_MAX -1 -#define MCFGPIO_IRQ_VECBASE -1 +#define MCFGPIO_PIN_MAX 48 +#define MCFGPIO_IRQ_MAX -1 +#define MCFGPIO_IRQ_VECBASE -1 + /****************************************************************************/ #endif /* m5272sim_h */ |